Hoja de datos de ADP151 Series de Analog Devices Inc.

ANALOG DEVICES —1_—E 3T’ H g _‘_—C :1 l i ,1; $ 44—— \JrF—VL Mi u i til—o— ”Q
Ultralow Noise, 200 mA,
CMOS Linear Regulator
Data Sheet ADP151
Rev. I Document Feedback
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FEATURES
Ultralow noise: 9 µV rms
No noise bypass capacitor required
Stable with 1 µF ceramic input and output capacitors
Maximum output current: 200 mA
Input voltage range: 2.2 V to 5.5 V
Low quiescent current
IGND = 10 µA with IOUT = 0 µA
IGND = 265 A with IOUT = 200 mA
Low shutdown current: <1 µA
Low dropout voltage: 135 mV at IOUT = 200 mA
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2.5%
16 fixed output voltage options: 1.1 V to 3.3 V
PSRR performance of 70 dB at 10 kHz
Current-limit and thermal overload protection
Logic controlled enable
Internal pull-down resistor on EN input
5-lead TSOT package
6-lead LFCSP package
4-ball, 0.4 mm pitch WLCSP
AEC-Q100 qualified for automotive applications
APPLICATIONS
RF, voltage controlled oscillator (VCO), and phase locked
loop (PLL) power supplies
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Portable medical devices
TYPICAL APPLICATION CIRCUITS
NC = NO CONNECT
1
2
3
5
4
1µF
1µF
VOUT = 1.8VVIN = 2.3V
VOUT
NC
VIN
GND
EN
OFF
ON
0
8627-001
Figure 1. TSOT ADP151 with Fixed Output Voltage, 1.8 V
VIN VOUT
12
EN GND
C
OUT
1µF
C
IN
V
OUT
= 1.8V
V
IN
= 2.3V
TOP VIEW
(Not to Scale)
A
B
OFF
ON
08627-002
Figure 2. WLCSP ADP151 with Fixed Output Voltage, 1.8 V
ADP151
TOP VIEW
(Not to Scale)
4
6
5
GND
VOUT
NC
3
1
2
EN
VIN
NC
08627-047
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
ON
OFF
1µF 1µF
V
IN
= 2.3
V
V
OUT
= 1.8
V
Figure 3. LFCSP ADP151 with Fixed Output Voltage, 1.8 V
GENERAL DESCRIPTION
The ADP151 is an ultralow noise, low dropout (LDO) linear
regulator that operates from 2.2 V to 5.5 V and provides up to
200 mA of output current. The low 135 mV dropout voltage at
200 mA load improves efficiency and allows operation over a
wide input voltage range.
Using an innovative circuit topology, the ADP151 achieves
ultralow noise performance without the necessity of a bypass
capacitor, making the device ideal for noise sensitive analog
and RF applications. The ADP151 also achieves ultralow noise
performance without compromising the power supply rejection
ratio (PSRR) or transient line and load performance. The low
265 A of operating supply current at 200 mA load makes the
ADP151 suitable for battery-operated portable equipment.
The ADP151 also includes an internal pull-down resistor on
the EN input.
The ADP151 is specifically designed for stable operation with
tiny 1 µF, ±30% ceramic input and output capacitors to meet
the requirements of high performance, space constrained
applications.
The ADP151 is capable of 16 fixed output voltage options,
ranging from 1.1 V to 3.3 V.
Short-circuit and thermal overload protection circuits prevent
damage in adverse conditions. The ADP151 is available in tiny
5-lead TSOT, 6-lead LFCSP, and 4-ball, 0.4 mm pitch, halide-
free WLCSP packages for the smallest footprint solution to
meet a variety of portable power application requirements.
ADP151 Data Sheet
Rev. I | Page 2 of 23
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Typical Application Circuits ........................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Input and Output Capacitor, Recommended Specifications . 4
Absolute Maximum Ratings ........................................................... 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Applications Information ............................................................. 12
Capacitor Selection .................................................................... 12
Enable Feature ............................................................................ 13
Adjustable Output Voltage Operation .................................... 13
Current-Limit and Thermal Overload Protection ................ 15
Thermal Considerations ........................................................... 15
Printed Circuit Board Layout Considerations ........................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
Automotive Products ................................................................ 23
REVISION HISTORY
9/2020—Rev. H to Rev. I
Changes to Ordering Guide .......................................................... 23
1/2020—Rev. G to Rev. H
Changes to Features Section ........................................................... 1
Added Current-Limit Threshold, W Grade Parameter, Table 1
and Input Voltage Rising, W Grade Parameter, Table 1 ............ 4
Changes to Ordering Guide .......................................................... 22
Added Automotive Products Section .......................................... 23
12/2019—Rev. F to Rev. G
Changes to Features Section .................................................................... 1
Deleted Input Voltage Rising, W Grade Parameter, Table 1 ............ 4
Changes to Ordering Guide .......................................................... 22
Deleted Automotive Products Section ........................................ 23
12/2019—Rev. E to Rev. F
Changes to Features Section and General Description Section ....... 1
Added Input Voltage Rising, W Grade Parameter, Table 1.............. 4
Changes to Ordering Guide .......................................................... 22
Added Automotive Products Section .......................................... 23
4/2012—Rev. D to Rev. E
Changes to Figure 33 ..................................................................... 13
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
3/2011—Rev. C to Rev. D
Changes to Current-Limit Threshold Temperature Range ....... 4
Added EPAD Notation .................................................................... 6
Changes to Ordering Guide .......................................................... 22
1/2011—Rev. B to Rev. C
Changes to Figure 23 ........................................................................ 9
12/2010—Rev. A to Rev. B
Added LFCSP Package ...................................................... Universal
Added Figure 3; Renumbered Sequentially ................................... 1
Added Table 2 Caption; Renumbered Sequentially ..................... 4
Changes to Table 4 ............................................................................ 5
Added Figure 6, Changes to Table 5 ............................................... 6
Changes to Figure 23 ........................................................................ 9
Changes to Figure 37 and Figure 38 ............................................ 14
Added Figure 51 to Figure 56 ....................................................... 18
Added Figure 59 ............................................................................. 19
Added Figure 62 ............................................................................. 20
Added Figure 65 ............................................................................. 21
Updated Outline Dimensions ...................................................... 21
Changes to Ordering Guide .......................................................... 23
8/2010—Rev. 0 to Rev. A
Changes to Figure 8 .......................................................................... 7
Changes to Figure 15 Caption and Figure 16 Caption ................ 8
Changes to Figure 17 Caption and Figure 18 Caption ................ 9
Changes to Ordering Guide .......................................................... 21
3/2010—Revision 0: Initial Version
Data Sheet ADP151
Rev. I | Page 3 of 23
SPECIFICATIONS
VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater, EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, and TA = 25°C, unless otherwise noted.
Note that VIN is the input voltage, VOUT is the output voltage, IOUT is the output current, CIN is the input capacitance, and COUT is the
output capacitance.
Table 1.
Parameter Symbol Test Conditions/Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN T
J = −40°C to +125°C 2.2 5.5 V
OPERATING SUPPLY CURRENT IGND I
OUT = 0 µA 10 µA
I
OUT = 0 µA, TJ = −40°C to +125°C 20 µA
I
OUT = 100 µA 20 µA
I
OUT = 100 µA, TJ = −40°C to +125°C 40 µA
I
OUT = 10 mA 60 µA
I
OUT = 10 mA, TJ = −40°C to +125°C 90 µA
I
OUT = 200 mA 265 A
I
OUT = 200 mA, TJ = −40°C to +125°C 350 A
SHUTDOWN CURRENT IGND-SD EN = GND 0.2 µA
EN = GND, TJ = −40°C to +125°C 1.0 µA
OUTPUT VOLTAGE ACCURACY VOUT
I
OUT = 10 mA −1 +1 %
TSOT/LFCSP TJ = −40°C to +125°C
V
OUT < 1.8 V
100 µA < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V −3 +2 %
V
OUT ≥1.8 V
100 µA < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V −2.5 +1.5 %
WLCSP TJ = −40°C to +125°C
V
OUT < 1.8 V
100 µA < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V −2.5 +2 %
V
OUT ≥1.8 V
100 µA < IOUT < 200 mA, VIN = (VOUT + 0.4 V) to 5.5 V −2 +1.5 %
REGULATION
Line Regulation VOUT/VIN V
IN = (VOUT + 0.4 V) to 5.5 V, TJ = −40°C to +125°C −0.05 +0.05 %/V
Load Regulation (TSOT/LFCSP)1 VOUT/IOUT V
OUT < 1.8 V %/mA
I
OUT = 100 µA to 200 mA 0.006 %/mA
I
OUT = 100 µA to 200 mA, TJ = −40°C to +125°C 0.012 %/mA
V
OUT ≥ 1.8 V
I
OUT = 100 µA to 200 mA 0.003 %/mA
I
OUT = 100 µA to 200 mA, TJ = −40°C to +125°C 0.008 %/mA
Load Regulation (WLCSP)1 VOUT/IOUT V
OUT < 1.8 V %/mA
I
OUT = 100 µA to 200 mA 0.004 %/mA
I
OUT = 100 µA to 200 mA, TJ = −40°C to +125°C 0.009 %/mA
V
OUT ≥1.8 V
I
OUT = 100 µA to 200 mA 0.002 %/mA
I
OUT = 100 µA to 200 mA, TJ = −40°C to +125°C 0.006 %/mA
DROPOUT VOLTAGE2 V
DROPOUT I
OUT = 10 mA 10 mV
I
OUT = 10 mA, TJ = −40°C to +125°C 30 mV
TSOT/LFCSP IOUT = 200 mA 150 mV
I
OUT = 200 mA, TJ = −40°C to +125°C 230 mV
WLCSP IOUT = 200 mA 135 mV
I
OUT = 200 mA, TJ = −40°C to +125°C 200 mV
ADP151 Data Sheet
Rev. I | Page 4 of 23
Parameter Symbol Test Conditions/Conditions Min Typ Max Unit
START-UP TIME3 t
START-UP V
OUT = 3.3 V 180 µs
CURRENT-LIMIT THRESHOLD4 I
LIMIT T
J = 0°C to +125°C 220 300 400 mA
W grade, TJ = −40°C to +125°C 205 300 400 mA
UNDERVOLTAGE LOCKOUT TJ = −40°C to +125°C
Input Voltage Rising UVLORISE 1.96 V
W grade 1.86 V
Input Voltage Falling UVLOFALL 1.28 V
Hysteresis UVLOHYS 120 mV
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD T
J rising 150 °C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
EN INPUT
EN Input Logic High VIH 2.2 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.2 V ≤ VIN ≤ 5.5 V 0.4 V
EN Input Pull-Down Resistance REN V
IN = EN voltage (VEN) = 5.5 V 2.6 MΩ
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 9 µV rms
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V 9 µV rms
10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.1 V 9 µV rms
POWER SUPPLY REJECTION RATIO PSRR
VIN = VOUT + 0.5 V 10 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 70 dB
100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 55 dB
VIN = VOUT + 1 V 10 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 70 dB
100 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 55 dB
10 kHz, VIN = 2.2 V, VOUT = 1.1 V, IOUT = 10 mA 70 dB
100 kHz, VIN = 2.2 V, VOUT = 1.1 V, IOUT = 10 mA 55 dB
1 Based on an end-point calculation using 0.1 mA and 200 mA loads. See Figure 8 for typical load regulation performance for loads less than 1 mA.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This voltage applies only for output
voltages above 2.2 V.
3 Start-up time is defined as the time between the rising edge of EN and VOUT being at 90% of its nominal value.
4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V (that is, 2.7 V).
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Minimum Input and Output Capacitance1 C
MIN TA = −40°C to +125°C 0.7 µF
Capacitor ESR RESR T
A = −40°C to +125°C 0.001 0.2
1 The minimum input and output capacitance must be greater than 0.7 F over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
and Y5V and Z5U capacitors are not recommended for use with any low dropout (LDO) regulator.
ESD (electrostatic dischivge) sensitive device. Charged devmes and ("mm board: (an duchavge wnhom daemon Akhough mu pvoducl feamves pmemed or pvopnemy pmxeznan cwcumy, damage may mm on deva summed to my» enevgy ESD Thevelove, pvopev ESD pvecaullons should be mken m avold pevfovmance degradauon or loss offuncuonalvty
Data Sheet ADP151
Rev. I | Page 5 of 23
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +6.5 V
VOUT to GND −0.3 V to VIN
EN to GND −0.3 V to +6.5 V
Temperature Range
Storage −65°C to +150°C
Operating Junction −40°C to +125°C
Operating Ambient −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP151 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. TJ of the
device is dependent on TA, the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA).
To calculate the maximum TJ from TA and PD use the following
equation:
TJ = TA + (PD × θJA)
The θJA of the package is based on modeling and calculation
using a 4-layer board. θJA is highly dependent on the application
and board layout. In applications where high maximum PD
exists, close attention to thermal board design is required. The
value of θJA may vary, depending on PCB material, layout, and
environmental conditions. The specified values of θJA are based
on a 4-layer, 4 inches × 3 inches circuit board. See JESD51-7
and JESD51-9 for detailed information on the board
construction. For additional information, see the AN-617
Application Note, MicroCSP Wafer Level Chip Scale Package.
ΨJB is the junction to board, thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling
and calculation using a 4-layer board. The JESD51-12,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than a
single path as in θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real-
world applications. To calculate the maximum TJ from the
board temperature (TB) and PD, use the following equation:
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Ψ
JB Unit
5-Lead TSOT (UJ-5) 170 43 °C/W
4-Ball WLCSP (CB-4-3) 260 58 °C/W
6-Lead LFCSP (CP-6-3) 63.6 28.3 °C/W
ESD CAUTION
I’II’H’I
ADP151 Data Sheet
Rev. I | Page 6 of 23
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
TOP VIEW
(Not to Scale)
ADP151
1
2
3
5
4
VIN
GND
EN
VOUT
NC
0
8627-003
Figure 4. 5-Lead TSOT Pin Configuration
12
A
B
TOP VIEW
(Not to Scale)
VIN VOUT
EN GND
08627-004
Figure 5. 4-Ball WLCSP Ball Configuration
ADP151
TOP VIEW
(Not to Scale)
3
1
2
GND
VOUT
NC
4
6
5
EN
VIN
NC
08627-048
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 6. 6-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
TSOT WLCSP LFCSP
1 A1 6 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
2 B2 3 GND Ground.
3 B1 4 EN
Enable Input. Drive EN high to turn on the regulator and drive EN low to turn
off the regulator. For automatic startup, connect EN to VIN.
4 Not applicable 2 NC No Connect. Not connected internally.
5 A2 1 VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater
capacitor.
Not applicable Not applicable 5 NC No Connect. Not connected internally.
Not applicable Not applicable EPAD Exposed Pad. The exposed pad must be connected to ground. The exposed
pad enhances the thermal performance of the package.
Data Sheet ADP151
Rev. I | Page 7 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 µF, and TA = 25°C, unless otherwise noted.
3.35
3.25
3.27
3.29
3.31
3.33
4052585125
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
08627-005
Figure 7. VOUT vs. Junction Temperature
3.35
3.25
3.27
3.29
3.31
3.33
0.01 10001001010.1
V
OUT
(V)
I
LOAD
(mA)
08627-006
Figure 8. VOUT vs. Load Current (ILOAD)
3.35
3.25
3.27
3.29
3.31
3.33
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
V
OUT
(V)
V
IN
(V)
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
08627-007
Figure 9. VOUT vs. VIN
1k
100
10
1
–40 –5 25 85 125
GROUND CURRENTA)
JUNCTION TEMPERATURE (°C)
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
08627-008
Figure 10. Ground Current vs. Junction Temperature
1k
10
100
0.01 10001001010.1
GROUND CURRENTA)
I
LOAD
(mA)
08627-009
Figure 11. Ground Current vs. ILOAD
GROUND CURRENTA)
V
IN
(V)
1k
10
100
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
LOAD = 10µA
LOAD = 100µA
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
08627-010
Figure 12. Ground Current vs. VIN
ADP151 Data Sheet
Rev. I | Page 8 of 23
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–50 –25 1251007550250
SHUTDOWN CURRENTA)
TEMPERATURE (°C)
V
IN
= 3.6V
V
IN
= 3.8V
V
IN
= 4.2V
V
IN
= 4.4V
V
IN
= 4.8V
V
IN
= 5.5V
08627-011
Figure 13. Shutdown Current vs. Temperature at Various Input Voltages
120
100
80
60
40
20
0
1 10 100 1000
DROPOUT VOLTAGE (mA)
I
LOAD
(mA)
08627-012
Figure 14. Dropout Voltage vs. ILOAD
3.40
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55
V
OUT
(V)
V
IN
(V)
I
OUT
= 1mA
I
OUT
= 5mA
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 200mA
08627-013
Figure 15. VOUT vs. VIN (in Dropout)
800
700
600
500
400
300
200
100
0
3.10 3.553.503.453.403.353.303.253.203.15
GROUND CURRENTA)
V
IN
(V)
I
OUT
= 1mA
I
OUT
= 5mA
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 200mA
08627-014
Figure 16. Ground Current vs. VIN (in Dropout)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
200mA
100mA
10mA
1mA
100µA
08627-015
Figure 17. PSRR vs. Frequency, VOUT = 1.2 V, VIN = 2.2 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
200mA
100mA
10mA
1mA
100µA
08627-016
Figure 18. PSRR vs. Frequency, VOUT = 2.8 V, VIN = 3.3 V
Data Sheet ADP151
Rev. I | Page 9 of 23
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
200mA
100mA
10mA
1mA
100µA
08627-017
Figure 19. PSRR vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
V
OUT
= 3.3V, I
OUT
= 200mA
V
OUT
= 3.3V, I
OUT
= 10mA
V
OUT
= 2.8V, I
OUT
= 200mA
V
OUT
= 2.8V, I
OUT
= 10mA
V
OUT
= 1.1V, I
OUT
= 200mA
V
OUT
= 1.1V, I
OUT
= 10mA
08627-018
Figure 20. PSRR vs. Frequency at Various Output Voltages and Load Currents,
VOUT − VIN = 0.5 V, Except for VOUT = 1.1 V, VIN = 2.2 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
PSRR (dB)
FREQUENCY (Hz)
I
OUT
= 200mA, V
IN
= 3.3V
I
OUT
= 10mA, V
IN
=3.3V
I
OUT
= 200mA, V
IN
= 3.8V
I
OUT
= 10mA, V
IN
= 3.8V
08627-019
Figure 21. PSRR vs. Frequency at Various Voltages and Load Currents,
VOUT = 2.8 V
14
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0.001 0.01 0.1 1 10 100 1k
NOISE (µV rms)
LOAD CURRENT (mA)
3.3V
2.8V
1.2V
1.1V
08627-020
Figure 22. Output Noise vs. Load Current for Various Output Voltages,
VIN = 5 V, COUT = 1 µF
1000
10
100
10 100k10k1k100
NOISE SPECTRAL DENSITY (nV/ Hz)
FREQUENCY (Hz)
3.3V
2.8V
1.2V
1.1V
08627-021
Figure 23. Output Noise Spectral Density vs. Frequency,
VIN = 5 V, ILOAD = 10 mA, COUT = 1 µF
CH1 200mA CH2 50mV M20µs A CH1 64.0mA
T 10.00%
1
2
T
LOAD CURRENT
V
OUT
08627-022
Figure 24. Load Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA to 200 mA
CH1J' cH1f
ADP151 Data Sheet
Rev. I | Page 10 of 23
CH1 1V CH2 2mV M10µs A CH1 4.56V
T 10.80%
1
2
T
INPUT VOLTAGE
V
OUT
08627-023
Figure 25. Line Transient Response, CIN, COUT = 1 F, ILOAD = 200 mA
CH1 1V CH2 2mV M10µs A CH1 4.56V
T 10.80%
1
2
T
INPUT VOLTAGE
V
OUT
08627-024
Figure 26. Line Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA
Data Sheet ADP151
Rev. I | Page 11 of 23
THEORY OF OPERATION
The ADP151 is an ultralow noise, low quiescent current, LDO
linear regulator that operates from 2.2 V to 5.5 V and can provide
up to 200 mA of output current. Drawing a low 265 A of
operating supply current (typical) at full load makes the
ADP151 ideal for battery operated, portable equipment.
Shutdown current consumption is typically 0.2 µA.
Using a proprietary architecture, the ADP151 provides superior
noise performance for noise sensitive analog and RF applications
without the need for a noise bypass capacitor. The ADP151 is
also optimized for use with small 1 µF ceramic capacitors.
08627-025
REFERENCE
SHORT-CIRCUIT,
UVLO, AND
THERMAL
PROTECT
SHUTDOWN
R1
R2
R
EN
V
OU
T
VIN
GND
EN
Figure 27. Internal Block Diagram
Internally, the ADP151 consists of a reference, an error
amplifier, a feedback voltage divider, and a PMOS pass
transistor. Output current is delivered via the PMOS pass
device, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the
feedback voltage is lower than the reference voltage, the gate
of the PMOS device pulls lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the gate of the PMOS device
pulls higher, allowing less current to pass and decreasing the
output voltage.
An internal pull-down resistor on the EN input holds the input
low when the pin is left open.
The ADP151 is available in 16 output voltage options, ranging
from 1.1 V to 3.3 V. The ADP151 uses the EN pin to enable and
disable the VOUT pin under normal operating conditions. When
EN is high, VOUT turns on, and when EN is low, VOUT turns
off. For automatic startup, tie EN to VIN.
ADP151 Data Sheet
Rev. I | Page 12 of 23
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP151 is designed for operation with small, space-saving
ceramic capacitors but can function with most commonly used
capacitors as long as care is taken with regard to the effective
series resistance (ESR) value. The ESR of the output capacitor
affects the stability of the LDO control loop. A minimum of
1 µF capacitance with an ESR of 1 Ω or less is recommended
to ensure the stability of the ADP151. Transient response to
changes in load current is also affected by output capacitance.
Using a larger value of output capacitance improves the
transient response of the ADP151 to large changes in load
current. Figure 28 shows the transient responses for an output
capacitance value of 1 µF.
CH1 200mA CH2 50mV M20µs A CH1 64mA
T 10.00%
1
2
T
LOAD CURRENT
V
OUT
08627-026
Figure 28. Output Transient Response, COUT = 1 µF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance are encountered. If greater
than 1 µF of output capacitance is required, the input capacitor
must be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the
ADP151 as long as the capacitor meets the minimum
capacitance and maximum ESR requirements. Ceramic
capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied
voltage. Capacitors must have an adequate dielectric to ensure
the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and
Z5U dielectrics are not recommended due to their poor
temperature and dc bias characteristics.
Figure 29 depicts the capacitance vs. voltage bias characteristic
of an 0402, 1 µF, 10 V X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and
voltage rating. In general, a capacitor in a larger package or
higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is ~±15% over the −40°C to
+85°C temperature range and is not a function of package or
voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0246810
CAPACITANCE (µF)
VOLTAGE BIAS
08627-027
Figure 29. Capacitance vs. Voltage Bias Characteristic
Use Equation 1 to determine the worst case capacitance,
accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is 15% for an X5R dielectric,
the tolerance of the capacitor (TOL) is 10%, and CBIAS is 0.94 µF
at 1.8 V, as shown in Figure 29.
Substituting these values in Equation 1 yields the following:
CEFF = 0.94 µF × (1 − 0.15) × (1 − 0.1) = 0.719 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP151, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Data Sheet ADP151
Rev. I | Page 13 of 23
ENABLE FEATURE
The ADP151 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 30,
when a rising voltage on EN crosses the active threshold,
VOUT turns on. When a falling voltage on EN crosses the
inactive threshold, VOUT turns off.
3.0
2.5
2.0
1.5
0.5
1.0
0
0 0.5 1.0 1.5 2.0 2.5
V
OUT
ENABLE VOLTAGE
08627-028
Figure 30. ADP151 Typical EN Pin Operation
As shown in Figure 30, the EN pin has hysteresis built in to
prevent on and off oscillations that can occur due to noise on
the EN pin as this pin passes through the threshold points.
The EN pin active and inactive thresholds are derived from the
VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 31 shows typical EN active and inactive
thresholds when the input voltage varies from 2.2 V to 5.5 V.
1200
1000
800
600
200
400
0
2.0 2.5 3.0 3.5 4.5 5.04.0 5.5
ENABLE VOLTAGE
INPUT VOLTAGE
V
EN
RISE
V
EN
FALL
08627-029
Figure 31. Typical EN Pin Thresholds vs. Input Voltage
The ADP151 uses an internal soft start to limit the inrush
current when the output is enabled. The start-up time for the
3.3 V option is approximately 160 µs from the time the EN
active threshold is crossed to when the output reaches 90% of
its final value. As shown in Figure 32, the start-up time is
dependent on the output voltage setting.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
045040035030025020015010050
ENABLE VOLTAGE
TIME (µs)
ENABLE
3.3V
2.8V
1.1V
08627-030
Figure 32. Typical Start-Up Behavior
ADJUSTABLE OUTPUT VOLTAGE OPERATION
The unique architecture of the ADP151 makes an adjustable
version difficult to implement in silicon. However, it is possible
to create an adjustable regulator at the expense of increasing the
quiescent current of the regulator circuit.
The ADP151, and similar LDOs, are designed to regulate the
output voltage (VOUT) appearing at the VOUT pin with respect
to the GND pin. If the GND pin is at a potential other than 0 V
(for example, at the offset voltage (VOFFSET)), the ADP151
output voltage is VOUT + VOFFSET. By taking advantage of this
behavior, it is possible to create an adjustable ADP151 circuit
that retains most of the desirable characteristics of the ADP151.
08627-131
U1
1
2
3
5
4
C2
C1
V
OUT
V
IN
VOUT
NC
VIN
GND
EN
C3
R2
V
OFFSET
R1
V
OUT
= V
LDO
× (1 + R2/R1)
Figure 33. Adjustable LDO Using the ADP151
The circuit shown in Figure 33 is an example of an adjustable
LDO using the ADP151. A stable VOFFSET voltage is created by
passing a known current through R2. The current through R2 is
determined by the voltage across R1. Because the voltage across
R1 is set by the voltage between VOUT and GND, the current
passing through R2 is fixed, and VOFFSET is stable.
To minimize the effect variation of the ADP151 ground current
(IGND) with load, it is best to keep R1 as small as possible. It is
also best to size the current passing through R2 to at least 20×
greater than the maximum expected ground current.
ADP151 Data Sheet
Rev. I | Page 14 of 23
To create a 4 V LDO circuit, start with the 3.3 V version of the
ADP151 to minimize the value of R2. Because VOUT is 4 V, VOFFSET
must be 0.7 V, and the current through R2 must be 7 mA. R1 is,
therefore, 3.3 V/7 mA or 471 . A 470  standard value introduces
less than 1% error. Capacitor C3 is necessary to stabilize the LDO.
A value of 1 µF is adequate.
Figure 34 through Figure 38 show the typical performance of
the 4 V LDO circuit.
The noise performance of the 4 V LDO circuit is only about
1 µV worse than the same LDO used at 3.3 V because the
output noise of the circuit is almost solely determined by the
LDO and not the external components. The small difference
may be attributed to the internally generated noise in the LDO
ground current working with R2. By keeping R2 small, this
noise contribution can be minimized.
The PSRR of the 4 V circuit is as much as 10 dB poorer than the
3.3 V LDO with 500 mV of headroom because the ground
current of the LDO varies slightly with input voltage. This, in
turn, modulates VOFFSET and reduces the PSRR of the regulator.
By increasing the headroom to 1 V, the PSRR performance is
nearly restored to the performance of the fixed output LDO.
4.04
4.03
4.02
4.01
4.00
3.99
3.98
3.97
3.96
4052585125
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
08627-132
LOAD = 10mA
LOAD = 20mA
LOAD = 50mA
LOAD = 100mA
LOAD = 150mA
LOAD = 200mA
Figure 34. 4 V LDO Circuit, Typical Load Regulation over Temperature
V
OUT
(V)
V
IN
(V)
08627-133
LOAD = 10mA
LOAD = 20mA
LOAD = 50mA
LOAD = 100mA
LOAD = 150mA
LOAD = 200mA
4.040
4.035
4.030
4.025
4.020
4.015
4.010
4.005
4.000
4.4 5.2 5.44.84.6 5.0
Figure 35. 4 V LDO Circuit, Typical Line Regulation over Load Current
11
10
9
8
1 100 1k10
NOISE (µV rms)
LOAD CURRENT (mA)
08627-134
Figure 36. 4 V LDO Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
08627-049
200mA
100mA
50mA
10mA
Figure 37. 4 V LDO Circuit, Typical PSRR vs. Load Current, 1 V Headroom
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
PSRR (dB)
08627-050
200mA
100mA
50mA
10mA
Figure 38. 4 V LDO Circuit, Typical PSRR vs. Load Current, 500 mV Headroom
Data Sheet ADP151
Rev. I | Page 15 of 23
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP151 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP151 is designed to current limit when the
output load reaches 300 mA (typical). When the output load
exceeds 300 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power
dissipation) when the junction temperature starts to rise above
150°C, the output is turned off, reducing the output current
to 0. When the junction temperature drops below 135°C, the
output is turned on again, and the output current is restored to
its nominal value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP151 current limits, so that only 300 mA
is conducted into the short. If self heating of the junction causes
its temperature to rise above 150°C, thermal shutdown activates,
turning off the output and reducing the output current to 0. As the
junction temperature cools and drops below 135°C, the output
turns on and conducts 300 mA into the short, again causing the
junction temperature to rise above 150°C. This thermal oscillation
between 135°C and 150°C causes a current oscillation between
300 mA and 0 mA that continues as long as the short remains
at the output.
Current-limit and thermal limit protections protect the device
against accidental overload conditions. For reliable operation,
device power dissipation must be externally limited so that
junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
In most applications, the ADP151 does not dissipate much heat
due to its high efficiency. However, in applications with a high
ambient temperature and a high supply voltage to output voltage
differential, the heat dissipated in the package can cause the
junction temperature of the die to exceed the maximum
junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. The converter recovers only after the
junction temperature has decreased below 135°C to prevent any
permanent damage. Therefore, thermal analysis for the chosen
application is important to guarantee reliable performance over
all conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the temperature
rise of the package due to the power dissipation, as shown in
Equation 2.
To guarantee reliable operation, the junction temperature of
the ADP151 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used and the amount
of copper used to solder the package GND pins to the PCB.
Table 6 shows typical θJA values of the 5-lead TSOT, the 6-lead
LFCSP, and the 4-ball WLCSP for various PCB copper sizes.
Table 7 shows the typical ΨJB values of the 5-lead TSOT, the
6-lead LFCSP, and the 4-ball WLCSP.
Table 6. Typical θJA Values
Copper Size (mm2)
θJA (°C/W)
TSOT WLCSP LFCSP
01 170 260 231.2
50 152 159 161.8
100 146 157 150.1
300 134 153 111.5
500 131 151 91.8
1 Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
Model ΨJB (°C/W)
5-Lead TSOT 43
4-Ball WLCSP 58
6-Lead LFCSP 28.3
To calculate the junction temperature of the ADP151, use the
following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = ((VINVOUT) × ILOAD) + (VIN × IGND) (3)
where:
VIN and VOUT are input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is small and can be
ignored. Therefore, the junction temperature equation simplifies
to the following:
TJ = TA + (((VINVOUT) × ILOAD) × θJA) (4)
As shown in Equation 4, for a given ambient temperature,
input to output voltage differential, and continuous load
current, there exists a minimum copper size requirement for
the PCB to ensure that the junction temperature does not rise
above 125°C.
ADP151 Data Sheet
Rev. I | Page 16 of 23
Figure 39 through Figure 59 show junction temperature
calculations for various ambient temperatures, load currents,
VIN to VOUT differentials, and areas of PCB copper.
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
MAXIMUM JUNCTION TEMPERATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
08627-031
Figure 39. WLCSP 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
MAXIMUM JUNCTION TEMPERATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
08627-032
Figure 40. WLCSP 100 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
MAXIMUM JUNCTION TEMPERATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
08627-033
Figure 41. WLCSP 50 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-034
Figure 42. WLCSP 500 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-035
Figure 43. WLCSP 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-036
Figure 44. WLCSP 50 mm2 of PCB Copper, TA = 50°C
Data Sheet ADP151
Rev. I | Page 17 of 23
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-037
Figure 45. TSOT 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-038
Figure 46. TSOT 100 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-039
Figure 47. TSOT 50 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-040
Figure 48. TSOT 500 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-041
Figure 49. TSOT 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-042
Figure 50. TSOT 50 mm2 of PCB Copper, TA = 50°C
MAXIMUM JUNCTION YEMPERAYURE
ADP151 Data Sheet
Rev. I | Page 18 of 23
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-051
Figure 51. LFCSP 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
VIN VOUT (V)
JUNCTION TEMPERATURE,
T
J (°C)
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 150mA
ILOAD = 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-052
Figure 52. LFCSP 100 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
VIN VOUT (V)
JUNCTION TEMPERATURE,
J (°C)
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 150mA
ILOAD = 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-053
Figure 53. LFCSP 50 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-055
Figure 54. LFCSP 500 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-056
Figure 55. LFCSP 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE, T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM
JUNCTION
TEMPERATURE
08627-057
Figure 56. LFCSP 50 mm2 of PCB Copper, TA = 50°C
Data Sheet ADP151
Rev. I | Page 19 of 23
In the case where the board temperature is known, use the
thermal characterization parameter (ΨJB) to estimate the
junction temperature rise (see Figure 57 and Figure 58).
Maximum TJ is calculated from the TB and PD using the
following formula:
TJ = TB + (PD × ΨJB) (5)
The typical value of ΨJB is 58°C/W for the 4-ball WLCSP,
43°C/W for the 5-lead TSOT, and 28.3°C/W for the 6-lead
LFCSP.
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-043
Figure 57. WLCSP, TA = 85°C
140
120
100
80
60
40
20
0
0.3 4.84.33.83.32.82.31.81.30.8
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-044
Figure 58. TSOT, TA = 85°C
140
120
100
80
60
40
20
0
0.3 5.34.33.32.3
1.3
V
IN
– V
OUT
(V)
JUNCTION TEMPERATURE,
T
J
(°C)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 200mA
MAXIMUM JUNCTION TEMPERATURE
08627-059
Figure 59. LFCSP, TA = 85°C
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ADP151 Data Sheet
Rev. I | Page 20 of 23
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP151. However, as listed in Table 6, a point of diminishing
returns is eventually reached beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and the
GND pins. Place the output capacitor as close as possible to the
VOUT and the GND pins. Use of 0402 or 0603 size capacitors
and resistors achieves the smallest possible footprint solution
on boards where area is limited.
08627-045
Figure 60. Example TSOT PCB Layout
08627-046
Figure 61. Example WLCSP PCB Layout
08627-054
Figure 62. Example LFCSP PCB Layout
GO 70C)
Data Sheet ADP151
Rev. I | Page 21 of 23
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-193-AB
0.95 BSC
1.90 REF
0.90
0.70
0.20
0.08
0.60
0.45
0.30
0.50
0.30
0.10 MAX
1.00 MAX
54
12 3
END VIEW
TOP VIEW
SIDE VIEW
04-05-2017-B
PKG-000882
3.05
2.90
2.75
3.05
2.80
2.55
1.75
1.60
1.45
SEATING
PLANE
Figure 63. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
0.800
0.760 SQ
0.720
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
A
12
B
BALL A1
IDENTIFIER
0.40
REF
0.660
0.600
0.540
END VIEW
0.280
0.260
0.240
0.430
0.400
0.370
SEATING
PLANE 0.230
0.200
0.170
COPLANARITY
0.05
04-18-2012-A
Figure 64. 4-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-4-3)
Dimensions show in millimeters
ADP151 Data Sheet
Rev. I | Page 22 of 23
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
6
1
4
3
0.35
0.30
0.25
BOTTOM VIEW
PIN 1 INDEX
AREA
0.60
0.55
0.50
1.10
1.00
0.90
0.20 REF
0.05 MAX
0.02 NOM
0.65 BSC
EXPOSED
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
2.10
2.00 SQ
1.90
0.15 MIN
08-17-2018-D
SEATING
PLANE
PIN 1
INDICATORAREAOPTIONS
(SEEDETAILA)
DETAIL A
(JEDEC 95)
PKG-003581
Figure 65. 6-Lead Lead Frame Chip Scale Package [LFCSP],
2.00 mm × 2.00 mm Body and 0.55 mm Package Height
(CP-6-3)
Dimensions show in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Output Voltage (V)3 Package Description Package Option4 Marking Code
ADP151ACBZ-1.1-R7 –40°C to +125°C 1.1 4-Ball WLCSP CB-4-3 8R
ADP151ACBZ-1.2-R7 –40°C to +125°C 1.2 4-Ball WLCSP CB-4-3 4R
ADP151ACBZ-1.5-R7 –40°C to +125°C 1.5 4-Ball WLCSP CB-4-3 4S
ADP151ACBZ-1.8-R7 –40°C to +125°C 1.8 4-Ball WLCSP CB-4-3 4T
ADP151ACBZ-2.1-R7 –40°C to +125°C 2.1 4-Ball WLCSP CB-4-3 5E
ADP151ACBZ-2.5-R7 –40°C to +125°C 2.5 4-Ball WLCSP CB-4-3 4U
ADP151ACBZ-2.6-R7 –40°C to +125°C 2.6 4-Ball WLCSP CB-4-3 8Q
ADP151ACBZ-2.75-R7 –40°C to +125°C 2.75 4-Ball WLCSP CB-4-3 4V
ADP151ACBZ-2.8-R7 –40°C to +125°C 2.8 4-Ball WLCSP CB-4-3 4X
ADP151ACBZ-2.85-R7 –40°C to +125°C 2.85 4-Ball WLCSP CB-4-3 4Y
ADP151ACBZ-3.0-R7 –40°C to +125°C 3.0 4-Ball WLCSP CB-4-3 4Z
ADP151ACBZ-3.3-R7 –40°C to +125°C 3.3 4-Ball WLCSP CB-4-3 50
ADP151WACBZ-1.1-R7 –40°C to +125°C 1.1 4-Ball WLCSP CB-4-3 F4
ADP151WACBZ-1.2-R7 –40°C to +125°C 1.2 4-Ball WLCSP CB-4-3 F5
ADP151WACBZ-1.5-R7 –40°C to +125°C 1.5 4-Ball WLCSP CB-4-3 F6
ADP151WACBZ-1.8-R7 –40°C to +125°C 1.8 4-Ball WLCSP CB-4-3 EW
ADP151WACBZ-2.1-R7 –40°C to +125°C 2.1 4-Ball WLCSP CB-4-3 F7
ADP151WACBZ-2.5-R7 –40°C to +125°C 2.5 4-Ball WLCSP CB-4-3 F8
ADP151WACBZ-2.6-R7 –40°C to +125°C 2.6 4-Ball WLCSP CB-4-3 F9
ADP151WACBZ-2.75-R7 –40°C to +125°C 2.75 4-Ball WLCSP CB-4-3 FA
ADP151WACBZ-2.8-R7 –40°C to +125°C 2.8 4-Ball WLCSP CB-4-3 FB
ADP151WACBZ-2.85-R7 –40°C to +125°C 2.85 4-Ball WLCSP CB-4-3 FC
ADP151WACBZ-3.0-R7 –40°C to +125°C 3.0 4-Ball WLCSP CB-4-3 FD
ADP151WACBZ-3.3-R7 –40°C to +125°C 3.3 4-Ball WLCSP CB-4-3 FE
ANALOG DEVICES www.analag.com
Data Sheet ADP151
Rev. I | Page 23 of 23
Model1, 2 Temperature Range Output Voltage (V)3 Package Description Package Option4 Marking Code
ADP151AUJZ-1.2-R7 –40°C to +125°C 1.2 5-Lead TSOT UJ-5 LF6
ADP151AUJZ-1.5-R7 –40°C to +125°C 1.5 5-Lead TSOT UJ-5 LF7
ADP151AUJZ-1.8-R7 –40°C to +125°C 1.8 5-Lead TSOT UJ-5 LF8
ADP151AUJZ-2.5-R7 –40°C to +125°C 2.5 5-Lead TSOT UJ-5 LF9
ADP151AUJZ-2.8-R7 –40°C to +125°C 2.8 5-Lead TSOT UJ-5 LFG
ADP151AUJZ-2.9-R7 –40°C to +125°C 2.9 5-Lead TSOT UJ-5 LTL
ADP151AUJZ-3.0-R7 –40°C to +125°C 3.0 5-Lead TSOT UJ-5 LFH
ADP151AUJZ-3.3-R7 –40°C to +125°C 3.3 5-Lead TSOT UJ-5 LFJ
ADP151WAUJZ-1.8-R7 –40°C to +125°C 1.8 5-Lead TSOT UJ-5 LVP
ADP151ACPZ-1.2-R7 –40°C to +125°C 1.2 6-Lead LFCSP CP-6-3 LF6
ADP151ACPZ-1.5-R7 –40°C to +125°C 1.5 6-Lead LFCSP CP-6-3 LF7
ADP151ACPZ-1.8-R7 –40°C to +125°C 1.8 6-Lead LFCSP CP-6-3 LF8
ADP151ACPZ-2.5-R7 –40°C to +125°C 2.5 6-Lead LFCSP CP-6-3 LF9
ADP151ACPZ-2.7-R7 –40°C to +125°C 2.7 6-Lead LFCSP CP-6-3 LKZ
ADP151ACPZ-2.8-R7 –40°C to +125°C 2.8 6-Lead LFCSP CP-6-3 LFG
ADP151ACPZ-3.0-R7 –40°C to +125°C 3.0 6-Lead LFCSP CP-6-3 LFH
ADP151ACPZ-3.3-R7 –40°C to +125°C 3.3 6-Lead LFCSP CP-6-3 LFJ
ADP151UJZ-REDYKIT TSOT Evaluation Board Kit
ADP151CPZ-REDYKIT LFCSP Evaluation Board Kit
ADP151CB-3.3-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 For additional voltage options for the ADP151ACBZ package option, contact a local Analog Devices, Inc., sales or distribution representative.
4 The ADP151ACBZ package option is halide free.
AUTOMOTIVE PRODUCTS
The ADP151W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2010–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08627-9/20(I)