Hoja de datos de SN65LVDM176 de Texas Instruments

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FEATURES
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
SN65LVDM176D (Marked as DM176 or LVM176)
SN65LVDM176DGK (Marked as M76)
(TOP VIEW)
logic diagram (positive logic)
B
7
A
6
1
R
2
RE
3
DE
4
D
DESCRIPTION
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER
•Low-Voltage Differential Driver and Receiverfor Half-Duplex Operation•Designed for Signaling Rates of 400 Mbit/s•ESD Protection Exceeds 15 kV on Bus Pins•Operates From a Single 3.3-V Supply•Low-Voltage Differential Signaling WithTypical Output Voltages of 350 mV and a50- ΩLoad•Valid Output With as Little as 50 mV InputVoltage Difference•Propagation Delay Times
– Driver: 1.7 ns Typ
– Receiver: 3.7 ns Typ•Power Dissipation at 200 MHz
– Driver: 50 mW Typical
– Receiver: 60 mW Typical•LVTTL Levels Are 5-V Tolerant•Bus Pins Are High Impedance When Disabledor With V
CC
Less Than 1.5 V•Open-Circuit Fail-Safe Receiver•Surface-Mount Packaging
– D Package (SOIC)
– DGK Package (MSOP)
The SN65LVDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltagedifferential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar toTIA/EIA-644 standard compliant devices (SN65LVDS) counterparts except that the output current of the drivers isdoubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50- Ωloadand allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of lessthan 50 mV with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for half-duplex or multiplex baseband datatransmission over controlled impedance media of approximately 100- Ωcharacteristic impedance. Thetransmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate anddistance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to theenvironment, and other application specific characteristics).
The SN65LVDM176 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2000, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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FUNCTION TABLES
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE MSOP(D)
(1)
(DGK)
(1)
–40°C to 85°C SN65LVDM176D SN65LVDM176DGK
(1) The D package is available taped and reeled. Add the suffix R to the device type(e.g.,SN65LVDM176DR).
DRIVER
(1)
OUTPUTSINPUT ENABLED DE
A B
L H L H
H H H L
Open H L H
X L Z Z
(1) H = high level, L = low level, X = irrelevant, Z = high impedance
RECEIVER
(1)
DIFFERENTIAL INPUTS ENABLE OUTPUTV
ID
= V
A
- V
B
RE R
V
ID
≥50 mV L H
50 mV < V
ID
< 50 mV L ?
V
ID
≤-50 mV L L
Open L H
X H Z
(1) H = high level, L = low level, X = irrelevant, Z = high impedance
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
300 kΩ
50 Ω
VCC
7 V
D or RE
Input
300 kΩ
50 Ω
VCC
7 V
DE
Input
5 Ω
10 kΩ
7 V
Y or Z
Output
VCC
7 V
VCC
7 V
R Output
VCC
5 Ω
B InputA Input
300 kΩ300 kΩ
7 V
ABSOLUTE MAXIMUM RATINGS
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
Supply voltage
(2)
–0.5 V to 4 V
D, R, DE, RE –0.5 V to 6 VInput voltage range
A or B –0.5 V to 4 V
A, B , and GND
(3)
CLass 3, A:15 kV, B:600 VElectrostatic discharge
All terminals Class 3, A:7 kV, B:500 V
Continuous total power dissipation See Dissipation Rating Table
T
A
Operating free-air temperature range –40°C to 85°C
T
stg
Storage temperature range –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7.
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DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
2.4
VID
2
VID
2
DEVICE ELECTRICAL CHARACTERISTICS
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
T
A
≤25°C DERATING FACTOR T
A
= 85°CPACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
D 725 mW 5.8 mW/°C 377 mW
DGK 424 mW 3.4 mW/°C 220 mW
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
|V
ID
| Magnitude of differential input voltage 0.1 0.6 V
V
IC
Common-mode input voltage (see Figure 1 ) V
V
CC
–0.8
T
A
Operating free-air temperature –40 85 °C
Figure 1.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Driver and receiver enabled, no receiver load, driver R
L
= 50 Ω10 15
Driver enabled, receiver disabled, R
L
= 50 Ω9 15I
CC
Supply current mADriver disabled, receiver enabled, no load 1.8 5
Disabled 0.5 2
(1) All typical values are at 25°C and with a 3.3-V supply.
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DRIVER ELECTRICAL CHARACTERISTICS
RECEIVER ELECTRICAL CHARACTERISTICS
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
OD
| Differential output voltage magnitude 247 340 454R
L
= 50 Ω, See Figure 2
mVChange in differential output voltage magnitude between logic
and Figure 3∆|V
OD
| –50 50states
1.37V
OC(SS)
Steady-state common-mode output voltage 1.125 V5
Change in steady-state common-mode output voltage between See Figure 4∆V
OC(SS)
–50 50 mVlogic states
V
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mV
DE 0.5 10I
IH
High-level input current
(1)
V
IH
= 5 V µAD 2 20
DE –0.5 –10I
IL
Low-level input current
(1)
V
IL
= 0.8 V µAD 2 10
V
OA
or V
OB
= 0 V –10I
OS
Short-circuit output current
(1)
mAV
OD
= 0 V –10
C
I
Input capacitance 3 pF
(1) The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for thisparameter.
over recommended operating conditions (unless otherwise noted)
TYP
(PARAMETER TEST CONDITIONS MIN MAX UNIT1)
V
IT+
Positive-going differential input voltage threshold 50See Figure 6 mVV
IT–
Negative-going differential input voltage threshold –50
V
OH
High-level output voltage I
OH
= –8 mA 2.4 V
V
OL
Low-level output voltage I
OL
= 8 mA 0.4 V
V
I
= 0 V –2 –20I
I
Input current (A or B inputs)
(2)
µAV
I
= 2.4 V –1.2
I
I(OFF)
Power-off input current (A or B inputs) V
CC
= 0 V or 1.8 V 20 µA
I
IH
High-level input current (enables) V
IH
= 5 V 10 µA
I
IL
Low-level input current (enables) V
IL
= 0.8 V 10 µA
I
OZ
High-impedance output current
(2)
V
O
= 0 V or 5 V ±1 µA
(1) All typical values are at 25°C and with a 3.3-V supply.(2) The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for thisparameter.
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DRIVER SWITCHING CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
DRIVER
VOD
VOB
VOA
VOC
VI
IOA
IOB
IID
B
A
VOA VOB
2
Driver Enabled
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 0.5 1.7 2.7
nst
PHL
Propagation delay time, high-to-low-level output 0.5 1.7 2.7R
L
= 50 Ω, C
L
= 10 pF,t
sk(p)
Pulse skew (|t
pHL
– t
pLH
|) 0.2 nsSee Figure 3t
r
Differential output signal rise time 0.6 1
nst
f
Differential output signal fall time 0.6 1
t
sk(pp)
(2)
Part-to-part skew 1 ns
t
PZH
Propagation delay time, high-impedance-to-high-level output 8 12
t
PZL
Propagation delay time, high-impedance-to-low-level output 7 10See Figure 5 nst
PHZ
Propagation delay time, high-level-to-high-impedance output 3 10
t
PLZ
Propagation delay time, low-level-to-high-impedance output 4 10
(1) All typical values are at 25°C and with a 3.3 V supply.(2) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
over recommended operating conditions (unless otherwise noted)
TYP
(PARAMETER TEST CONDITIONS MIN MAX UNIT1)
t
PLH
Propagation delay time, low-to-high-level output 2.3 3.7 4.5
t
PHL
Propagation delay time, high-to-low-level output 2.3 3.7 4.5 ns
t
sk(p)
Pulse skew (|t
pHL
– t
pLH
|) C
L
= 10 pF, See Figure 7 0.4
t
r
Output signal rise time 0.8 1.5
nst
f
Output signal fall time 0.8 1.5
t
sk(pp)
(2)
Part-to-part skew 1 ns
t
PZH
Propagation delay time, high-level-to-high-impedance output 3 10
t
PZL
Propagation delay time, low-level-to-low-impedance output 3 10See Figure 8 nst
PHZ
Propagation delay time, high-impedance-to-high-level output 4 10
t
PLZ
Propagation delay time, low-impedance-to-high-level output 6 10
(1) All typical values are at 25°C and with a 3.3-V supply.(2) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Figure 2. Driver Voltage and Current Definitions
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2 V
1.4 V
0.8 V
100%
80%
20%
0%
0 V
VOD(H)
VOD(L)
Output
Input
tPHL
tPLH
tftr
_
+
VOD 50 Ω
3.75 kΩ
3.75 kΩ
0 ≤ Vtest ≤ 2.4 V
A
B
DA
Input
VOC
B
A
Input
CL = 10 pF
(2 Places)
3 V
0 V
VOC(PP) VOC(SS)
VO
25 Ω, ±1% (2 Places)
DD
Driver Enabled
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 3. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T. The measurement of V
OC(PP)
is made on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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1.2 V
B
A
0.8 V or 2 V
25 Ω, ±1% (2 Places)
CL = 10 pF
(2 Places)
DE VOA VOB
2 V
0.8 V
tPHZ
tPZH
tPLZ
tPZL
1.4 V
~1.4 V
1.2 V
1.25 V
1.2 V
~1 V
1.15 V
DE
VOA or VOB
VOB or VOA
RECEIVER
VIB
VID
VIA
VIC VO
A
B
R
VIA VIB
2
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
Figure 6. Receiver Voltage Definitions
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VIB
VID
VIA VO
CL
10 pF
VOH
VOL
1.4 V
VO
VIA
VIB
VID
1.4 V
1 V
0.4 V
0 V
–0.4 V
tPHL tPLH
tr
tf
0.4 V
2.4 V
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES RESULTING DIFFERENTIAL RESULTING COMMON-(V) INPUT VOLTAGE MODE INPUT VOLTAGE(mV) (V)
V
IA
V
IB
V
ID
V
IC
1.225 1.175 50 1.2
1.175 1.225 –50 1.2
2.41 2.36 50 2.385
2.36 2.41 –50 2.385
0.05 0 50 0.025
0 0.05 –50 0.025
1.5 0.9 600 1.2
0.9 1.5 –600 1.2
2.4 1.8 600 2.1
1.8 2.4 –600 2.1
0.6 0 600 0.3
0 0.6 –600 0.3
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 7. Timing Test Circuit and Waveforms
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VO
CL
10 pF +
–
500 Ω
1.2 V B
A
RE
Inputs VTEST
tPZL
VTEST
A
tPZL tPLZ
2.5 V
1.4 V
VOL +0.5 V VOL
2 V
1.4 V
0.8 V
2.5 V
1 V
RE
R
tPZH
VTEST
A
tPZH tPHZ
VOH
1.4 V
VOH –0.5 V
0 V
2 V
1.4 V
0.8 V
0 V
1.4 V
RE
R
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 5000 ± 10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 8. Enable/Disable Time Test Circuit and Waveforms
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TYPICAL CHARACTERISTICS
IOL − Low-Level Output Current − mA
1
080
2
VCC = 3.3 V
TA = 25°C
3
124
VOL− Low-Level Output Voltage − V
4
6 102
IOH − High-Level Output Current − mA
1
.5
0−4 −6
3
0
1.5
VCC = 3.3 V
TA = 25°C
2
2.5
−8−2
VOH− High-Level Output Voltage − V
3.5
0
IOH − High-Level Output Current − mA
4
0−80
2
−20
VOH
−40 −60
3
1
− High-Level Output Voltage − V
VCC = 3.3 V
TA = 25°C
0
IOL − Low-Level Output Current − mA
5
060
2
10
VOL
20 30
3
1
− Low-Level Output Votlage − V
40 50
4
VCC = 3.3 V
TA = 25°C
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
DRIVER DRIVERLOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 9. Figure 10.
RECEIVER RECEIVERHIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGEvs vsHIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 11. Figure 12.
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SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
TYPICAL CHARACTERISTICS (continued)
DRIVER DRIVERHIGH-TO-LOW LEVEL PROPAGATION DELAY TIME LOW-TO-HIGH LEVEL PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 13. Figure 14.
RECEIVER RECEIVERHIGH-TO-LOW LEVEL PROPAGATION DELAY TIME LOW-TO-HIGH LEVEL PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 15. Figure 16.
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APPLICATION INFORMATION
10
0.1 1M
Data Rate – Hz
1
100k 10M 100M
100
Transmission Distance – m
1000
5% Jitter
30% Jitter
24 AWG UTP 96 Ω (PVC Dielectric)
FAIL SAFE
Rt = 100 Ω (Typ)
300 kΩ300 kΩ
VCC
VIT ≈ 2.3 V
A
B
Y
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
The devices are generally used as building blocks for high-speed point-to-point data transmission. Grounddifferences are less than 1 V with a low common-mode output and balanced interface for very low noiseemissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECLspeeds without the power and dual supply requirements.
Figure 17. Data Transmission Distance Versus Rate
One of the most common problems with differential signaling applications is how the system responds when nodifferential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in thatits output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV andwithin its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles theopen-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could bewhen the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiverwill pull each line of the signal pair to near V
CC
through 300-k Ωresistors as shown in Figure 18 . The fail-safefeature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force theoutput to a high-level regardless of the differential input voltage.
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
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100 Ω
D
A
B
DE
RE
R
100 ΩA
B
D
DE
RE
R
Bidirectional Half-Duplex Applications
Multipoint Bus Applications
100 Ω
D/R
D/R
D/R
D/R
D/R
D/R
D/R
D/R
100 Ω
Note A: Keep drivers and receivers as close to the LVDS bus side connector as possible.
_
+_
+
SN65LVDM176
SLLS320D – DECEMBER 1998 – REVISED JULY 2000
APPLICATION INFORMATION (continued)
It is only under these conditions that the output of the receiver will be valid with less than a 50-mV differentialinput voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function aslong as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground thatcould defeat the pullup currents from the receiver and the fail-safe feature.
Figure 19. Bidirectional Half-Duplex and Multipoint Bus Applications
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN65LVDM176D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DM176
SN65LVDM176DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 M76
SN65LVDM176DGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 M76
SN65LVDM176DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 M76
SN65LVDM176DGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 M76
SN65LVDM176DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DM176
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
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l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDM176DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
SN65LVDM176DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDM176DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
SN65LVDM176DR SOIC D 8 2500 340.5 336.1 25.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65LVDM176D D SOIC 8 75 507 8 3940 4.32
SN65LVDM176D D SOIC 8 75 505.46 6.76 3810 4
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
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EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
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