Hoja de datos de FAN3223-25

© 2016 Semiconductor Components Industries, LLC Publication Order Number
December-2017, Rev. 2 FAN3224/D
FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
FAN3223 / FAN3224 / FAN3225
Dual 4-A High-Speed, Low-Side Gate Drivers
Features
Industry-Standard Pinouts
4.5-V to 18-V Operating Range
5-A Peak Sink/Source at VDD = 12 V
4.3-A Sink / 2.8-A Source at VOUT = 6 V
Choice of TTL or CMOS Input Thresholds
Three Versions of Dual Independent Drivers:
- Dual Inverting + Enable (FAN3223)
- Dual Non-Inverting + Enable (FAN3224)
- Dual-Inputs (FAN3225)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
12-ns / 9-ns Typical Rise/Fall Times (2.2-nF Load)
Under 20-ns Typical Propagation Delay Matched
w ithin 1 ns to the Other Channel
Double Current Capability by Paralleling Channels
8-Lead 3x3 mm MLP or 8-Lead SOIC Package
Rated fr om 40°C to +125°C Ambient
Automotive Qualified to AEC-Q100 (F085 Version)
Applications
Sw itch-Mode Pow er Supplies
High-Efficiency MOSFET Sw itching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
Automotive-Qualified Systems (F085 version)
Description
The FA N3 223-25 family of dual 4 A gate dr ivers is
designed to drive N-channel enhancement-mode
MOSFETs in low -side sw itching applications by
providing high peak current pulses dur ing the short
sw itching intervals. The driver is available w ith either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output LOW until the supply voltage is w ithin the
operating range. In addition, the drivers feature matched
internal propagation delays betw een A and B channels
for applications requiring dual gate drives w ith critical
timing, such as synchronous rectifiers. Th is also
enables connecting tw o drivers in parallel to effectively
double the current capability driving a single MOSFET.
The FAN322X drivers incorporate MillerDrive™
architecture for the final output stage. This bipolar-
MOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize sw itching loss, w hile providing rail-
to-rail voltage sw ing and reverse current capability.
The FAN3223 offers two inverting drivers and the
FA N3224 offers tw o non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FA N3225, each channel has dual
inputs of opposite polarity, w hich allow s configuration as
non-inverting or inverting w ith an optional enable
function using the second input. If one or both inputs are
left unconnected, internal resistors bias the inputs such
that the output is pulled LOW to hold the pow er
MOSFET OFF.
1
ENA
INA
GND
ENB
VDD
INB
OUTA
OUTB
2
3
4
8
6
5
A7
B
1ENB
VDD
OUTA
OUTB
2
3
4
8
6
5
7
A
B
ENA
INA
GND
INB
1INA+
VDD
OUTA
OUTB
2
3
4
8
6
5
7
INB+
GND
INB
-
INA
-
+
-A
+
-B
FAN3223 FAN3224 FAN3225
Figure 1. Pin Configurations
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Ordering Information
Part Number Logic Input
Threshold Package Packing
Method Quantity
per Reel
FAN3223CMPX
Dual Inverting
Channels + Dual
Enable
CMOS
3x3 mm MLP-8
Tape & Reel
3,000
FAN3223CMX
SOIC-8
Tape & Reel
2,500
FAN3223CMX-F085
(1)
SOIC-8
Tape & Reel
2,500
FAN3223TMPX
TTL
3x3 mm MLP-8
Tape & Reel
3,000
FAN3223TMX
SOIC-8
Tape & Reel
2,500
FAN3223TMX-F08 5(1)
SOIC-8
Tape & Reel
2,500
FAN3224CMPX
Dual Non-Inverting
Channels + Dual
Enable
CMOS
3x3 mm MLP-8
Tape & Reel
3,000
FAN3224CMX
SOIC-8
Tape & Reel
2,500
FAN3224CMX-F085
(1)
SOIC-8
Tape & Reel
2,500
FAN3224TMPX
TTL
3x3 mm MLP-8
Tape & Reel
3,000
FAN3224TMX
SOIC-8
Tape & Reel
2,500
FAN3224TMX-F08 5
(1)
SOIC-8
Tape & Reel
2,500
FAN3224TUMX-F085(2)
SOIC-8
Tape & Reel
2,500
FAN3225CMPX
Dual Channels of Tw o-
Input / One-Output
Drivers
CMOS
3x3 mm MLP-8
Tape & Reel
3,000
FAN3225CMX
SOIC-8
Tape & Reel
2,500
FAN3225CMX-F085(1)
SOIC-8
Tape & Reel
2,500
FAN3225TMPX
TTL
3x3 mm MLP-8
Tape & Reel
3,000
FAN3225TMX
SOIC-8
Tape & Reel
2,500
FAN3225TMX-F085(1)
SOIC-8
Tape & Reel
2,500
Note s:
1. Qualified to AEC-Q100.
2. Modified UVLO thresholds.
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Package Outlines
18
7
2
6
3
45
2
3
8
6
1
4
7
5
Figure 2. 3x3 mm MLP-8 (Top View) Figure 3. SOIC-8 (Top View)
Thermal Characteristics(3)
Package
Θ
JL
(4)
Θ
JT
(5)
Θ
JA
(6)
Ψ
JB
(7)
Ψ
JT
(8)
Unit
8-Lead 3x3 mm Molded Leadless Package (MLP)
1.2
64
42
2.8
0.7
°C/W
8-Pin Small Outline Integrated Circuit (SOIC)
38 29 87 41 2.3 °C/W
Notes:
3. Estimates derived from thermal simulation; actual values depend on the application.
4. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
thermal pad) that are typically soldered to a PCB.
5. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
6. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airfl ow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
7. Psi _JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 6. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
8. Psi _JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 6.
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
1
ENA
INA
GND
ENB
VDD
INB
OUTA
OUTB
2
3
4
8
6
5
A
7
B
1
ENB
VDD
OUTA
OUTB
2
3
4
8
6
5
7
A
B
ENA
INA
GND
INB
1
INA+
VDD
OUTA
OUTB
2
3
4
8
6
5
7
INB+
GND
INB
-
INA
-
+
-A
+
-B
FAN3223 FAN3224 FAN3225
Figure 4. Pin Assignments (Repeated)
Pin Definitions
Name Pin Description
ENA Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENB Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
GND Ground. Common ground reference for input and output circuits.
INA Input to Channel A.
INA + Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA - Inverting Input to Channel A. Connect to GND to enable output.
INB Input to Channel B.
INB+ Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB- Inverting Input to Channel B. Connect to GND to enable output.
OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTB Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is
above UVLO threshold.
P1 Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
VDD Supply Voltage. Provides pow er to the IC.
Output Logic
FAN3223 (x=A or B)
FAN3224 (x=A or B)
FAN3225 (x=A or B)
ENx INx
OUTx
ENx INx OUTx INx+ INx OUTx
0
0
0
0
0(9)
0
0(9)
0
0
0
1(9)
0
0
1
0
0(9)
1(9)
0
1(9)
0
1
1(9)
0(9)
0
1
0
1
1(9)
1(9)
0
1(9)
1
1
1
1(9)
0
Note :
9. Default input signal if no external connection is made.
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Block Diagrams
6
VDD
7
V
DD_OK
5
INA
2
100k
ENA
1
GND
3
V
DD
UVLO
100k
8
V
DD
ENB
INB
4
OUTA
OUTB
100k
100k
100k
100k
V
DD
V
DD
Figure 5. FAN3223 Block Diagram
6VDD
7OUTA
VDD_OK
5
INA 2
100k
ENA 1
GND 3
V
DD
UVLO
100k
8
V
DD
ENB
INB 4
OUTB
100k
100k
100k
100k
Figure 6. FAN3224 Block Diagram
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Block Diagrams
6
VDD
7
OUTA
V
DD_OK
5
OUTB
INA-
1
INA+
8
GND
2
V
DD
UVLO
3
INB-
INB+
4
100k
100k
100k
100k
V
DD
100k
100k
Figure 7. FAN3225 Block Diagram
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter Min. Max. Unit
VDD VDD to PGND -0.3 20.0 V
VEN ENA and ENB to GND GND - 0.3 VDD + 0.3 V
VIN INA , INA+, INA , INB, INB+ and INBto GND GND - 0.3 VDD + 0.3 V
VOUT OUTA and OUTB to GND DC GND - 0.3 VDD + 0.3 V
TL Lead Soldering Temperature (10 Seconds) +260 ºC
TJ Junction Temperature -55 +150 ºC
TSTG Storage Temperature -65 +150 ºC
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VDD Supply Voltage Range 4.5 18.0 V
VDD Supply Voltage Range (FAN3224TU only) 9.5 18.0 V
VEN Enable Voltage ENA and ENB 0 VDD V
VIN Input Voltage INA , INA +, INA , INB, INB+ and INB 0 VDD V
VOUT OUTA and OUTB to GND Repetitive Pulse < 200 ns -2.0 VDD + 0.3 V
TA Operating Ambient Temperature -40 +125 ºC
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherw ise noted, VDD=12 V, TJ=-
40°C to +12C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter Conditions Min. Typ. Max. Unit
Supply
VDD Operating Range 4.5 18.0 V
IDD Supply Current, Inputs / EN Not
Connected
All except FAN3225C 0.70 0.95 mA
FAN3225C
(10)
0.21 0.35 mA
VON Turn-On Voltage INA=ENA =VDD, INB=ENB=0 V 3.5 3.9 4.3 V
VOFF Turn-Off Voltage INA =ENA =VDD, INB=ENB=0 V 3.3 3.7 4.1 V
FAN322xTMX-F085, FAN322xCMX-F085 (Automotive-Qualified Versions)
VDD Operating Range 4.5 18.0 V
IDD Supply Current, Inputs / EN Not
Connected(15)
All Except FAN3225C 0.70 1.20 mA
FAN3225C
(10)
0.21 0.35 mA
VON
Turn-On Voltage(15)
INA=ENA=VDD, INB=ENB=0 V 3.4 3.9 4.5 V
VOFF Turn-Off Voltage
(15)
INA=ENA=VDD, INB=ENB=0 V 3.2 3.7 4.3 V
FAN3224TUM X-F085 (Modified UVLO Version)
VDD Operating Range 9.5 18.0 V
IDD
Supply Current, Inputs / EN Not
Connected(15) 0.70 1.20 mA
VON Turn-On Voltage
(15)
INA=ENA=VDD, INB=ENB=0 V 8.0 9.1 10.2 V
VOFF Turn-Off Voltage
(15)
INA=ENA=VDD, INB=ENB=0 V 7.0 8.2 9.3 V
Inputs (FAN322xT)
(11)
VINL_T INx Logic LOW Threshold 0.8 1.2 V
VINH_T INx Logic HIGH Threshold 1.6 2.0 V
VHYS_T TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V
I
IN+
Non-Inverting Input Current
IN from 0 to V
DD
-1
175
µA
I
IN-
Inverting Input Current
IN from 0 to V
DD
-175
1
µA
FAN322xTMX-F085, FAN3224TUMX-F085 (Automotive-Qualified Versions)
V
INL_T
INx Logic LOW Threshold
0.8
1.2
V
V
INH_T
INx Logic HIGH Threshold
1.6
2.0
V
V
HYS_T
TTL Logic Hysteresis Voltage
0.1
0.4
0.9
V
I
INx_T
Non-inverting Input Current(15)
IN=0 V
-1.5
1.5
µA
I
INx_T
Non-inverting Input Current(15)
IN=V
DD
80
120
175
µA
I
INx_T
Inverting Input Current(15)
IN=0 V
-175
-120
-90
µA
I
INx_T
Inverting Input Current(15)
IN=V
DD
-1.5
1.5
µA
Inputs (FAN322xC)(11)
VINL_C INx Logic Low Threshold 30 38 %VDD
VINH_C INx Logic High Threshold 55 70 %VDD
VHYS_C CMOS Logic Hysteresis Voltage 17 %VDD
I
IN+
Non-Inverting Input Current
IN from 0 to V
DD
-1
175
µA
Sinkmg ing
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherw ise noted, VDD=12 V, TJ=-
40°C to +12C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter Conditions Min. Typ. Max. Unit
I
IN-
Inverting Input Current
IN f rom 0 to V
DD
-175
1
µA
FAN322xCMX-F085 (Automotive-Qualified Versions)
V
INL_C
INx Logic Low Threshold
30
38
%V
DD
V
INH_C
INx Logic High Threshold
55
70
%V
DD
V
HYS_C
CMOS Logic Hysteresis Voltage
17
%V
DD
I
INx_T
Non-Inverting Input Current(15)
IN=0 V
-1.5
1.5
µA
I
INx_T
Non-Inverting Input Current(15)
IN=V
DD
90
120
175
µA
I
INx_T
Inverting Input Current(15)
IN=0 V
-175
-120
-90
µA
I
INx_T
Inverting Input Current(15)
IN=V
DD
-1.5
1.5
µA
ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)
V
ENL
Enable Logic Low Threshold
EN f rom 5 V to 0 V
0.8
1.2
V
V
ENH
Enable Logic High Threshold
EN f rom 0 V to 5 V
1.6
2.0
V
V
HYS_T
TTL Logic Hysteresis Voltage(12)
0.4
V
R
PU
Enable Pull-Up Resistance(12)
100
kΩ
tD3
EN to Output Propagation Delay(13)
0 V to 5 V EN, 1 V/ns Slew
Rate 9 17 26 ns
tD4
5 V to 0 V EN, 1 V/ns Slew
Rate 11 18 28 ns
FAN3223C-TMX-F085, FAN3224C-TMX-F085, FAN3224TUMX-F085 (Automotive-Qualified Versions)
V
ENL
Enable Logic Low Threshold
EN f rom 5 V to 0 V
0.8
1.2
V
V
ENH
Enable Logic High Threshold
EN f rom 0 V to 5 V
1.6
2.0
V
V
HYS_T
TTL Logic Hysteresis Voltage(12)
0.4
V
R
PU
Enable Pull-Up Resistance(12)
100
kΩ
tD3
EN to Output Propagation Delay(13,15)
0 V to 5V EN, 1 V/ns Slew
Rate 6 17 34 ns
tD4 5 V to 0V EN, 1 V/ns Slew
Rate 6 19 31 ns
Outputs
ISINK OUT Current, Mid-Voltage, Sinking(12) OUT at V DD/2, CLOAD=0.22 µF,
f=1 kHz 4.3 A
ISOURCE
OUT Current, Mid-Voltage,
Sourcing(12)
OUT at V
DD
/2, C
LOAD
=0.22 µF,
f=1 kHz -2.8 A
I
PK_SINK
OUT Current, Peak, Sinking(12)
C
LOAD
=0.22 µF, f=1 kHz
5
A
I
PK_SOURCE
OUT Current, Peak, Sourcing(12)
C
LOAD
=0.22 µF, f=1 kHz
-5
A
t
RISE
Output Rise Time(14)
C
LOAD
=2200 pF
12
20
ns
t
FALL
Output Fall Time(14)
C
LOAD
=2200 pF
9
17
ns
tDEL.MATCH
Propagation Matching Betw een
Channels
INA=INB, OUTA and OUTB at
50% Point 2 4 ns
I
RVS
Output Reverse Current Withstand(12)
500
mA
tD1, tD2
Output Propagation Delay, CMOS
Inputs(14) 0 12 VIN, 1 V/ns Slew Rate 10 18 29 ns
tD1, tD2 Output Propagation Delay, TTL
Inputs(14) 0 5 VIN, 1 V/ns Slew Rate 9 17 29 ns
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherw ise noted, VDD=12 V, TJ=-
40°C to +12C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter Conditions Min. Typ. Max. Unit
All Except for FAN3225C-TMX-F085 (Automotive-Qualified Versions)
t
RISE
Output Rise Time(14)
C
LOAD
=2200 pF
12
20
ns
t
FALL
Output Fall Time(14)
C
LOAD
=2200 pF
9
17
ns
tDEL.MATCH
Propagation Matching Betw een
Channels
INA=INB, OUTA and OUTB at
50% Point 2 4 ns
I
RVS
Output Reverse Current Withstand(12)
500
mA
tD1, tD2
Output Propagation Delay, CMOS
Inputs(14,15) 0 12 VIN, 1 V/ns Slew Rate 9 18 34 ns
tD1, tD2 Output Propagation Delay, TTL
Inputs(14,15) 0 5 VIN, 1 V/ns Slew Rate 6 16 30 ns
VOH High Level Output Voltage
(15)
VOH =VDDVOUT, IOUT=1 mA 15 35 mV
V
OL
Low Level Output Voltage(15)
I
OUT
= 1 mA
10
25
mV
FAN3225C_TMX_F085 (Automotive-Qualificed Versions)
t
RISE
Output Rise Time(14)
C
LOAD
=2200 pF
12
28
ns
t
FALL
Output Fall Time(14)
C
LOAD
=2200 pF
9
26
ns
VOH High Level Output Voltage
(15)
VOH =VDDVOUT, IOUT=1 mA 15 37 mV
V
OL
Low Level Output Voltage(15)
I
OUT
= 1 mA
10
25
mV
Notes:
10. Low er supply current due to inactive TTL circuitry.
11. EN inputs have TTL thresholds; refer to the ENABLE section.
12. Not tested in production.
13. See Timing Diagrams of Figure 10 and Figure 11.
14. See Timing Diagrams of Figure 8 and Figure 9.
15. Applies only to _F085 versions.
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Timing Diagrams
Input
tD1 tD2
tRISE tFALL
VINL
VINH
90%
10%
Output
90%
10%
Output
tD1 tD2
tFALL tRISE
VINL
VINH
Input
Figure 8. Non-Inverting (EN HIGH or Floating) Figure 9. Inverting (EN HIGH or Floating)
90%
10%
Output
Enable
t
D3
t
D4
V
ENL
V
ENH
Input
HIGH
LOW
t
RISE
t
FALL
90%
10%
Output
Enable
tD3 tD4
VENL
VENH
Input
HIGH
LOW
tRISE tFALL
Figure 10. Non-Inverting (IN HIGH) Figure 11. Inverting (IN LOW)
Inn (MA) 08 05 DA 02 00 15 FAN3223c, 24c TTL Input 0 B 2 0 6 E 3 Inputs and Enables Floating, Inputs and Enables — 0'4 Outputs Low Floating, Outputs Low 0.2 0.0 551012141515 4681012141618 Vun - Supply Voltage W) van » Supply Voltage (V) 0 5 FAN-32250 O 4 3 03 5 n .9 02 All Inputs Floating, 0 1 Outputs Law 0 O A 6 8 10 12 14 16 18 Van - Supply Voltage (V) 1‘“! Both h | 'l h‘ 15 Both h | 'l h‘ c annes swl c mg, a annesswl c mg, CMOS Input halve for one channel TTL Input halve for one channel VDD=15V Von: 15V a vDD : 12v VDD : 8V vDD = 4.5V 200 40!] 600 SWItching Frequency (kHz) 800 1000 0 200 400 600 800 1000 Switching Frequency (kHz)
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 12. IDD (Static) vs. Supply Voltage(16) Figure 13. IDD (Static) vs. Supply Voltage(16)
Figure 14. I
DD
(Static) vs. Supply Voltage(16)
Figure 15. IDD (No-Load) vs. Frequency Figure 16. IDD (No-Load) vs. Frequency
Inn (MA) Inn (mA) Both channels swmchmg, Each channe‘s switching CMOS "1pm halve [or one channel TTL mp“t halve [or one channel 80 Vun=15V \ BO Vnu=15V fix _ VDD = 12V so vDD - 12V 21‘ 60 VDD = 8V 5 VDD = 3v n 40 VDD:45V 3 40 Vun=45V 20 20 0 0 0 200 400 600 800 1000 0 200 400 500 800 1000 Switching Frequency (kHz) Swilchmg Frequency (kHz) 1.0 1.0 FAN3223C,24C TTL Input 0.3 0 8 0.6 E 0 6 o 4 E 0_4 Inputs and Enables '"P”‘_5 and Enables Floafing, Outputs Low 0 2 Floating. Outputs Low 0.2 0 O 0.0 .50 .25 o 25 50 75 100 125 750 725 n 25 50 75 100 125 Temperature (”6) Temperature ('C) 0 5 FAN3225C 0 4 a 0.3 E. n —= 0.2 / All Inputs Floating, 0'1 Outnuts Low 0 O 750 725 0 50 75 100 125 Temperatu re ("(2)
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 17. IDD (2.2 nF Load) vs. Frequency Figure 18. IDD (2.2 nF Load) vs. Frequency
Figure 19. IDD (Static) vs. Temperature(16) Figure 20. IDD (Static) vs. Temperature(16)
Figure 21. IDD (Static) vs. Temperature(16)
12 1.8 CMOSInput 1‘7 TTLInput V S‘ 10 9 m I T; 1.6 'u 8 ‘0 B V“ 3 15 .c .c g 5 § 1.4 :5 E 13 5 4 ‘5 LEE vIL g 1.2 2 1.1 0 1.0 0 4 8 12 15 20 0 4 8 12 16 20 Supply Voltage (V) Supply Voltage (V) 100% ,3 90% CMOSlnput f 30% a 5 70% V... g 60% \ o g 50/0 3 40% r“ ‘E 30% I; 20% W n. 5 10% 0% 0 4 a 12 16 20 Supply Voltage (V) 7.0 18 65 CMOSIHPUt 17 TTLlnput a km“ a 16 \ € 60 € 3 ' 3 15 Vm ; I g 5.5 E 14 .c .: t 50 t 1 3 W a ' VrL g — E g— : 1 2 ' 4.5 _ 1 1 4 D 1 0 750 725 0 25 50 75 100 125 .50 .25 g 25 50 75 100 125 Temperature (‘6) Temperature (‘6)
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 22. Input Thresholds vs. Supply Voltage Figure 23. Input Thresholds vs. Supply Voltage
Figure 24. Input Threshold % vs. Supply Voltage
Figure 25. Input Thresholds vs. Temperature Figure 26. Input Thresholds vs. Temperature
50 50 48 CMOS Input 43 TTL Input S 46 g 4.6 g 44 g 4.4 f, 42 g 42 E 40 Device 0N g 40 Devlce ON ._ .c \_ o 38 _ ._ 35 5' 36 —, g 3-5 ‘_ , :z 34 Devlce OFF 3 34 Dewce OFF 32 3.2 30 3.0 —50 —25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Tempelature ("6) Temperature ('C) FAN3224TU OnIy Device 0N DovicaOFF >50 -25 0 25 50 75 100 125 Temperature (“C ] 90 80 A 30 CMOS Inverfing Input A 70 TTL Inverting Input 2 E w 70 v 60 I; 60 f INfaIlta OUTrIse ; IN IaII to OUT use i / g 50 f 50 IN use In OUT Ian 40 ‘ 7 IN rIse to OUT IaII : : .9 40 ‘9 “ fi 30 §' 30 s: E 20 g 20 n 10 A 10 D 0 A 6 5 10 12 14 16 18 4 6 8 1D 12 14 16 18 VW - SupplyVoltage 1V) Vnn ‘ SUPPIY Voltage (V)
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 27. UVLO Thresholds vs. Temperature Figure 28. UVLO Threshold vs. Temperature
Figure 29. UVLO Thresholds vs. Temperature
Figure 30. Propagation Delay vs. Supply
Voltage
Figure 31. Propagation Delay vs. Supply
Voltage
Pmpagation Delays (ns) Propagation Delays (ns) Propagation Delays (ns) 7o CMOS Non-inverting Input 7‘ so TTL Non-Inverting Input : 60 $ 50 50 — IN or EN lall to OUT falI lN IaHtDOLJTfaII 3 40 /7 40 = 7 'N "5““ OUT "SE S 30 ‘ W or EN Ilse lo OUT rise 30 X m . g 20 \< 20="" e="" 10="" n.="" 10="" d="" 0="" 4="" 6="" 8="" 10="" 12="" 14="" 16="" 18="" 4="" 6="" 8="" 10="" 12="" 14="" 16="" 18="" v.,.,="" -="" supply="" voltage="" (v)="" van="" .="" supply="" vultage="" (v)="" 30="" 30="" cmos="" invertlng="" input="" 3;="" ttl="" lnverting="" input="" 25="" 5="" 25="" m="" 20="" in="" rise="" lo="" out="" fall="" 5'="" in="" rise="" to="" out="" (all="" 3="" 20="" :="" 15="" 8="" 15="" a:="" in="" fan="" to="" out="" me="" 3‘="" in="" fall="" to="" out="" rise="" 10="" 3="" 10="" n.="" 5="" 5="" -50="" -25="" o="" 25="" 50="" 75="" 100="" 125="" 150="" .50="" .25="" u="" 25="" 50="" 75="" 100="" 125="" 150="" temperature="" ("(2)="" temperature="" ca)="" 30="" 30="" cmos="" non-inverting="" input="" ,3="" ttl="" non-inverting="" input="" 25="" 5="" 25="" in="" fall="" io="" out="" fall="" %="" in="" or="" en="" iall="" to="" out="" la”="" 20="" g="" 20="" 5="" 15="" .="" .="" fi="" 15="" in="" "5910="" out="" ”se="" 3="" in="" or="" en="" rise="" to="" out="" rise="" e="" 10="" 9="" 10="" n.="" 5="" 5="" 50="" ,25="" d="" 25="" 50="" 75="" 100="" 125="" 150="" -50="" —25="" 0="" 25="" 50="" 75="" 100="" 125="" 150="" temperature="" ("0)="" temperature="" (“c)="">
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 32. Propagation Delay vs. Supply
Voltage
Figure 33. Propagation Delay vs. Supply
Voltage
Figure 34. Propagation Delays vs. Temperature
Figure 35. Propagation Delays vs. Temperature
200 175 R 150 m 5.125 a; g 100 l— 75 so 25 Fall 250 1 1 q : 33m: CMOS or TTL Input C1 :3“? CM05 or TTL Input 200 ’07 o : 22nF 5 cl :22nF w 150 E i: . m 100 C1 : l3 GHF cl:133nF g l \ q=mp¥__ 50 WWF‘ \— qnzw¥ 5922"; ‘ h 0 l 5 10 15 20 0 5 10 15 Supply Voltage (V) Supply Voltage (V) 20 R13 CMDS or TTL Input g 15 Rise Time 3 14 / E i: 12 / i 10 Fall Tune LL .5 8 E 5 fl 4 r:L = 2.2nF I! 2 0 750 725 0 25 50 75 100 Temperatu re (“0) 125
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 36. Propagation Delays vs. Temperature
Figure 37. Propagation Delays vs. Temperature
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 38. Fall Time vs. Supply Voltage Figure 39. Rise Time vs. Supply Voltage
Figure 40. Rise and Fall Times vs. Temperature
20115 / div v‘N (2v « aw) t (‘I'I'L \npul)
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 41. Rise/Fall Waveforms with 2.2 nF
Load Figure 42. Rise/Fall Waveforms with 10 nF
Load
w I V 3 low (5A/ div) Vour (5v / div) ‘ ViN [5w div) (m inpui) 0mm = 0.22;”: c= 200ns / div ___.._. k‘ ' low (2A / div) ' VOUT (5v I div) 1 ,.—...—..——___.__ ‘ ViN(5V/div) = .........J (“me“) Cm 022% i : ZDOHS /div loin (2A! div) ’ Vow (5V [div] VIN (5V / div) (‘I'rL inpui) Dim = D 22m: W— t=200 nsldiv ‘I but (2A/ div) — m V... (5w div) ('I'FL Input) Cm“) = 0,22“: m...— t= 200 ms! diV
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherw ise noted.
Figure 43. Quasi-Static Source Current
with VDD=12 V(17) Figure 44. Quasi-Static Sink Current with
VDD=12 V(17)
Figure 45. Quasi-Static Source Current
with VDD=8 V(17) Figure 46. Quasi-Static Sink Current with
VDD=8 V(17)
Notes:
16. For any inverting inputs pulled low , non-inverting inputs pulled high, or outputs driven high, static IDD increases by
the current flow ing through the corresponding pull-up/dow n resistor show n in the block diagram.
17. The initial spike in each current w aveform is a measurement artifact caused by the stray inductance of the
current-measurement loop.
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Test Circuit
470 µF
Al. El.
VDD
V
OUT
1 µF
ceramic
4.7 µF
ceramic
C
LOAD
0.22 µF
I
OUT
IN
1 kHz
Current Probe
LECROY AP015
Figure 47. Quasi-Static IOUT / VOUT Test Circuit
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21
FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Applications Information
Input Thresholds
Each member of the FA N322x driver family consists of
tw o identical channels that may be used independently
at rated current or connected in parallel to double the
individual current capacity. In the FA N3223 and
FA N3224, channels A and B can be enabled or disabled
independently using ENA or ENB, respectively. Th e EN
pin has TTL thresholds for parts w ith either CMOS or
TTL input thresholds. If ENA and ENB are not
connected, an internal pull-up resistor enables the driver
channels by default. ENA and ENB have TTL thresholds
in parts w ith either TTL or CMOS INx threshold. If the
channel A and channel B inputs and outputs are
connected in parallel to increase the driver current
capacity, ENA and ENB should be connected and
driven together.
The FA N322x family offers versions in either TTL or
CMOS input thresholds. In the FA N322x T, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the VDD voltage, and there is a
hysteresis voltage of approximately 0.4 V. These levels
permit the inputs to be driven from a range of input logic
signal levels for w hich a voltage over 2 V is considered
logic HIGH. The driving signal for the TTL inputs should
have fast rising and falling edges w ith a slew rate of
6 V/µs or faster, so a rise time from 0 to 3.3 V should be
550 ns or less. With reduced slew rate, circuit noise
could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the driver input, causing
erratic operation.
In the FA N322x C, the logic input thresholds are
dependent on the VDD level and, w ith VDD of 12V, the
logic rising edge threshold is approximately 55% of VDD
and the input falling edge threshold is approximately
38% of VDD. The CMOS input configuration offers a
hysteresis voltage of approximately 17% of VDD. The
CMOS inputs can be used w ith relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
w indow . This allow s setting precise timing intervals by
fitting an R-C c ircuit betw een the controlling signal and
the IN pin of the dr iver. The s low rising edge at the IN
pin of the driver introduces a delay betw een the
controlling signal and the OUT pin of the driver.
Static Supply Current
In the IDD (static) typical performance characteristics
(Figure 12 - Figure 14 and Figure 19 - Figure 21), the
curve is produced w ith all inputs/enables floating (OUT
is low ) and indicates the low est static IDD current for the
tested configuration. For other states, additional current
flow s through the 100 k resistors on the inputs and
outputs show n in the block diagram of each part (see
Figure 5 - Figure 7). In these cases, the actual static IDD
current is the value obtained from the curves plus this
additional current.
MillerDrive™ Gate Drive Technology
FA N322x gate drivers incorporate the MillerDrive™
architecture show n in Figure 48. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a w ide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT sw ings betw een 1/3 to 2/3
VDD and the MOS devices pull the output to the HIGH or
LOW rail.
The purpose of the MillerDrive™ architecture is to
speed up sw itching by providing high current during the
Miller plateau region w hen the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications that have zero voltage sw itching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast sw itching even
though the Miller plateau is not present. This situation
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is sw itched ON.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slow er rise or fall time
at the MOSFET gate is needed.
Input
stage
V
DD
V
OUT
Figure 48. MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN322x startup logic is optimized to drive ground-
referenced N-channel MOSFETs w ith an under-voltage
lockout (UVLO) function to ensure that the IC starts up
in an orderly fashion. When VDD is rising, yet below the
UVL O level, this circuit holds the output LOW,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.2 V before the
part shuts dow n. This hysteresis helps prevent chatter
when low VDD supply voltages have noise from the
pow er sw itching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver w ould turn the P-channel
MOSFET ON w ith VDD below the UVLO level.
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
VDD Bypass Capacitor Guidelines
To enable this IC to turn a dev ice ON quickly, a local
high-frequency bypass capacitor, CBYP, w ith low ESR
and ESL should be connected betw een the V DD and
GND pins w ith minimal trace length. This capac itor is
in addition to the bulk electrolytic capacitance of 10 µF
to 47 µF commonly found on the driver and controller
bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to 5%. This
is often achieved w ith a value 20 times the equivalent
load capacitance CEQV, defined here as QGATE/VDD.
Ceramic capacitors of 0.1 µF to 1 µF or larger are
common choices, as are dielectrics, such as X5R and
X7 R w ith good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into tw o capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10 nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
sw itching simultaneously, the combined peak current
sourced from the CBYP w ould be tw ice as large as w hen
a single channel is sw itching.
Layout and Connection Guidelines
The FA N32 23-25 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays,
and pow erful output stages capable of delivering current
peaks over 4 A to facilitate voltage transition times from
under 10 ns to over 150 ns. The follow ing layout and
connection guidelines are strongly recommended:
Keep high-current output and pow er ground paths
separate logic and enable input signals and signal
ground paths. This is espec ially critical w hen
dealing w ith TTL-level logic thresholds at driver
inputs and enable pins.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed sw itching, w hile reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
If the inputs to a channel are not externally
connected, the internal 100 k resistors indicated
on bloc k diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to V DD or GND using short
traces to prevent noise from causing spurious
output sw itching.
Many high-speed pow er circuits can be susceptible
to noise injected from their ow n output or other
external sources, possibly caus ing output re-
triggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts w ith long input, enable, or output leads.
For best results, make connections to all pins as
short and direct as possible.
The FAN322x is compatible w ith many other
industry-standard drivers. In single input parts w ith
enable pins, there is an internal 100 k resistor tied
to VDD to enable the driver by default; this should
be considered in the PCB layout.
The turn-on and turn-off current paths should be
minimized, as discussed in the follow ing section.
Figure 49 show s the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET ON. The current is supplied from the local
bypass capacitor, CBYP, and flow s through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized CBYP acts
to contain the high peak current pulses w ithin this driver-
MOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
PWM
V
DS
V
DD
C
BYP
FAN322x
Figure 49. Current Path for MOSFET Turn-On
Figure 50 show s the current path w hen the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a s mall
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
PWM
V
DS
V
DD
C
BYP
FAN322x
Figure 50. Current Path for MOSFET Turn-Off
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Truth Table of Logic Operation
The FAN3225 truth table indicates the operational states
using the dual-input configuration. In a non-inverting
driver configuration, the IN- pin should be a logic LOW
signal. If the IN- pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN+ pin.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
In the non-inverting driver configuration in Figure 51, the
IN- pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
HIGH to disable the dr iver and the output remains LOW,
regardless of the state of the IN+ pin.
VDD
GND
IN-
IN+
OUT
PWM
FAN3225
Figure 51. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application in Figure 52, the IN+
pin is tied HIGH. Pulling the IN+ pin to GND forces the
output LOW, regardless of the state of the IN- pin.
VDD
GND
IN-
IN+
OUT
PWM
FAN3225
Figure 52. Dual-Input Driver Enabled,
Inverting Configuration
Operational Waveforms
At pow er-up, the driver output remains LOW until the
VDD voltage reaches the turn-on threshold. The
magnitude of the OUT pulses rises w ith VDD until
steady-state VDD is reached. The non-inverting
operation illustrated in Figure 53 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase w ith the input.
VDD
IN+
IN-
OUT
Turn-on threshold
Figure 53. Non-Inverting Startup Waveforms
For the inverting configuration of Figure 52, startup
waveforms are show n in Figure 54. With IN+ tied to
VDD and the input signal applied to IN, the OUT
pulses are inverted w ith respect to the input. At pow er-
up, the inverted output remains LOW until the VDD
voltage reaches the turn-on threshold, then it follows the
input w ith inverted phase.
VDD
IN+
(VDD)
IN-
OUT
Turn-on threshold
Figure 54. Inverting Startup Waveforms
To curve a numerrcar exarmle, assume tor a 12v vDD (Var/a5) system, Ihe synchmnuus rechher swmches er Figure 55 have a (ma gate charge of so nC at Ves : 7 v. Thererere. Iwu devrces rh pavaHel w ould have 120 he gate charge. At a swnehih
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Thermal Guidelines
Gate drivers used to sw itch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
pow er. It is important to determine the driver pow er
dissipation and the resulting junction temperature in the
application to ensure that the part is operating w ithin
acceptable temperature limits.
The total pow er dissipation in a gate driver is the sum of
tw o components, PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC (1)
PGATE (Gate Driving Loss): The most significant pow er
loss results from supplying gate current (charge per
unit time) to sw itch the load MOSFET on and off at
the sw itching frequency. The pow er dissipation that
results from driving a MOSFET at a specified gate-
source voltage, VGS, w ith gate charge, QG, at
sw itching frequency, fSW, is determined by:
PGATE = QG • VGS • fSW • n (2)
w here n is the number of driver channels in use (1 or 2).
PDYNAMIC (Dynamic Pre-Drive / Shoot-through
Current): A pow er loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-dow n resistors. The internal
current consumption (IDYNAMIC) can be estimated using
the graphs in Figure 15 and Figure 16 of the Typical
Performance Characteristics to determine the current
IDYNAMIC draw n from VDD under actual operating
conditions:
PDYNAMIC = IDYNAMIC • VDD • n (3)
where n is the number of driver ICs in use. Note that n is
usually be one IC even if the IC has tw o channels,
unless two or more.driver ICs are in parallel to driv e a
large load.
Once the pow er dissipated in the driver is determined,
the driver junction rise w ith respect to circuit board can
be evaluated using the follow ing thermal equation,
assuming
ψ
JB w as determined for a similar thermal
design (heat sinking and air flow ):
TJ = PTOTAL
ψ
JB + TB (4)
w here:
TJ = driver junction temperature;
ψ
JB = (psi) thermal characterization parameter
relating temperature rise to total pow er
dissipation; and
TB = board temperature in location as defined in
the Thermal Characteristics table.
To give a numerical example, assume for a 12 V VDD
(VBIAS) sy stem, the synchronous rectifier sw itches of
Figure 55 have a total gate charge of 60 n C at
VGS = 7 V. Therefore, tw o devices in parallel w ould have
120 nC gate charge. At a sw itching frequency of
300 kHz, the total pow er dissipation is:
PGATE = 120 nC 7 V 300 kHz • 2 = 0.504 W (5)
PDYNAMIC = 3.0 mA 12 V 1 = 0.036 W (6)
PTOTAL = 0.540 W (7)
The SOIC-8 has a junction-to-board ther mal
characterization parameter of
ψ
JB = 42°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along w ith airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; w ith 80%
derating, TJ w ould be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
TB,MAX = TJ - PTOTAL
ψ
JB (8)
TB,MAX = 120°C 0.54 W 42°C/W = 97°C (9)
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Typical Application Diagrams
V
IN
PWM
1
2
36
7
8
45
Timing/
Isolation
V
OUT
FAN3224
Vbias
FAN3224
1
2
36
7
8
45
VDDGND
ENBENA
B
A
Figure 55. High Current Forward Converter
with Synchronous Rectification
Figure 56. Center-Tapped Bridge Output with
Synchronous Rectifiers
PWM-A
PWM-B
PWM-C
PWM-D
Secondary
Phase Shift
Controller
Vin
QA
QB
QC
QD
SR-2
SR-1
FAN3224
FAN3225
FAN3225
Figure 57. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous
Rectifiers (Simplified)
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FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Table 1. Related Products
Type Part
Number
Gate
Drive(18)
(Sink/Src)
Input
Threshold
Logic Package
Single 1 A
FAN3111C +1.1 A / -0.9 A CMOS Single Channel of Dual-Input/Single-Output SOT23-5, MLP6
Single 1 A
FAN3111E +1.1 A / -0.9 A External
(19)
Single Non-Inverting Channel with External Reference SOT23-5, MLP6
Single 2 A
FAN3100C +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6
Single 2 A
FAN3100T +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6
Single 2 A
FAN3180 +2.4 A / -1.6 A TTL Single Non-Inverting Channel + 3.3-V LDO SOT23-5
Dual 2 A
FAN3216T
+2.4 A / -1.6 A
TTL
Dual Inverting Channels
SOIC8
Dual 2 A
FAN3217T
+2.4 A / -1.6 A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 2 A
FAN3226C
+2.4 A / -1.6 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3226T
+2.4 A / -1.6 A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3227C
+2.4 A / -1.6 A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A FAN3227T +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8
Dual 2 A FAN3228C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8
Dual 2 A FAN3228T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8
Dual 2 A FAN3229C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8
Dual 2 A FAN3229T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8
Dual 2 A FAN3268T +2.4 A / -1.6 A TTL 20 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables SOIC8
Dual 2 A FAN3278T +2.4 A / -1.6 A TTL 30 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables SOIC8
Dual 4 A
FAN3213T
+4.3 A / -2.8 A
TTL
Dual Inverting Channels
SOIC8
Dual 4 A FAN3214T +4.3 A / -2.8 A TTL Dual Non-Inverting Channels SOIC8
Dual 4 A FAN3223C +4.3 A / -2.8 A CMOS Dual Inv erting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3223T +4.3 A / -2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3224C +4.3 A / -2.8 A CMOS Dual Non-Inv erting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3224T +4.3 A / -2.8 A TTL Dual Non-Inv erting Channels + Dual Enable SOIC8, MLP8
Dual 4 A FAN3225C +4.3 A / -2.8 A CMOS Dual Channels of Tw o-Input/One-Output SOIC8, MLP8
Dual 4 A FAN3225T +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8
Single 9 A
FAN3121C +9.7 A / -7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8
Single 9 A
FAN3121T
+9.7 A / -7.1 A
TTL
Single Inverting Channel + Enable
SOIC8, MLP8
Single 9 A
FAN3122T +9.7 A / -7.1 A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8
Single 9 A
FAN3122C
+9.7 A / -7.1 A
TTL
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Dual 12 A
FAN3240
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 0
SOIC8
Dual 12 A
FAN3241
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 1
SOIC8
Notes:
18. Typical currents w ith OUTx at 6 V and VDD=12 V.
19. Thresholds proportional to an externally supplied reference voltage.
www.onsemi.com
27
FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Physical Dimensions
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION VEEC, DATED 11/2001.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP08Drev3
0.10 C A B
0.05 C
TOP VIEW
BOTTOM VIEW
RECOMMENDED LAND PATTERN
0.10 C
0.08 C
3.00
3.00
0.10 C
2X
2X
SEATING
PLANE
0.10 C
(0.20)
1.99
3.30
(0.65)
14
5
8
5
8
4
1
0.65 1.95
0.65 TYP
2.37
1.42
0.42 TYP
PIN #1 IDENT
AB
0.80 MAX
0.05
0.00 C
FRONT VIEW
2.25MAX
PIN #1 IDENT
1.30MAX
0.45
0.20
0.25
0.35
Figure 58. 3x3 mm, 8-Lead Molded Leadless Package (MLP)
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28
FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
Physical Dimensions (Continued)
SEE DETAIL A
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M
E) DRAWING FILENAME: M08Arev16
LAND PATTERN RECOMMENDATION
SEATING PLANE
C
GAGE PLANE
x 45°
DETAIL A
SCALE: 2:1
PIN ONE
INDICATOR
4
8
1
B
5
A
5.60
0.65
1.75
1.27
6.00±0.20 3.90±0.10
4.90±0.10
1.27
0.42±0.09
0.175±0.075
1.75 MAX
0.36
(0.86)
R0.10
R0.10
0.65±0.25
(1.04)
OPTION A - BEVEL EDGE
OPTION B - NO BEVEL EDGE
0.25 C B A
0.10
0.22±0.03
(0.635)
Figure 59. 8-Lead Small Outline Integrated Circuit (SOIC)
PUBLICATION ORDERING INFORMATION LII'ERAI’HREFULFILLNENI': ebsi! W
www.onsemi.com
29
FAN3223 / FAN3224 / FAN3225 Dual 4-A High-Speed, Low-Side Gate Drivers
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