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Artix-7 FPGAs Datasheet

Xilinx Inc.

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Datasheet

EN230 (v1.1) May 3, 2013 www.xilinx.com
Errata Notification 1
© Copyright 2012–2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
Introduction
Thank you for participating in the Artix™-7 FPGAs Engineering Sample Program. As part of this program, we are pleased
to provide to you engineering samples of the devices listed in Ta b l e 1 . Although Xilinx has made every effort to ensure the
highest possible quality, these devices are subject to the limitations described in the following errata.
Devices
These errata apply to the devices shown in Ta bl e 1 .
Hardware Errata Details
This section provides a detailed description of each hardware issue known at the release time of this document.
IEEE Std 1149.1 Boundary-Scan
IEEE Std 1149.1 for Dedicated and SelectIO Resources (Applies only to XC7A100T Device)
IEEE Std 1149.1 (JTAG) boundary-scan test commands SAMPLE, PRELOAD, EXTEST, and HIGHZ are not functional. All
other JTAG commands, including device configuration and the ChipScope™ debugging tool, function as expected.
Design Tool Requirements
The devices listed in Ta bl e 1 , unless otherwise specified, require the following Xilinx Design Tools:
Speed specification v1.07 (or later) of Xilinx® ISE® Design Suite 14.4 or Vivado™ Design Suite 2012.4 with device
pack (or later) available at http://www.xilinx.com/support/download/.
For GTP transceiver attribute updates, refer to Answer Record 47852.
See Artix-7 FPGA Answer Record 52049 for the most current known issues and work-arounds for Xilinx Design Tools.
3
Artix-7 XC7A100T and XC7A200T FPGA
CES and CES9910 Errata
EN230 (v1.1) May 3, 2013 Errata Notification
Tabl e 1 : Devices Affected by These Errata
Product Family Device JTAG ID
(Revision Code) Packages Speed Grades Junction
Temperature
Artix-7 XC7A100T CES 0 All -1, -2 0°C to 85°C
XC7A200T CES
XC7A100T CES9910 –40°C to 100°C
XC7A200T CES9910
Artix-7 XC7A100T and XC7A200T FPGA CES and CES9910 Errata
EN230 (v1.1) May 3, 2013 www.xilinx.com
Errata Notification 2
Traceability
Figure 1 shows an example device top mark for the devices listed in Ta b l e 1 .
Additional Questions or Clarifications
For additional questions regarding these errata, contact Xilinx Technical Support:
http://www.xilinx.com/support/clearexpress/websupport.htm or your Xilinx Sales Representative:
http://www.xilinx.com/company/contact/index.htm.
X-Ref Target - Figure 1
Figure 1: Example Device Top Mark
XC7A100T
FGG676xxxXXXX
DxxxxxxxA
1C ES
Date Code
Device Type
Package
Speed Grade
Operating Range
Lot Code
Engineering Sample
EN230_01_101012
Artix-7 XC7A100T and XC7A200T FPGA CES and CES9910 Errata
EN230 (v1.1) May 3, 2013 www.xilinx.com
Errata Notification 3
Revision History
The following table shows the revision history for this document:
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to
product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain
products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP
cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or
intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx
products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.
Engineering Sample Disclaimer
ENGINEERING SAMPLE (ES) DEVICES ARE MADE AVAILABLE SOLELY FOR PURPOSES OF RESEARCH, DEVELOPMENT AND
PROTOTYPING. ALL ES DEVICES ARE SOLD “AS-IS” WITH NO WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED. XILINX
DOES NOT WARRANT THAT ES DEVICES ARE FULLY VERIFIED, TESTED, OR WILL OPERATE IN ACCORDANCE WITH DATA
SHEET SPECIFICATIONS. XILINX DISCLAIMS ANY OBLIGATIONS FOR TECHNICAL SUPPORT AND BUG FIXES. XILINX SHALL
NOT BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION DIRECT, INDIRECT, INCIDENTAL, SPECIAL, RELIANCE,
OR CONSEQUENTIAL DAMAGES ARISING FROM OR IN CONNECTION WITH THE USE OF ES DEVICES IN ANY MANNER
WHATSOEVER, EVEN IF XILINX HAS BEEN ADVISED OF THE POSSIBILITY THEREOF. XILINX MAKES NO REPRESENTATION
THAT ES DEVICES PROVIDE ANY PARTICULAR FUNCTIONALITY, OR THAT ES DEVICES WILL MEET THE REQUIREMENTS OF A
PARTICULAR USER APPLICATION. XILINX DOES NOT WARRANT THAT ES DEVICES ARE ERROR-FREE, NOR DOES XILINX
MAKE ANY OTHER REPRESENTATIONS OR WARRANTIES, WHETHER EXPRESS OR IMPLIED, STATUTORY OR OTHERWISE,
INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
NON-INFRINGEMENT. THE FOREGOING STATES THE ENTIRE LIABILITY OF XILINX WITH RESPECT TO ES DEVICES.
Date Version Description of Revisions
10/25/12 1.0 Initial Xilinx release.
05/03/13 1.1 Removed XADC-ADC Accuracy because the specifications are now included in the data sheet,
DS181, Artix-7 FPGAs Data Sheet: DC and Switching Characteristics, v1.5, February 1, 2013.
Updated Design Tool Requirements.

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