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Zynq-7000 All Programmable SoC Overview

Xilinx Inc.

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Datasheet

DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 1
© Copyright 2011–2018 Xilinx, Inc. Xilinx, the Xilinx logo, Zynq, Virtex, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. AMBA, AMBA Designer, ARM, Cortex-A9, CoreSight, Cortex, PrimeCell, ARM Powered, and ARM Connected Partner are trademarks
of ARM Ltd. All other trademarks are the property of their respective owners.
Introduction
The Zynq®-7000 SoCs are available in -3, -2, -1, and -1LI
speed grades, with -3 having the highest performance. The
-1LI devices can operate at either of two programmable
logic (PL) VCCINT/VCCBRAM voltages, 0.95V and 1.0V, and are
screened for lower maximum static power. The speed
specification of a -1LI device is the same as the -1 speed
grade. When operated at PL VCCINT/VCCBRAM = 0.95V, the
-1LI static and dynamic power is reduced. Zynq-7000 device
DC and AC characteristics are specified in commercial,
extended, industrial and expanded (Q-temp) temperature
ranges. Except for the operating temperature range or
unless otherwise noted, all the DC and AC electrical
parameters are the same for a particular speed grade (that
is, the timing characteristics of a -1 speed grade industrial
device are the same as for a -1 speed grade commercial
device). However, only selected speed grades and/or
devices are available in the commercial, extended,
industrial, or Q-temp temperature ranges.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parameters
included are common to popular designs and typical
applications.
The available device/package combinations are outlined in:
Zynq-7000 SoC Overview (DS190)
XA Zynq-7000 SoC Overview (DS188)
Defense-grade Zynq-7000Q SoC Overview (DS196)
This Zynq-7000 SoC data sheet, which covers the
specifications for the XC7Z007S, XC7Z012S, XC7Z014S,
XC7Z010, XA7Z010, XC7Z015, XC7Z020, XA7Z020, and
XQ7Z020, complements the Zynq-7000 SoC documentation
suite available on the Xilinx website at www.xilinx.com/zynq.
DC Characteristics
Zynq-7000 SoC
(Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020):
DC and AC Switching Characteristics
DS187 (v1.20.1) July 2, 2018 Product Specification
Table 1: Absolute Maximum Ratings(1)
Symbol Description Min Max Units
Processing System (PS)
VCCPINT PS internal logic supply voltage –0.5 1.1 V
VCCPAUX PS auxiliary supply voltage –0.5 2.0 V
VCCPLL PS PLL supply –0.5 2.0 V
VCCO_DDR PS DDR I/O supply voltage –0.5 2.0 V
VCCO_MIO(2) PS MIO I/O supply voltage –0.5 3.6 V
VPREF PS input reference voltage –0.5 2.0 V
VPIN(2)(3)(4)(5) PS MIO I/O input voltage –0.40 VCCO_MIO +0.55 V
PS DDR I/O input voltage –0.55 VCCO_DDR +0.55 V
Programmable Logic (PL)
VCCINT PL internal supply voltage –0.5 1.1 V
VCCAUX PL auxiliary supply voltage –0.5 2.0 V
VCCBRAM PL supply voltage for the block RAM memories –0.5 1.1 V
VCCO PL supply voltage for HR I/O banks –0.5 3.6 V
VREF Input reference voltage –0.5 2.0 V
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 2
VIN(3)(4)(5)
I/O input voltage for HR I/O banks –0.40 VCCO +0.55 V
I/O input voltage (when VCCO =3.3V) for V
REF and differential I/O standards
except TMDS_33(6) –0.40 2.625 V
VCCBATT Key memory battery backup supply –0.5 2.0 V
GTP Transceiver (XC7Z015 Only)
VMGTAVCC Analog supply voltage for the GTP transmitter and receiver circuits –0.5 1.1 V
VMGTAVTT Analog supply voltage for the GTP transmitter and receiver termination
circuits –0.5 1.32 V
VMGTREFCLK Reference clock absolute input voltage –0.5 1.32 V
VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V
IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating 14 mA
IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX
termination = VMGTAVTT –12mA
IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND 6.5 mA
IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating 14 mA
IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX
termination = VMGTAVTT –12mA
XADC
VCCADC XADC supply relative to GNDADC –0.5 2.0 V
VREFP XADC reference input relative to GNDADC –0.5 2.0 V
Temperature
TSTG Storage temperature (ambient) –65 150 °C
TSOL
Maximum soldering temperature for Pb/Sn component bodies(7) +220 °C
Maximum soldering temperature for Pb-free component bodies(7) +260 °C
TjMaximum junction temperature(7) +125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1.
3. The lower absolute voltage specification always applies.
4. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) or the Zynq-7000 SoC Technical Reference Manual
(UG585).
5. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.
6. See Table 11 for TMDS_33 specifications.
7. For soldering guidelines and thermal considerations, see the Zynq-7000 SoC Packaging and Pinout Specification (UG865).
Table 2: Recommended Operating Conditions(1)(2)
Symbol Description Min Typ Max Units
PS
VCCPINT PS internal logic supply voltage 0.95 1.00 1.05 V
VCCPAUX PS auxiliary supply voltage 1.71 1.80 1.89 V
VCCPLL PS PLL supply 1.71 1.80 1.89 V
VCCO_DDR PS DDR I/O supply voltage 1.14 1.89 V
VCCO_MIO(3) PS MIO I/O supply voltage for MIO banks 1.71 3.465 V
Table 1: Absolute Maximum Ratings(1) (Cont’d)
Symbol Description Min Max Units
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 3
VPIN(4) PS DDR and MIO I/O input voltage –0.20 VCCO_DDR +0.20
VCCO_MIO +0.20 V
PL
VCCINT(5) PL internal supply voltage 0.95 1.00 1.05 V
PL -1LI (0.95V) internal supply voltage 0.92 0.95 0.98 V
VCCAUX PL auxiliary supply voltage 1.71 1.80 1.89 V
VCCBRAM(5) PL block RAM supply voltage 0.95 1.00 1.05 V
PL -1LI (0.95V) block RAM supply voltage 0.92 0.95 0.98 V
VCCO(6)(7) PL supply voltage for HR I/O banks 1.14 3.465 V
VIN(4)
I/O input voltage –0.20 VCCO +0.20 V
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O
standards except TMDS_33(8) –0.20 – 2.625 V
IIN(9) Maximum current through any (PS or PL) pin in a powered or unpowered
bank when forward biasing the clamp diode –– 10 mA
VCCBATT(10) Battery voltage 1.0 1.89 V
GTP Transceiver (XC7Z015 Only)
VMGTAVCC(11) Analog supply voltage for the GTP transmitter and receiver circuits 0.97 1.0 1.03 V
VMGTAVTT(11) Analog supply voltage for the GTP transmitter and receiver termination
circuits 1.17 1.2 1.23 V
XADC
VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V
VREFP Externally supplied reference voltage 1.20 1.25 1.30 V
Temperature
Tj
Junction temperature operating range for commercial (C) temperature
devices 0– 85 °C
Junction temperature operating range for extended (E) temperature
devices 0 – 100 °C
Junction temperature operating range for industrial (I) temperature
devices –40 – 100 °C
Junction temperature operating range for expanded (Q) temperature
devices –40 – 125 °C
Notes:
1. All voltages are relative to ground. The PL and PS share a common ground.
2. For the design of the power distribution system consult the Zynq-7000 SoC PCB Design Guide (UG933).
3. Applies to both MIO supply banks VCCO_MIO0 and VCCO_MIO1.
4. The lower absolute voltage specification always applies.
5. VCCINT and VCCBRAM should be connected to the same supply.
6. Configuration data is retained even if VCCO drops to 0V.
7. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%.
8. See Table 11 for TMDS_33 specifications.
9. A total of 200 mA per PS or PL bank should not be exceeded.
10. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
11. Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTP Transceiver User Guide (UG482).
Table 2: Recommended Operating Conditions(1)(2) (Cont’d)
Symbol Description Min Typ Max Units
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 4
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ(1) Max Units
VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 V
VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 V
IREF PS_DDR_VREF 0/1, PS_MIO_VREF, and VREF leakage current per pin 15 µA
ILInput or output leakage current per pin (sample-tested) 15 µA
CIN(2) PL die input capacitance at the pad 8 pF
CPIN(2) PS die input capacitance at the pad 8 pF
IRPU
Pad pull-up (when selected) @ VIN =0V, V
CCO = 3.3V 90 330 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO = 2.5V 68 250 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO = 1.8V 34 220 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO = 1.5V 23 150 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO = 1.2V 12 120 µA
IRPD
Pad pull-down (when selected) @ VIN = 3.3V 68 330 µA
Pad pull-down (when selected) @ VIN = 1.8V 45 180 µA
ICCADC Analog supply current, analog circuits in powered up state 25 mA
IBATT(3) Battery supply current 150 nA
RIN_TERM(4)
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_40) 28 40 55 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_50) 35 50 65 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_60) 44 60 83 Ω
n Temperature diode ideality factor 1.010
r Temperature diode series resistance 2 Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
4. Termination resistance to a VCCO/2 level.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 5
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and PL HR I/O Banks(1)(2)
AC Voltage Overshoot % of UI @–40°C to 125°C AC Voltage Undershoot % of UI @–40°C to 125°C
VCCO + 0.55 100
–0.40 100
–0.45 61.7
–0.50 25.8
–0.55 11.0
VCCO + 0.60 46.6 –0.60 4.77
VCCO + 0.65 21.2 –0.65 2.10
VCCO + 0.70 9.75 –0.70 0.94
VCCO + 0.75 4.55 –0.75 0.43
VCCO + 0.80 2.15 –0.80 0.20
VCCO + 0.85 1.02 –0.85 0.09
VCCO + 0.90 0.49 –0.90 0.04
VCCO + 0.95 0.24 –0.95 0.02
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO+ 0.20V or below GND –0.20V, must not exceed the values
in this table.
Table 5: Typical Quiescent Supply Current
Symbol Description Device Speed Grade Units
-3 -2 -1 -1LI
ICCPINTQ PS quiescent VCCPINT supply current
XC7Z007S N/A 122 122 N/A mA
XC7Z012S N/A 122 122 N/A mA
XC7Z014S N/A 122 122 N/A mA
XC7Z010 122 122 122 85 mA
XC7Z015 122 122 122 85 mA
XC7Z020 122 122 122 85 mA
XA7Z010 N/A N/A 122 N/A mA
XA7Z020 N/A N/A 122 N/A mA
XQ7Z020 N/A 122 122 85 mA
ICCPAUXQ PS quiescent VCCPAUX supply current
XC7Z007S N/A 13 13 N/A mA
XC7Z012S N/A 13 13 N/A mA
XC7Z014S N/A 13 13 N/A mA
XC7Z010 13 13 13 11 mA
XC7Z015 13 13 13 11 mA
XC7Z020 13 13 13 11 mA
XA7Z010 N/A N/A 13 N/A mA
XA7Z020 N/A N/A 13 N/A mA
XQ7Z020 N/A 13 13 11 mA
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 6
ICCDDRQ PS quiescent VCCO_DDR supply current
XC7Z007S N/A 4 4 N/A mA
XC7Z012S N/A 4 4 N/A mA
XC7Z014S N/A 4 4 N/A mA
XC7Z010 4 4 4 4 mA
XC7Z015 4 4 4 4 mA
XC7Z020 4 4 4 4 mA
XA7Z010 N/A N/A 4 N/A mA
XA7Z020 N/A N/A 4 N/A mA
XQ7Z020N/A444mA
ICCINTQ PL quiescent VCCINT supply current
XC7Z007S N/A 34 34 N/A mA
XC7Z012S N/A 77 77 N/A mA
XC7Z014S N/A 78 78 N/A mA
XC7Z010 34 34 34 21/23(4) mA
XC7Z015 77 77 77 47/53(4) mA
XC7Z020 78 78 78 48/54(4) mA
XA7Z010 N/A N/A 34 N/A mA
XA7Z020 N/A N/A 78 N/A mA
XQ7Z020 N/A 78 78 48/54(4) mA
ICCAUXQ PL quiescent VCCAUX supply current
XC7Z007S N/A 18 18 N/A mA
XC7Z012S N/A 35 35 N/A mA
XC7Z014S N/A 38 38 N/A mA
XC7Z010 18 18 18 16 mA
XC7Z015 35 35 35 31 mA
XC7Z020 38 38 38 34 mA
XA7Z010 N/A N/A 18 N/A mA
XA7Z020 N/A N/A 38 N/A mA
XQ7Z020 N/A 38 38 34 mA
ICCOQ PL quiescent VCCO supply current
XC7Z007S N/A 3 3 N/A mA
XC7Z012S N/A 3 3 N/A mA
XC7Z014S N/A 3 3 N/A mA
XC7Z010 3 3 3 3 mA
XC7Z015 3 3 3 3 mA
XC7Z020 3 3 3 3 mA
XA7Z010 N/A N/A 3 N/A mA
XA7Z020 N/A N/A 3 N/A mA
XQ7Z020N/A333mA
Table 5: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1 -1LI
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 7
ICCBRAMQ PL quiescent VCCBRAM supply current
XC7Z007S N/A 3 3 N/A mA
XC7Z012S N/A 4 4 N/A mA
XC7Z014S N/A 6 6 N/A mA
XC7Z010 3 3 3 1/2(4) mA
XC7Z015 4 4 4 2/2(4) mA
XC7Z020 6 6 6 3/4(4) mA
XA7Z010 N/A N/A 3 N/A mA
XA7Z020 N/A N/A 6 N/A mA
XQ7Z020N/A663/4
(4) mA
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO™ resources.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. The Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) estimates operating current. When the
required power-on current exceeds the estimated operating current, XPE can display the power-on current.
4. The first value is at 0.95V, and the second value is at 1.0V.
Table 5: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device Speed Grade Units
-3 -2 -1 -1LI
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 8
PS Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0,
VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The
PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have
reached minimum operating levels to ensure PS eFUSE integrity. For additional information about PS_POR_B timing
requirements refer to Resets.
The recommended power-off sequence is the reverse of the power-on sequence. If VCCPAUX, VCCPLL, and the PS VCCO supplies
(VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) have the same recommended voltage levels, then they can be powered by the same
supply and ramped simultaneously. Xilinx recommends powering VCCPLL with the same supply as VCCPAUX, with an optional
ferrite bead filter. Before VCCPINT reaches 0.80V at least one of the four following conditions is required during the power-off
stage: the PS_POR_B input is asserted to GND, the reference clock to the PS_CLK input is disabled, VCCPAUX is lower than
0.70V, or VCCO_MIO0 is lower than 0.90V. The condition must be held until VCCPINT reaches 0.40V to ensure PS eFUSE integrity.
For VCCO_MIO0 and VCCO_MIO1 voltages of 3.3V:
The voltage difference between VCCO_MIO0 /VCCO_MIO1 and VCCPAUX must not exceed 2.625V for longer than
TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
PL Power-On/Off Power Supply Sequencing
The recommended power-on sequence for the PL is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw
and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on
sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply
and ramped simultaneously. If VCCAUX and VCCO have the same recommended voltage levels then both can be powered by
the same supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
GTP Transceivers (XC7Z015 Only)
The recommended power-on sequence to achieve minimum current draw for the GTP transceivers (XC7Z015 only) is VCCINT,
VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. Both VMGTAVCC and VCCINT can be ramped simultaneously. The
recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during
power-up and power-down.
•When V
MGTAVTT is powered before VMGTAVCC and VMGTAVTT –V
MGTAVCC > 150 mV and VMGTAVCC <0.7V, the V
MGTAVTT
current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be
up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
•When V
MGTAVTT is powered before VCCINT and VMGTAVTT –V
CCINT > 150 mV and VCCINT <0.7V, the V
MGTAVTT current
draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to
0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
PS—PL Power Sequencing
The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and
VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent
damage.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 9
Power Supply Requirements
Table 6 shows the minimum current, in addition to ICCQ, that is required by Zynq-7000 devices for proper power-on and
configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four PL supplies
have passed through their power-on reset threshold voltages. The Zynq-7000 device must not be configured until after
VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at
www.xilinx.com/power) to estimate current drain on these supplies.
Table 6: Power-On Current for Zynq-7000 Devices
Device ICCPINTMIN ICCPAUXMIN ICCDDRMIN ICCINTMIN ICCAUXMIN ICCOMIN ICCBRAMMIN Units
XC7Z007S ICCPINTQ +70 ICCPAUXQ +40 ICCDDRQ +100mA
per bank ICCINTQ +40 ICCAUXQ +60 ICCOQ +90mA
per bank ICCBRAMQ +40 mA
XC7Z012S ICCPINTQ +70 ICCPAUXQ +40 ICCDDRQ +100mA
per bank ICCINTQ +130 ICCAUXQ +60 ICCOQ +90mA
per bank ICCBRAMQ +40 mA
XC7Z014S ICCPINTQ +70 ICCPAUXQ +40 ICCDDRQ +100mA
per bank ICCINTQ +70 ICCAUXQ +60 ICCOQ +90mA
per bank ICCBRAMQ +40 mA
XC7Z010
XA7Z010 ICCPINTQ +70 ICCPAUXQ +40 ICCDDRQ +100mA
per bank ICCINTQ +40 ICCAUXQ +60 ICCOQ +90mA
per bank ICCBRAMQ +40 mA
XC7Z015 ICCPINTQ +70 ICCPAUXQ +40 ICCDDRQ +100mA
per bank ICCINTQ +130 ICCAUXQ +60 ICCOQ +90mA
per bank ICCBRAMQ +40 mA
XC7Z020
XA7Z020
XQ7Z020
ICCPINTQ +70 ICCPAUXQ +40 ICCDDRQ +100mA
per bank ICCINTQ +70 ICCAUXQ +60 ICCOQ +90mA
per bank ICCBRAMQ +40 mA
Table 7: Power Supply Ramp Time
Symbol Description Conditions Min Max Units
TVCCPINT Ramp time from GND to 90% of VCCPINT 0.2 50 ms
TVCCPAUX Ramp time from GND to 90% of VCCPAUX 0.2 50 ms
TVCCO_DDR Ramp time from GND to 90% of VCCO_DDR 0.2 50 ms
TVCCO_MIO Ramp time from GND to 90% of VCCO_MIO 0.2 50 ms
TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms
TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms
TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms
TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms
TVCCO2VCCAUX
Allowed time per power cycle for VCCO –V
CCAUX > 2.625V
and VCCO_MIO –V
CCPAUX > 2.625V
Tj = 125°C(1) –300
msTj = 100°C(1) –500
Tj = 85°C(1) –800
TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms
TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms
Notes:
1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with worst case VCCO of 3.465V.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 10
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH
voltage levels shown. Other standards are sample tested.
PS I/O Levels
Table 8: PS DC Input and Output Levels(1)
Bank I/O
Standard
VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
MIO LVCMOS18 –0.300 35% VCCO_MIO 65% VCCO_MIO VCCO_MIO + 0.300 0.450 VCCO_MIO – 0.450 8 –8
MIO LVCMOS25 –0.300 0.700 1.700 VCCO_MIO + 0.300 0.400 VCCO_MIO – 0.400 8 –8
MIO LVCMOS33 –0.300 0.800 2.000 3.450 0.400 VCCO_MIO – 0.400 8 –8
MIO HSTL_I_18 –0.300 VPREF – 0.100 VPREF +0.100 V
CCO_MIO + 0.300 0.400 VCCO_MIO – 0.400 8 –8
DDR SSTL18_I –0.300 VPREF – 0.125 VPREF +0.125 V
CCO_DDR +0.300 V
CCO_DDR/2–0.470 V
CCO_DDR/2 + 0.470 8 –8
DDR SSTL15 –0.300 VPREF – 0.100 VPREF +0.100 V
CCO_DDR +0.300 V
CCO_DDR/2–0.175 V
CCO_DDR/2 + 0.175 13.0 –13.0
DDR SSTL135 –0.300 VPREF – 0.090 VPREF +0.090 V
CCO_DDR +0.300 V
CCO_DDR/2–0.150 V
CCO_DDR/2 + 0.150 13.0 –13.0
DDR HSUL_12 –0.300 VPREF – 0.130 VPREF +0.130 V
CCO_DDR + 0.300 20% VCCO_DDR 80% VCCO_DDR 0.1 –0.1
Notes:
1. Tested according to relevant specifications.
Table 9: PS Complementary Differential DC Input and Output Levels
Bank I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH
V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min
DDR DIFF_HSUL_12 0.300 0.600 0.850 0.100 20% VCCO 80% VCCO 0.100 –0.100
DDR DIFF_SSTL135 0.300 0.675 1.000 0.100 (VCCO_DDR/2) – 0.150 (VCCO_DDR/2) + 0.150 13.0 –13.0
DDR DIFF_SSTL15 0.300 0.750 1.125 0.100 (VCCO_DDR/2) – 0.175 (VCCO_DDR/2) + 0.175 13.0 –13.0
DDR DIFF_SSTL18_I 0.300 0.900 1.425 0.100 (VCCO_DDR/2) – 0.470 (VCCO_DDR/2) + 0.470 8.00 –8.00
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q–Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
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Product Specification 11
PL I/O Levels
Table 10: SelectIO DC Input and Output Levels(1)(2)
I/O Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00
HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00
HSTL_II –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16.00 –16.00
HSTL_II_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16.00 –16.00
HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO +0.300 20%V
CCO 80% VCCO 0.10 –0.10
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO –0.400 Note 3 Note 3
LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO +0.300 25%V
CCO 75% VCCO Note 4 Note 4
LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO –0.450 Note 5 Note 5
LVCMOS25 –0.300 0.7 1.700 VCCO + 0.300 0.400 VCCO –0.400 Note 4 Note 4
LVCMOS33 –0.300 0.8 2.000 3.450 0.400 VCCO –0.400 Note 4 Note 4
LVTTL –0.300 0.8 2.000 3.450 0.400 2.400 Note 5 Note 5
MOBILE_DDR –0.300 20% VCCO 80% VCCO VCCO +0.300 10%V
CCO 90% VCCO 0.10 –0.10
PCI33_3 –0.400 30% VCCO 50% VCCO VCCO +0.500 10%V
CCO 90% VCCO 1.50 –0.50
SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO +0.300 V
CCO/2 – 0.150 VCCO/2 + 0.150 13.00 13.00
SSTL135_R –0.300 VREF – 0.090 VREF + 0.090 VCCO +0.300 V
CCO/2 – 0.150 VCCO/2 + 0.150 8.90 –8.90
SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO +0.300 V
CCO/2 – 0.175 VCCO/2 + 0.175 13.00 13.00
SSTL15_R –0.300 VREF – 0.100 VREF + 0.100 VCCO +0.300 V
CCO/2 – 0.175 VCCO/2 + 0.175 8.90 –8.90
SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO +0.300 V
CCO/2 – 0.470 VCCO/2 + 0.470 8.00 –8.00
SSTL18_II –0.300 VREF – 0.125 VREF + 0.125 VCCO +0.300 V
CCO/2 – 0.600 VCCO/2 + 0.600 13.40 13.40
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).
Table 11: Differential SelectIO DC Input and Output Levels
I/O Standard VICM(1) VID(2) VOCM(3) VOD(4)
V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max
BLVDS_25 0.300 1.200 1.425 0.100 1.250 Note 5
MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600
PPDS_25 0.200 0.900 VCCAUX 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400
RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600
TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.400 0.600 0.800
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q–Q).
3. VOCM is the output common mode voltage.
4. VOD is the output differential voltage (Q–Q).
5. VOD for BLVDS will vary significantly depending on topology and loading.
6. LVDS_25 is specified in Table 13.
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Product Specification 12
LVDS DC Specifications (LVDS_25)
Table 12: Complementary Differential SelectIO DC Input and Output Levels
I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH
V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min
DIFF_HSTL_I 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_II 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSUL_12 0.300 0.600 0.850 0.100 20% VCCO 80% VCCO 0.100 –0.100
DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 10% VCCO 90% VCCO 0.100 –0.100
DIFF_SSTL135 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0 –13.0
DIFF_SSTL135_R 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9 –8.9
DIFF_SSTL15 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0 –13.0
DIFF_SSTL15_R 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9 –8.9
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.00 –8.00
DIFF_SSTL18_II 0.300 0.900 1.425 0.100 (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4 –13.4
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q–Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
Table 13: LVDS_25 DC Specifications(1)
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply voltage 2.375 2.5 2.625 V
VOH Output High voltage for Q and Q RT = 100Ω across Q and Q signals 1.675 V
VOL Output Low voltage for Q and Q RT = 100Ω across Q and Q signals 0.700 V
VODIFF
Differential output voltage:
(Q – Q), Q = High
(Q –Q), Q=High
RT = 100Ω across Q and Q signals 247 350 600 mV
VOCM Output common-mode voltage RT = 100Ω across Q and Q signals 1.00 1.25 1.425 V
VIDIFF
Differential input voltage:
(Q – Q), Q = High
(Q –Q), Q=High
100 350 600 mV
VICM Input common-mode voltage 0.3 1.2 1.500 V
Notes:
1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the
7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.
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Product Specification 13
AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in the ISE® Design Suite 14.7 and
Vivado® Design Suite 2016.3 as outlined in Table 14.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting
might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with
this designation are intended to give a better indication of the expected performance of production silicon. The probability
of under-reporting delays is greatly reduced as compared to Advance data.
Production Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
Testing of AC Switching Characteristics
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are
representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.
Speed Grade Designations
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 15 correlates the current status of each Zynq-7000
device on a per speed grade basis.
Table 14: Zynq-7000 SoC Speed Specification Version By Device
ISE 14.7 Vivado 2016.3 Device
1.08 1.11 XC7Z010 and XC7Z020
N/A 1.11 XC7Z007S, XC7Z012S, XC7Z014S, and XC7Z015
1.06 1.09 XA7Z010 and XA7Z020
1.06 1.10 XQ7Z020
Table 15: Zynq-7000 Device Speed Grade Designations
Device Speed Grade Designations
Advance Preliminary Production
XC7Z007S -2E, -2I, -1C, -1I
XC7Z012S -2E, -2I, -1C, -1I
XC7Z014S -2E, -2I, -1C, -1I
XC7Z010 -3E, -2E, -2I, -1C, -1I, -1LI
XC7Z015 -3E, -2E, -2I, -1C, -1I, -1LI
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Product Specification 14
Production Silicon and Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 16 lists the production released Zynq-7000 device, speed grade, and the minimum corresponding supported speed
specification version and software revisions. The software and speed specifications listed are the minimum releases required
for production. All subsequent releases of software and speed specifications are valid.
Selecting the Correct Speed Grade and Voltage in the Vivado Tools
It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.
To select the -3, -2, or -1 (PL 1.0V) speed specifications in the Vivado tools, select the Zynq-7000, XA Zynq-7000, or
Defense Grade Zynq-7000 sub-family, and then select the part name that is the device name followed by the package name
followed by the speed grade. For example, select the xc7z020clg484-3 part name for the XC7Z020 device in the CLG484
package and -3 speed grade.
XC7Z020 -3E, -2E, -2I, -1C, -1I, -1LI
XA7Z010 -1I, -1Q
XA7Z020 -1I, -1Q
XQ7Z020 -2I, -1I, -1Q, -1LI
Table 16: Zynq-7000 Device Production Software and Speed Specification Release
Device Speed Grade Designations
-3E -2E -2I -1C -1I -1LI -1Q
XC7Z007S N/A Vivado tools 2016.3 v1.11 N/A N/A
XC7Z012S N/A Vivado tools 2016.3 v1.11 N/A N/A
XC7Z014S N/A Vivado tools 2016.3 v1.11 N/A N/A
XC7Z010 ISE tools 14.5
v1.06 and
Vivado tools 2013.1
v1.06
ISE tools 14.4 and the 14.4 device pack v1.05
and Vivado tools 2013.1 v1.06
Vivado tools
2014.4 v1.11 N/A
XC7Z015 Vivado tools 2013.4 v1.09 Vivado tools
2014.4 v1.11 N/A
XC7Z020 ISE tools 14.5
v1.06 and
Vivado tools 2013.1
v1.06
ISE tools 14.4 and the 14.4 device pack v1.05
and Vivado tools 2013.1 v1.06
Vivado tools
2014.4 v1.11 N/A
XA7Z010
N/A
ISE tools 14.5
v1.04 and
Vivado tools 2013.1
v1.04
N/A
ISE tools 14.6
v1.05 and
Vivado tools 2013.2
v1.05
XA7Z020
N/A
ISE tools 14.5
v1.04 and
Vivado tools 2013.1
v1.04
N/A
ISE tools 14.6
v1.05 and
Vivado tools 2013.2
v1.05
XQ7Z020
N/A
ISE tools 14.6
v1.05 and
Vivado tools 2013.2
v1.05
N/A
ISE tools 14.6
v1.05 and
Vivado tools 2013.2
v1.05
Vivado tools
2015.4 v1.10
ISE tools 14.7
v1.06 and
Vivado tools 2013.3
v1.06
Table 15: Zynq-7000 Device Speed Grade Designations (Cont’d)
Device Speed Grade Designations
Advance Preliminary Production
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Product Specification 15
To select the -1LI (PL 0.95V) speed specifications in the Vivado tools, select the Zynq-7000 sub-family and then select the
part name that is the device name followed by an i followed by the package name followed by the speed grade. For example,
select the xc7z020iclg484-1L part name for the XC7Z020 device in the CLG484 package and -1LI (PL 0.95V) speed grade.
The -1LI (PL 0.95V) speed specifications are not supported in the ISE tools.
A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See
Table 16 for the subset of the Zynq-7000 devices supported in the ISE tools.
PS Performance Characteristics
For further design requirement details, refer to the Zynq-7000 SoC Technical Reference Manual (UG585).
Table 17: CPU Clock Domains Performance
Symbol Clock Ratio Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
FCPU_6X4X_621_MAX(1)
6:2:1
Maximum CPU clock frequency 866 766 667 667 MHz
FCPU_3X2X_621_MAX Maximum CPU_3X clock frequency 433 383 333 333 MHz
FCPU_2X_621_MAX Maximum CPU_2X clock frequency 288 255 222 222 MHz
FCPU_1X_621_MAX Maximum CPU_1X clock frequency 144 127 111 111 MHz
FCPU_6X4X_421_MAX(1)
4:2:1
Maximum CPU clock frequency 710 600 533 533 MHz
FCPU_3X2X_421_MAX Maximum CPU_3X clock frequency 355 300 267 267 MHz
FCPU_2X_421_MAX Maximum CPU_2X clock frequency 355 300 267 267 MHz
FCPU_1X_421_MAX Maximum CPU_1X clock frequency 178 150 133 133 MHz
Notes:
1. The maximum frequency during BootROM execution is 500 MHz across all speed specifications.
Table 18: PS DDR Clock Domains Performance(1)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
FDDR3_MAX Maximum DDR3 interface performance 1066 1066 1066 1066 Mb/s
FDDR3L_MAX Maximum DDR3L interface performance 1066 1066 1066 1066 Mb/s
FDDR2_MAX Maximum DDR2 interface performance 800 800 800 800 Mb/s
FLPDDR2_MAX Maximum LPDDR2 interface performance 800 800 800 800 Mb/s
FDDRCLK_2XMAX Maximum DDR_2X clock frequency 444 408 355 355 MHz
Notes:
1. All performance numbers apply to both internal and external VREF configurations.
Table 19: PS-PL Interface Performance
Symbol Description Min Max Units
FEMIOGEMCLK EMIO gigabit Ethernet controller maximum frequency 125 MHz
FEMIOSDCLK EMIO SD controller maximum frequency 25 MHz
FEMIOSPICLK EMIO SPI controller maximum frequency 25 MHz
FEMIOJTAGCLK EMIO JTAG controller maximum frequency 20 MHz
FEMIOTRACECLK EMIO trace controller maximum frequency 125 MHz
FFTMCLK Fabric trace monitor maximum frequency 125 MHz
FEMIODMACLK DMA maximum frequency 100 MHz
FAXI_MAX Maximum AXI interface performance 250 MHz
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Product Specification 16
PS Switching Characteristics
Clocks
Resets
The PS_POR_B deassertion must meet the following requirements to avoid coinciding with the secure lockdown window.
Figure 1 shows the timing relationship between PS_POR_B and the last power supply ramp (VCCINT, VCCBRAM, VCCAUX, or VCCO
in bank 0). TSLW minimum and maximum parameters define the beginning and end, respectively, of the secure lockdown
window relative to the last PL power supply reaching 250 mV. The PS_POR_B must not be deasserted within the secure
lockdown window.
Table 20: System Reference Clock Input Requirements
Symbol Description Min Typ Max Units
TJTPSCLK PS_CLK RMS clock jitter tolerance ±0.5 %
TDCPSCLK PS_CLK duty cycle 40 60 %
TRFPSCLK PS_CLK rise and fall time 6 ns
FPSCLK PS_CLK frequency 30 60 MHz
Table 21: PS PLL Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TLOCK_PSPLL PLL maximum lock time 60 60 60 60 µs
FPSPLL_MAX PLL maximum output frequency 2000 1800 1600 1600 MHz
FPSPLL_MIN PLL minimum output frequency 780 780 780 780 MHz
Table 22: PS Reset Assertion Timing Requirements
Symbol Description Min Typ Max Units
TPSPOR Required PS_POR_B assertion time(1) 100 – µs
TPSRST Required PS_SRST_B assertion time 3 PS_CLK Clock Cycles
Notes:
1. PS_POR_B needs to be asserted Low until TPSPOR after PS supply voltages reach minimum levels.
X-Ref Target - Figure 1
Figure 1: PS_POR_B and Power Supply Ramp Timing Requirements
PS_POR_B
Last Ramping PL Supply
Secure Lockdown Window
Do not deassert PS_POR_B
T
SLW(min)
T
SLW(max)
250 mV
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Product Specification 17
PS Configuration
DDR Memory Interfaces
Table 23: PS Reset/Power Supply Timing Requirements
Symbol Description PS_CLK Frequency
(MHz) Min Max Units
TSLW(1) 128 KB CRC eFUSE disabled and PLL enabled.
Default configuration
30 12 39 ms
33.33 12 40 ms
60 13 40 ms
128 KB CRC eFUSE disabled and PLL in bypass. 30 –32 13 ms
33.33 –27 13 ms
60 –9 25 ms
128 KB CRC eFUSE enabled and PLL enabled.(2) 30 –19 9 ms
33.33 –16 12 ms
60 –3 25 ms
128 KB CRC eFUSE enabled and PLL in bypass.(2) 30 –830 –788 ms
33.33 –746 –705 ms
60 –408 –374 ms
Notes:
1. Valid for power supply ramp times of less than 6 ms. For ramp times longer than 6 ms, see the BootROM Performance section of the
Zynq-7000 SoC Technical Reference Manual (UG585).
2. If any PS and PL power supplies are tied together, observe the PS_POR_B assertion time requirement (TPSPOR) in Table 22 and its
accompanying note.
Table 24: Processor Configuration Access Port Switching Characteristics
Symbol Description Min Typ Max Units
FPCAPCK Maximum processor configuration access port (PCAP)
frequency ––100 MHz
Table 25: DDR3 Interface Switching Characteristics (1066 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 450 ps
TDQDS(3) Output DQ to DQS skew 131 ps
TDQDH(4) Output DQS to DQ skew 288 ps
TDQSS Output clock to DQS skew –0.11 0.09 TCK
TCACK(5) Command/address output setup time with respect to CLK 532 ps
TCKCA(6) Command/address output hold time with respect to CLK 637 ps
Notes:
1. Recommended VCCO_DDR =1.55%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
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Product Specification 18
Table 26: DDR3 Interface Switching Characteristics (800 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 232 ps
TDQDH(4) Output DQS to DQ skew 401 ps
TDQSS Output clock to DQS skew –0.10 0.06 TCK
TCACK(5) Command/address output setup time with respect to CLK 722 ps
TCKCA(6) Command/address output hold time with respect to CLK 882 ps
Notes:
1. Recommended VCCO_DDR =1.55%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 27: DDR3L Interface Switching Characteristics (1066 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 450 ps
TDQDS(3) Output DQ to DQS skew 189 ps
TDQDH(4) Output DQS to DQ skew 267 ps
TDQSS Output clock to DQS skew –0.13 0.04 TCK
TCACK(5) Command/address output setup time with respect to CLK 410 ps
TCKCA(6) Command/address output hold time with respect to CLK 629 ps
Notes:
1. Recommended VCCO_DDR = 1.35V ±5%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)
to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 28: DDR3L Interface Switching Characteristics (800 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 321 ps
TDQDH(4) Output DQS to DQ skew 380 ps
TDQSS Output clock to DQS skew –0.12 0.04 TCK
TCACK(5) Command/address output setup time with respect to CLK 636 ps
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 19
TCKCA(6) Command/address output hold time with respect to CLK 853 ps
Notes:
1. Recommended VCCO_DDR = 1.35V ±5%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 29: LPDDR2 Interface Switching Characteristics (800 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 196 ps
TDQDH(4) Output DQS to DQ skew 328 ps
TDQSS Output clock to DQS skew 0.90 1.06 TCK
TCACK(5) Command/address output setup time with respect to CLK 202 ps
TCKCA(6) Command/address output hold time with respect to CLK 353 ps
Notes:
1. Recommended VCCO_DDR =1.25%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)
to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 30: LPDDR2 Interface Switching Characteristics (400 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 664 ps
TDQDH(4) Output DQS to DQ skew 766 ps
TDQSS Output clock to DQS skew 0.90 1.06 TCK
TCACK(5) Command/address output setup time with respect to CLK 731 ps
TCKCA(6) Command/address output hold time with respect to CLK 907 ps
Notes:
1. Recommended VCCO_DDR =1.25%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)
to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 28: DDR3L Interface Switching Characteristics (800 Mb/s)(1) (Cont’d)
Symbol Description Min Max Units
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 20
Table 31: DDR2 Interface Switching Characteristics (800 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 147 ps
TDQDH(4) Output DQS to DQ skew 376 ps
TDQSS Output clock to DQS skew –0.07 0.08 TCK
TCACK(5) Command/address output setup time with respect to CLK 732 ps
TCKCA(6) Command/address output hold time with respect to CLK 938 ps
Notes:
1. Recommended VCCO_DDR =1.85%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Table 32: DDR2 Interface Switching Characteristics (400 Mb/s)(1)
Symbol Description Min Max Units
TDQVALID(2) Input data valid window 500 ps
TDQDS(3) Output DQ to DQS skew 385 ps
TDQDH(4) Output DQS to DQ skew 662 ps
TDQSS Output clock to DQS skew –0.11 0.06 TCK
TCACK(5) Command/address output setup time with respect to CLK 1760 ps
TCKCA(6) Command/address output hold time with respect to CLK 1739 ps
Notes:
1. Recommended VCCO_DDR =1.85%.
2. Measurement is taken from VREF to VREF.
3. Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.
4. Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.
5. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses
VIL(AC) to VREF of CLK.
6. Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crosses
VIH(DC) to VREF of CLK.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 21
X-Ref Target - Figure 2
Figure 2: DDR Output Timing Diagram
X-Ref Target - Figure 3
Figure 3: DDR Input Timing Diagram
Write NOP NOP NOP NOP
Bank, Col n
D0 D1 D3
TDQDH
TDQDS
TDQDH
TDQDS
TDQSS
TCKCA
TCACK
TCKCA
TCACK
DS187_01_012213
CLK
CLK
Command
Address
DQS
DQS
DQ D2
D0 D1 D2 D3
T
DQVALID
CLK
CLK
DQS
DQS
DQ
DS187_02_012213
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 22
Static Memory Controller
Table 33: SMC Interface Delay Characteristics(1)(2)
Symbol Description Min Max Units
TNANDDOUT NAND_IO output delay from last register to pad 4.12 6.45 ns
TNANDALE NAND_ALE output delay from last register to pad 5.08 6.33 ns
TNANDCLE NAND_CLE output delay from last register to pad 4.87 6.40 ns
TNANDWE NAND_WE_B output delay from last register to pad 4.69 5.89 ns
TNANDRE NAND_RE_B output delay from last register to pad 5.12 6.44 ns
TNANDCE NAND_CE_B output delay from last register to pad 4.68 5.89 ns
TNANDDIN NAND_IO setup time and input delay from pad to first register 1.48 3.09 ns
TNANDBUSY NAND_BUSY setup time and input delay from pad to first register 2.48 3.33 ns
TSRAMA SRAM_A output delay from last register to pad 3.94 5.73 ns
TSRAMDOUT SRAM_DQ output delay from last register to pad 4.66 6.45 ns
TSRAMCE SRAM_CE output delay from last register to pad 4.57 5.95 ns
TSRAMOE SRAM_OE_B output delay from last register to pad 4.79 6.13 ns
TSRAMBLS SRAM_BLS_B output delay from last register to pad 5.25 6.74 ns
TSRAMWE SRAM_WE_B output delay from last register to pad 5.12 6.48 ns
TSRAMDIN SRAM_DQ setup time and input delay from pad to first register 1.93 3.05 ns
TSRAMWAIT SRAM_WAIT setup time and input delay from pad to first register 2.26 3.15 ns
FSMC_REF_CLK SMC reference clock frequency 100 MHz
Notes:
1. All parameters do not include the package flight time and register controlled delays.
2. Refer to the ARM® PrimeCell® Static Memory Controller (PL350 series) Technical Reference Manual for more SMC timing details.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 23
Quad-SPI Interfaces
Table 34: Quad-SPI Interface Switching Characteristics
Symbol Description Load
Conditions Min Max Units
Feedback Clock Enabled
TDCQSPICLK1 Quad-SPI clock duty cycle All(1)(2) 44 56 %
TQSPICKO1 Data and slave select output delay 15 pF(1) –0.10(3) 2.30 ns
30 pF(2) –1.00 3.80
TQSPIDCK1 Input data setup time 15 pF(1) 2.00 ns
30 pF(2) 3.30 –
TQSPICKD1 Input data hold time 15 pF(1) 1.30 ns
30 pF(2) 1.50 –
TQSPISSCLK1 Slave select asserted to next clock edge All(1)(2) 1–F
QSPI_REF_CLK cycle
TQSPICLKSS1 Clock edge to slave select deasserted All(1)(2) 1–F
QSPI_REF_CLK cycle
FQSPICLK1 Quad-SPI device clock frequency 15 pF(1) – 100(4)
MHz
30 pF(2) –70
(4)
Feedback Clock Disabled
TDCQSPICLK2 Quad-SPI clock duty cycle All(1)(2) 44 56 %
TQSPICKO2 Data and slave select output delay 15 pF(1) –0.10 3.80 ns
30 pF(2) –1.00 3.80 ns
TQSPIDCK2 Input data setup time All(1)(2) 6–ns
TQSPICKD2 Input data hold time All(1)(2) 12.5 – ns
TQSPISSCLK2 Slave select asserted to next clock edge All(1)(2) 1–F
QSPI_REF_CLK cycle
TQSPICLKSS2 Clock edge to slave select deasserted All(1)(2) 1–F
QSPI_REF_CLK cycle
FQSPICLK2 Quad-SPI device clock frequency All(1)(2) –40MHz
Feedback Clock Enabled or Disabled
FQSPI_REF_CLK Quad-SPI reference clock frequency All(1)(2) –200MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, feedback clock pin has no load. Quad-SPI single slave select
4-bit I/O mode.
2. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 30 pF loads in 4-bit stacked I/O configuration, feedback clock pin has no
load. Quad-SPI single slave select 4-bit I/O mode.
3. The TQSPICKO1 is an effective value. Use it to compute the available memory device input setup and hold timing budgets based on the given
device clock-out duty-cycle limits.
4. Requires appropriate component selection/board design.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 24
X-Ref Target - Figure 4
Figure 4: Quad-SPI Interface (Feedback Clock Enabled) Timing Diagram
X-Ref Target - Figure 5
Figure 5: Quad-SPI Interface (Feedback Clock Disabled) Timing Diagram
QSPI{1,0}_SS_B
QSPI_SCLK_OUT
CPOL = 0
QSPI{1,0}_IO_[3,0]
QSPI_SCLK_OUT
CPOL = 1
DS187_03_110515
TQSPICKO1
TQSPISSCLK1
TQSPISSCLK1
TQSPICLKSS1
TQSPICLKSS1
TQSPIDCK1
TQSPICKD1
OUT1OUT0 INn-2 INn-1 INn
OUT0 OUT1 INn-1
QSPI{1,0}_SS_B
QSPI_SCLK_OUT
(CPOL = 0)
QSPI_SCLK_OUT
(CPOL = 1)
QSPI{0,1}_IO_[3:0]
T
QSPICKD2
T
QSPIDCK2
T
QSPICKO2
T
QSPICLKSS2
T
QSPISSCLK2
T
QSPICLKSS2
T
QSPISSCLK2
INn
DS187_04_110515
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 25
ULPI Interfaces
Table 35: ULPI Interface Clock Receiving Mode Switching Characteristics(1)(2)
Symbol Description Min Typ Max Units
TULPIDCK Input setup to ULPI clock, all inputs 3.00 ns
TULPICKD Input hold to ULPI clock, all inputs 1.00 ns
TULPICKO ULPI clock to output valid, all outputs 1.70 8.86 ns
FULPICLK ULPI device clock frequency 60 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, 60 MHz device clock frequency.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 6
Figure 6: ULPI Interface Timing Diagram
TULPICKO
TULPICKO
TULPICKD
TULPIDCK
TULPICKD
TULPIDCK
USB{0,1}_ULPI_CLK
USB{0,1}_ULPI_DATA[7:0] (Input)
USB{0,1}_ULPI_DIR,
USB{0,1}_ULPI_NXT
USB{0,1}_ULPI_STP
USB{0,1}_ULPI_DATA[7:0] (Output)
DS187_05_021013
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 26
RGMII and MDIO Interfaces
Table 36: RGMII and MDIO Interface Switching Characteristics(1)(2)(3)
Symbol Description Min Typ Max Units
TDCGETXCLK Transmit clock duty cycle 45 55 %
TGEMTXCKO RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time –0.50 0.50 ns
TGEMRXDCK RGMII_RX_D[3:0], RGMII_RX_CTL input setup time 0.80 ns
TGEMRXCKD RGMII_RX_D[3:0], RGMII_RX_CTL input hold time 0.80 ns
TMDIOCLK MDC output clock period 400 ns
TMDIOCKH MDC clock High time 160 ns
TMDIOCKL MDC clock Low time 160 ns
TMDIODCK MDIO input data setup time 80 ns
TMDIOCKD MDIO input data hold time 0 ns
TMDIOCKO MDIO data output delay –20 170 ns
FGETXCLK RGMII_TX_CLK transmit clock frequency 125 MHz
FGERXCLK RGMII_RX_CLK receive clock frequency 125 MHz
FENET_REF_CLK Ethernet reference clock frequency 125 MHz
Notes:
1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads. Values in this table are specified during 1000 Mb/s operation.
2. LVCMOS25 slow slew rate and LVCMOS33 are not supported.
3. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 7
Figure 7: RGMII Interface Timing Diagram
RGMII_TX_CLK
MDIO_CLK
RGMII_RX_CLK
TGEMTXCKO
TMDIOCKH TMDIOCLK TMDIOCKL
TGEMRXCKD
RGMII_TX_D[3:0]
RGMII_TX_CTL
RGMII_RX_D[3:0]
RGMII_RX_CTL
TGEMRXDCK
TMDIOCKD
MDIO_IO (Input)
TMDIODCK
DS187_06_021013
MDIO_IO (Output)
TMDIOCKO
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 27
SD/SDIO Interfaces
Table 37: SD/SDIO Interface High Speed Mode Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCSDHSCLK SD device clock duty cycle 50 %
TSDHSCKO Clock to output delay, all outputs 2.00 12.00 ns
TSDHSDCK Input setup time, all inputs 3.00 ns
TSDHSCKD Input hold time, all inputs 1.05 ns
FSD_REF_CLK SD reference clock frequency 125 MHz
FSDHSCLK High speed mode SD device clock frequency 0 50 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 8
Figure 8: SD/SDIO Interface High Speed Mode Timing Diagram
Table 38: SD/SDIO Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCSDSCLK SD device clock duty cycle 50 %
TSDSCKO Clock to output delay, all outputs 2.00 12.00 ns
TSDSDCK Input setup time, all inputs 4.00 ns
TSDSCKD Input hold time, all inputs 3.00 ns
FSD_REF_CLK SD reference clock frequency 125 MHz
FSDIDCLK Clock frequency in identification mode 400 KHz
FSDSCLK Standard mode SD device clock frequency 0 25 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 9
Figure 9: SD/SDIO Interface Standard Mode Timing Diagram
TSDHSCKO
TSDHSCKD
TSDHSDCK
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
DS187_07_021013
DS191_108_030113
TSDSCKO
TSDSCKD
TSDSDCK
SD{0,1}_CLK
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (input)
SD{0,1}_DATA[3:0],
SD{0,1}_CMD (output)
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 28
I2C Interfaces
Table 39: I2C Fast Mode Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCI2CFCLK I2C{0,1}SCL duty cycle 50 %
TI2CFCKO I2C{0,1}SDAO clock to out delay 900 ns
TI2CFDCK I2C{0,1}SDAI setup time 100 ns
FI2CFCLK I2C{0,1}SCL clock frequency 400 KHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 10
Figure 10: I2C Fast Mode Interface Timing Diagram
Table 40: I2C Standard Mode Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCI2CSCLK I2C{0,1}SCL duty cycle 50 %
TI2CSCKO I2C{0,1}SDAO clock to out delay 3450 ns
TI2CSDCK I2C{0,1}SDAI setup time 250 ns
FI2CSCLK I2C{0,1}SCL clock frequency 100 KHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 11
Figure 11: I2C Standard Mode Interface Timing Diagram
TI2CFCKO
TI2CFDCK
DS187_08_021013
I2C{0,1}SCL
I2C{0,1}SDAI
I2C{0,1}SDAO
TI2CSCKO
TI2CSDCK
DS187_09_021013
I2C{0,1}SCL
I2C{0,1}SDAI
I2C{0,1}SDAO
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 29
SPI Interfaces
Table 41: SPI Master Mode Interface Switching Characteristics(1)
Symbol Description Min Typ Max Units
TDCMSPICLK SPI master mode clock duty cycle 50 %
TMSPIDCK Input setup time for SPI{0,1}_MISO 2.00 – ns
TMSPICKD Input hold time for SPI{0,1}_MISO 8.20 – ns
TMSPICKO Output delay for SPI{0,1}_MOSI and SPI{0,1}_SS –3.10 – 3.90 ns
TMSPISSCLK Slave select asserted to first active clock edge 1 FSPI_REF_CLK cycles
TMSPICLKSS Last active clock edge to slave select deasserted 0.5 FSPI_REF_CLK cycles
FMSPICLK SPI master mode device clock frequency 50.00 MHz
FSPI_REF_CLK SPI reference clock frequency 200.00 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
X-Ref Target - Figure 12
Figure 12: SPI Master (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 13
Figure 13: SPI Master (CPHA = 1) Interface Timing Diagram
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2
T
MSPICKD
T
MSPIDCK
T
MSPICKO
T
MSPICLKSS
T
MSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_10_021013
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2 Dn–3D0
TMSPICKD
TMSPIDCK
TMSPICKO
TMSPICLKSS
TMSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_11_021013
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 30
Table 42: SPI Slave Mode Interface Switching Characteristics(1)(2)
Symbol Description Min Max Units
TSSPIDCK Input setup time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – FSPI_REF_CLK cycles
TSSPICKD Input hold time for SPI{0,1}_MOSI and SPI{0,1}_SS 1 – FSPI_REF_CLK cycles
TSSPICKO Output delay for SPI{0,1}_MISO 0 2.6 FSPI_REF_CLK cycles
TSSPISSCLK Slave select asserted to first active clock edge 1 FSPI_REF_CLK cycles
TSSPICLKSS Last active clock edge to slave select deasserted 1 FSPI_REF_CLK cycles
FSSPICLK SPI slave mode device clock frequency 25 MHz
FSPI_REF_CLK SPI reference clock frequency 200 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 14
Figure 14: SPI Slave (CPHA = 0) Interface Timing Diagram
X-Ref Target - Figure 15
Figure 15: SPI Slave (CPHA = 1) Interface Timing Diagram
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2 Dn–3D0
T
SSPICKO
T
SSPICKD
T
SSPIDCK
T
SSPICLKSS
T
SSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_12_021013
Dn Dn–1 Dn–2 Dn–3D0
Dn Dn–1 Dn–2 Dn–3D0
TSSPICKO
TSSPICKD
TSSPIDCK
TSSPICLKSS
TSSPISSCLK
SPI{0,1}_SS
SPI{0,1}_CLK (CPOL=0)
SPI{0,1}_CLK (CPOL=1)
SPI{0,1}_MOSI
SPI{0,1}_MISO
DS187_13_021013
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 31
CAN Interfaces
PJTAG Interfaces
UART Interfaces
Table 43: CAN Interface Switching Characteristics(1)
Symbol Description Min Max Units
TPWCANRX Minimum receive pulse width 1 µs
TPWCANTX Minimum transmit pulse width 1 µs
FCAN_REF_CLK
Internally sourced CAN reference clock frequency 100 MHz
Externally sourced CAN reference clock frequency 40 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
Table 44: PJTAG Interface(1)(2)
Symbol Description Min Max Units
TPJTAGDCK PJTAG input setup time 2.4 ns
TPJTAGCKD PJTAG input hold time 2.0 ns
TPJTAGCKO PJTAG clock to out delay 12.5 ns
TPJTAGCLK PJTAG clock frequency 20 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
2. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
X-Ref Target - Figure 16
Figure 16: PJTAG Interface Timing Diagram
Table 45: UART Interface Switching Characteristics(1)
Symbol Description Min Max Units
BAUDTXMAX Maximum transmit baud rate 1 Mb/s
BAUDRXMAX Maximum receive baud rate 1 Mb/s
FUART_REF_CLK UART reference clock frequency 100 MHz
Notes:
1. Test conditions: LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 32
GPIO Interfaces
Trace Interface
Triple Timer Counter Interface
Watchdog Timer
Table 46: GPIO Banks Switching Characteristics(1)
Symbol Description Min Max Units
TPWGPIOH Input high pulse width 10 x 1/cpu1x µs
TPWGPIOL Input low pulse width 10 x 1/cpu1x µs
Notes:
1. Pulse width requirement for interrupt.
X-Ref Target - Figure 17
Figure 17: GPIO Interface Timing Diagram
Table 47: Trace Interface Switching Characteristics(1)
Symbol Description Min Max Units
TTCECKO Trace clock to output delay, all outputs –1.4 1.5 ns
TDCTCECLK Trace clock duty cycle 40 60 %
FTCECLK Trace clock frequency 80 MHz
Notes:
1. Test conditions: LVCMOS25, fast slew rate, 8 mA drive strength, 15 pF loads.
Table 48: Triple Timer Counter interface Switching Characteristics(1)
Symbol Description Min Max Units
TPWTTCOCLK Triple timer counter output clock pulse width 2 x 1/cpu1x ns
FTTCOCLK Triple timer counter output clock frequency cpu1x/4 MHz
TTTCICLKH Triple timer counter input clock high pulse width 1.5 x 1/cpu1x ns
TTTCICLKL Triple timer counter input clock low pulse width 1.5 x 1/cpu1x ns
FTTCICLK Triple timer counter input clock frequency cpu1x/3 MHz
Notes:
1. All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional external clock jitter.
Table 49: Watchdog Timer Switching Characteristics
Symbol Description Min Max Units
FWDTCLK(1) Watchdog timer input clock frequency 10 MHz
Notes:
1. Applies to external input clock through MIO pin only.
T
PWGPIOL
T
PWGPIOH
GPIO
DS187_15_021013
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 33
PL Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in the PL. The
numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same
guidelines as the AC Switching Characteristics, page 13.
Table 50: PL Networking Applications Interface Performances
Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) 680 680 600 600 Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) 1250 1250 950 950 Mb/s
SDR LVDS receiver (SFI-4.1)(1) 680 680 600 600 Mb/s
DDR LVDS receiver (SPI-4.2)(1) 1250 1250 950 950 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Table 51: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator(1)(2)
Memory Standard Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
4:1 Memory Controllers
DDR3 1066(3) 800 800 667 Mb/s
DDR3L 800 800 667 N/A Mb/s
DDR2 800 800 667 533 Mb/s
2:1 Memory Controllers
DDR3 800 700 620 620 Mb/s
DDR3L 800 700 620 N/A Mb/s
DDR2 800 700 620 533 Mb/s
LPDDR2 667 667 533 400 Mb/s
Notes:
1. VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User
Guide (UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. The maximum PHY rate is 800 Mb/s in bank 13 of the XC7Z015, XC7Z020, XA7Z020, and XQ7Z020 devices.
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 34
PL Switching Characteristics
IOB Pad Input/Output/3-State
Table 52 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based
on standard), and 3-state delays.
•T
IOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
•T
IOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
•T
IOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM
termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
Table 52: IOB High Range (HR) Switching Characteristics
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3 -2 -1C/-1I/
-1LI -1Q -3 -2 -1C/-1I/
-1LI -1Q -3 -2 -1C/-1I/
-1LI -1Q
LVTTL_S4 1.26 1.34 1.41 1.53 3.80 3.93 4.18 4.18 3.82 3.96 4.20 4.20 ns
LVTTL_S8 1.26 1.34 1.41 1.53 3.54 3.66 3.92 3.92 3.56 3.69 3.93 3.93 ns
LVTTL_S12 1.261.341.411.533.523.653.903.903.543.683.913.91 ns
LVTTL_S16 1.261.341.411.533.073.193.453.453.093.223.463.46 ns
LVTTL_S24 1.261.341.411.533.293.413.673.673.313.443.683.68 ns
LVTTL_F4 1.26 1.34 1.41 1.53 3.26 3.38 3.64 3.64 3.28 3.41 3.65 3.65 ns
LVTTL_F8 1.26 1.34 1.41 1.53 2.74 2.87 3.12 3.12 2.76 2.90 3.13 3.13 ns
LVTTL_F12 1.261.341.411.532.732.853.103.102.742.883.123.12 ns
LVTTL_F16 1.261.341.411.532.562.682.932.932.572.712.952.95 ns
LVTTL_F24 1.261.341.411.532.522.652.903.232.542.682.913.24 ns
LVDS_25 0.730.810.880.891.291.411.671.671.311.441.681.68 ns
MINI_LVDS_25 0.73 0.81 0.88 0.89 1.27 1.40 1.65 1.65 1.29 1.43 1.66 1.66 ns
BLVDS_25 0.73 0.81 0.88 0.88 1.84 1.96 2.21 2.76 1.85 1.99 2.23 2.77 ns
RSDS_25
(point to point) 0.73 0.81 0.88 0.89 1.27 1.40 1.65 1.65 1.29 1.43 1.66 1.66 ns
PPDS_25 0.73 0.81 0.88 0.89 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns
TMDS_33 0.730.810.880.921.411.541.791.791.431.571.801.80 ns
PCI33_3 1.24 1.32 1.39 1.52 3.10 3.22 3.48 3.48 3.12 3.25 3.49 3.49 ns
HSUL_12_S 0.67 0.75 0.82 0.88 1.81 1.93 2.18 2.18 1.82 1.96 2.20 2.20 ns
HSUL_12_F 0.67 0.75 0.82 0.88 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns
DIFF_HSUL_12_S 0.68 0.76 0.83 0.86 1.81 1.93 2.18 2.18 1.82 1.96 2.20 2.20 ns
DIFF_HSUL_12_F 0.68 0.76 0.83 0.86 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns
MOBILE_DDR_S 0.760.840.910.911.681.802.062.061.701.832.072.07 ns
MOBILE_DDR_F 0.760.840.910.911.381.511.761.761.401.541.771.77 ns
DIFF_MOBILE_DDR_S 0.70 0.78 0.85 0.85 1.70 1.82 2.07 2.07 1.71 1.85 2.09 2.09 ns
DIFF_MOBILE_DDR_F 0.70 0.78 0.85 0.85 1.45 1.57 1.82 1.82 1.46 1.60 1.84 1.84 ns
HSTL_I_S 0.67 0.75 0.82 0.86 1.62 1.74 1.99 1.99 1.63 1.77 2.01 2.01 ns
HSTL_II_S 0.65 0.73 0.80 0.86 1.41 1.54 1.79 1.79 1.43 1.57 1.80 1.81 ns
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Product Specification 35
HSTL_I_18_S 0.67 0.75 0.82 0.88 1.29 1.41 1.67 1.67 1.31 1.44 1.68 1.68 ns
HSTL_II_18_S 0.66 0.75 0.81 0.88 1.41 1.54 1.79 1.79 1.43 1.57 1.80 1.80 ns
DIFF_HSTL_I_S 0.68 0.76 0.83 0.86 1.59 1.71 1.96 1.96 1.60 1.74 1.98 1.98 ns
DIFF_HSTL_II_S 0.68 0.76 0.83 0.86 1.511.631.881.881.521.661.901.90 ns
DIFF_HSTL_I_18_S 0.71 0.79 0.86 0.86 1.38 1.51 1.76 1.76 1.40 1.54 1.77 1.77 ns
DIFF_HSTL_II_18_S 0.70 0.78 0.85 0.88 1.46 1.58 1.84 1.84 1.48 1.61 1.85 1.85 ns
HSTL_I_F 0.67 0.75 0.82 0.86 1.10 1.22 1.48 1.49 1.12 1.25 1.49 1.51 ns
HSTL_II_F 0.65 0.73 0.80 0.86 1.12 1.24 1.49 1.49 1.13 1.27 1.51 1.51 ns
HSTL_I_18_F 0.67 0.75 0.82 0.88 1.13 1.26 1.51 1.54 1.15 1.29 1.52 1.56 ns
HSTL_II_18_F 0.66 0.75 0.81 0.88 1.12 1.24 1.49 1.51 1.13 1.27 1.51 1.52 ns
DIFF_HSTL_I_F 0.68 0.76 0.83 0.86 1.18 1.30 1.56 1.56 1.20 1.33 1.57 1.57 ns
DIFF_HSTL_II_F 0.68 0.76 0.83 0.86 1.211.331.591.591.231.361.601.60 ns
DIFF_HSTL_I_18_F 0.71 0.79 0.86 0.86 1.21 1.33 1.59 1.59 1.23 1.36 1.60 1.60 ns
DIFF_HSTL_II_18_F 0.70 0.78 0.85 0.88 1.21 1.33 1.59 1.59 1.23 1.36 1.60 1.60 ns
LVCMOS33_S4 1.26 1.34 1.41 1.52 3.80 3.93 4.18 4.18 3.82 3.96 4.20 4.20 ns
LVCMOS33_S8 1.26 1.34 1.41 1.52 3.52 3.65 3.90 3.90 3.54 3.68 3.91 3.91 ns
LVCMOS33_S12 1.26 1.34 1.41 1.52 3.09 3.21 3.46 3.46 3.10 3.24 3.48 3.48 ns
LVCMOS33_S16 1.26 1.34 1.41 1.52 3.40 3.52 3.77 3.78 3.42 3.55 3.79 3.79 ns
LVCMOS33_F4 1.26 1.34 1.41 1.52 3.26 3.38 3.64 3.64 3.28 3.41 3.65 3.65 ns
LVCMOS33_F8 1.26 1.34 1.41 1.52 2.74 2.87 3.12 3.12 2.76 2.90 3.13 3.13 ns
LVCMOS33_F12 1.26 1.34 1.41 1.52 2.56 2.68 2.93 2.93 2.57 2.71 2.95 2.95 ns
LVCMOS33_F16 1.26 1.34 1.41 1.52 2.56 2.68 2.93 3.06 2.57 2.71 2.95 3.07 ns
LVCMOS25_S4 1.12 1.20 1.27 1.38 3.13 3.26 3.51 3.51 3.15 3.29 3.52 3.52 ns
LVCMOS25_S8 1.12 1.20 1.27 1.38 2.88 3.01 3.26 3.26 2.90 3.04 3.27 3.27 ns
LVCMOS25_S12 1.12 1.20 1.27 1.38 2.48 2.60 2.85 2.85 2.49 2.63 2.87 2.87 ns
LVCMOS25_S16 1.12 1.20 1.27 1.38 2.82 2.94 3.20 3.20 2.84 2.97 3.21 3.21 ns
LVCMOS25_F4 1.12 1.20 1.27 1.38 2.74 2.87 3.12 3.12 2.76 2.90 3.13 3.13 ns
LVCMOS25_F8 1.12 1.20 1.27 1.38 2.18 2.30 2.56 2.56 2.20 2.33 2.57 2.57 ns
LVCMOS25_F12 1.12 1.20 1.27 1.38 2.16 2.29 2.54 2.54 2.18 2.32 2.55 2.56 ns
LVCMOS25_F16 1.12 1.20 1.27 1.38 2.01 2.13 2.39 2.63 2.03 2.16 2.40 2.65 ns
LVCMOS18_S4 0.74 0.83 0.89 0.97 1.62 1.74 1.99 1.99 1.63 1.77 2.01 2.01 ns
LVCMOS18_S8 0.74 0.83 0.89 0.97 2.18 2.30 2.56 2.56 2.20 2.33 2.57 2.57 ns
LVCMOS18_S12 0.74 0.83 0.89 0.97 2.18 2.30 2.56 2.56 2.20 2.33 2.57 2.57 ns
LVCMOS18_S16 0.74 0.83 0.89 0.97 1.52 1.65 1.90 1.90 1.54 1.68 1.91 1.91 ns
LVCMOS18_S24 0.74 0.83 0.89 0.97 1.60 1.72 1.98 2.40 1.62 1.75 1.99 2.41 ns
LVCMOS18_F4 0.74 0.83 0.89 0.97 1.45 1.57 1.82 1.82 1.46 1.60 1.84 1.84 ns
LVCMOS18_F8 0.74 0.83 0.89 0.97 1.68 1.80 2.06 2.06 1.70 1.83 2.07 2.07 ns
LVCMOS18_F12 0.74 0.83 0.89 0.97 1.68 1.80 2.06 2.06 1.70 1.83 2.07 2.07 ns
LVCMOS18_F16 0.74 0.83 0.89 0.97 1.40 1.52 1.77 1.78 1.42 1.55 1.79 1.79 ns
Table 52: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3 -2 -1C/-1I/
-1LI -1Q -3 -2 -1C/-1I/
-1LI -1Q -3 -2 -1C/-1I/
-1LI -1Q
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Product Specification 36
Table 53 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as
the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster
than TIOTPHZ when the INTERMDISABLE pin is used.
LVCMOS18_F24 0.74 0.83 0.89 0.97 1.34 1.46 1.71 2.28 1.35 1.49 1.73 2.29 ns
LVCMOS15_S4 0.77 0.86 0.93 0.96 2.05 2.18 2.43 2.43 2.07 2.21 2.45 2.45 ns
LVCMOS15_S8 0.77 0.86 0.93 0.96 2.09 2.21 2.46 2.46 2.10 2.24 2.48 2.48 ns
LVCMOS15_S12 0.77 0.86 0.93 0.96 1.59 1.71 1.96 1.96 1.60 1.74 1.98 1.98 ns
LVCMOS15_S16 0.77 0.86 0.93 0.96 1.59 1.71 1.96 1.96 1.60 1.74 1.98 1.98 ns
LVCMOS15_F4 0.77 0.86 0.93 0.96 1.85 1.97 2.23 2.23 1.87 2.00 2.24 2.24 ns
LVCMOS15_F8 0.77 0.86 0.93 0.96 1.60 1.72 1.98 1.98 1.62 1.75 1.99 1.99 ns
LVCMOS15_F12 0.77 0.86 0.93 0.96 1.35 1.47 1.73 1.73 1.37 1.50 1.74 1.74 ns
LVCMOS15_F16 0.77 0.86 0.93 0.96 1.34 1.46 1.71 2.07 1.35 1.49 1.73 2.09 ns
LVCMOS12_S4 0.87 0.95 1.02 1.19 2.57 2.69 2.95 2.95 2.59 2.72 2.96 2.96 ns
LVCMOS12_S8 0.87 0.95 1.02 1.19 2.09 2.21 2.46 2.46 2.10 2.24 2.48 2.48 ns
LVCMOS12_S12 0.87 0.95 1.02 1.19 1.79 1.91 2.17 2.17 1.81 1.94 2.18 2.18 ns
LVCMOS12_F4 0.87 0.95 1.02 1.19 1.98 2.10 2.35 2.35 1.99 2.13 2.37 2.37 ns
LVCMOS12_F8 0.87 0.95 1.02 1.19 1.54 1.66 1.92 1.92 1.56 1.69 1.93 1.93 ns
LVCMOS12_F12 0.87 0.95 1.02 1.19 1.38 1.51 1.76 1.76 1.40 1.54 1.77 1.77 ns
SSTL135_S 0.67 0.75 0.82 0.88 1.35 1.47 1.73 1.73 1.37 1.50 1.74 1.74 ns
SSTL15_S 0.600.680.750.751.301.431.681.711.321.461.691.73 ns
SSTL18_I_S 0.670.750.820.861.671.792.042.041.681.822.062.06 ns
SSTL18_II_S 0.67 0.75 0.82 0.88 1.31 1.43 1.68 1.68 1.32 1.46 1.70 1.70 ns
DIFF_SSTL135_S 0.68 0.76 0.83 0.88 1.35 1.47 1.73 1.73 1.37 1.50 1.74 1.74 ns
DIFF_SSTL15_S 0.68 0.76 0.83 0.88 1.30 1.43 1.68 1.71 1.32 1.46 1.69 1.73 ns
DIFF_SSTL18_I_S 0.71 0.79 0.86 0.88 1.68 1.80 2.06 2.06 1.70 1.83 2.07 2.07 ns
DIFF_SSTL18_II_S 0.71 0.79 0.86 0.88 1.38 1.51 1.76 1.76 1.40 1.54 1.77 1.77 ns
SSTL135_F 0.67 0.75 0.82 0.88 1.12 1.24 1.49 1.49 1.13 1.27 1.51 1.51 ns
SSTL15_F 0.600.680.750.751.071.191.451.451.091.221.461.46 ns
SSTL18_I_F 0.670.750.820.861.121.241.491.531.131.271.511.54 ns
SSTL18_II_F 0.67 0.75 0.82 0.88 1.12 1.24 1.49 1.51 1.13 1.27 1.51 1.52 ns
DIFF_SSTL135_F 0.68 0.76 0.83 0.88 1.12 1.24 1.49 1.49 1.13 1.27 1.51 1.51 ns
DIFF_SSTL15_F 0.68 0.76 0.83 0.88 1.07 1.19 1.45 1.45 1.09 1.22 1.46 1.46 ns
DIFF_SSTL18_I_F 0.71 0.79 0.86 0.88 1.23 1.35 1.60 1.60 1.24 1.38 1.62 1.62 ns
DIFF_SSTL18_II_F 0.71 0.79 0.86 0.88 1.21 1.33 1.59 1.59 1.23 1.36 1.60 1.60 ns
Table 52: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
-3 -2 -1C/-1I/
-1LI -1Q -3 -2 -1C/-1I/
-1LI -1Q -3 -2 -1C/-1I/
-1LI -1Q
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Product Specification 37
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 54 shows the test setup parameters used for measuring input delay.
Table 53: IOB 3-state Output Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TIOTPHZ T input to pad high-impedance 2.06 2.19 2.37 2.37 ns
TIOIBUFDISABLE IBUF turn-on time from IBUFDISABLE to O output 2.11 2.30 2.60 2.60 ns
Table 54: Input Delay Measurement Methodology
Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6
LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75
LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65
LVTTL, 3.3V LVTTL 0.1 3.2 1.65
MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9
PCI33, 3.3V PCI33_3 0.1 3.2 1.65
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 VREF –0.5 V
REF +0.5 V
REF 0.60
HSTL, Class I & II, 1.5V HSTL_I, HSTL_II VREF –0.65 V
REF +0.65 V
REF 0.75
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF –0.8 V
REF +0.8 V
REF 0.90
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL, 1.35V SSTL135, SSTL135_R VREF – 0.575 VREF + 0.575 VREF 0.675
SSTL, 1.5V SSTL15, SSTL15_R VREF –0.65 V
REF +0.65 V
REF 0.75
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF –0.8 V
REF +0.8 V
REF 0.90
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0(6)
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0(6)
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0(6)
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_SSTL, 1.2V DIFF_SSTL12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125 0(6)
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0(6)
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0(6)
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 0.9 – 0.125 0.9 + 0.125 0(6)
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Product Specification 38
Output Delay Measurements
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay
of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure 18 and Figure 19.
LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(6)
BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0(6)
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 18.
6. The value given is the differential input voltage.
X-Ref Target - Figure 18
Figure 18: Single-Ended Test Setup
X-Ref Target - Figure 19
Figure 19: Differential Test Setup
Table 54: Input Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
VREF
RREF
VMEAS
(Voltage Level When Taking
Delay Measurement)
CREF
(Probe Capacitance)
FPGA Output
DS187_20_090914
RREF VMEAS
+
CREF
FPGA Output
DS187_21_090914
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 39
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction
of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 55.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
Table 55: Output Delay Measurement Methodology
Description I/O Standard Attribute RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
LVCMOS/LVDCI/HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 1M 0 0.75 0
LVCMOS/LVDCI/HSLVDCI, 1.8V LVCMOS18, LVDCI_15, HSLVDCI_18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
PCI33, 3.3V PCI33_3 25 10 1.65 0
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 VREF 0.6
HSTL, Class I, 1.5V HSTL_I 50 0 VREF 0.75
HSTL, Class II, 1.5V HSTL_II 25 0 VREF 0.75
HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 VREF 0.6
SSTL12, 1.2V SSTL12 50 0 VREF 0.6
SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 VREF 0.675
SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 VREF 0.75
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
SSTL18_I, SSTL18_II 50 0 VREF 0.9
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 VREF 0.9
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6
DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 VREF 0.75
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 VREF 0.9
DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 VREF 0.6
DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 VREF 0.6
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 VREF 0.675
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 VREF 0.75
DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 100 0 0(2) 0
LVDS, 2.5V LVDS_25 100 0 0(2) 0
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0
Mini LVDS, 2.5V MINI_LVDS_25 100 0 0(2) 0
PPDS_25 PPDS_25 100 0 0(2) 0
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 40
Input/Output Logic Switching Characteristics
RSDS_25 RSDS_25 100 0 0(2) 0
TMDS_33 TMDS_33 50 0 0(2) 3.3
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
Table 56: ILOGIC Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Setup/Hold
TICE1CK/
TICKCE1
CE1 pin setup/hold with respect to CLK 0.48/0.02 0.54/0.02 0.76/0.02 0.76/0.02 ns
TISRCK/
TICKSR
SR pin setup/hold with respect to CLK 0.60/0.01 0.70/0.01 1.13/0.01 1.13/0.01 ns
TIDOCK/
TIOCKD
D pin setup/hold with respect to CLK without Delay 0.01/0.27 0.01/0.29 0.01/0.33 0.01/0.33 ns
TIDOCKD/
TIOCKDD
DDLY pin setup/hold with respect to CLK (using IDELAY) 0.02/0.27 0.02/0.29 0.02/0.33 0.02/0.33 ns
Combinatorial
TIDI D pin to O pin propagation delay, no Delay 0.11 0.11 0.13 0.13 ns
TIDID DDLY pin to O pin propagation delay (using IDELAY) 0.11 0.12 0.14 0.14 ns
Sequential Delays
TIDLO D pin to Q1 pin using flip-flop as a latch without Delay 0.41 0.44 0.51 0.51 ns
TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using
IDELAY) 0.41 0.44 0.51 0.51 ns
TICKQ CLK to Q outputs 0.53 0.57 0.66 0.66 ns
TRQ_ILOGIC SR pin to OQ/TQ out 0.96 1.08 1.32 1.32 ns
TGSRQ_ILOGIC Global set/reset to Q outputs 7.60 7.60 10.51 10.51 ns
Set/Reset
TRPW_ILOGIC Minimum pulse width, SR inputs 0.61 0.72 0.72 0.72 ns, Min
Table 57: OLOGIC Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Setup/Hold
TODCK/
TOCKD
D1/D2 pins setup/hold with respect to CLK 0.67/–0.11 0.71/–0.11 0.84/–0.11 0.84/–0.06 ns
TOOCECK/
TOCKOCE
OCE pin setup/hold with respect to CLK 0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 ns
TOSRCK/
TOCKSR
SR pin setup/hold with respect to CLK 0.37/0.21 0.44/0.21 0.80/0.21 0.80/0.21 ns
TOTCK/
TOCKT
T1/T2 pins setup/hold with respect to CLK 0.69/–0.14 0.73/–0.14 0.89/–0.14 0.89/–0.11 ns
Table 55: Output Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 41
Input Serializer/Deserializer Switching Characteristics
TOTCECK/
TOCKTCE
TCE pin setup/hold with respect to CLK 0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.01 ns
Combinatorial
TODQ D1 to OQ out or T1 to TQ out 0.83 0.96 1.16 1.16 ns
Sequential Delays
TOCKQ CLK to OQ/TQ out 0.47 0.49 0.56 0.56 ns
TRQ_OLOGIC SR pin to OQ/TQ out 0.72 0.80 0.95 0.95 ns
TGSRQ_OLOGIC Global set/reset to Q outputs 7.60 7.60 10.51 10.51 ns
Set/Reset
TRPW_OLOGIC Minimum pulse width, SR inputs 0.64 0.74 0.74 0.74 ns, Min
Table 58: ISERDES Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Setup/Hold for Control Lines
TISCCK_BITSLIP/
TISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV 0.01/0.14 0.02/0.15 0.02/0.17 0.02/0.17 ns
TISCCK_CE /
TISCKC_CE(2) CE pin setup/hold with respect to CLK (for CE1) 0.45/–0.01 0.50/–0.01 0.72/–0.01 0.72/–0.01 ns
TISCCK_CE2 /
TISCKC_CE2(2)
CE pin setup/hold with respect to CLKDIV (for
CE2) –0.10/0.33 –0.10/0.36 0.10/0.40 –0.10/0.40 ns
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D D pin setup/hold with respect to CLK 0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 ns
TISDCK_DDLY/
TISCKD_DDLY
DDLY pin setup/hold with respect to CLK (using
IDELAY)(1) –0.02/0.12 –0.02/0.14 0.02/0.17 –0.02/0.17 ns
TISDCK_D_DDR/
TISCKD_D_DDR
D pin setup/hold with respect to CLK at DDR
mode –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 ns
TISDCK_DDLY_DDR/
TISCKD_DDLY_DDR
D pin setup/hold with respect to CLK at DDR
mode (using IDELAY)(1) 0.12/0.12 0.14/0.14 0.17/0.17 0.17/0.17 ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.53 0.54 0.66 0.66 ns
Propagation Delays
TISDO_DO D input to DO output pin 0.11 0.11 0.13 0.13 ns
Notes:
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report.
Table 57: OLOGIC Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 42
Output Serializer/Deserializer Switching Characteristics
Input/Output Delay Switching Characteristics
Table 59: OSERDES Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Setup/Hold
TOSDCK_D/
TOSCKD_D
D input setup/hold with respect to CLKDIV 0.42/0.03 0.45/0.03 0.63/0.03 0.63/0.08 ns
TOSDCK_T/
TOSCKD_T(1)
T input setup/hold with respect to CLK 0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.13 ns
TOSDCK_T2/
TOSCKD_T2(1) T input setup/hold with respect to CLKDIV 0.31/–0.13 0.34/–0.13 0.39/–0.13 0.39/–0.13 ns
TOSCCK_OCE/
TOSCKC_OCE
OCE input setup/hold with respect to CLK 0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 ns
TOSCCK_S SR (reset) input setup with respect to CLKDIV 0.47 0.52 0.85 0.85 ns
TOSCCK_TCE/
TOSCKC_TCE
TCE input setup/hold with respect to CLK 0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 ns
Sequential Delays
TOSCKO_OQ Clock to out from CLK to OQ 0.40 0.42 0.48 0.48 ns
TOSCKO_TQ Clock to out from CLK to TQ 0.47 0.49 0.56 0.56 ns
Combinatorial
TOSDO_TTQ T input to TQ out 0.83 0.92 1.11 1.11 ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report.
Table 60: Input Delay Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
IDELAYCTRL
TDLYCCO_RDY Reset to ready for IDELAYCTRL 3.67 3.67 3.67 3.67 µs
FIDELAYCTRL_REF
Attribute REFCLK frequency = 200.0(1) 200 200 200 200 MHz
Attribute REFCLK frequency = 300.0(1) 300 300 N/A N/A MHz
Attribute REFCLK frequency = 400.0(1) 400 400 N/A N/A MHz
IDELAYCTRL_
REF_PRECISION REFCLK precision ±10 ±10 ±10 ±10 MHz
TIDELAYCTRL_RPW Minimum reset pulse width 59.28 59.28 59.28 59.28 ns
IDELAY
TIDELAYRESOLUTION IDELAY chain delay resolution 1/(32 x 2 x FREFs
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 43
TIDELAYPAT_JIT and
TODELAYPAT_JIT
Pattern dependent period jitter in delay chain for
clock pattern.(2) 0 0 0 0 ps per tap
Pattern dependent period
jitter in delay chain for
random data pattern
(PRBS 23)(3)
REFCLK 200 MHz ±5 ±5 ±5 ±5 ps per tap
REFCLK 300 MHz ±3.33 ±3.33 ±3.33 N/A ps per tap
REFCLK 400 MHz ±2.50 ±2.50 N/A N/A ps per tap
Pattern dependent period
jitter in delay chain for
random data pattern
(PRBS 23)(4)
REFCLK 200 MHz ±9.0 ±9.0 ±9.0 ±9.0 ps per tap
REFCLK 300 MHz ±6.0 ±6.0 ±6.0 N/A ps per tap
REFCLK 400 MHz ±4.5 ±4.5 N/A N/A ps per tap
TIDELAY_CLK_MAX Maximum frequency of CLK input to IDELAY 680.00 680.00 600.00 600.00 MHz
TIDCCK_CE / TIDCKC_CE CE pin setup/hold with respect to C for IDELAY 0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 ns
TIDCCK_INC/ TIDCKC_INC INC pin setup/hold with respect to C for IDELAY 0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 ns
TIDCCK_RST/ TIDCKC_RST RST pin setup/hold with respect to C for IDELAY 0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 ns
TIDDO_IDATAIN Propagation delay through IDELAY Note 5 Note 5 Note 5 Note 5 ps
Notes:
1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.
Table 61: IO_FIFO Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
IO_FIFO Clock to Out Delays
TOFFCKO_DO RDCLK to Q outputs 0.55 0.60 0.68 0.68 ns
TCKO_FLAGS Clock to IO_FIFO flags 0.55 0.61 0.77 0.77 ns
Setup/Hold
TCCK_D/TCKC_D D inputs to WRCLK 0.47/0.02 0.51/0.02 0.58/0.02 0.58/0.18 ns
TIFFCCK_WREN /
TIFFCKC_WREN
WREN to WRCLK 0.42/–0.01 0.47/–0.01 0.53/–0.01 0.53/–0.01 ns
TOFFCCK_RDEN/
TOFFCKC_RDEN
RDEN to RDCLK 0.53/0.02 0.58/0.02 0.66/0.02 0.66/0.02 ns
Minimum Pulse Width
TPWH_IO_FIFO RESET, RDCLK, WRCLK 1.62 2.15 2.15 2.15 ns
TPWL_IO_FIFO RESET, RDCLK, WRCLK 1.62 2.15 2.15 2.15 ns
Maximum Frequency
FMAX RDCLK and WRCLK 266.67 200.00 200.00 200.00 MHz
Table 60: Input Delay Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 44
CLB Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 62: CLB Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Combinatorial Delays
TILO An – Dn LUT address to A 0.10 0.11 0.13 0.13 ns, Max
TILO_2 An – Dn LUT address to AMUX/CMUX 0.27 0.30 0.36 0.36 ns, Max
TILO_3 An – Dn LUT address to BMUX_A 0.42 0.46 0.55 0.55 ns, Max
TITO An – Dn inputs to A – D Q outputs 0.94 1.05 1.27 1.27 ns, Max
TAXA AX inputs to AMUX output 0.62 0.69 0.84 0.84 ns, Max
TAXB AX inputs to BMUX output 0.58 0.66 0.83 0.83 ns, Max
TAXC AX inputs to CMUX output 0.60 0.68 0.82 0.82 ns, Max
TAXD AX inputs to DMUX output 0.68 0.75 0.90 0.90 ns, Max
TBXB BX inputs to BMUX output 0.51 0.57 0.69 0.69 ns, Max
TBXD BX inputs to DMUX output 0.62 0.69 0.82 0.82 ns, Max
TCXC CX inputs to CMUX output 0.42 0.48 0.58 0.58 ns, Max
TCXD CX inputs to DMUX output 0.53 0.59 0.71 0.71 ns, Max
TDXD DX inputs to DMUX output 0.52 0.58 0.70 0.70 ns, Max
Sequential Delays
TCKO Clock to AQ – DQ outputs 0.40 0.44 0.53 0.53 ns, Max
TSHCKO Clock to AMUX – DMUX outputs 0.47 0.53 0.66 0.66 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TAS/TAH AN – DN input to CLK on A – D flip-flops 0.07/0.12 0.09/0.14 0.11/0.18 0.11/0.28 ns, Min
TDICK/TCKDI
AX–D
X input to CLK on A – D flip-flops 0.06/0.19 0.07/0.21 0.09/0.26 0.09/0.35 ns, Min
AX–D
X input through MUXs and/or carry logic to
CLK on A – D flip-flops 0.59/0.08 0.66/0.09 0.81/0.11 0.81/0.20 ns, Min
TCECK_CLB/
TCKCE_CLB CE input to CLK on A – D flip-flops 0.15/0.00 0.17/0.00 0.21/0.01 0.21/0.13 ns, Min
TSRCK/TCKSR SR input to CLK on A – D flip-flops 0.38/0.03 0.43/0.04 0.53/0.05 0.53/0.18 ns, Min
Set/Reset
TSRMIN SR input minimum pulse width 0.52 0.78 1.04 1.04 ns, Min
TRQ Delay from SR input to AQ – DQ flip-flops 0.53 0.59 0.71 0.71 ns, Max
TCEO Delay from CE input to AQ – DQ flip-flops 0.52 0.58 0.70 0.70 ns, Max
FTOG Toggle frequency (for export control) 1412 1286 1098 1098 MHz
Table 63: CLB Distributed RAM Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Sequential Delays
TSHCKO(1) Clock to A – B outputs 0.98 1.09 1.32 1.32 ns, Max
TSHCKO_1 Clock to AMUX – BMUX outputs 1.37 1.53 1.86 1.86 ns, Max
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 45
CLB Shift Register Switching Characteristics (SLICEM Only)
Setup and Hold Times Before/After Clock CLK
TDS_LRAM/
TDH_LRAM A – D inputs to CLK 0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 ns, Min
TAS_LRAM/
TAH_LRAM
Address An inputs to clock 0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 ns, Min
Address An inputs through MUXs and/or carry
logic to clock
0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 ns, Min
TWS_LRAM/
TWH_LRAM WE input to clock 0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 ns, Min
TCECK_LRAM/
TCKCE_LRAM CE input to CLK 0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 ns, Min
Clock CLK
TMPW_LRAM Minimum pulse width 1.05 1.13 1.25 1.25 ns, Min
TMCP Minimum clock period 2.10 2.26 2.50 2.50 ns, Min
Notes:
1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
Table 64: CLB Shift Register Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Sequential Delays
TREG Clock to A – D outputs 1.19 1.33 1.61 1.61 ns, Max
TREG_MUX Clock to AMUX – DMUX output 1.58 1.77 2.15 2.15 ns, Max
TREG_M31 Clock to DMUX output via M31 output 1.12 1.23 1.46 1.46 ns, Max
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG/
TWH_SHFREG
WE input 0.37/0.10 0.41/0.12 0.51/0.17 0.51/0.17 ns, Min
TCECK_SHFREG/
TCKCE_SHFREG
CE input to CLK 0.37/0.10 0.42/0.11 0.52/0.17 0.52/0.17 ns, Min
TDS_SHFREG/
TDH_SHFREG
A – D inputs to CLK 0.33/0.34 0.37/0.37 0.44/0.43 0.44/0.44 ns, Min
Clock CLK
TMPW_SHFREG Minimum pulse width 0.77 0.86 0.98 0.98 ns, Min
Table 63: CLB Distributed RAM Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
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Product Specification 46
Block RAM and FIFO Switching Characteristics
Table 65: Block RAM and FIFO Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Block RAM and FIFO Clock to Out Delays
TRCKO_DO and
TRCKO_DO_REG(1)
Clock CLK to DOUT output (without output
register)(2)(3) 1.85 2.13 2.46 2.46 ns, Max
Clock CLK to DOUT output (with output
register)(4)(5) 0.64 0.74 0.89 0.89 ns, Max
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT output with ECC (without
output register)(2)(3) 2.77 3.04 3.84 3.84 ns, Max
Clock CLK to DOUT output with ECC (with
output register)(4)(5) 0.73 0.81 0.94 0.94 ns, Max
TRCKO_DO_CASCOUT and
TRCKO_DO_CASCOUT_REG
Clock CLK to DOUT output with cascade
(without output register)(2) 2.61 2.88 3.30 3.30 ns, Max
Clock CLK to DOUT output with cascade (with
output register)(4) 1.16 1.28 1.46 1.46 ns, Max
TRCKO_FLAGS Clock CLK to FIFO flags outputs(6) 0.76 0.87 1.05 1.05 ns, Max
TRCKO_POINTERS Clock CLK to FIFO pointers outputs(7) 0.94 1.02 1.15 1.15 ns, Max
TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode only
mode 0.78 0.85 0.94 0.94 ns, Max
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without output register) 2.56 2.81 3.55 3.55 ns, Max
Clock CLK to BITERR (with output register) 0.68 0.76 0.89 0.89 ns, Max
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC
(without output register) 0.75 0.88 1.07 1.07 ns, Max
Clock CLK to RDADDR output with ECC
(with output register) 0.84 0.93 1.08 1.08 ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA/
TRCKC_ADDRA ADDR inputs(8) 0.45/0.31 0.49/0.33 0.57/0.36 0.57/0.52 ns, Min
TRDCK_DI_WF_NC/
TRCKD_DI_WF_NC
Data input setup/hold time when block RAM is
configured in WRITE_FIRST or NO_CHANGE
mode(9)
0.58/0.60 0.65/0.63 0.74/0.67 0.74/0.67 ns, Min
TRDCK_DI_RF/
TRCKD_DI_RF
Data input setup/hold time when block RAM is
configured in READ_FIRST mode(9) 0.20/0.29 0.22/0.34 0.25/0.41 0.25/0.50 ns, Min
TRDCK_DI_ECC/
TRCKD_DI_ECC
DIN inputs with block RAM ECC in standard
mode(9) 0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 ns, Min
DIN inputs with block RAM ECC encode only(9) 0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 ns, Min
DIN inputs with FIFO ECC in standard mode(9) 1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 ns, Min
TRDCK_DI_ECCW/
TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only(9) 0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 ns, Min
TRDCK_DI_ECC_FIFO/
TRCKD_DI_ECC_FIFO DIN inputs with FIFO ECC in standard mode(9) 1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64
ns, Min
TRCCK_INJECTBITERR/
TRCKC_INJECTBITERR Inject single/double bit error in ECC mode 0.58/0.35 0.64/0.37 0.74/0.40 0.74/0.52 ns, Min
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 47
TRCCK_EN/
TRCKC_EN Block RAM enable (EN) input 0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 ns, Min
TRCCK_REGCE/
TRCKC_REGCE CE input of output register 0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 ns, Min
TRCCK_RSTREG/
TRCKC_RSTREG Synchronous RSTREG input 0.29/0.07 0.32/0.07 0.35/0.07 0.35/0.17 ns, Min
TRCCK_RSTRAM/
TRCKC_RSTRAM Synchronous RSTRAM input 0.32/0.42 0.34/0.43 0.36/0.46 0.36/0.57 ns, Min
TRCCK_WEA/
TRCKC_WEA Write enable (WE) input (block RAM only) 0.44/0.18 0.48/0.19 0.54/0.20 0.54/0.42 ns, Min
TRCCK_WREN/
TRCKC_WREN WREN FIFO inputs 0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 ns, Min
TRCCK_RDEN/
TRCKC_RDEN RDEN FIFO inputs 0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 ns, Min
Reset Delays
TRCO_FLAGS Reset RST to FIFO flags/pointers(10) 0.90 0.98 1.10 1.10 ns, Max
TRREC_RST/
TRREM_RST
FIFO reset recovery and removal timing(11) 1.87/–0.81 2.07/–0.81 2.37/–0.81 2.37/–0.58 ns, Max
Maximum Frequency
FMAX_BRAM_WF_NC
Block RAM (write first and no change modes)
When not in SDP RF mode. 509.68 460.83 388.20 388.20 MHz
FMAX_BRAM_RF_PERFORMA
NCE
Block RAM (read first, performance mode)
When in SDP RF mode but no address overlap
between port A and port B.
509.68 460.83 388.20 388.20 MHz
FMAX_BRAM_RF_DELAYED_
WRITE
Block RAM (read first, delayed write mode)
When in SDP RF mode and there is possibility
of overlap between port A and port B
addresses.
447.63 404.53 339.67 339.67 MHz
FMAX_CAS_WF_NC
Block RAM cascade (write first, no change
mode)
When cascade but not in RF mode.
467.07 418.59 345.78 345.78 MHz
FMAX_CAS_RF_PERFORMAN
CE
Block RAM cascade
(read first, performance mode)
When in cascade with RF mode and no
possibility of address overlap/one port is
disabled.
467.07 418.59 345.78 345.78 MHz
FMAX_CAS_RF_DELAYED_W
RITE
When in cascade RF mode and there is a
possibility of address overlap between port A
and port B.
405.35 362.19 297.35 297.35 MHz
Table 65: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 48
FMAX_FIFO FIFO in all modes without ECC 509.68 460.83 388.20 388.20 MHz
FMAX_ECC Block RAM and FIFO in ECC configuration 410.34 365.10 297.53 297.53 MHz
Notes:
1. The timing report shows all of these parameters as TRCKO_DO.
2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, and
TRCKO_WRERR.
7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
Table 65: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 49
DSP48E1 Switching Characteristics
Table 66: DSP48E1 Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK 0.26/0.12 0.30/0.13 0.37/0.14 0.37/0.28 ns
TDSPDCK_B_BREG/TDSPCKD_B_BREG B input to B register CLK 0.33/0.15 0.38/0.16 0.45/0.18 0.45/0.25 ns
TDSPDCK_C_CREG/TDSPCKD_C_CREG C input to C register CLK 0.17/0.17 0.20/0.19 0.24/0.21 0.24/0.26 ns
TDSPDCK_D_DREG/TDSPCKD_D_DREG D input to D register CLK 0.25/0.25 0.32/0.27 0.42/0.27 0.42/0.42 ns
TDSPDCK_ACIN_AREG/
TDSPCKD_ACIN_AREG ACIN input to A register CLK 0.23/0.12 0.27/0.13 0.32/0.14 0.32/0.17 ns
TDSPDCK_BCIN_BREG/
TDSPCKD_BCIN_BREG BCIN input to B register CLK 0.25/0.15 0.29/0.16 0.36/0.18 0.36/0.18 ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, B}_MREG_MULT/
TDSPCKD_{A, B}_MREG_MULT
{A, B} input to M register CLK
using multiplier 2.40/–0.01 2.76/–0.01 3.29/–0.01 3.29/–0.01 ns
TDSPDCK_{A, D}_ADREG/
TDSPCKD_ {A, D}_ADREG
{A, D} input to AD register CLK 1.29/–0.02 1.48/–0.02 1.76/–0.02 1.76/–0.02 ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT/
TDSPCKD_{A, B} _PREG_MULT
{A, B} input to P register CLK
using multiplier 4.02/–0.28 4.60/–0.28 5.48/–0.28 5.48/–0.28 ns
TDSPDCK_D_PREG_MULT/
TDSPCKD_D_PREG_MULT
D input to P register CLK using
multiplier 3.93/–0.73 4.50/–0.73 5.35/–0.73 5.35/–0.73 ns
TDSPDCK_{A, B} _PREG/
TDSPCKD_{A, B} _PREG
A or B input to P register CLK not
using multiplier 1.73/–0.28 1.98/–0.28 2.35/–0.28 2.35/–0.28 ns
TDSPDCK_C_PREG/
TDSPCKD_C_PREG
C input to P register CLK not
using multiplier 1.54/–0.26 1.76/–0.26 2.10/–0.26 2.10/–0.26 ns
TDSPDCK_PCIN_PREG/
TDSPCKD_PCIN_PREG PCIN input to P register CLK 1.32/–0.15 1.51/–0.15 1.80/–0.15 1.80/–0.15 ns
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA;CEB}_{AREG;BREG}/
TDSPCKD_{CEA;CEB}_{AREG;BREG}
{CEA; CEB} input to {A; B} register
CLK 0.35/0.06 0.42/0.08 0.52/0.11 0.52/0.11 ns
TDSPDCK_CEC_CREG/
TDSPCKD_CEC_CREG CEC input to C register CLK 0.28/0.10 0.34/0.11 0.42/0.13 0.42/0.13 ns
TDSPDCK_CED_DREG/
TDSPCKD_CED_DREG CED input to D register CLK 0.36/–0.03 0.43/–0.03 0.52/–0.03 0.52/–0.03 ns
TDSPDCK_CEM_MREG/
TDSPCKD_CEM_MREG CEM input to M register CLK 0.17/0.18 0.21/0.20 0.27/0.23 0.27/0.23 ns
TDSPDCK_CEP_PREG/
TDSPCKD_CEP_PREG CEP input to P register CLK 0.36/0.01 0.43/0.01 0.53/0.01 0.53/0.01 ns
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/
TDSPCKD_{RSTA; RSTB}_{AREG; BREG}
{RSTA, RSTB} input to {A, B}
register CLK 0.41/0.11 0.46/0.13 0.55/0.15 0.55/0.24 ns
TDSPDCK_RSTC_CREG/
TDSPCKD_RSTC_CREG RSTC input to C register CLK 0.07/0.10 0.08/0.11 0.09/0.12 0.09/0.25 ns
TDSPDCK_RSTD_DREG/
TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.44/0.07 0.50/0.08 0.59/0.09 0.59/0.09 ns
TDSPDCK_RSTM_MREG/
TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.21/0.22 0.23/0.24 0.27/0.28 0.27/0.28 ns
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 50
TDSPDCK_RSTP_PREG/
TDSPCKD_RSTP_PREG RSTP input to P register CLK 0.27/0.01 0.30/0.01 0.35/0.01 0.35/0.03 ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output
using multiplier 3.79 4.35 5.18 5.18 ns
TDSPDO_D_P_MULT D input to P output using multiplier 3.72 4.26 5.07 5.07 ns
TDSPDO_A_P A input to P output not using
multiplier 1.53 1.75 2.08 2.08 ns
TDSPDO_C_P C input to P output 1.33 1.53 1.82 1.82 ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT}
output 0.55 0.63 0.74 0.74 ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT
{A, B} input to CARRYCASCOUT
output using multiplier 4.06 4.65 5.54 5.54 ns
TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT
output using multiplier 3.97 4.54 5.40 5.40 ns
TDSPDO_{A, B}_CARRYCASCOUT
{A, B} input to CARRYCASCOUT
output not using multiplier 1.77 2.03 2.41 2.41 ns
TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT
output 1.58 1.81 2.15 2.15 ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT ACIN input to P output using
multiplier 3.65 4.19 5.00 5.00 ns
TDSPDO_ACIN_P ACIN input to P output not using
multiplier 1.37 1.57 1.88 1.88 ns
TDSPDO_ACIN_ACOUT ACIN input to ACOUT output 0.38 0.44 0.53 0.53 ns
TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to CARRYCASCOUT
output using multiplier 3.90 4.47 5.33 5.33 ns
TDSPDO_ACIN_CARRYCASCOUT ACIN input to CARRYCASCOUT
output not using multiplier 1.61 1.85 2.21 2.21 ns
TDSPDO_PCIN_P PCIN input to P output 1.11 1.28 1.52 1.52 ns
TDSPDO_PCIN_CARRYCASCOUT PCIN input to CARRYCASCOUT
output 1.36 1.56 1.85 1.85 ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG CLK PREG to P output 0.33 0.37 0.44 0.44 ns
TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT
output 0.52 0.59 0.69 0.69 ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG CLK MREG to P output 1.68 1.93 2.31 2.31 ns
TDSPCKO_CARRYCASCOUT_MREG CLK MREG to CARRYCASCOUT
output 1.92 2.21 2.64 2.64 ns
TDSPCKO_P_ADREG_MULT CLK ADREG to P output using
multiplier 2.72 3.10 3.69 3.69 ns
TDSPCKO_CARRYCASCOUT_ADREG_MULT
CLK ADREG to
CARRYCASCOUT output using
multiplier
2.96 3.38 4.02 4.02 ns
Table 66: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 51
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT CLK AREG to P output using
multiplier 3.94 4.51 5.37 5.37 ns
TDSPCKO_P_BREG CLK BREG to P output not using
multiplier 1.64 1.87 2.22 2.22 ns
TDSPCKO_P_CREG CLK CREG to P output not using
multiplier 1.69 1.93 2.30 2.30 ns
TDSPCKO_P_DREG_MULT CLK DREG to P output using
multiplier 3.91 4.48 5.32 5.32 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} CLK (ACOUT, BCOUT) to {A,B}
register output 0.64 0.73 0.87 0.87 ns
TDSPCKO_CARRYCASCOUT_
{AREG, BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
4.19 4.79 5.70 5.70 ns
TDSPCKO_CARRYCASCOUT_BREG CLK BREG to CARRYCASCOUT
output not using multiplier 1.88 2.15 2.55 2.55 ns
TDSPCKO_CARRYCASCOUT_DREG_MULT CLK DREG to CARRYCASCOUT
output using multiplier 4.16 4.76 5.65 5.65 ns
TDSPCKO_CARRYCASCOUT_CREG CLK CREG to CARRYCASCOUT
output 1.94 2.21 2.63 2.63 ns
Maximum Frequency
FMAX With all registers used 628.93 550.66 464.25 464.25 MHz
FMAX_PATDET With pattern detector 531.63 465.77 392.93 392.93 MHz
FMAX_MULT_NOMREG Two register multiply without
MREG 349.28 305.62 257.47 257.47 MHz
FMAX_MULT_NOMREG_PATDET Two register multiply without
MREG with pattern detect 317.26 277.62 233.92 233.92 MHz
FMAX_PREADD_MULT_NOADREG Without ADREG 397.30 346.26 290.44 290.44 MHz
FMAX_PREADD_MULT_NOADREG_PATDET Without ADREG with pattern
detect 397.30 346.26 290.44 290.44 MHz
FMAX_NOPIPELINEREG Without pipeline registers (MREG,
ADREG) 260.01 227.01 190.69 190.69 MHz
FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG,
ADREG) with pattern detect 241.72 211.15 177.43 177.43 MHz
Table 66: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 52
Clock Buffers and Networks
Table 67: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TBCCCK_CE/TBCCKC_CE(1) CE pins setup/hold 0.13/0.39 0.14/0.41 0.18/0.42 0.18/0.84 ns
TBCCCK_S/TBCCKC_S(1) S pins setup/hold 0.13/0.39 0.14/0.41 0.18/0.42 0.18/0.84 ns
TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O 0.08 0.09 0.11 0.11 ns
Maximum Frequency
FMAX_BUFG Global clock tree (BUFG) 628.00 628.00 464.00 464.00 MHz
Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 68: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TBIOCKO_O Clock to out delay from I to O 1.16 1.32 1.61 1.61 ns
Maximum Frequency
FMAX_BUFIO I/O clock tree (BUFIO) 680.00 680.00 600.00 600.00 MHz
Table 69: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TBRCKO_O Clock to out delay from I to O 0.64 0.80 1.04 1.04 ns
TBRCKO_O_BYP Clock to out delay from I to O with Divide
Bypass attribute set 0.35 0.41 0.54 0.54 ns
TBRDO_O Propagation delay from CLR to O 0.85 0.89 1.14 1.14 ns
Maximum Frequency
FMAX_BUFR(1) Regional clock tree (BUFR) 420.00 375.00 315.00 315.00 MHz
Notes:
1. The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency.
Table 70: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TBHCKO_O BUFH delay from I to O 0.11 0.11 0.14 0.14 ns
TBHCCK_CE/TBHCKC_CE CE pin setup and hold 0.20/0.13 0.23/0.16 0.29/0.21 0.29/0.43 ns
Maximum Frequency
FMAX_BUFH Horizontal clock buffer (BUFH) 628.00 628.00 464.00 464.00 MHz
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 53
MMCM Switching Characteristics
Table 71: Duty-Cycle Distortion and Clock-Tree Skew
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TDCD_CLK Global clock tree duty-cycle distortion(1) All 0.20 0.20 0.20 0.20 ns
TCKSKEW Global clock tree skew(2)
XC7Z007S N/A 0.27 0.27 N/A ns
XC7Z012S N/A 0.39 0.42 N/A ns
XC7Z014S N/A 0.38 0.42 N/A ns
XC7Z010 0.27 0.27 0.27 N/A ns
XC7Z015 0.33 0.39 0.42 N/A ns
XC7Z020 0.33 0.38 0.42 N/A ns
XA7Z010 N/A N/A 0.27 0.27 ns
XA7Z020 N/A N/A 0.42 0.42 ns
XQ7Z020 N/A 0.38 0.42 0.42 ns
TDCD_BUFIO I/O clock tree duty-cycle distortion All 0.14 0.14 0.14 0.14 ns
TBUFIOSKEW I/O clock tree skew across one clock region All 0.03 0.03 0.03 0.03 ns
TDCD_BUFR Regional clock tree duty-cycle distortion All 0.18 0.18 0.18 0.18 ns
Notes:
1. These parameters represent the worst-case duty-cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty-cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate application specific clock skew.
Table 72: MMCM Specification
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
MMCM_FINMAX Maximum input clock frequency 800.00 800.00 800.00 800.00 MHz
MMCM_FINMIN Minimum input clock frequency 10.00 10.00 10.00 10.00 MHz
MMCM_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max
MMCM_FINDUTY
Allowable input duty cycle: 10—49 MHz 25 25 25 25 %
Allowable input duty cycle: 50—199 MHz 30 30 30 30 %
Allowable input duty cycle: 200—399 MHz 35 35 35 35 %
Allowable input duty cycle: 400—499 MHz 40 40 40 40 %
Allowable input duty cycle: >500 MHz 45 45 45 45 %
MMCM_FMIN_PSCLK Minimum dynamic phase-shift clock frequency 0.01 0.01 0.01 0.01 MHz
MMCM_FMAX_PSCLK Maximum dynamic phase-shift clock frequency 550.00 500.00 450.00 450.00 MHz
MMCM_FVCOMIN Minimum MMCM VCO frequency 600.00 600.00 600.00 600.00 MHz
MMCM_FVCOMAX Maximum MMCM VCO frequency 1600.00 1440.00 1200.00 1200.00 MHz
MMCM_FBANDWIDTH
Low MMCM bandwidth at typical(1) 1.00 1.00 1.00 1.00 MHz
High MMCM bandwidth at typical(1) 4.00 4.00 4.00 4.00 MHz
MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs(2) 0.12 0.12 0.12 0.12 ns
MMCM_TOUTJITTER MMCM output jitter Note 3
MMCM_TOUTDUTY MMCM output clock duty-cycle precision(4) 0.20 0.20 0.20 0.20 ns
Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020)
DS187 (v1.20.1) July 2, 2018 www.xilinx.com
Product Specification 54
MMCM_TLOCKMAX MMCM maximum lock time 100.00 100.00 100.00 100.00 µs
MMCM_FOUTMAX MMCM maximum output frequency 800.00 800.00 800.00 800.00 MHz
MMCM_FOUTMIN MMCM minimum output frequency(5)(6) 4.69 4.69 4.69 4.69 MHz
MMCM_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max
MMCM_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 ns
MMCM_FPFDMAX Maximum frequency at the phase frequency
detector 550.00 500.00 450.00 450.00 MHz
MMCM_FPFDMIN Minimum frequency at the phase frequency
detector 10.00 10.00 10.00 10.00 MHz
MMCM_TFBDELAY Maximum delay in the feedback path 3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN/
TMMCMCKD_PSEN Setup and hold of phase-shift enable 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
TMMCMDCK_PSINCDEC/
TMMCMCKD_PSINCDEC
Setup and hold of phase-shift
increment/decrement 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
TMMCMCKO_PSDONE Phase shift clock-to-out of PSDONE 0.59 0.68 0.81 0.81 ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
TMMCMDCK_DADDR/
TMMCMCKD_DADDR DADDR setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
TMMCMDCK_DI/
TMMCMCKD_DI DI setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
TMMCMDCK_DEN/
TMMCMCKD_DEN DEN setup/hold 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 ns, Min
TMMCMDCK_DWE/
TMMCMCKD_DWE DWE setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
TMMCMCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.99 ns, Max
FDCK DCLK frequency 200.00 200.00 200.00 200.00 MHz, Max
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
6. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.
Table 72: MMCM Specification (Cont’d)
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
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Product Specification 55
PLL Switching Characteristics
Table 73: PLL Specification
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
PLL_FINMAX Maximum input clock frequency 800.00 800.00 800.00 800.00 MHz
PLL_FINMIN Minimum input clock frequency 19.00 19.00 19.00 19.00 MHz
PLL_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max
PLL_FINDUTY
Allowable input duty cycle: 19—49 MHz 25 25 25 25 %
Allowable input duty cycle: 50—199 MHz 30 30 30 30 %
Allowable input duty cycle: 200—399 MHz 35 35 35 35 %
Allowable input duty cycle: 400—499 MHz 40 40 40 40 %
Allowable input duty cycle: >500 MHz 45 45 45 45 %
PLL_FVCOMIN Minimum PLL VCO frequency 800.00 800.00 800.00 800.00 MHz
PLL_FVCOMAX Maximum PLL VCO frequency 2133.00 1866.00 1600.00 1600.00 MHz
PLL_FBANDWIDTH
Low PLL bandwidth at typical(1) 1.00 1.00 1.00 1.00 MHz
High PLL bandwidth at typical(1) 4.00 4.00 4.00 4.00 MHz
PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs(2) 0.12 0.12 0.12 0.12 ns
PLL_TOUTJITTER PLL output jitter Note 3
PLL_TOUTDUTY PLL output clock duty-cycle precision(4) 0.20 0.20 0.20 0.20 ns
PLL_TLOCKMAX PLL maximum lock time 100.00 100.00 100.00 100.00 µs
PLL_FOUTMAX PLL maximum output frequency 800.00 800.00 800.00 800.00 MHz
PLL_FOUTMIN PLL minimum output frequency(5) 6.25 6.25 6.25 6.25 MHz
PLL_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max
PLL_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 ns
PLL_FPFDMAX Maximum frequency at the phase frequency
detector 550.00 500.00 450.00 450.00 MHz
PLL_FPFDMIN Minimum frequency at the phase frequency
detector 19.00 19.00 19.00 19.00 MHz
PLL_TFBDELAY Maximum delay in the feedback path 3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
TPLLCCK_DADDR/TPLLCKC
_DADDR Setup and hold of D address 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
TPLLCCK_DI/TPLLCKC_DI Setup and hold of D input 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
TPLLCCK_DEN/TPLLCKC_
DEN Setup and hold of D enable 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 ns, Min
TPLLCCK_DWE/TPLLCKC_
DWE Setup and hold of D write enable 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, Min
TPLLCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.99 ns, Max
FDCK DCLK frequency 200.00 200.00 200.00 200.00 MHz, Max
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
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Product Specification 56
Device Pin-to-Pin Output Parameter Guidelines
Table 74: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1)
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.
TICKOF Clock-capable clock input and OUTFF at
pins/banks closest to the BUFGs without
MMCM/PLL (near clock region)(2)
XC7Z007S N/A 5.68 6.65 N/A ns
XC7Z012S N/A 5.96 6.90 N/A ns
XC7Z014S N/A 6.05 7.08 N/A ns
XC7Z010 5.08 5.68 6.65 N/A ns
XC7Z015 5.34 5.96 6.90 N/A ns
XC7Z020 5.42 6.05 7.08 N/A ns
XA7Z010 N/A N/A 6.65 6.65 ns
XA7Z020 N/A N/A 7.08 7.08 ns
XQ7Z020 N/A 6.05 7.08 7.08 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of Zynq-7000 SoC Packaging and Pinout Specification (UG865).
Table 75: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1)
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, without MMCM/PLL.
TICKOFFAR Clock-capable clock input and OUTFF at
pins/banks farthest from the BUFGs without
MMCM/PLL (far clock region)(2)
XC7Z007S N/A 5.68 6.65 N/A ns
XC7Z012S N/A 6.25 7.21 N/A ns
XC7Z014S N/A 6.34 7.40 N/A ns
XC7Z010 5.08 5.68 6.65 N/A ns
XC7Z015 5.60 6.25 7.21 N/A ns
XC7Z020 5.69 6.34 7.40 N/A ns
XA7Z010 N/A N/A 6.65 6.65 ns
XA7Z020 N/A N/A 7.40 7.40 ns
XQ7Z020 N/A 6.34 7.40 7.40 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of Zynq-7000 SoC Packaging and Pinout Specification (UG865).
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Product Specification 57
Table 76: Clock-Capable Clock Input to Output Delay With MMCM
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with MMCM.
TICKOFMMCMCC Clock-capable clock input and OUTFF with
MMCM
XC7Z007S N/A 1.03 1.03 N/A ns
XC7Z012S N/A 1.04 1.06 N/A ns
XC7Z014S N/A 1.04 1.05 N/A ns
XC7Z010 1.04 1.03 1.03 N/A ns
XC7Z015 1.05 1.04 1.06 N/A ns
XC7Z020 1.05 1.04 1.05 N/A ns
XA7Z010 N/A N/A 1.03 1.03 ns
XA7Z020 N/A N/A 1.05 1.05 ns
XQ7Z020 N/A 1.04 1.05 1.05 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
Table 77: Clock-Capable Clock Input to Output Delay With PLL
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flops, Fast Slew Rate, with PLL.
TICKOFPLLCC Clock-capable clock input and OUTFF
with PLL
XC7Z007S N/A 0.82 0.82 N/A ns
XC7Z012S N/A 0.82 0.82 N/A ns
XC7Z014S N/A 0.82 0.82 N/A ns
XC7Z010 0.82 0.82 0.82 N/A ns
XC7Z015 0.82 0.82 0.82 N/A ns
XC7Z020 0.82 0.82 0.82 N/A ns
XA7Z010 N/A N/A 0.82 0.82 ns
XA7Z020 N/A N/A 0.82 0.82 ns
XQ7Z020 N/A 0.82 0.82 0.82 ns
Notes:
1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
Table 78: Pin-to-Pin, Clock-to-Out using BUFIO
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.
TICKOFCS Clock to out of I/O clock 5.14 5.76 6.81 6.81 ns
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Product Specification 58
Device Pin-to-Pin Input Parameter Guidelines
Table 79: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSFD/ TPHFD Full delay (legacy delay or default delay)
global clock input and IFF(2) without
MMCM/PLL with ZHOLD_DELAY on HR
I/O banks
XC7Z007S N/A 2.13/–0.17 2.44/–0.17 N/A ns
XC7Z012S N/A 2.55/–0.18 3.03/–0.18 N/A ns
XC7Z014S N/A 2.74/–0.25 3.18/–0.25 N/A ns
XC7Z010 2.00/–0.17 2.13/–0.17 2.44/–0.17 N/A ns
XC7Z015 2.38/–0.18 2.55/–0.18 3.03/–0.18 N/A ns
XC7Z020 2.55/–0.25 2.74/–0.25 3.18/–0.25 N/A ns
XA7Z010 N/A N/A 2.44/–0.17 2.44/–0.17 ns
XA7Z020 N/A N/A 3.18/–0.25 3.18/–0.25 ns
XQ7Z020 N/A 2.74/–0.25 3.18/–0.25 3.18/–0.25 ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch.
Table 80: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSMMCMCC/
TPHMMCMCC
No delay clock-capable clock input and
IFF(2) with MMCM
XC7Z007S N/A 2.68/–0.62 3.22/–0.62 N/A ns
XC7Z012S N/A 2.80/–0.62 3.34/–0.62 N/A ns
XC7Z014S N/A 2.82/–0.62 3.38/–0.62 N/A ns
XC7Z010 2.36/–0.62 2.68/–0.62 3.22/–0.62 N/A ns
XC7Z015 2.47/–0.62 2.80/–0.62 3.34/–0.62 N/A ns
XC7Z020 2.48/–0.62 2.82/–0.62 3.38/–0.62 N/A ns
XA7Z010 N/A N/A 3.22/–0.62 3.22/–0.62 ns
XA7Z020 N/A N/A 3.38/–0.62 3.38/–0.62 ns
XQ7Z020 N/A 2.82/–0.62 3.38/–0.62 3.38/–0.62 ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Product Specification 59
Table 81: Clock-Capable Clock Input Setup and Hold With PLL
Symbol Description Device Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)
TPSPLLCC/
TPHPLLCC
No delay clock-capable clock input and
IFF(2) with PLL
XC7Z007S N/A 3.03/–0.19 3.64/–0.19 N/A ns
XC7Z012S N/A 3.15/–0.20 3.76/–0.20 N/A ns
XC7Z014S N/A 3.17/–0.20 3.80/–0.20 N/A ns
XC7Z010 2.67/–0.19 3.03/–0.19 3.64/–0.19 N/A ns
XC7Z015 2.78/–0.20 3.15/–0.20 3.76/–0.20 N/A ns
XC7Z020 2.79/–0.20 3.17/–0.20 3.80/–0.20 N/A ns
XA7Z010 N/A N/A 3.64/–0.19 3.64/–0.19 ns
XA7Z020 N/A N/A 3.80/–0.20 3.80/–0.20 ns
XQ7Z020 N/A 3.17/–0.20 3.80/–0.20 3.80/–0.20 ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 82: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
TPSCS/TPHCS Setup and hold of I/O clock –0.38/1.39 –0.38/1.55 –0.38/1.86 –0.38/1.86 ns
Table 83: Sample Window
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
TSAMP Sampling error at receiver pins(1) 0.59 0.64 0.70 0.70 ns
TSAMP_BUFIO Sampling error at receiver pins using BUFIO(2) 0.35 0.40 0.46 0.46 ns
Notes:
1. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the PL DDR input registers, measured across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
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Product Specification 60
Additional Package Parameter Guidelines
The parameters in this section provide the necessary values for calculating timing budgets for PL clock transmitter and
receiver data-valid windows.
Table 84: Package Skew
Symbol Description Device Package Value Units
TPKGSKEW Package skew(1)
XC7Z007S CLG225 101 ps
CLG400 155 ps
XC7Z012S CLG485 182 ps
XC7Z014S CLG400 166 ps
CLG484 248 ps
XC7Z010 CLG225 101 ps
CLG400 155 ps
XC7Z015 CLG485 182 ps
XC7Z020 CLG400 166 ps
CLG484 248 ps
XA7Z010 CLG225 101 ps
CLG400 155 ps
XA7Z020 CLG400 166 ps
CLG484 248 ps
XQ7Z020 CL400 166 ps
CL484 248 ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die
pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
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Product Specification 61
GTP Transceiver Specifications (Only available in the XC7Z012S and XC7Z015)
GTP Transceiver DC Input and Output Levels
Table 85 summarizes the DC output specifications of the GTP transceivers in the XC7Z012S and XC7Z015. Consult the
7 Series FPGAs GTP Transceiver User Guide (UG482) for further details.
Note: In Figure 21, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2.
Table 85: GTP Transceiver DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
DVPPOUT Differential peak-to-peak output
voltage(1)
Transmitter output swing is set to
maximum setting
1000 – mV
VCMOUTDC DC common mode output
voltage
Equation based VMGTAVTT –DV
PPOUT/4 mV
ROUT Differential output resistance 100 Ω
VCMOUTAC Common mode output voltage: AC coupled 1/2 VMGTAVTT mV
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew 12 ps
DVPPIN Differential peak-to-peak input
voltage
External AC coupled 150 2000 mV
VIN Single-ended input voltage(2) DC coupled VMGTAVTT = 1.2V –200 VMGTAVTT mV
VCMIN Common mode input voltage DC coupled VMGTAVTT = 1.2V 2/3 VMGTAVTT –mV
RIN Differential input resistance 100 Ω
CEXT Recommended external AC coupling capacitor(3) 100 – nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in the 7 Series FPGAs GTP Transceiver User
Guide (UG482) and can result in values lower than reported in this table.
2. Voltage measured at the pin referenced to GND.
3. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 20
Figure 20: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 21
Figure 21: Differential Peak-to-Peak Voltage
0
+V P
N
ds187_17_070314
Single-Ended
Peak-to-Peak
Voltage
0
+V
–V
P–N
ds187_18_070314
Differential
Peak-to-Peak
Voltage
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Product Specification 62
Table 86 summarizes the DC specifications of the clock input of the GTP transceiver. Consult the 7 Series FPGAs GTP
Transceiver User Guide (UG482) for further details.
GTP Transceiver Switching Characteristics
Consult the 7 Series FPGAs GTP Transceiver User Guide (UG482) for further information.
Table 86: GTP Transceiver Clock DC Input Level Specification
Symbol DC Parameter Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 350 2000 mV
RIN Differential input resistance 100 Ω
CEXT Required external AC coupling capacitor 100 nF
Table 87: GTP Transceiver Performance
Symbol Description Output
Divider
Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
FGTPMAX Maximum GTP transceiver data rate 6.25 6.25 3.75 N/A Gb/s
FGTPMIN Minimum GTP transceiver data rate 0.500 0.500 0.500 N/A Gb/s
FGTPRANGE PLL line rate range
1 3.2–6.25 3.2–6.25 3.2–3.75 N/A Gb/s
2 1.6–3.3 1.6–3.3 1.6–3.2 N/A Gb/s
4 0.8–1.65 0.8–1.65 0.8–1.6 N/A Gb/s
8 0.5–0.825 0.5–0.825 0.5–0.8 N/A Gb/s
FGTPPLLRANGE GTP transceiver PLL frequency range 1.6–3.3 1.6–3.3 1.6–3.3 N/A GHz
Table 88: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol Description Speed Grade Units
-3 -2 -1C/-1I/-1LI -1Q
FGTPDRPCLK GTPDRPCLK maximum frequency 175 175 156 N/A MHz
Table 89: GTP Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequency range 60 660 MHz
TRCLK Reference clock rise time 20% – 80% 200 ps
TFCLK Reference clock fall time 80% – 20% 200 ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 60 %
X-Ref Target - Figure 22
Figure 22: Reference Clock Timing Parameters
ds187_19_081513
80%
20%
T
FCLK
T
RCLK
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Product Specification 63
Table 90: GTP Transceiver PLL/Lock Time Adaptation
Symbol Description Conditions All Speed Grades Units
Min Typ Max
TLOCK Initial PLL lock 1 ms
TDLOCK Clock recovery phase acquisition and
adaptation time.
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data