Kintex-7 FPGAs Datasheet

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Datasheet

DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 1
© 2011–2018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
Introduction
Kintex®-7 FPGAs are available in -3, -2, -1, -1L, and -2L
speed grades, with -3 having the highest performance. The
-2L devices are screened for lower maximum static power
and can operate at lower core voltages for lower dynamic
power than the -2 devices. The -2L industrial (I) temperature
devices operate only at VCCINT = 0.95V. The -2L extended (E)
temperature devices can operate at either VCCINT =0.9V or
1.0V. The -2LE devices when operated at VCCINT =1.0V, and
the -2LI devices when operated at VCCINT = 0.95V, have the
same speed specifications as the -2 speed grade, except
where noted. When the -2LE devices are operated at
VCCINT = 0.9V, the speed specifications, static power, and
dynamic power are reduced. The -1L military (M)
temperature devices have the same speed specifications as
the -1 military temperature devices and are screened for
lower maximum static power.
Kintex-7 FPGA DC and AC characteristics are specified in
commercial, extended, industrial, and military temperature
ranges. Except for the operating temperature range or
unless otherwise noted, all the DC and AC electrical
parameters are the same for a particular speed grade (that
is, the timing characteristics of a -1 speed grade military
temperature device are the same as for a -1 speed grade
commercial temperature device). However, only selected
speed grades and/or devices are available in each
temperature range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parameters
included are common to popular designs and typical
applications.
Available device and package combinations can be found in
:
7 Series FPGAs Overview (DS180)
Defense-Grade 7 Series FPGAs Overview (DS185)
This Kintex-7 FPGA data sheet, part of an overall set of
documentation on the 7 series FPGAs, is available on the
Xilinx website at www.xilinx.com/documentation.
DC Characteristics
Kintex-7 FPGAs Data Sheet:
DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 Product Specification
Table 1: Absolute Maximum Ratings (1)
Symbol Description Min Max Units
FPGA Logic
VCCINT Internal supply voltage –0.5 1.1 V
VCCAUX Auxiliary supply voltage –0.5 2.0 V
VCCBRAM Supply voltage for the block RAM memories –0.5 1.1 V
VCCO
Output drivers supply voltage for HR I/O banks –0.5 3.6 V
Output drivers supply voltage for HP I/O banks –0.5 2.0 V
VCCAUX_IO Auxiliary supply voltage –0.5 2.06 V
VREF Input reference voltage –0.5 2.0 V
VIN(2)(3)(4)
I/O input voltage for HR I/O banks –0.40 VCCO +0.55 V
I/O input voltage for HP I/O banks –0.55 VCCO +0.55 V
I/O input voltage (when VCCO =3.3V) for V
REF and differential I/O standards except
TMDS_33(5)
–0.40 2.625 V
VCCBATT Key memory battery backup supply –0.5 2.0 V
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 2
GTX Transceiver
VMGTAVCC Analog supply voltage for the GTX transmitter and receiver circuits –0.5 1.1 V
VMGTAVTT Analog supply voltage for the GTX transmitter and receiver termination circuits –0.5 1.32 V
VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers –0.5 1.935 V
VMGTREFCLK GTX transceiver reference clock absolute input voltage –0.5 1.32 V
VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTX transceiver
column
–0.5 1.32 V
VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V
IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating 14 mA
IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT 12 mA
IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND 6.5 mA
IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating 14 mA
IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT 12 mA
XADC
VCCADC XADC supply relative to GNDADC –0.5 2.0 V
VREFP XADC reference input relative to GNDADC –0.5 2.0 V
Temperature
TSTG Storage temperature (ambient) –65 150 °C
TSOL
Maximum soldering temperature for Pb/Sn component bodies (6) –+220°C
Maximum soldering temperature for Pb-free component bodies (6) –+260°C
TjMaximum junction temperature(6) –+125°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. The lower absolute voltage specification always applies.
3. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471).
4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5.
5. See Table 10 for TMDS_33 specifications.
6. For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475).
Table 2: Recommended Operating Conditions (1)(2)
Symbol Description Min Typ Max Units
FPGA Logic
VCCINT(3)
For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: internal supply voltage 0.97 1.00 1.03 V
For -2LE (0.9V) devices: internal supply voltage 0.87 0.90 0.93 V
For -2LI (0.95V) devices: internal supply voltage 0.93 0.95 0.97 V
VCCBRAM(3)
For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: block RAM supply voltage 0.97 1.00 1.03 V
For -2LE (0.9V) devices: block RAM supply voltage 0.87 0.90 1.03 V
For -2LI (0.95V) devices: block RAM supply voltage 0.93 0.95 0.97 V
VCCAUX Auxiliary supply voltage 1.71 1.80 1.89 V
VCCO(4)(5) Supply voltage for HR I/O banks 1.14 3.465 V
Supply voltage for HP I/O banks 1.14 1.89 V
Table 1: Absolute Maximum Ratings (1) (Cont’d)
Symbol Description Min Max Units
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 3
VCCAUX_IO(6) Auxiliary supply voltage when set to 1.8V 1.71 1.80 1.89 V
Auxiliary supply voltage when set to 2.0V 1.94 2.00 2.06 V
VIN(7)
I/O input voltage –0.20 VCCO +0.2 V
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O
standards except TMDS_33(8) –0.20 2.625 V
IIN(9) Maximum current through any pin in a powered or unpowered bank when
forward biasing the clamp diode.
––10mA
VCCBATT(10) Battery voltage 1.0 1.89 V
GTX Transceiver
VMGTAVCC(11)
Analog supply voltage for the GTX transceiver QPLL frequency range
10.3125 GHz(12)(13) 0.97 1.0 1.08 V
Analog supply voltage for the GTX transceiver QPLL frequency range
> 10.3125 GHz 1.02 1.05 1.08 V
VMGTAVTT(11) Analog supply voltage for the GTX transmitter and receiver termination
circuits 1.17 1.2 1.23 V
VMGTVCCAUX(11) Auxiliary analog QPLL voltage supply for the transceivers 1.75 1.80 1.85 V
VMGTAVTTRCAL(11) Analog supply voltage for the resistor calibration circuit of the GTX
transceiver column 1.17 1.2 1.23 V
XADC
VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V
VREFP Externally supplied reference voltage 1.20 1.25 1.30 V
Temperature
Tj
Junction temperature operating range for commercial (C) temperature
devices
0–85°C
Junction temperature operating range for extended (E) temperature
devices
0–100°C
Junction temperature operating range for industrial (I) temperature devices –40 100 °C
Junction temperature operating range for military (M) temperature devices –55 125 °C
Notes:
1. All voltages are relative to ground.
2. For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide (UG483).
3. VCCINT and VCCBRAM should be connected to the same supply.
4. Configuration data is retained even if VCCO drops to 0V.
5. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), and 3.3V (HR I/O only) at ±5%.
6. For more information, refer to the VCCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471).
7. The lower absolute voltage specification always applies.
8. See Table 10 for TMDS_33 specifications.
9. A total of 200 mA per bank should not be exceeded.
10. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
11. Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
12. For data rates 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption.
13. For lower power consumption, VMGTAVCC should be 1.0V ±3% over the entire CPLL frequency range.
Table 2: Recommended Operating Conditions (1)(2) (Cont’d)
Symbol Description Min Typ Max Units
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 4
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ(1) Max Units
VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 V
VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 V
IREF VREF leakage current per pin 15 µA
ILInput or output leakage current per pin (sample-tested) 15 µA
CIN(2) Die input capacitance at the pad 8 pF
IRPU
Pad pull-up (when selected) @ VIN =0V, V
CCO =3.3V 90 330 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =2.5V 68 250 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.8V 34 220 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.5V 23 150 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.2V 12 120 µA
IRPD
Pad pull-down (when selected) @ VIN =3.3V 68 330 µA
Pad pull-down (when selected) @ VIN =1.8V 45 180 µA
ICCADC Analog supply current, analog circuits in powered up state 25 mA
IBATT(3) Battery supply current 150 nA
RIN_TERM(4)
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_40)
28 40 55 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_50)
35 50 65 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_60)
44 60 83 Ω
n Temperature diode ideality factor 1.010
r Temperature diode series resistance 2 Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
4. Termination resistance to a VCCO/2 level.
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2)
AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C
VCCO + 0.55 100
–0.40 100
–0.45 61.7
–0.50 25.8
–0.55 11.0
VCCO + 0.60 46.6 –0.60 4.77
VCCO + 0.65 21.2 –0.65 2.10
VCCO + 0.70 9.75 –0.70 0.94
VCCO + 0.75 4.55 –0.75 0.43
VCCO + 0.80 2.15 –0.80 0.20
VCCO + 0.85 1.02 –0.85 0.09
VCCO + 0.90 0.49 –0.90 0.04
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 5
VCCO + 0.95 0.24 –0.95 0.02
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND 0.20V, must not exceed the values
in this table.
Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2)
AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C
VCCO + 0.55 100 –0.55 100
VCCO + 0.60 50.0(3) –0.60 50.0(3)
VCCO + 0.65 50.0(3) –0.65 50.0(3)
VCCO + 0.70 47.0 –0.70 50.0(3)
VCCO + 0.75 21.2 –0.75 50.0(3)
VCCO + 0.80 9.71 –0.80 50.0(3)
VCCO + 0.85 4.51 –0.85 28.4
VCCO + 0.90 2.12 –0.90 12.7
VCCO + 0.95 1.01 –0.95 5.79
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND 0.20V, must not exceed the values
in this table.
3. For UI lasting less than 20 µs.
Table 6: Typical Quiescent Supply Current
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LM -1M -2LI -2LE
ICCINTQ Quiescent VCCINT supply
current
XC7K70T 241 241 241 N/A N/A N/A 187 mA
XC7K160T 474 474 474 N/A N/A 271 368 mA
XC7K325T 810 810 810 N/A N/A 463 629 mA
XC7K355T 993 993 993 N/A N/A 568 771 mA
XC7K410T 1080 1080 1080 N/A N/A 618 838 mA
XC7K420T 1313 1313 1313 N/A N/A 751 1019 mA
XC7K480T 1313 1313 1313 N/A N/A 751 1019 mA
XQ7K325T N/A 810 810 810 810 463 629 mA
XQ7K410T N/A 1080 1080 N/A 1080 618 838 mA
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) (Cont’d)
AC Voltage Overshoot % of UI at –55°C to 125°C AC Voltage Undershoot % of UI at –55°C to 125°C
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 6
ICCOQ Quiescent VCCO supply
current
XC7K70T 1 1 1 N/A N/A N/A 1 mA
XC7K160T 1 1 1 N/A N/A 1 1 mA
XC7K325T 1 1 1 N/A N/A 1 1 mA
XC7K355T 1 1 1 N/A N/A 1 1 mA
XC7K410T 1 1 1 N/A N/A 1 1 mA
XC7K420T 1 1 1 N/A N/A 1 1 mA
XC7K480T 1 1 1 N/A N/A 1 1 mA
XQ7K325T N/A 1 1 1 1 1 1 mA
XQ7K410T N/A 1 1 N/A 1 1 1 mA
ICCAUXQ Quiescent VCCAUX supply
current
XC7K70T 21 21 21 N/A N/A N/A 21 mA
XC7K160T 40 40 40 N/A N/A 36 40 mA
XC7K325T 68 68 68 N/A N/A 61 68 mA
XC7K355T 75 75 75 N/A N/A 67 75 mA
XC7K410T 85 85 85 N/A N/A 76 85 mA
XC7K420T 99 99 99 N/A N/A 89 99 mA
XC7K480T 99 99 99 N/A N/A 89 99 mA
XQ7K325T N/A 68 68 68 68 68 68 mA
XQ7K410T N/A 85 85 N/A 85 85 85 mA
ICCAUX_IOQ Quiescent VCCAUX_IO supply
current
XC7K70T N/A N/A N/A N/A N/A N/A N/A mA
XC7K160T 2 2 2 N/A N/A 1 2 mA
XC7K325T 2 2 2 N/A N/A 1 2 mA
XC7K355TN/AN/AN/AN/AN/AN/AN/AmA
XC7K410T 2 2 2 N/A N/A 1 2 mA
XC7K420TN/AN/AN/AN/AN/AN/AN/AmA
XC7K480TN/AN/AN/AN/AN/AN/AN/AmA
XQ7K325T N/A 2 2 2 2 2 2 mA
XQ7K410T N/A 2 2 N/A 2 2 2 mA
Table 6: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LM -1M -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 7
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw
and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on
sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply
and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be
powered by the same supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC,
VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT
can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve
minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-
up and power-down.
•When V
MGTAVTT is powered before VMGTAVCC and VMGTAVTT –V
MGTAVCC > 150 mV and VMGTAVCC <0.7V, the V
MGTAVTT
current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be
up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
•When V
MGTAVTT is powered before VCCINT and VMGTAVTT –V
CCINT > 150 mV and VCCINT <0.7V, the V
MGTAVTT current
draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to
0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
Table 7 shows the minimum current, in addition to ICCQ, that are required by Kintex-7 devices for proper power-on and
configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied.
ICCBRAMQ Quiescent VCCBRAM supply
current
XC7K70T 6 6 6 N/A N/A N/A 6 mA
XC7K160T 14 14 14 N/A N/A 8 14 mA
XC7K325T 19 19 19 N/A N/A 10 19 mA
XC7K355T 31 31 31 N/A N/A 17 31 mA
XC7K410T 34 34 34 N/A N/A 19 34 mA
XC7K420T 41 41 41 N/A N/A 23 41 mA
XC7K480T 41 41 41 N/A N/A 23 41 mA
XQ7K325T N/A 19 19 19 19 19 19 mA
XQ7K410T N/A 34 34 N/A 34 34 34 mA
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO resources.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for
conditions other than those specified.
Table 6: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LM -1M -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 8
Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power)
to estimate current drain on these supplies.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH
voltage levels shown. Other standards are sample tested.
Table 7: Power-On Current for Kintex-7 Devices
Device ICCINTMIN ICCAUXMIN ICCOMIN ICCAUX_IOMIN ICCBRAMMIN Units
XC7K70T ICCINTQ + 450 ICCAUXQ +40 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +40 mA
XC7K160T ICCINTQ + 550 ICCAUXQ +50 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +40 mA
XC7K325T ICCINTQ + 600 ICCAUXQ +80 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +40 mA
XC7K355T ICCINTQ + 1450 ICCAUXQ +109 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +81 mA
XC7K410T ICCINTQ + 1500 ICCAUXQ +125 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +90 mA
XC7K420T ICCINTQ + 2200 ICCAUXQ +180 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +108 mA
XC7K480T ICCINTQ + 2200 ICCAUXQ +180 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +108 mA
XQ7K325T ICCINTQ + 600 ICCAUXQ +80 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +40 mA
XQ7K410T ICCINTQ + 1500 ICCAUXQ +125 I
CCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ +90 mA
Table 8: Power Supply Ramp Time
Symbol Description Conditions Min Max Units
TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms
TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms
TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms
TVCCAUX_IO Ramp time from GND to 90% of VCCAUX_IO 0.2 50 ms
TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms
TVCCO2VCCAUX Allowed time per power cycle for VCCO – VCCAUX > 2.625V
TJ = 125°C(1) –300
msTJ = 100°C(1) –500
TJ = 85°C(1) –800
TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms
TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms
TMGTVCCAUX Ramp time from GND to 90% of VMGTVCCAUX 0.2 50 ms
Notes:
1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.
Table 9: SelectIO DC Input and Output Levels (1)(2)
I/O Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 VREF – 0.100 VREF +0.100 V
CCO + 0.300 0.400 VCCO –0.400 8 8
HSTL_I_12 –0.300 VREF – 0.080 VREF +0.080 V
CCO + 0.300 25% VCCO 75% VCCO 6.3 –6.3
HSTL_I_18 –0.300 VREF – 0.100 VREF +0.100 V
CCO + 0.300 0.400 VCCO –0.400 8 8
HSTL_II –0.300 VREF – 0.100 VREF +0.100 V
CCO + 0.300 0.400 VCCO – 0.400 16 16
HSTL_II_18 –0.300 VREF – 0.100 VREF +0.100 V
CCO + 0.300 0.400 VCCO – 0.400 16 16
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 9
HSUL_12 –0.300 VREF – 0.130 VREF +0.130 V
CCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO –0.400 Note 3 Note 3
LVCMOS15,
LVDCI_15
–0.300 35% VCCO 65% VCCO VCCO + 0.300 25% VCCO 75% VCCO Note 4 Note 4
LVCMOS18,
LVDCI_18
–0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO –0.450 Note 5 Note 5
LVCMOS25 –0.300 0.700 1.700 VCCO + 0.300 0.400 VCCO –0.400 Note 6 Note 6
LVCMOS33 –0.300 0.800 2.000 3.450 0.400 VCCO –0.400 Note 6 Note 6
LVTTL –0.300 0.800 2.000 3.450 0.400 2.400 Note 7 Note 7
MOBILE_DDR –0.300 20% VCCO 80% VCCO VCCO + 0.300 10% VCCO 90% VCCO 0.1 –0.1
PCI33_3 –0.400 30% VCCO 50% VCCO VCCO + 0.500 10% VCCO 90% VCCO 1.5 –0.5
SSTL12 –0.300 VREF – 0.100 VREF +0.100 V
CCO + 0.300 VCCO/2–0.150 V
CCO/2 + 0.150 14.25 –14.25
SSTL135 –0.300 VREF – 0.090 VREF +0.090 V
CCO + 0.300 VCCO/2–0.150 V
CCO/2 + 0.150 13.0 –13.0
SSTL135_R –0.300 VREF – 0.090 VREF +0.090 V
CCO + 0.300 VCCO/2–0.150 V
CCO/2 + 0.150 8.9 –8.9
SSTL15 –0.300 VREF – 0.100 VREF +0.100 V
CCO + 0.300 VCCO/2–0.175 V
CCO/2 + 0.175 13.0 –13.0
SSTL15_R –0.300 VREF – 0.100 VREF +0.100 V
CCO + 0.300 VCCO/2–0.175 V
CCO/2 + 0.175 8.9 –8.9
SSTL18_I –0.300 VREF – 0.125 VREF +0.125 V
CCO + 0.300 VCCO/2–0.470 V
CCO/2 + 0.470 8 8
SSTL18_II –0.300 VREF – 0.125 VREF +0.125 V
CCO + 0.300 VCCO/2–0.600 V
CCO/2 + 0.600 13.4 –13.4
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. Supported drive strengths of 4, 8, 12, or 16 mA
7. Supported drive strengths of 4, 8, 12, 16, or 24 mA
8. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471).
Table 9: SelectIO DC Input and Output Levels (1)(2) (Cont’d)
I/O Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 10
Table 10: Differential SelectIO DC Input and Output Levels
I/O Standard VICM(1) VID(2) VOCM(3) VOD(4)
V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max
BLVDS_25 0.300 1.200 1.425 0.100 1.250 Note 5
MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600
PPDS_25 0.200 0.900 VCCAUX 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400
RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600
TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.400 0.600 0.800
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOCM is the output common mode voltage.
4. VOD is the output differential voltage (Q – Q).
5. VOD for BLVDS will vary significantly depending on topology and loading.
6. LVDS_25 is specified in Table 12.
7. LVDS is specified in Table 13.
Table 11: Complementary Differential SelectIO DC Input and Output Levels
I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH
V, Min V, Typ V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min
DIFF_HSTL_I 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_II 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSUL_12 0.300 0.600 0.850 0.100 20% VCCO 80% VCCO 0.100 –0.100
DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 10% VCCO 90% VCCO 0.100 –0.100
DIFF_SSTL12 0.300 0.600 0.850 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 14.25 –14.25
DIFF_SSTL135 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0 –13.0
DIFF_SSTL135_R 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9 –8.9
DIFF_SSTL15 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0 13.0
DIFF_SSTL15_R 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9 –8.9
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.00 –8.00
DIFF_SSTL18_II 0.300 0.900 1.425 0.100 (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4 13.4
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 11
LVDS DC Specifications (LVDS_25)
The LVDS_25 standard is available in the HR I/O banks. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) for
more information.
LVDS DC Specifications (LVDS)
The LVDS standard is available in the HP I/O banks. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more
information.
Table 12: LVDS_25 DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.375 2.500 2.625 V
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals 1.675 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.700 V
VODIFF
Differential Output Voltage:
(Q – Q), Q = High
(Q –Q), Q=High
RT = 100 Ω across Q and Q signals 247 350 600 mV
VOCM Output Common-Mode Voltage RT = 100 Ω across Q and Q signals 1.000 1.250 1.425 V
VIDIFF
Differential Input Voltage:
(Q – Q), Q = High
(Q –Q), Q=High
100 350 600 mV
VICM Input Common-Mode Voltage 0.300 1.200 1.500 V
Notes:
1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Refer to the
7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.
Table 13: LVDS DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 1.710 1.800 1.890 V
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals 1.675 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.825 V
VODIFF
Differential Output Voltage:
(Q – Q), Q = High
(Q –Q), Q=High
RT = 100 Ω across Q and Q signals 247 350 600 mV
VOCM Output Common-Mode Voltage RT = 100 Ω across Q and Q signals 1.000 1.250 1.425 V
VIDIFF
Differential Input Voltage:
(Q – Q), Q = High
(Q –Q), Q=High
Common-mode input voltage = 1.25V 100 350 600 mV
VICM Input Common-Mode Voltage Differential input voltage = ±350 mV 0.300 1.200 1.425 V
Notes:
1. Differential inputs for LVDS can be placed in banks with VCCO levels that are different from the required level for outputs. Refer to the 7Series
FPGAs SelectIO Resources User Guide (UG471) for more information.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 12
AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite 2015.4 and
ISE® software 14.7 as outlined in Table 14.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting
might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with
this designation are intended to give a better indication of the expected performance of production silicon. The probability
of under-reporting delays is greatly reduced as compared to Advance data.
Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to production before faster speed grades.
Testing of AC Switching Characteristics
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are
representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex-7 FPGAs.
Table 14: Kintex-7 FPGA Speed Specification Version By Device
Version In: Typical VCCINT Device
ISE 14.7 Vivado 2015.4 (Table 2)
1.10 1.12 1.0V XC7K70T(1), XC7K160T(1), XC7K325T, XC7K355T, XC7K410T, XC7K420T,
XC7K480T
N/A 1.12 0.95V XC7K160T(1), XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T
1.09 1.09 0.9V XC7K70T, XC7K160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T
1.05 1.09 1.0V XQ7K325T, XQ7K410T
1.05 1.09 0.9V XQ7K325T, XQ7K410T
Notes:
1. GTX data rates greater than 6.6 Gb/s in the FBG484 package in the -3 and -2 speed grades require Vivado Design Suite 2017.1 or later.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 13
Speed Grade Designations
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 15 correlates the current status of each Kintex-7
device on a per speed grade basis.
Production Silicon and Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 16 lists the production released Kintex-7 device, speed grade, and the minimum corresponding supported speed
specification version and software revisions. The software and speed specifications listed are the minimum releases required
for production. All subsequent releases of software and speed specifications are valid.
Table 15: Kintex-7 Device Speed Grade Designations
Device Speed Grade Designations
Advance Preliminary Production
XC7K70T -3, -2, -2LE(1.0V), -1, and -2LE (0.9V)
XC7K160T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K325T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K355T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K410T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K420T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XC7K480T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V)
XQ7K325T -2I, -2LE(1.0V), -1I, -2LE(0.9V), -2LI (0.95V), -1LM, and -1M
XQ7K410T -2I, -2LE(1.0V), -1I, -2LE(0.9V), -2LI (0.95V), and -1M
Table 16: Kintex-7 Device Production Software and Speed Specification Release
Device
Speed Grade Designations
1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M -1LM -2LI -2LE
XC7K70T Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A N/A N/A Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K160T Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K325T Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K355T Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K410T Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K420T Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XC7K480T Vivado tools 2012.4 v1.08
or ISE tools 14.2 v1.06
N/A N/A Vivado tools 2014.4 v1.12 Vivado tools 2012.4 v1.07
or ISE tools 14.3 v1.06
XQ7K325T N/A Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
Vivado tools
2015.4 v1.09
Vivado tools 2015.4 v1.07 Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
XQ7K410T N/A Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
N/A Vivado tools 2015.4 v1.07 Vivado tools 2013.1 v1.04
or ISE tools 14.5 v1.04
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 14
Selecting the Correct Speed Grade and Voltage in the Vivado Tools
It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.
To select the 1.0V speed specifications in the Vivado tools, select the Kintex-7 or Defense Grade Kintex-7Q sub-family, and
then select the part name that is the device name followed by the package name followed by the speed grade. For example,
select the xc7k325tffg900-3 part name for the XC7K325T device in the FFG900 package and -3 (1.0V) speed grade or select
the xc7k325tffg900-2L part name for the XC7K325T device in the FFG900 package and -2LE (1.0V) speed grade.
To select the -2LI (0.95V) speed specifications in the Vivado tools, select the Kintex-7 sub-family and then select the part
name that is the device name followed by an i followed by the package name followed by the speed grade. For example,
select the xc7k325tiffg900-2L part name for the XC7K325T device in the FFG900 package and -2LI (0.95V) speed grade. The
-2LI (0.95V) speed specifications are not supported in the ISE tools.
To select the -2LE (0.9V) speed specifications in the Vivado tools, select the Kintex-7 Low Voltage or Defense Grade
Kintex-7Q Low Voltage sub-family, and then select the part name that is the device name followed by an l followed by the
package name followed by the speed grade. For example, select the xc7k325tlffg900-2L part name for the XC7K325T
device in the FFG900 package and -2LE (0.9V) speed grade.
A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See
Table 16 for the subset of 7 series FPGAs supported in the ISE tools.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Kintex-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to
the same guidelines as the AC Switching Characteristics, page 12. In each table, the I/O bank type is either High Performance
(HP) or High Range (HR).
Table 18 and Table 19 provide the maximum data rates for applicable memory standards using the Kintex-7 FPGAs memory
PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado
or ISE Design Suite, following guidelines in the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide
(UG586), electrical analysis, and characterization of the system.
Table 17: Networking Applications Interface Performances
Description
I/O
Bank
Type
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1/-1M/-1LM -2LI -2LE
SDR LVDS transmitter (using OSERDES;
DATA_WIDTH = 4 to 8)
HR 710 710 625 710 625 Mb/s
HP 710 710 625 710 625 Mb/s
DDR LVDS transmitter (using OSERDES;
DATA_WIDTH = 4 to 14)
HR 1250 1250 950 1250 950 Mb/s
HP 1600 1400 1250 1400 1250 Mb/s
SDR LVDS receiver (SFI-4.1)(1) HR 710 710 625 710 625 Mb/s
HP 710 710 625 710 625 Mb/s
DDR LVDS receiver (SPI-4.2)(1) HR 1250 1250 950 1250 950 Mb/s
HP 1600 1400 1250 1400 1250 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 15
Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FF and RF Packages)(1)(2)
Memory
Standard
I/O Bank
Type VCCAUX_IO
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
4:1 Memory Controllers
DDR3
HP 2.0V 1866(3) 1866(3) 1600 1066 1600 1333 Mb/s
HP 1.8V 1600 1333 1066 800 1333 1066 Mb/s
HR N/A 1066 1066 800 800 1066 800 Mb/s
DDR3L
HP 2.0V 1600 1600 1333 1066 1600 1066 Mb/s
HP 1.8V 1333 1066 800 800 1066 800 Mb/s
HR N/A 800 800 667 N/A 800 667 Mb/s
DDR2
HP 2.0V 800 800 800 667 800 800 Mb/s
HP 1.8V 800 800 800 667 800 800 Mb/s
HR N/A 800 800 800 533 800 800 Mb/s
RLDRAM III
HP 2.0V 800 667 667 550 667 533 MHz
HP 1.8V 550 500 450 400 500 450 MHz
HR N/A N/A
2:1 Memory Controllers
DDR3
HP 2.0V 1066 1066 800 667 1066 800 Mb/s
HP 1.8V 1066 1066 800 667 1066 800 Mb/s
HR N/A 1066 1066 800 667 1066 800 Mb/s
DDR3L
HP 2.0V 1066 1066 800 667 1066 800 Mb/s
HP 1.8V 1066 1066 800 667 1066 800 Mb/s
HR N/A 800 800 667 N/A 800 667 Mb/s
DDR2
HP 2.0V
800 800 800
667
800 800 Mb/sHP 1.8V 667
HR N/A 533
QDR II+(4)
HP 2.0V 550 500 450 300 500 450 MHz
HP 1.8V
HR N/A 500 450 400 300 450 400 MHz
RLDRAM II
HP 2.0V
533 500 450 400 500 450 MHzHP 1.8V
HR N/A
LPDDR2
HP 2.0V 667 667 667 533 667 667 Mb/s
HP 1.8V 667 667 667 533 667 667 Mb/s
HR N/A 667 667 667 533 667 667 Mb/s
Notes:
1. VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide
(UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. For designs using 1866 Mb/s components, contact Xilinx Technical Support.
4. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 16
Table 19: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FB Packages)(1)(2)
Memory
Standard
I/O Bank
Type VCCAUX_IO(3)
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
4:1 Memory Controllers
DDR3 HP N/A 1333 1066 800 800 1066 800 Mb/s
HR N/A 1066 800 800 800 800 800 Mb/s
DDR3L HP N/A 1066 800 667 667 800 667 Mb/s
HR N/A 800 800 667 N/A 800 667 Mb/s
DDR2 HP N/A 800 800 800 667 800 800 Mb/s
HR N/A 800 667 667 533 667 667 Mb/s
RLDRAM III HP N/A 550 500 450 350 500 450 MHz
HR N/A N/A
2:1 Memory Controllers
DDR3 HP N/A 1066 1066 800 667 1066 800 Mb/s
HR N/A 1066 800 800 667 800 800 Mb/s
DDR3L HP N/A 1066 800 667 667 800 667 Mb/s
HR N/A 800 800 667 N/A 800 667 Mb/s
DDR2 HP N/A 800 800 800 667 800 800 Mb/s
HR N/A 800 667 667 533 667 667 Mb/s
QDR II+(4) HP N/A 550 500 450 300 500 450 MHz
HR N/A 450 400 350 300 400 350 MHz
RLDRAM II HP N/A 533 500 450 400 500 450 MHz
HR N/A
LPDDR2 HP N/A 667 667 667 400 667 667 Mb/s
HR N/A 667 667 533 400 667 533 Mb/s
Notes:
1. VREF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide
(UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. FB packages do not have separate VCCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks.
4. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 17
IOB Pad Input/Output/3-State
Table 20 (high-range IOB (HR)) and Table 21 (high-performance IOB (HP)) summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
•T
IOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
•T
IOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
•T
IOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI
termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the
IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
Table 20: IOB High Range (HR) Switching Characteristics
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
LVTTL_S4 1.31 1.42 1.64 1.64 1.42 1.51 3.77 3.90 4.00 4.00 3.90 4.13 3.52 3.67 3.86 3.86 3.67 3.85 ns
LVTTL_S8 1.31 1.42 1.64 1.64 1.42 1.51 3.50 3.64 3.73 3.73 3.64 3.86 3.26 3.40 3.60 3.60 3.40 3.58 ns
LVTTL_S12 1.31 1.42 1.64 1.64 1.42 1.51 3.49 3.62 3.72 3.72 3.62 3.84 3.24 3.39 3.58 3.58 3.39 3.56 ns
LVTTL_S16 1.31 1.42 1.64 1.64 1.42 1.51 3.03 3.17 3.26 3.26 3.17 3.39 2.79 2.93 3.13 3.13 2.93 3.11 ns
LVTTL_S24 1.31 1.42 1.64 1.64 1.42 1.51 3.25 3.39 3.48 3.48 3.39 3.61 3.01 3.15 3.35 3.35 3.15 3.33 ns
LVTTL_F4 1.31 1.42 1.64 1.64 1.42 1.51 3.22 3.36 3.45 3.45 3.36 3.58 2.98 3.12 3.32 3.32 3.12 3.30 ns
LVTTL_F8 1.31 1.42 1.64 1.64 1.42 1.51 2.71 2.84 2.93 2.93 2.84 3.06 2.46 2.61 2.80 2.80 2.61 2.78 ns
LVTTL_F12 1.31 1.42 1.64 1.64 1.42 1.51 2.69 2.82 2.92 2.92 2.82 3.05 2.44 2.59 2.79 2.79 2.59 2.77 ns
LVTTL_F16 1.31 1.42 1.64 1.64 1.42 1.51 2.57 2.85 3.15 3.15 2.85 2.88 2.33 2.61 3.02 3.02 2.61 2.60 ns
LVTTL_F24 1.31 1.42 1.64 1.64 1.42 1.51 2.41 2.64 2.89 3.04 2.64 2.94 2.16 2.41 2.76 2.91 2.41 2.66 ns
LVDS_25 0.64 0.68 0.80 0.87 0.68 0.83 1.36 1.47 1.55 1.55 1.47 1.58 1.11 1.24 1.41 1.41 1.24 1.30 ns
MINI_LVDS_25 0.68 0.70 0.79 0.87 0.70 0.83 1.36 1.47 1.55 1.55 1.47 1.59 1.11 1.24 1.41 1.41 1.24 1.31 ns
BLVDS_25 0.65 0.69 0.80 0.85 0.69 0.83 1.83 2.02 2.20 2.57 2.02 2.16 1.59 1.79 2.07 2.44 1.79 1.88 ns
RSDS_25
(point to point) 0.63 0.68 0.79 0.87 0.68 0.83 1.36 1.48 1.55 1.55 1.48 1.59 1.11 1.24 1.41 1.41 1.24 1.31 ns
PPDS_25 0.65 0.69 0.80 0.87 0.69 0.83 1.36 1.49 1.58 1.58 1.49 1.59 1.11 1.25 1.45 1.45 1.25 1.31 ns
TMDS_33 0.72 0.76 0.86 0.90 0.76 0.83 1.43 1.54 1.60 1.60 1.54 1.70 1.18 1.31 1.47 1.47 1.31 1.42 ns
PCI33_3 1.28 1.41 1.65 1.65 1.41 1.50 2.71 3.08 3.52 3.52 3.08 3.42 2.46 2.84 3.39 3.39 2.84 3.14 ns
HSUL_12_S 0.63 0.64 0.71 0.85 0.64 0.79 1.77 1.90 2.00 2.00 1.90 2.13 1.52 1.67 1.86 1.86 1.67 1.85 ns
HSUL_12_F 0.63 0.64 0.71 0.85 0.64 0.79 1.26 1.40 1.50 1.50 1.40 1.61 1.01 1.16 1.37 1.37 1.16 1.33 ns
DIFF_HSUL_
12_S 0.58 0.61 0.70 0.84 0.61 0.81 1.55 1.68 1.78 1.78 1.68 1.92 1.30 1.45 1.65 1.65 1.45 1.64 ns
DIFF_HSUL_
12_F 0.58 0.61 0.70 0.84 0.61 0.81 1.16 1.28 1.35 1.35 1.28 1.50 0.92 1.04 1.21 1.21 1.04 1.22 ns
MOBILE_DDR_S 0.64 0.66 0.74 0.74 0.66 0.89 2.58 2.91 3.31 3.31 2.91 1.95 2.33 2.68 3.17 3.17 2.68 1.67 ns
MOBILE_DDR_F 0.64 0.66 0.74 0.74 0.66 0.89 1.91 2.13 2.36 2.36 2.13 1.69 1.66 1.89 2.23 2.23 1.89 1.41 ns
DIFF_MOBILE_
DDR_S 0.63 0.66 0.75 0.75 0.66 0.79 2.51 2.84 3.24 3.24 2.84 1.95 2.26 2.61 3.10 3.10 2.61 1.67 ns
DIFF_MOBILE_
DDR_F 0.63 0.66 0.75 0.75 0.66 0.79 1.89 2.11 2.34 2.34 2.11 1.72 1.64 1.88 2.21 2.21 1.88 1.44 ns
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 18
HSTL_I_S 0.61 0.64 0.73 0.84 0.64 0.79 1.55 1.69 1.80 1.80 1.69 1.91 1.30 1.46 1.67 1.67 1.46 1.63 ns
HSTL_II_S 0.61 0.64 0.73 0.84 0.64 0.78 1.21 1.34 1.43 1.61 1.34 1.70 0.96 1.11 1.30 1.47 1.11 1.42 ns
HSTL_I_18_S 0.64 0.67 0.76 0.85 0.67 0.79 1.28 1.39 1.45 1.45 1.39 1.58 1.04 1.16 1.31 1.32 1.16 1.30 ns
HSTL_II_18_S 0.64 0.67 0.76 0.85 0.67 0.79 1.18 1.31 1.40 1.57 1.31 1.69 0.93 1.08 1.27 1.44 1.08 1.41 ns
DIFF_HSTL_I_S 0.63 0.67 0.77 0.84 0.67 0.78 1.42 1.54 1.61 1.78 1.54 1.84 1.17 1.31 1.48 1.65 1.31 1.56 ns
DIFF_HSTL_II_S 0.63 0.67 0.77 0.84 0.67 0.79 1.15 1.24 1.27 1.61 1.24 1.78 0.91 1.01 1.14 1.47 1.01 1.50 ns
DIFF_HSTL_I_
18_S 0.65 0.69 0.78 0.84 0.69 0.79 1.27 1.38 1.43 1.45 1.38 1.67 1.03 1.14 1.30 1.32 1.14 1.39 ns
DIFF_HSTL_II_
18_S 0.65 0.69 0.78 0.85 0.69 0.81 1.14 1.23 1.26 1.57 1.23 1.72 0.90 1.00 1.13 1.44 1.00 1.44 ns
HSTL_I_F 0.61 0.64 0.73 0.84 0.64 0.79 1.10 1.19 1.23 1.31 1.19 1.41 0.85 0.96 1.10 1.18 0.96 1.13 ns
HSTL_II_F 0.61 0.64 0.73 0.84 0.64 0.78 1.05 1.18 1.28 1.31 1.18 1.42 0.80 0.95 1.15 1.18 0.95 1.14 ns
HSTL_I_18_F 0.64 0.67 0.76 0.85 0.67 0.79 1.05 1.18 1.28 1.36 1.18 1.44 0.80 0.95 1.15 1.22 0.95 1.16 ns
HSTL_II_18_F 0.64 0.67 0.76 0.85 0.67 0.79 1.03 1.14 1.23 1.32 1.14 1.42 0.78 0.90 1.10 1.19 0.90 1.14 ns
DIFF_HSTL_I_F 0.63 0.67 0.77 0.84 0.67 0.78 1.09 1.18 1.22 1.31 1.18 1.48 0.84 0.95 1.09 1.18 0.95 1.20 ns
DIFF_HSTL_II_F 0.63 0.67 0.77 0.84 0.67 0.79 1.02 1.11 1.14 1.31 1.11 1.48 0.77 0.88 1.01 1.18 0.88 1.20 ns
DIFF_HSTL_I_
18_F 0.65 0.69 0.78 0.84 0.69 0.79 1.08 1.17 1.21 1.36 1.17 1.48 0.83 0.94 1.07 1.22 0.94 1.20 ns
DIFF_HSTL_II_
18_F 0.65 0.69 0.78 0.85 0.69 0.81 1.01 1.10 1.13 1.32 1.10 1.48 0.76 0.87 1.00 1.19 0.87 1.20 ns
LVCMOS33_S4 1.31 1.40 1.60 1.60 1.40 1.54 3.77 3.90 4.00 4.00 3.90 4.13 3.52 3.67 3.86 3.86 3.67 3.85 ns
LVCMOS33_S8 1.31 1.40 1.60 1.60 1.40 1.54 3.49 3.62 3.72 3.72 3.62 3.84 3.24 3.39 3.58 3.58 3.39 3.56 ns
LVCMOS33_S12 1.31 1.40 1.60 1.60 1.40 1.54 3.05 3.18 3.28 3.28 3.18 3.41 2.80 2.95 3.15 3.15 2.95 3.13 ns
LVCMOS33_S16 1.31 1.40 1.60 1.60 1.40 1.54 3.06 3.43 3.88 3.88 3.43 3.72 2.81 3.20 3.75 3.75 3.20 3.44 ns
LVCMOS33_F4 1.31 1.40 1.60 1.60 1.40 1.54 3.22 3.36 3.45 3.45 3.36 3.58 2.98 3.12 3.32 3.32 3.12 3.30 ns
LVCMOS33_F8 1.31 1.40 1.60 1.60 1.40 1.54 2.71 2.84 2.93 2.93 2.84 3.06 2.46 2.61 2.80 2.80 2.61 2.78 ns
LVCMOS33_F12 1.31 1.40 1.60 1.60 1.40 1.54 2.57 2.85 3.15 3.15 2.85 2.88 2.33 2.61 3.02 3.02 2.61 2.60 ns
LVCMOS33_F16 1.31 1.40 1.60 1.60 1.40 1.54 2.44 2.69 2.96 2.96 2.69 2.88 2.19 2.45 2.82 2.82 2.45 2.60 ns
LVCMOS25_S4 1.08 1.16 1.32 1.35 1.16 1.36 3.08 3.22 3.31 3.31 3.22 3.44 2.84 2.98 3.18 3.18 2.98 3.16 ns
LVCMOS25_S8 1.08 1.16 1.32 1.35 1.16 1.36 2.85 2.98 3.07 3.08 2.98 3.20 2.60 2.75 2.94 2.94 2.75 2.92 ns
LVCMOS25_S12 1.08 1.16 1.32 1.35 1.16 1.36 2.44 2.57 2.67 2.67 2.57 2.80 2.19 2.34 2.54 2.54 2.34 2.52 ns
LVCMOS25_S16 1.08 1.16 1.32 1.35 1.16 1.36 2.79 2.92 3.01 3.01 2.92 3.14 2.54 2.68 2.88 2.88 2.68 2.86 ns
LVCMOS25_F4 1.08 1.16 1.32 1.35 1.16 1.36 2.71 2.84 2.93 2.93 2.84 3.06 2.46 2.61 2.80 2.80 2.61 2.78 ns
LVCMOS25_F8 1.08 1.16 1.32 1.35 1.16 1.36 2.14 2.28 2.37 2.37 2.28 2.50 1.90 2.04 2.24 2.24 2.04 2.22 ns
LVCMOS25_F12 1.08 1.16 1.32 1.35 1.16 1.36 2.15 2.29 2.52 2.52 2.29 2.48 1.91 2.05 2.38 2.38 2.05 2.20 ns
LVCMOS25_F16 1.08 1.16 1.32 1.35 1.16 1.36 1.92 2.17 2.45 2.45 2.17 2.33 1.67 1.94 2.32 2.32 1.94 2.05 ns
LVCMOS18_S4 0.64 0.66 0.74 0.95 0.66 0.87 1.55 1.68 1.78 1.78 1.68 1.91 1.30 1.45 1.65 1.65 1.45 1.63 ns
LVCMOS18_S8 0.64 0.66 0.74 0.95 0.66 0.87 2.14 2.28 2.37 2.37 2.28 2.50 1.90 2.04 2.24 2.24 2.04 2.22 ns
LVCMOS18_S12 0.64 0.66 0.74 0.95 0.66 0.87 2.14 2.28 2.37 2.37 2.28 2.50 1.90 2.04 2.24 2.24 2.04 2.22 ns
LVCMOS18_S16 0.64 0.66 0.74 0.95 0.66 0.87 1.49 1.62 1.72 1.72 1.62 1.84 1.24 1.39 1.58 1.58 1.39 1.56 ns
Table 20: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 19
LVCMOS18_S24 0.64 0.66 0.74 0.95 0.66 0.87 1.74 1.92 2.08 2.22 1.92 1.92 1.50 1.69 1.95 2.08 1.69 1.64 ns
LVCMOS18_F4 0.64 0.66 0.74 0.95 0.66 0.87 1.38 1.51 1.61 1.64 1.51 1.77 1.13 1.28 1.47 1.50 1.28 1.49 ns
LVCMOS18_F8 0.64 0.66 0.74 0.95 0.66 0.87 1.64 1.78 1.87 1.87 1.78 2.00 1.40 1.54 1.74 1.74 1.54 1.72 ns
LVCMOS18_F12 0.64 0.66 0.74 0.95 0.66 0.87 1.64 1.78 1.87 1.87 1.78 2.00 1.40 1.54 1.74 1.74 1.54 1.72 ns
LVCMOS18_F16 0.64 0.66 0.74 0.95 0.66 0.87 1.52 1.68 1.81 1.81 1.68 1.72 1.28 1.45 1.68 1.68 1.45 1.44 ns
LVCMOS18_F24 0.64 0.66 0.74 0.95 0.66 0.87 1.34 1.46 1.55 2.09 1.46 1.66 1.09 1.23 1.42 1.96 1.23 1.38 ns
LVCMOS15_S4 0.66 0.69 0.81 0.93 0.69 0.90 1.86 2.00 2.09 2.09 2.00 2.22 1.62 1.76 1.96 1.96 1.76 1.94 ns
LVCMOS15_S8 0.66 0.69 0.81 0.93 0.69 0.90 2.05 2.18 2.28 2.28 2.18 2.41 1.80 1.95 2.14 2.15 1.95 2.13 ns
LVCMOS15_S12 0.66 0.69 0.81 0.93 0.69 0.90 1.83 2.03 2.23 2.23 2.03 1.91 1.59 1.80 2.10 2.10 1.80 1.63 ns
LVCMOS15_S16 0.66 0.69 0.81 0.93 0.69 0.90 1.76 1.95 2.13 2.13 1.95 1.91 1.52 1.72 1.99 1.99 1.72 1.63 ns
LVCMOS15_F4 0.66 0.69 0.81 0.93 0.69 0.90 1.63 1.76 1.86 1.86 1.76 1.98 1.38 1.53 1.72 1.72 1.53 1.70 ns
LVCMOS15_F8 0.66 0.69 0.81 0.93 0.69 0.90 1.79 1.99 2.18 2.18 1.99 1.92 1.55 1.76 2.05 2.05 1.76 1.64 ns
LVCMOS15_F12 0.66 0.69 0.81 0.93 0.69 0.90 1.40 1.54 1.65 1.65 1.54 1.67 1.15 1.31 1.52 1.52 1.31 1.39 ns
LVCMOS15_F16 0.66 0.69 0.81 0.93 0.69 0.90 1.37 1.51 1.61 1.89 1.51 1.66 1.13 1.27 1.48 1.75 1.27 1.38 ns
LVCMOS12_S4 0.88 0.91 1.00 1.17 0.91 1.01 2.53 2.67 2.76 2.76 2.67 2.89 2.29 2.43 2.63 2.63 2.43 2.61 ns
LVCMOS12_S8 0.88 0.91 1.00 1.17 0.91 1.01 2.05 2.18 2.28 2.28 2.18 2.41 1.80 1.95 2.14 2.15 1.95 2.13 ns
LVCMOS12_S12 0.88 0.91 1.00 1.17 0.91 1.01 1.75 1.89 1.98 1.98 1.89 2.11 1.51 1.65 1.85 1.85 1.65 1.83 ns
LVCMOS12_F4 0.88 0.91 1.00 1.17 0.91 1.01 1.94 2.07 2.17 2.17 2.07 2.30 1.69 1.84 2.04 2.04 1.84 2.02 ns
LVCMOS12_F8 0.88 0.91 1.00 1.17 0.91 1.01 1.50 1.64 1.73 1.73 1.64 1.86 1.26 1.40 1.60 1.60 1.40 1.58 ns
LVCMOS12_F12 0.88 0.91 1.00 1.17 0.91 1.01 1.54 1.71 1.87 1.87 1.71 1.69 1.29 1.48 1.74 1.74 1.48 1.41 ns
SSTL135_S 0.61 0.64 0.73 0.85 0.64 0.79 1.27 1.40 1.50 1.53 1.40 1.64 1.02 1.17 1.36 1.40 1.17 1.36 ns
SSTL15_S 0.61 0.64 0.73 0.73 0.64 0.73 1.24 1.37 1.47 1.53 1.37 1.59 0.99 1.14 1.33 1.40 1.14 1.31 ns
SSTL18_I_S 0.64 0.67 0.76 0.84 0.67 0.79 1.59 1.74 1.85 1.85 1.74 1.95 1.34 1.50 1.72 1.72 1.50 1.67 ns
SSTL18_II_S 0.64 0.67 0.76 0.85 0.67 0.78 1.27 1.40 1.50 1.50 1.40 1.63 1.02 1.17 1.36 1.36 1.17 1.35 ns
DIFF_SSTL135_
S0.59 0.61 0.73 0.85 0.61 0.79 1.27 1.40 1.50 1.53 1.40 1.64 1.02 1.17 1.36 1.40 1.17 1.36 ns
DIFF_SSTL15_S 0.63 0.67 0.77 0.85 0.67 0.79 1.24 1.37 1.47 1.53 1.37 1.59 0.99 1.14 1.33 1.40 1.14 1.31 ns
DIFF_SSTL18_
I_S 0.65 0.69 0.78 0.85 0.69 0.79 1.50 1.63 1.72 1.82 1.63 1.95 1.26 1.40 1.59 1.69 1.40 1.67 ns
DIFF_SSTL18_
II_S 0.65 0.69 0.78 0.85 0.69 0.79 1.13 1.22 1.25 1.50 1.22 1.66 0.88 0.99 1.12 1.36 0.99 1.38 ns
Table 20: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 20
SSTL135_F 0.61 0.64 0.73 0.85 0.64 0.79 1.04 1.17 1.26 1.31 1.17 1.42 0.79 0.93 1.13 1.18 0.93 1.14 ns
SSTL15_F 0.61 0.64 0.73 0.73 0.64 0.73 1.04 1.17 1.26 1.26 1.17 1.39 0.79 0.93 1.13 1.13 0.93 1.11 ns
SSTL18_I_F 0.64 0.67 0.76 0.84 0.67 0.79 1.12 1.22 1.26 1.34 1.22 1.44 0.88 0.99 1.13 1.21 0.99 1.16 ns
SSTL18_II_F 0.64 0.67 0.76 0.85 0.67 0.78 1.05 1.18 1.28 1.32 1.18 1.42 0.80 0.95 1.15 1.19 0.95 1.14 ns
DIFF_SSTL135_
F0.59 0.61 0.73 0.85 0.61 0.79 1.04 1.17 1.26 1.31 1.17 1.42 0.79 0.93 1.13 1.18 0.93 1.14 ns
DIFF_SSTL15_F 0.63 0.67 0.77 0.85 0.67 0.79 1.04 1.17 1.26 1.26 1.17 1.39 0.79 0.93 1.13 1.13 0.93 1.11 ns
DIFF_SSTL18_I_
F0.65 0.69 0.78 0.85 0.69 0.79 1.10 1.19 1.23 1.34 1.19 1.52 0.85 0.96 1.10 1.21 0.96 1.24 ns
DIFF_SSTL18_II
_F 0.65 0.69 0.78 0.85 0.69 0.79 1.02 1.10 1.14 1.32 1.10 1.50 0.77 0.87 1.00 1.19 0.87 1.22 ns
Table 20: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 21
Table 21: IOB High Performance (HP) Switching Characteristics
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
LVDS 0.75 0.79 0.92 0.96 0.79 0.89 1.05 1.17 1.24 1.26 1.17 1.43 0.88 1.01 1.08 1.10 1.01 1.32 ns
HSUL_12_S 0.69 0.72 0.82 0.98 0.72 0.95 1.65 1.84 2.05 2.05 1.84 1.80 1.48 1.68 1.89 1.89 1.68 1.70 ns
HSUL_12_F 0.69 0.72 0.82 0.98 0.72 0.95 1.39 1.54 1.68 1.68 1.54 1.49 1.22 1.38 1.52 1.52 1.38 1.39 ns
DIFF_HSUL_12_
S0.69 0.72 0.82 0.98 0.72 0.92 1.65 1.84 2.05 2.05 1.84 1.47 1.48 1.68 1.89 1.89 1.68 1.37 ns
DIFF_HSUL_12_F 0.69 0.72 0.82 0.98 0.72 0.92 1.39 1.54 1.68 1.68 1.54 1.35 1.22 1.38 1.52 1.52 1.38 1.24 ns
DIFF_HSUL_12_
DCI_S 0.69 0.72 0.82 0.82 0.72 0.92 1.78 1.91 2.05 2.05 1.91 1.46 1.61 1.76 1.89 1.89 1.76 1.35 ns
DIFF_HSUL_12_
DCI_F 0.69 0.72 0.82 0.82 0.72 0.92 1.56 1.67 1.76 1.76 1.67 1.35 1.39 1.51 1.60 1.60 1.51 1.24 ns
HSTL_I_S 0.68 0.72 0.82 0.90 0.72 0.84 1.15 1.28 1.38 1.38 1.28 1.46 0.98 1.12 1.22 1.22 1.12 1.35 ns
HSTL_II_S 0.68 0.72 0.82 0.90 0.72 0.84 1.05 1.17 1.26 1.27 1.17 1.44 0.88 1.01 1.10 1.11 1.01 1.34 ns
HSTL_I_18_S 0.70 0.72 0.82 0.95 0.72 0.86 1.12 1.24 1.34 1.34 1.24 1.41 0.95 1.08 1.18 1.18 1.08 1.31 ns
HSTL_II_18_S 0.70 0.72 0.82 0.90 0.72 0.86 1.06 1.18 1.26 1.27 1.18 1.44 0.89 1.02 1.10 1.11 1.02 1.34 ns
HSTL_I_12_S 0.68 0.72 0.82 0.96 0.72 0.94 1.14 1.27 1.37 1.37 1.27 1.43 0.97 1.11 1.21 1.21 1.11 1.32 ns
HSTL_I_DCI_S 0.68 0.72 0.82 0.90 0.72 0.78 1.11 1.23 1.33 1.33 1.23 1.36 0.94 1.07 1.17 1.17 1.07 1.26 ns
HSTL_II_DCI_S 0.68 0.72 0.82 0.85 0.72 0.78 1.05 1.17 1.26 1.26 1.17 1.33 0.88 1.01 1.10 1.10 1.01 1.23 ns
HSTL_II_T_DCI_
S0.70 0.72 0.82 0.82 0.72 0.76 1.15 1.28 1.38 1.38 1.28 1.40 0.98 1.12 1.22 1.22 1.12 1.29 ns
HSTL_I_DCI_18_
S0.70 0.72 0.82 0.90 0.72 0.76 1.11 1.23 1.33 1.33 1.23 1.36 0.94 1.07 1.17 1.17 1.07 1.26 ns
HSTL_II_DCI_18_
S0.70 0.72 0.82 0.82 0.72 0.76 1.05 1.16 1.24 1.24 1.16 1.32 0.88 1.00 1.08 1.08 1.00 1.21 ns
HSTL_II
_T_DCI_18_S 0.70 0.72 0.82 0.84 0.72 0.76 1.11 1.23 1.33 1.34 1.23 1.36 0.94 1.07 1.17 1.18 1.07 1.26 ns
DIFF_HSTL_I_S 0.75 0.79 0.92 1.02 0.79 0.89 1.15 1.28 1.38 1.38 1.28 1.47 0.98 1.12 1.22 1.22 1.12 1.37 ns
DIFF_HSTL_II_S 0.75 0.79 0.92 1.02 0.79 0.89 1.05 1.17 1.26 1.32 1.17 1.47 0.88 1.01 1.10 1.16 1.01 1.37 ns
DIFF_HSTL_I_
DCI_S 0.75 0.79 0.92 0.92 0.79 0.76 1.15 1.28 1.38 1.38 1.28 1.47 0.98 1.12 1.22 1.22 1.12 1.37 ns
DIFF_HSTL_II_
DCI_S 0.75 0.79 0.92 0.92 0.79 0.76 1.05 1.17 1.26 1.26 1.17 1.40 0.88 1.01 1.10 1.10 1.01 1.29 ns
DIFF_HSTL_I_
18_S 0.75 0.79 0.92 0.98 0.79 0.89 1.12 1.24 1.34 1.34 1.24 1.46 0.95 1.08 1.18 1.18 1.08 1.35 ns
DIFF_HSTL_II_
18_S 0.75 0.79 0.92 0.99 0.79 0.89 1.06 1.18 1.26 1.32 1.18 1.47 0.89 1.02 1.10 1.16 1.02 1.37 ns
DIFF_HSTL_I_
DCI_18_S 0.75 0.79 0.92 0.92 0.79 0.75 1.11 1.23 1.33 1.33 1.23 1.46 0.94 1.07 1.17 1.17 1.07 1.35 ns
DIFF_HSTL_II_
DCI_18_S 0.75 0.79 0.92 0.93 0.79 0.75 1.05 1.16 1.24 1.26 1.16 1.41 0.88 1.00 1.08 1.10 1.00 1.31 ns
DIFF_HSTL_II
_T_DCI_18_S 0.75 0.79 0.92 0.92 0.79 0.76 1.11 1.23 1.33 1.33 1.23 1.46 0.94 1.07 1.17 1.17 1.07 1.35 ns
HSTL_I_F 0.68 0.72 0.82 0.90 0.72 0.84 1.02 1.14 1.22 1.22 1.14 1.26 0.85 0.98 1.06 1.06 0.98 1.15 ns
HSTL_II_F 0.68 0.72 0.82 0.90 0.72 0.84 0.97 1.08 1.15 1.15 1.08 1.29 0.80 0.92 0.99 0.99 0.92 1.18 ns
HSTL_I_18_F 0.70 0.72 0.82 0.95 0.72 0.86 1.04 1.16 1.24 1.24 1.16 1.32 0.87 1.00 1.08 1.08 1.00 1.21 ns
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 22
HSTL_II_18_F 0.70 0.72 0.82 0.90 0.72 0.86 0.98 1.09 1.16 1.20 1.09 1.35 0.81 0.94 1.00 1.03 0.94 1.24 ns
HSTL_I_12_F 0.68 0.72 0.82 0.96 0.72 0.94 1.02 1.13 1.21 1.21 1.13 1.26 0.85 0.97 1.05 1.05 0.97 1.15 ns
HSTL_I_DCI_F 0.68 0.72 0.82 0.90 0.72 0.78 1.04 1.16 1.24 1.24 1.16 1.30 0.87 1.00 1.08 1.08 1.00 1.20 ns
HSTL_II_DCI_F 0.68 0.72 0.82 0.85 0.72 0.78 0.97 1.08 1.15 1.15 1.08 1.22 0.80 0.92 0.99 0.99 0.92 1.12 ns
HSTL_II_T_DCI_F 0.70 0.72 0.82 0.82 0.72 0.76 1.02 1.14 1.22 1.22 1.14 1.26 0.85 0.98 1.06 1.06 0.98 1.15 ns
HSTL_I_DCI_
18_F 0.70 0.72 0.82 0.90 0.72 0.76 1.04 1.16 1.24 1.24 1.16 1.30 0.87 1.00 1.08 1.08 1.00 1.20 ns
HSTL_II_DCI_
18_F 0.70 0.72 0.82 0.82 0.72 0.76 0.98 1.09 1.16 1.16 1.09 1.27 0.81 0.93 1.00 1.00 0.93 1.17 ns
HSTL_II
_T_DCI_18_F 0.70 0.72 0.82 0.84 0.72 0.76 1.04 1.16 1.24 1.24 1.16 1.30 0.87 1.00 1.08 1.08 1.00 1.20 ns
DIFF_HSTL_I_F 0.75 0.79 0.92 1.02 0.79 0.89 1.02 1.14 1.22 1.22 1.14 1.35 0.85 0.98 1.06 1.06 0.98 1.24 ns
DIFF_HSTL_II_F 0.75 0.79 0.92 1.02 0.79 0.89 0.97 1.08 1.15 1.20 1.08 1.35 0.80 0.92 0.99 1.03 0.92 1.24 ns
DIFF_HSTL_I_
DCI_F 0.75 0.79 0.92 0.92 0.79 0.76 1.02 1.14 1.22 1.22 1.14 1.35 0.85 0.98 1.06 1.06 0.98 1.24 ns
DIFF_HSTL_II_
DCI_F 0.75 0.79 0.92 0.92 0.79 0.76 0.97 1.08 1.15 1.15 1.08 1.30 0.80 0.92 0.99 0.99 0.92 1.20 ns
DIFF_HSTL_I_
18_F 0.75 0.79 0.92 0.98 0.79 0.89 1.04 1.16 1.24 1.24 1.16 1.38 0.87 1.00 1.08 1.08 1.00 1.28 ns
DIFF_HSTL_II_
18_F 0.75 0.79 0.92 0.99 0.79 0.89 0.98 1.09 1.16 1.24 1.09 1.40 0.81 0.94 1.00 1.08 0.94 1.29 ns
DIFF_HSTL_I_
DCI_18_F 0.75 0.79 0.92 0.92 0.79 0.75 1.04 1.16 1.24 1.24 1.16 1.38 0.87 1.00 1.08 1.08 1.00 1.28 ns
DIFF_HSTL_II_
DCI_18_F 0.75 0.79 0.92 0.93 0.79 0.75 0.98 1.09 1.16 1.18 1.09 1.33 0.81 0.93 1.00 1.02 0.93 1.23 ns
DIFF_HSTL_II
_T_DCI_18_F 0.75 0.79 0.92 0.92 0.79 0.76 1.04 1.16 1.24 1.24 1.16 1.38 0.87 1.00 1.08 1.08 1.00 1.28 ns
LVCMOS18_S2 0.47 0.50 0.60 0.90 0.50 0.87 3.95 4.28 4.85 4.85 4.28 3.40 3.78 4.13 4.69 4.69 4.13 3.29 ns
LVCMOS18_S4 0.47 0.50 0.60 0.90 0.50 0.87 2.67 2.98 3.43 3.43 2.98 2.69 2.50 2.82 3.27 3.27 2.82 2.59 ns
LVCMOS18_S6 0.47 0.50 0.60 0.90 0.50 0.87 2.14 2.38 2.72 2.72 2.38 2.18 1.97 2.22 2.56 2.56 2.22 2.07 ns
LVCMOS18_S8 0.47 0.50 0.60 0.90 0.50 0.87 1.98 2.21 2.52 2.52 2.21 2.02 1.81 2.05 2.36 2.36 2.05 1.92 ns
LVCMOS18_S12 0.47 0.50 0.60 0.90 0.50 0.87 1.70 1.91 2.17 2.17 1.91 1.85 1.53 1.75 2.01 2.01 1.75 1.74 ns
LVCMOS18_S16 0.47 0.50 0.60 0.90 0.50 0.87 1.57 1.75 1.97 1.97 1.75 1.76 1.40 1.59 1.81 1.81 1.59 1.65 ns
LVCMOS18_F2 0.47 0.50 0.60 0.90 0.50 0.87 3.50 3.87 4.48 4.48 3.87 2.85 3.33 3.71 4.32 4.32 3.71 2.74 ns
LVCMOS18_F4 0.47 0.50 0.60 0.90 0.50 0.87 2.23 2.50 2.87 2.87 2.50 2.26 2.06 2.34 2.71 2.71 2.34 2.15 ns
LVCMOS18_F6 0.47 0.50 0.60 0.90 0.50 0.87 1.80 2.00 2.26 2.26 2.00 1.52 1.63 1.84 2.09 2.09 1.84 1.42 ns
LVCMOS18_F8 0.47 0.50 0.60 0.90 0.50 0.87 1.46 1.72 2.04 2.04 1.72 1.51 1.29 1.56 1.88 1.88 1.56 1.40 ns
LVCMOS18_F12 0.47 0.50 0.60 0.90 0.50 0.87 1.26 1.40 1.53 1.53 1.40 1.46 1.09 1.24 1.37 1.37 1.24 1.35 ns
LVCMOS18_F16 0.47 0.50 0.60 0.90 0.50 0.87 1.19 1.33 1.44 1.66 1.33 1.46 1.02 1.17 1.28 1.50 1.17 1.35 ns
LVCMOS15_S2 0.59 0.62 0.73 0.88 0.62 0.86 3.55 3.89 4.45 4.45 3.89 3.11 3.38 3.73 4.29 4.29 3.73 3.01 ns
LVCMOS15_S4 0.59 0.62 0.73 0.88 0.62 0.86 2.45 2.70 3.06 3.06 2.70 2.46 2.28 2.54 2.90 2.90 2.54 2.35 ns
LVCMOS15_S6 0.59 0.62 0.73 0.88 0.62 0.86 2.24 2.51 2.88 2.88 2.51 2.33 2.07 2.35 2.72 2.72 2.35 2.23 ns
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 23
LVCMOS15_S8 0.59 0.62 0.73 0.88 0.62 0.86 1.91 2.16 2.49 2.49 2.16 2.05 1.74 2.00 2.32 2.32 2.00 1.95 ns
LVCMOS15_S12 0.59 0.62 0.73 0.88 0.62 0.86 1.77 1.98 2.23 2.23 1.98 1.97 1.60 1.82 2.07 2.07 1.82 1.87 ns
LVCMOS15_S16 0.59 0.62 0.73 0.88 0.62 0.86 1.62 1.81 2.02 2.02 1.81 1.85 1.45 1.65 1.86 1.86 1.65 1.74 ns
LVCMOS15_F2 0.59 0.62 0.73 0.88 0.62 0.86 3.38 3.69 4.18 4.18 3.69 2.74 3.21 3.53 4.02 4.02 3.53 2.64 ns
LVCMOS15_F4 0.59 0.62 0.73 0.88 0.62 0.86 2.04 2.21 2.44 2.44 2.21 1.72 1.87 2.06 2.27 2.27 2.06 1.62 ns
LVCMOS15_F6 0.59 0.62 0.73 0.88 0.62 0.86 1.47 1.74 2.09 2.09 1.74 1.49 1.30 1.58 1.93 1.93 1.58 1.39 ns
LVCMOS15_F8 0.59 0.62 0.73 0.88 0.62 0.86 1.31 1.46 1.61 1.61 1.46 1.47 1.14 1.30 1.45 1.45 1.30 1.37 ns
LVCMOS15_F12 0.59 0.62 0.73 0.88 0.62 0.86 1.21 1.34 1.45 1.45 1.34 1.44 1.04 1.18 1.29 1.29 1.18 1.34 ns
LVCMOS15_F16 0.59 0.62 0.73 0.88 0.62 0.86 1.18 1.31 1.41 1.68 1.31 1.41 1.01 1.15 1.25 1.52 1.15 1.31 ns
LVCMOS12_S2 0.64 0.67 0.78 1.04 0.67 0.95 3.38 3.80 4.48 4.48 3.80 3.27 3.21 3.64 4.31 4.31 3.64 3.17 ns
LVCMOS12_S4 0.64 0.67 0.78 1.04 0.67 0.95 2.62 2.94 3.43 3.43 2.94 2.76 2.45 2.78 3.27 3.27 2.78 2.65 ns
LVCMOS12_S6 0.64 0.67 0.78 1.04 0.67 0.95 2.05 2.33 2.72 2.72 2.33 2.24 1.88 2.17 2.56 2.56 2.17 2.14 ns
LVCMOS12_S8 0.64 0.67 0.78 1.04 0.67 0.95 1.94 2.18 2.51 2.51 2.18 2.16 1.77 2.02 2.34 2.34 2.02 2.06 ns
LVCMOS12_F2 0.64 0.67 0.78 1.04 0.67 0.95 2.84 3.15 3.62 3.62 3.15 2.47 2.67 2.99 3.46 3.46 2.99 2.37 ns
LVCMOS12_F4 0.64 0.67 0.78 1.04 0.67 0.95 1.97 2.18 2.44 2.44 2.18 1.69 1.80 2.02 2.28 2.28 2.02 1.59 ns
LVCMOS12_F6 0.64 0.67 0.78 1.04 0.67 0.95 1.33 1.51 1.70 1.70 1.51 1.43 1.16 1.35 1.54 1.54 1.35 1.32 ns
LVCMOS12_F8 0.64 0.67 0.78 1.04 0.67 0.95 1.27 1.42 1.55 1.55 1.42 1.41 1.10 1.26 1.39 1.39 1.26 1.31 ns
LVDCI_18 0.47 0.50 0.60 0.87 0.50 0.86 1.99 2.15 2.35 2.35 2.15 2.44 1.82 1.99 2.19 2.19 1.99 2.34 ns
LVDCI_15 0.59 0.62 0.73 0.92 0.62 0.87 1.98 2.23 2.58 2.58 2.23 2.40 1.81 2.07 2.41 2.41 2.07 2.29 ns
LVDCI_DV2_18 0.47 0.50 0.60 0.88 0.50 0.87 1.99 2.15 2.34 2.34 2.15 1.86 1.82 1.99 2.18 2.18 1.99 1.76 ns
LVDCI_DV2_15 0.59 0.62 0.73 0.88 0.62 0.87 1.98 2.23 2.58 2.58 2.23 1.83 1.81 2.07 2.41 2.41 2.07 1.73 ns
HSLVDCI_18 0.68 0.72 0.82 0.90 0.72 0.86 1.99 2.15 2.35 2.35 2.15 2.43 1.82 1.99 2.19 2.19 1.99 2.32 ns
HSLVDCI_15 0.68 0.72 0.82 0.93 0.72 0.84 1.98 2.23 2.58 2.58 2.23 2.27 1.81 2.07 2.41 2.41 2.07 2.17 ns
SSTL18_I_S 0.68 0.72 0.82 0.95 0.72 0.86 1.02 1.15 1.24 1.24 1.15 1.41 0.85 0.99 1.08 1.08 0.99 1.31 ns
SSTL18_II_S 0.68 0.72 0.82 1.01 0.72 0.87 1.17 1.29 1.37 1.38 1.29 1.55 1.00 1.13 1.21 1.22 1.13 1.45 ns
SSTL18_I_DCI_S 0.68 0.72 0.82 0.87 0.72 0.76 0.92 1.06 1.17 1.18 1.06 1.32 0.75 0.90 1.01 1.02 0.90 1.21 ns
SSTL18_II_DCI_S 0.68 0.72 0.82 0.82 0.72 0.78 0.88 0.98 1.08 1.12 0.98 1.26 0.71 0.83 0.92 0.96 0.83 1.15 ns
SSTL18_II_T_
DCI_S 0.68 0.72 0.82 0.98 0.72 0.78 0.92 1.06 1.17 1.18 1.06 1.32 0.75 0.90 1.01 1.02 0.90 1.21 ns
SSTL15_S 0.68 0.72 0.82 0.82 0.72 0.81 0.94 1.06 1.15 1.16 1.06 1.32 0.77 0.91 0.99 1.00 0.91 1.21 ns
SSTL15_DCI_S 0.68 0.72 0.82 0.90 0.72 0.78 0.94 1.06 1.15 1.16 1.06 1.30 0.77 0.90 0.99 1.00 0.90 1.20 ns
SSTL15_T_DCI_S 0.68 0.72 0.82 0.87 0.72 0.80 0.94 1.06 1.15 1.15 1.06 1.30 0.77 0.90 0.99 0.99 0.90 1.20 ns
SSTL135_S 0.69 0.72 0.82 0.93 0.72 0.89 0.97 1.10 1.19 1.20 1.10 1.35 0.80 0.94 1.03 1.03 0.94 1.24 ns
SSTL135_DCI_S 0.69 0.72 0.82 0.85 0.72 0.84 0.97 1.09 1.19 1.20 1.09 1.33 0.80 0.93 1.03 1.03 0.93 1.23 ns
SSTL135_T_
DCI_S 0.69 0.72 0.82 0.93 0.72 0.84 0.97 1.09 1.19 1.20 1.09 1.33 0.80 0.93 1.03 1.03 0.93 1.23 ns
SSTL12_S 0.69 0.72 0.82 1.02 0.72 0.95 0.96 1.09 1.18 1.18 1.09 1.33 0.79 0.93 1.02 1.02 0.93 1.23 ns
SSTL12_DCI_S 0.69 0.72 0.82 0.90 0.72 0.91 1.03 1.17 1.27 1.27 1.17 1.33 0.86 1.01 1.11 1.11 1.01 1.23 ns
SSTL12_T_DCI_S 0.69 0.72 0.82 0.88 0.72 0.91 1.03 1.17 1.27 1.27 1.17 1.33 0.86 1.01 1.11 1.11 1.01 1.23 ns
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 24
DIFF_SSTL18_
I_S 0.75 0.79 0.92 0.99 0.79 0.89 1.02 1.15 1.24 1.29 1.15 1.43 0.85 0.99 1.08 1.13 0.99 1.32 ns
DIFF_SSTL18_
II_S 0.75 0.79 0.92 0.93 0.79 0.89 1.17 1.29 1.37 1.40 1.29 1.55 1.00 1.13 1.21 1.24 1.13 1.45 ns
DIFF_SSTL18_
I_DCI_S 0.75 0.79 0.92 0.92 0.79 0.76 0.92 1.06 1.17 1.24 1.06 1.40 0.75 0.90 1.01 1.08 0.90 1.29 ns
DIFF_SSTL18_
II_DCI_S 0.75 0.79 0.92 0.96 0.79 0.75 0.88 0.98 1.08 1.18 0.98 1.33 0.71 0.83 0.92 1.02 0.83 1.23 ns
DIFF_SSTL18_
II_T_DCI_S 0.75 0.79 0.92 0.92 0.79 0.76 0.92 1.06 1.17 1.24 1.06 1.40 0.75 0.90 1.01 1.08 0.90 1.29 ns
DIFF_SSTL15_S 0.68 0.72 0.82 0.99 0.72 0.89 0.94 1.06 1.15 1.16 1.06 1.32 0.77 0.91 0.99 1.00 0.91 1.21 ns
DIFF_SSTL15_
DCI_S 0.68 0.72 0.82 0.96 0.72 0.75 0.94 1.06 1.15 1.16 1.06 1.30 0.77 0.90 0.99 1.00 0.90 1.20 ns
DIFF_SSTL15_T_
DCI_S 0.68 0.72 0.82 0.88 0.72 0.76 0.94 1.06 1.15 1.23 1.06 1.38 0.77 0.90 0.99 1.07 0.90 1.28 ns
DIFF_SSTL135_S 0.69 0.72 0.82 1.09 0.72 0.91 0.97 1.10 1.19 1.20 1.10 1.35 0.80 0.94 1.03 1.03 0.94 1.24 ns
DIFF_SSTL135_D
CI_S 0.69 0.72 0.82 0.90 0.72 0.76 0.97 1.09 1.19 1.20 1.09 1.33 0.80 0.93 1.03 1.03 0.93 1.23 ns
DIFF_SSTL135_
T_DCI_S 0.69 0.72 0.82 0.84 0.72 0.76 0.97 1.09 1.19 1.27 1.09 1.43 0.80 0.93 1.03 1.11 0.93 1.32 ns
DIFF_SSTL12_S 0.69 0.72 0.82 0.96 0.72 0.91 0.96 1.09 1.18 1.18 1.09 1.33 0.79 0.93 1.02 1.02 0.93 1.23 ns
DIFF_SSTL12_
DCI_S 0.69 0.72 0.82 0.87 0.72 0.78 1.03 1.17 1.27 1.27 1.17 1.33 0.86 1.01 1.11 1.11 1.01 1.23 ns
DIFF_SSTL12_
T_DCI_S 0.69 0.72 0.82 0.96 0.72 0.80 1.03 1.17 1.27 1.27 1.17 1.41 0.86 1.01 1.11 1.11 1.01 1.31 ns
SSTL18_I_F 0.68 0.72 0.82 0.95 0.72 0.86 0.94 1.06 1.15 1.15 1.06 1.32 0.77 0.91 0.99 0.99 0.91 1.21 ns
SSTL18_II_F 0.68 0.72 0.82 1.01 0.72 0.87 0.97 1.09 1.16 1.21 1.09 1.36 0.80 0.93 1.00 1.05 0.93 1.26 ns
SSTL18_I_DCI_F 0.68 0.72 0.82 0.87 0.72 0.76 0.89 1.02 1.10 1.15 1.02 1.30 0.72 0.86 0.94 0.99 0.86 1.20 ns
SSTL18_II_DCI_F 0.68 0.72 0.82 0.82 0.72 0.78 0.89 1.02 1.10 1.10 1.02 1.24 0.72 0.86 0.94 0.94 0.86 1.14 ns
SSTL18_II_T_
DCI_F 0.68 0.72 0.82 0.98 0.72 0.78 0.89 1.02 1.10 1.15 1.02 1.27 0.72 0.86 0.94 0.99 0.86 1.17 ns
SSTL15_F 0.68 0.72 0.82 0.82 0.72 0.81 0.89 1.01 1.09 1.09 1.01 1.24 0.72 0.85 0.93 0.93 0.85 1.14 ns
SSTL15_DCI_F 0.68 0.72 0.82 0.90 0.72 0.78 0.89 1.01 1.09 1.12 1.01 1.27 0.72 0.85 0.93 0.96 0.85 1.17 ns
SSTL15_T_DCI_F 0.68 0.72 0.82 0.87 0.72 0.80 0.89 1.01 1.09 1.12 1.01 1.27 0.72 0.85 0.93 0.96 0.85 1.17 ns
SSTL135_F 0.69 0.72 0.82 0.93 0.72 0.89 0.88 1.00 1.08 1.12 1.00 1.27 0.71 0.85 0.92 0.96 0.85 1.17 ns
SSTL135_DCI_F 0.69 0.72 0.82 0.85 0.72 0.84 0.89 1.00 1.08 1.12 1.00 1.27 0.72 0.85 0.92 0.96 0.85 1.17 ns
SSTL135_T_
DCI_F 0.69 0.72 0.82 0.93 0.72 0.84 0.89 1.00 1.08 1.12 1.00 1.27 0.72 0.85 0.92 0.96 0.85 1.17 ns
SSTL12_F 0.69 0.72 0.82 1.02 0.72 0.95 0.88 1.00 1.08 1.12 1.00 1.26 0.71 0.84 0.92 0.96 0.84 1.15 ns
SSTL12_DCI_F 0.69 0.72 0.82 0.90 0.72 0.91 0.91 1.03 1.11 1.11 1.03 1.24 0.74 0.88 0.95 0.95 0.88 1.14 ns
SSTL12_T_DCI_F 0.69 0.72 0.82 0.88 0.72 0.91 0.91 1.03 1.11 1.12 1.03 1.26 0.74 0.88 0.95 0.96 0.88 1.15 ns
DIFF_SSTL18_
I_F 0.75 0.79 0.92 0.99 0.79 0.89 0.94 1.06 1.15 1.23 1.06 1.38 0.77 0.91 0.99 1.07 0.91 1.28 ns
DIFF_SSTL18_
II_F 0.75 0.79 0.92 0.93 0.79 0.89 0.97 1.09 1.16 1.24 1.09 1.40 0.80 0.93 1.00 1.08 0.93 1.29 ns
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 25
Table 22 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as
the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than
TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always
faster than TIOTPHZ when the INTERMDISABLE pin is used.
DIFF_SSTL18_I_
DCI_F 0.75 0.79 0.92 0.92 0.79 0.76 0.89 1.02 1.10 1.23 1.02 1.36 0.72 0.86 0.94 1.07 0.86 1.26 ns
DIFF_SSTL18_II_
DCI_F 0.75 0.79 0.92 0.96 0.79 0.75 0.89 1.02 1.10 1.16 1.02 1.32 0.72 0.86 0.94 1.00 0.86 1.21 ns
DIFF_SSTL18_II_
T_DCI_F 0.75 0.79 0.92 0.92 0.79 0.76 0.89 1.02 1.10 1.24 1.02 1.38 0.72 0.86 0.94 1.08 0.86 1.28 ns
DIFF_SSTL15_F 0.68 0.72 0.82 0.99 0.72 0.89 0.89 1.01 1.09 1.09 1.01 1.24 0.72 0.85 0.93 0.93 0.85 1.14 ns
DIFF_SSTL15_D
CI_F 0.68 0.72 0.82 0.96 0.72 0.75 0.89 1.01 1.09 1.12 1.01 1.27 0.72 0.85 0.93 0.96 0.85 1.17 ns
DIFF_SSTL15_T_
DCI_F 0.68 0.72 0.82 0.88 0.72 0.76 0.89 1.01 1.09 1.20 1.01 1.35 0.72 0.85 0.93 1.03 0.85 1.24 ns
DIFF_SSTL135_F 0.69 0.72 0.82 1.09 0.72 0.91 0.88 1.00 1.08 1.12 1.00 1.27 0.71 0.85 0.92 0.96 0.85 1.17 ns
DIFF_SSTL135_
DCI_F 0.69 0.72 0.82 0.90 0.72 0.76 0.89 1.00 1.08 1.12 1.00 1.27 0.72 0.85 0.92 0.96 0.85 1.17 ns
DIFF_SSTL135_
T_DCI_F 0.69 0.72 0.82 0.84 0.72 0.76 0.89 1.00 1.08 1.20 1.00 1.35 0.72 0.85 0.92 1.03 0.85 1.24 ns
DIFF_SSTL12_F 0.69 0.72 0.82 0.96 0.72 0.91 0.88 1.00 1.08 1.12 1.00 1.26 0.71 0.84 0.92 0.96 0.84 1.15 ns
DIFF_SSTL12_
DCI_F 0.69 0.72 0.82 0.87 0.72 0.78 0.91 1.03 1.11 1.11 1.03 1.24 0.74 0.88 0.95 0.95 0.88 1.14 ns
DIFF_SSTL12_T_
DCI_F 0.69 0.72 0.82 0.96 0.72 0.80 0.91 1.03 1.11 1.18 1.03 1.33 0.74 0.88 0.95 1.02 0.88 1.23 ns
Table 22: IOB 3-state Output Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
TIOTPHZ T input to pad high-impedance 0.76 0.86 0.99 0.99 0.86 0.62 ns
TIOIBUFDISABLE_HR IBUF turn-on time from IBUFDISABLE to
O output for HR I/O banks
1.72 1.89 2.14 2.14 1.89 2.17 ns
TIOIBUFDISABLE_HP IBUF turn-on time from IBUFDISABLE to
O output for HP I/O banks
1.31 1.46 1.76 1.76 1.46 1.86 ns
Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE -3 -2/
-2LE -1 -1M/
-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 26
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 23 shows the test setup parameters used for measuring input delay.
Table 23: Input Delay Measurement Methodology
Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6
LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75
LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65
LVTTL, 3.3V LVTTL 0.1 3.2 1.65
MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9
PCI33, 3.3V PCI33_3 0.1 3.2 1.65
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 VREF –0.5 V
REF +0.5 V
REF 0.60
HSTL, Class I & II, 1.5V HSTL_I, HSTL_II VREF –0.65 V
REF +0.65 V
REF 0.75
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF –0.8 V
REF +0.8 V
REF 0.90
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL, 1.35V SSTL135, SSTL135_R VREF – 0.575 VREF + 0.575 VREF 0.675
SSTL, 1.5V SSTL15, SSTL15_R VREF –0.65 V
REF +0.65 V
REF 0.75
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF –0.8 V
REF +0.8 V
REF 0.90
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0(6)
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0(6)
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0(6)
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_SSTL, 1.2V DIFF_SSTL12 0.6 – 0.125 0.6 + 0.125 0(6)
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125 0(6)
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0(6)
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0(6)
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 0.9 – 0.125 0.9 + 0.125 0(6)
LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(6)
BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0(6)
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 27
Output Delay Measurements
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay
of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure 1 and Figure 2.
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction
of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 24.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4. Record the time to VMEAS.
TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0(6)
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1.
6. The value given is the differential input voltage.
X-Ref Target - Figure 1
Figure 1: Single-Ended Test Setup
X-Ref Target - Figure 2
Figure 2: Differential Test Setup
Table 23: Input Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS
(1)(4)(6)
VREF
(1)(3)(5)
VREF
RREF
VMEAS
(Voltage Level When Taking
Delay Measurement)
CREF
(Probe Capacitance)
FPGA Output
DS182_04_081114
RREF VMEAS
+
CREF
FPGA Output
DS182_05_080814
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 28
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
Table 24: Output Delay Measurement Methodology
Description I/O Standard Attribute RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
LVCMOS/LVDCI/HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 1M 0 0.75 0
LVCMOS/LVDCI/HSLVDCI, 1.8V LVCMOS18, LVDCI_15, HSLVDCI_18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
PCI33, 3.3V PCI33_3 25 10 1.65 0
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 VREF 0.6
HSTL, Class I, 1.5V HSTL_I 50 0 VREF 0.75
HSTL, Class II, 1.5V HSTL_II 25 0 VREF 0.75
HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 VREF 0.6
SSTL12, 1.2V SSTL12 50 0 VREF 0.6
SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 VREF 0.675
SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 VREF 0.75
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
SSTL18_I, SSTL18_II 50 0 VREF 0.9
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 VREF 0.9
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6
DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 VREF 0.75
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 VREF 0.9
DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 VREF 0.6
DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 VREF 0.6
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 VREF 0.675
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 VREF 0.75
DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9
LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 100 0 0(2) 0
LVDS, 2.5V LVDS_25 100 0 0(2) 0
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0
Mini LVDS, 2.5V MINI_LVDS_25 100 0 0(2) 0
PPDS_25 PPDS_25 100 0 0(2) 0
RSDS_25 RSDS_25 100 0 0(2) 0
TMDS_33 TMDS_33 50 0 0(2) 3.3
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 29
Input/Output Logic Switching Characteristics
Table 25: ILOGIC Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Setup/Hold
TICE1CK/
TICKCE1
CE1 pin Setup/Hold with respect to
CLK
0.42/0.00 0.48/0.00 0.67/0.00 0.67/0.00 0.48/0.00 0.56/–0.16 ns
TISRCK/TICKSR SR pin Setup/Hold with respect to CLK 0.53/0.01 0.61/0.01 0.99/0.01 0.99/0.01 0.61/0.01 0.88/–0.30 ns
TIDOCKE2/
TIOCKDE2
D pin Setup/Hold with respect to CLK
without Delay (HP I/O banks only)
0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 0.01/0.29 0.01/0.41 ns
TIDOCKDE2/
TIOCKDDE2
DDLY pin Setup/Hold with respect to
CLK (using IDELAY) (HP I/O banks
only)
0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 0.02/0.29 0.01/0.41 ns
TIDOCKE3/
TIOCKDE3
D pin Setup/Hold with respect to CLK
without Delay (HR I/O banks only)
0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.34 0.01/0.29 0.01/0.41 ns
TIDOCKDE3/
TIOCKDDE3
DDLY pin Setup/Hold with respect to
CLK (using IDELAY) (HR I/O banks
only)
0.01/0.27 0.02/0.29 0.02/0.34 0.02/0.34 0.02/0.29 0.01/0.41 ns
Combinatorial
TIDIE2 D pin to O pin propagation delay, no
Delay (HP I/O banks only)
0.09 0.10 0.12 0.12 0.10 0.14 ns
TIDIDE2 DDLY pin to O pin propagation delay
(using IDELAY) (HP I/O banks only)
0.10 0.11 0.13 0.13 0.11 0.15 ns
TIDIE3 D pin to O pin propagation delay, no
Delay (HR I/O banks only)
0.09 0.10 0.12 0.12 0.10 0.14 ns
TIDIDE3 DDLY pin to O pin propagation delay
(using IDELAY) (HR I/O banks only)
0.10 0.11 0.13 0.13 0.11 0.15 ns
Sequential Delays
TIDLOE2 D pin to Q1 pin using flip-flop as a latch
without Delay (HP I/O banks only)
0.36 0.39 0.45 0.45 0.39 0.54 ns
TIDLODE2 DDLY pin to Q1 pin using flip-flop as a
latch (using IDELAY) (HP I/O banks
only)
0.36 0.39 0.45 0.45 0.39 0.55 ns
TIDLOE3 D pin to Q1 pin using flip-flop as a latch
without Delay (HR I/O banks only)
0.36 0.39 0.45 0.45 0.39 0.54 ns
TIDLODE3 DDLY pin to Q1 pin using flip-flop as a
latch (using IDELAY) (HR I/O banks
only)
0.36 0.39 0.45 0.45 0.39 0.55 ns
TICKQ CLK to Q outputs 0.47 0.50 0.58 0.58 0.50 0.71 ns
TRQ_ILOGICE2 SR pin to OQ/TQ out (HP I/O banks
only)
0.84 0.94 1.16 1.16 0.94 1.32 ns
TGSRQ_ILOGICE2 Global Set/Reset to Q outputs
(HP I/O banks only)
7.60 7.60 10.51 10.51 7.60 11.39 ns
TRQ_ILOGICE3 SR pin to OQ/TQ out
(HR I/O banks only)
0.84 0.94 1.16 1.16 0.94 1.32 ns
TGSRQ_ILOGICE3 Global Set/Reset to Q outputs
(HR I/O banks only)
7.60 7.60 10.51 10.51 7.60 11.39 ns
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 30
Set/Reset
TRPW_ILOGICE2 Minimum Pulse Width, SR inputs (HP
I/O banks only)
0.54 0.63 0.63 0.63 0.63 0.68 ns,
Min
TRPW_ILOGICE3 Minimum Pulse Width, SR inputs (HR
I/O banks only)
0.54 0.63 0.63 0.63 0.63 0.68 ns,
Min
Table 26: OLOGIC Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Setup/Hold
TODCK/TOCKD D1/D2 pins Setup/Hold with
respect to CLK
0.45/–0.13 0.50/–0.13 0.58/–0.13 0.58/–0.13 0.50/–0.13 0.79/–0.18 ns
TOOCECK/
TOCKOCE
OCE pin Setup/Hold with
respect to CLK
0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 0.29/0.03 0.35/–0.10 ns
TOSRCK/TOCKSR SR pin Setup/Hold with respect
to CLK
0.32/0.18 0.38/0.18 0.70/0.18 0.70/0.18 0.38/0.18 0.62/–0.04 ns
TOTCK/TOCKT T1/T2 pins Setup/Hold with
respect to CLK
0.49/–0.16 0.56/–0.16 0.68/–0.16 0.68/–0.13 0.56/–0.16 0.67/–0.18 ns
TOTCECK/
TOCKTCE
TCE pin Setup/Hold with
respect to CLK
0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.06 0.30/0.01 0.31/–0.10 ns
Combinatorial
TODQ D1 to OQ out or T1 to TQ out 0.73 0.81 0.97 0.97 0.81 1.18 ns
Sequential Delays
TOCKQ CLK to OQ/TQ out 0.41 0.43 0.49 0.49 0.43 0.63 ns
TRQ_OLOGICE2 SR pin to OQ/TQ out (HP I/O
banks only)
0.63 0.70 0.83 0.83 0.70 1.12 ns
TGSRQ_OLOGICE2 Global Set/Reset to Q outputs
(HP I/O banks only)
7.60 7.60 10.51 10.51 7.60 11.39 ns
TRQ_OLOGICE3 SR pin to OQ/TQ out (HR I/O
banks only)
0.63 0.70 0.83 0.83 0.70 1.12 ns
TGSRQ_OLOGICE3 Global Set/Reset to Q outputs
(HR I/O banks only)
7.60 7.60 10.51 10.51 7.60 11.39 ns
Set/Reset
TRPW_OLOGICE2 Minimum Pulse Width, SR
inputs (HP I/O banks only)
0.54 0.54 0.63 0.63 0.54 0.68 ns,
Min
TRPW_OLOGICE3 Minimum Pulse Width, SR
inputs (HR I/O banks only)
0.54 0.54 0.63 0.63 0.54 0.68 ns,
Min
Table 25: ILOGIC Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 31
Input Serializer/Deserializer Switching Characteristics
Table 27: ISERDES Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Setup/Hold for Control Lines
TISCCK_BITSLIP/
TISCKC_BITSLIP
BITSLIP pin Setup/Hold with
respect to CLKDIV
0.01/0.12 0.02/0.13 0.02/0.15 0.02/0.15 0.02/0.13 0.02/0.21 ns
TISCCK_CE/
TISCKC_CE(2) CE pin Setup/Hold with respect
to CLK (for CE1)
0.39/–0.02 0.44/–0.02 0.63/–0.02 0.63/–0.02 0.44/–0.02 0.51/–0.22 ns
TISCCK_CE2/
TISCKC_CE2(2)
CE pin Setup/Hold with respect
to CLKDIV (for CE2)
–0.12/0.29 –0.12/0.31 –0.12/0.35 –0.12/0.35 –0.12/0.31 –0.17/0.40 ns
Setup/Hold for Data Lines
TISDCK_D/
TISCKD_D
D pin Setup/Hold with respect
to CLK
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.04/0.19 ns
TISDCK_DDLY/
TISCKD_DDLY
DDLY pin Setup/Hold with
respect to CLK (using
IDELAY)(1)
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.03/0.19 ns
TISDCK_D_DDR/
TISCKD_D_DDR
D pin Setup/Hold with respect
to CLK at DDR mode
–0.02/0.11 –0.02/0.12 –0.02/0.15 –0.02/0.15 –0.02/0.12 –0.04/0.19 ns
TISDCK_DDLY_DDR/
TISCKD_DDLY_DDR
D pin Setup/Hold with respect
to CLK at DDR mode (using
IDELAY)(1)
0.11/0.11 0.12/0.12 0.15/0.15 0.15/0.15 0.12/0.12 0.19/0.19 ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.46 0.47 0.58 0.58 0.47 0.67 ns
Propagation Delays
TISDO_DO D input to DO output pin 0.09 0.10 0.12 0.12 0.10 0.14 ns
Notes:
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 32
Output Serializer/Deserializer Switching Characteristics
Table 28: OSERDES Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Setup/Hold
TOSDCK_D/
TOSCKD_D
D input Setup/Hold with respect
to CLKDIV
0.37/0.02 0.40/0.02 0.55/0.02 0.55/0.02 0.40/0.02 0.44/–0.24 ns
TOSDCK_T/
TOSCKD_T(1)
T input Setup/Hold with respect
to CLK
0.49/–0.15 0.56/–0.15 0.68/–0.15 0.68/–0.15 0.56/–0.15 0.67/–0.25 ns
TOSDCK_T2/
TOSCKD_T2(1) T input Setup/Hold with respect
to CLKDIV
0.27/–0.15 0.30/–0.15 0.34/–0.15 0.34/–0.15 0.30/–0.15 0.46/–0.25 ns
TOSCCK_OCE/
TOSCKC_OCE
OCE input Setup/Hold with
respect to CLK
0.28/0.03 0.29/0.03 0.45/0.03 0.45/0.03 0.29/0.03 0.35/–0.15 ns
TOSCCK_S SR (Reset) input Setup with
respect to CLKDIV
0.41 0.46 0.75 0.75 0.46 0.70 ns
TOSCCK_TCE/
TOSCKC_TCE
TCE input Setup/Hold with
respect to CLK
0.28/0.01 0.30/0.01 0.45/0.01 0.45/0.01 0.30/0.01 0.31/–0.15 ns
Sequential Delays
TOSCKO_OQ Clock to out from CLK to OQ 0.35 0.37 0.42 0.42 0.37 0.54 ns
TOSCKO_TQ Clock to out from CLK to TQ 0.41 0.43 0.49 0.49 0.43 0.63 ns
Combinatorial
TOSDO_TTQ T input to TQ Out 0.73 0.81 0.97 0.97 0.81 1.18 ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 33
Input/Output Delay Switching Characteristics
Table 29: Input/Output Delay Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
IDELAYCTRL
TDLYCCO_RDY Reset to Ready for IDELAYCTRL 3.22 3.22 3.22 3.22 3.22 3.22 µs
FIDELAYCTRL_REF Attribute
REFCLK frequency = 200.00(1) 200.00 200.00 200.00 200.00 200.00 200.00 MHz
Attribute
REFCLK frequency = 300.00(1) 300.00 300.00 N/A N/A 300.00 N/A MHz
Attribute
REFCLK frequency = 400.00(1) 400.00 400.00 N/A N/A 400.00 N/A MHz
IDELAYCTRL_REF
_PRECISION
REFCLK precision ±10 ±10 ±10 ±10 ±10 ±10 MHz
TIDELAYCTRL_RPW Minimum Reset pulse width 52.00 52.00 52.00 52.00 52.00 52.00 ns
IDELAY/ODELAY
TIDELAYRESOLUTION IDELAY/ODELAY chain delay
resolution
1/(32x2xF
REFs
TIDELAYPAT_JIT and
TODELAYPAT_JIT
Pattern dependent period jitter in
delay chain for clock pattern.(2) 000000ps
per tap
Pattern dependent period jitter in
delay chain for random data pattern
(PRBS 23)(3)
±5 ±5 ±5 ±5 ±5 ±5 ps
per tap
Pattern dependent period jitter in
delay chain for random data pattern
(PRBS 23)(4)
±9 ±9 ±9 ±9 ±9 ±9 ps
per tap
TIDELAY_CLK_MAX/
TODELAY_CLK_MAX
Maximum frequency of CLK input to
IDELAY/ODELAY
800.00 800.00 710.00 710.00 800.00 710.00 MHz
TIDCCK_CE /
TIDCKC_CE
CE pin Setup/Hold with respect to C
for IDELAY
0.11/0.10 0.14/0.12 0.18/0.14 0.18/0.14 0.14/0.12 0.14/0.16 ns
TODCCK_CE /
TODCKC_CE
CE pin Setup/Hold with respect to C
for ODELAY
0.14/0.03 0.16/0.04 0.19/0.05 0.19/0.05 0.16/0.04 0.28/0.06 ns
TIDCCK_INC/
TIDCKC_INC
INC pin Setup/Hold with respect to
C for IDELAY
0.10/0.14 0.12/0.16 0.14/0.20 0.14/0.20 0.12/0.16 0.10/0.23 ns
TODCCK_INC/
TODCKC_INC
INC pin Setup/Hold with respect to
C for ODELAY
0.10/0.07 0.12/0.08 0.13/0.09 0.13/0.09 0.12/0.08 0.19/0.16 ns
TIDCCK_RST/
TIDCKC_RST
RST pin Setup/Hold with respect to
C for IDELAY
0.13/0.08 0.14/0.10 0.16/0.12 0.16/0.12 0.14/0.10 0.22/0.19 ns
TODCCK_RST/
TODCKC_RST
RST pin Setup/Hold with respect to
C for ODELAY
0.16/0.04 0.19/0.06 0.24/0.08 0.24/0.08 0.19/0.06 0.32/0.11 ns
TIDDO_IDATAIN Propagation delay through IDELAY Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ps
TODDO_ODATAIN Propagation delay through
ODELAY
Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 34
Table 30: IO_FIFO Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
IO_FIFO Clock to Out Delays
TOFFCKO_DO RDCLK to Q outputs 0.51 0.56 0.63 0.63 0.56 0.81 ns
TCKO_FLAGS Clock to IO_FIFO Flags 0.59 0.62 0.81 0.81 0.62 0.77 ns
Setup/Hold
TCCK_D/
TCKC_D
D inputs to WRCLK 0.43/–0.01 0.47/–0.01 0.53/–0.01 0.53/0.09 0.47/–0.01 0.76/–0.05 ns
TIFFCCK_WREN /
TIFFCKC_WREN
WREN to WRCLK 0.39/–0.01 0.43/–0.01 0.50/–0.01 0.50/–0.01 0.43/–0.01 0.70/–0.05 ns
TOFFCCK_RDEN/
TOFFCKC_RDEN
RDEN to RDCLK 0.49/0.01 0.53/0.02 0.61/0.02 0.61/0.02 0.53/0.02 0.79/–0.02 ns
Minimum Pulse Width
TPWH_IO_FIFO RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.08 0.92 1.29 ns
TPWL_IO_FIFO RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.08 0.92 1.29 ns
Maximum Frequency
FMAX RDCLK and WRCLK 533.05 470.37 400.00 400.00 470.37 333.33 MHz
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 35
CLB Switching Characteristics
Table 31: CLB Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Combinatorial Delays
TILO An – Dn LUT address to A 0.05 0.05 0.06 0.06 0.05 0.07 ns, Max
TILO_2 An – Dn LUT address to AMUX/CMUX 0.15 0.16 0.19 0.19 0.16 0.22 ns, Max
TILO_3 An – Dn LUT address to BMUX_A 0.24 0.25 0.30 0.30 0.25 0.37 ns, Max
TITO An – Dn inputs to A – D Q outputs 0.58 0.61 0.74 0.74 0.61 0.91 ns, Max
TAXA AX inputs to AMUX output 0.38 0.40 0.49 0.49 0.40 0.62 ns, Max
TAXB AX inputs to BMUX output 0.40 0.42 0.52 0.52 0.42 0.66 ns, Max
TAXC AX inputs to CMUX output 0.39 0.41 0.50 0.50 0.41 0.62 ns, Max
TAXD AX inputs to DMUX output 0.43 0.44 0.52 0.52 0.44 0.67 ns, Max
TBXB BX inputs to BMUX output 0.31 0.33 0.40 0.40 0.33 0.51 ns, Max
TBXD BX inputs to DMUX output 0.38 0.39 0.47 0.47 0.39 0.62 ns, Max
TCXC CX inputs to CMUX output 0.27 0.28 0.34 0.34 0.28 0.43 ns, Max
TCXD CX inputs to DMUX output 0.33 0.34 0.41 0.41 0.34 0.54 ns, Max
TDXD DX inputs to DMUX output 0.32 0.33 0.40 0.40 0.33 0.52 ns, Max
Sequential Delays
TCKO Clock to AQ – DQ outputs 0.26 0.27 0.32 0.32 0.27 0.40 ns, Max
TSHCKO Clock to AMUX – DMUX outputs 0.32 0.32 0.39 0.39 0.32 0.46 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TAS/TAH AN–D
N input to CLK on
A – D flip-flops
0.01/0.12 0.02/0.13 0.03/0.18 0.03/0.24 0.02/0.13 0.02/0.18 ns, Min
TDICK/TCKDI AX–D
X input to CLK on
A – D flip-flops
0.04/0.14 0.04/0.14 0.05/0.20 0.05/0.26 0.04/0.14 0.05/0.21 ns, Min
AX–D
X input through MUXs and/or
carry logic to CLK on A – D flip-flops
0.36/0.10 0.37/0.11 0.46/0.16 0.46/0.22 0.37/0.11 0.56/0.15 ns, Min
TCECK_CLB/
TCKCE_CLB
CE input to CLK on A – D flip-flops 0.19/0.05 0.20/0.05 0.25/0.05 0.25/0.11 0.20/0.05 0.24/0.04 ns, Min
TSRCK/TCKSR SR input to CLK on A – D flip-flops 0.30/0.05 0.31/0.07 0.37/0.09 0.37/0.22 0.31/0.07 0.48/0.05 ns, Min
Set/Reset
TSRMIN SR input minimum pulse width 0.52 0.78 1.04 1.04 0.78 0.95 ns, Min
TRQ Delay from SR input to
AQ – DQ flip-flops
0.38 0.38 0.46 0.46 0.38 0.59 ns, Max
TCEO Delay from CE input to
AQ – DQ flip-flops
0.34 0.35 0.43 0.43 0.35 0.54 ns, Max
FTOG Toggle frequency (for export control) 1818 1818 1818 1818 1818 1286 MHz
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 36
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 32: CLB Distributed RAM Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Sequential Delays
TSHCKO Clock to A – B outputs 0.68 0.70 0.85 0.85 0.70 1.08 ns, Max
TSHCKO_1 Clock to AMUX – BMUX outputs 0.91 0.95 1.15 1.15 0.95 1.44 ns, Max
Setup and Hold Times Before/After Clock CLK
TDS_LRAM/
TDH_LRAM
A – D inputs to CLK 0.45/0.23 0.45/0.24 0.54/0.27 0.54/0.28 0.45/0.24 0.69/0.33 ns, Min
TAS_LRAM/
TAH_LRAM
Address An inputs to clock 0.13/0.50 0.14/0.50 0.17/0.58 0.17/0.61 0.14/0.50 0.21/0.63 ns, Min
Address An inputs through MUXs
and/or carry logic to clock
0.40/0.16 0.42/0.17 0.52/0.23 0.52/0.29 0.42/0.17 0.63/0.23 ns, Min
TWS_LRAM/
TWH_LRAM
WE input to clock 0.29/0.09 0.30/0.09 0.36/0.09 0.36/0.11 0.30/0.09 0.46/0.10 ns, Min
TCECK_LRAM/
TCKCE_LRAM
CE input to CLK 0.29/0.09 0.30/0.09 0.37/0.09 0.37/0.11 0.30/0.09 0.47/0.10 ns, Min
Clock CLK
TMPW Minimum pulse width 0.68 0.77 0.91 0.91 0.77 1.11 ns, Min
TMCP Minimum clock period 1.35 1.54 1.82 1.82 1.54 2.22 ns, Min
Notes:
1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
Table 33: CLB Shift Register Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Sequential Delays
TREG Clock to A – D outputs 0.96 0.98 1.20 1.20 0.98 1.35 ns, Max
TREG_MUX Clock to AMUX – DMUX output 1.19 1.23 1.50 1.50 1.23 1.72 ns, Max
TREG_M31 Clock to DMUX output via M31
output
0.89 0.91 1.10 1.10 0.91 1.25 ns, Max
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG/
TWH_SHFREG
WE input 0.26/0.09 0.27/0.09 0.33/0.09 0.33/0.11 0.27/0.09 0.41/0.10 ns, Min
TCECK_SHFREG/
TCKCE_SHFREG
CE input to CLK 0.27/0.09 0.28/0.09 0.33/0.09 0.33/0.11 0.28/0.09 0.42/0.10 ns, Min
TDS_SHFREG/
TDH_SHFREG
A – D inputs to CLK 0.28/0.26 0.28/0.26 0.33/0.30 0.33/0.36 0.28/0.26 0.41/0.36 ns, Min
Clock CLK
TMPW_SHFREG Minimum pulse width 0.55 0.65 0.78 0.78 0.65 0.91 ns, Min
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 37
Block RAM and FIFO Switching Characteristics
Table 34: Block RAM and FIFO Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and
TRCKO_DO_REG(1)
Clock CLK to DOUT output
(without output register)(2)(3)
1.57 1.80 2.08 2.08 1.80 2.44 ns, Max
Clock CLK to DOUT output (with
output register)(4)(5)
0.54 0.63 0.75 0.75 0.63 0.86 ns, Max
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT output with
ECC (without output
register)(2)(3)
2.35 2.58 3.26 3.26 2.58 4.49 ns, Max
Clock CLK to DOUT output with
ECC (with output register)(4)(5) 0.62 0.69 0.80 0.80 0.69 0.94 ns, Max
TRCKO_DO_CASCOUT and
TRCKO_DO_CASCOUT_REG
Clock CLK to DOUT output with
Cascade (without output
register)(2)
2.21 2.45 2.80 2.80 2.45 3.19 ns, Max
Clock CLK to DOUT output with
Cascade (with output register)(4)
0.98 1.08 1.24 1.24 1.08 1.32 ns, Max
TRCKO_FLAGS Clock CLK to FIFO flags
outputs(6)
0.65 0.74 0.89 0.89 0.74 0.97 ns, Max
TRCKO_POINTERS Clock CLK to FIFO pointers
outputs(7) 0.79 0.87 0.98 0.98 0.87 1.10 ns, Max
TRCKO_PARITY_ECC Clock CLK to ECCPARITY in
ECC encode only mode
0.66 0.72 0.80 0.80 0.72 0.93 ns, Max
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without
output register)
2.17 2.38 3.01 3.01 2.38 4.15 ns, Max
Clock CLK to BITERR (with
output register)
0.57 0.65 0.76 0.76 0.65 0.89 ns, Max
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output
with ECC (without output
register)
0.64 0.74 0.90 0.90 0.74 0.98 ns, Max
Clock CLK to RDADDR output
with ECC (with output register)
0.71 0.79 0.92 0.92 0.79 1.10 ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA/
TRCKC_ADDRA
ADDR inputs(8) 0.38/
0.27
0.42/
0.28
0.48/
0.31
0.48/
0.38
0.42/
0.28
0.65/
0.38
ns, Min
TRDCK_DI_WF_NC/
TRCKD_DI_WF_NC
Data input setup/hold time when
block RAM is configured in
WRITE_FIRST or NO_CHANGE
mode(9)
0.49/
0.51
0.55/
0.53
0.63/
0.57
0.63/
0.57
0.55/
0.53
0.78/
0.64
ns, Min
TRDCK_DI_RF/
TRCKD_DI_RF
Data input setup/hold time when
block RAM is configured in
READ_FIRST mode(9)
0.17/
0.25
0.19/
0.29
0.21/
0.35
0.21/
0.35
0.19/
0.29
0.25/
0.32
ns, Min
TRDCK_DI_ECC/
TRCKD_DI_ECC
DIN inputs with block RAM ECC
in standard mode(9) 0.42/
0.37
0.47/
0.39
0.53/
0.43
0.53/
0.58
0.47/
0.39
0.66/
0.46
ns, Min
TRDCK_DI_ECCW/
TRCKD_DI_ECCW
DIN inputs with block RAM ECC
encode only(9)
0.79/
0.37
0.87/
0.39
0.99/
0.43
0.99/
0.58
0.87/
0.39
1.17/
0.41
ns, Min
TRDCK_DI_ECC_FIFO/
TRCKD_DI_ECC_FIFO
DIN inputs with FIFO ECC in
standard mode(9)
0.89/
0.47
0.98/
0.50
1.12/
0.54
1.12/
0.69
0.98/
0.50
1.32/
0.65
ns, Min
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 38
TRCCK_INJECTBITERR/
TRCKC_INJECTBITERR
Inject single/double bit error in
ECC mode
0.49/
0.30
0.55/
0.31
0.63/
0.34
0.63/
0.43
0.55/
0.31
0.78/
0.41
ns, Min
TRCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.30/
0.17
0.33/
0.18
0.38/
0.20
0.38/
0.32
0.33/
0.18
0.48/
0.22
ns, Min
TRCCK_REGCE/
TRCKC_REGCE
CE input of output register 0.21/
0.13
0.25/
0.13
0.31/
0.14
0.31/
0.19
0.25/
0.13
0.34/
0.16
ns, Min
TRCCK_RSTREG/
TRCKC_RSTREG
Synchronous RSTREG input 0.25/
0.06
0.27/
0.06
0.29/
0.06
0.29/
0.14
0.27/
0.06
0.35/
0.06
ns, Min
TRCCK_RSTRAM/
TRCKC_RSTRAM
Synchronous RSTRAM input 0.27/
0.35
0.29/
0.37
0.31/
0.39
0.31/
0.39
0.29/
0.37
0.34/
0.40
ns, Min
TRCCK_WEA/
TRCKC_WEA
Write Enable (WE) input (Block
RAM only)
0.38/
0.15
0.41/
0.16
0.46/
0.17
0.46/
0.29
0.41/
0.16
0.54/
0.19
ns, Min
TRCCK_WREN/
TRCKC_WREN
WREN FIFO inputs 0.39/
0.25
0.39/
0.30
0.40/
0.37
0.40/
0.49
0.39/
0.30
0.65/
0.37
ns, Min
TRCCK_RDEN/
TRCKC_RDEN
RDEN FIFO inputs 0.36/
0.26
0.36/
0.30
0.37/
0.37
0.37/
0.49
0.36/
0.30
0.60/
0.38
ns, Min
Reset Delays
TRCO_FLAGS Reset RST to FIFO
flags/pointers(10)
0.76 0.83 0.93 0.93 0.83 1.06 ns, Max
TRREC_RST/
TRREM_RST
FIFO reset recovery and removal
timing(11) 1.59/
–0.68
1.76/
–0.68
2.01/
–0.68
2.01/
–0.68
1.76/
–0.68
2.07/
–0.60
ns, Max
Maximum Frequency
FMAX_BRAM_WF_NC Block RAM
(Write first and No change
modes)
When not in SDP RF mode
601.32 543.77 458.09 458.09 543.77 372.44 MHz
FMAX_BRAM_RF
_PERFORMANCE
Block RAM
(Read first, Performance mode)
When in SDP RF mode but no
address overlap between port A
and port B
601.32 543.77 458.09 458.09 543.77 372.44 MHz
FMAX_BRAM_RF_
DELAYED_WRITE
Block RAM
(Read first, Delayed_write mode)
When in SDP RF mode and
there is possibility of overlap
between port A and port B
addresses
528.26 477.33 400.80 400.80 477.33 317.36 MHz
FMAX_CAS_WF_NC Block RAM Cascade
(Write first, No change mode)
When cascade but not in RF
mode
551.27 493.83 408.00 408.00 493.83 322.48 MHz
FMAX_CAS_RF
_PERFORMANCE
Block RAM Cascade
(Read first, Performance mode)
When in cascade with RF mode
and no possibility of address
overlap/one port is disabled
551.27 493.83 408.00 408.00 493.83 322.48 MHz
Table 34: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 39
FMAX_CAS_RF_
DELAYED_WRITE
When in cascade RF mode and
there is a possibility of address
overlap between port A and port
B
478.24 427.35 350.88 350.88 427.35 267.38 MHz
FMAX_FIFO FIFO in all modes without ECC 601.32 543.77 458.09 458.09 543.77 372.44 MHz
FMAX_ECC Block RAM and FIFO in ECC
configuration
484.26 430.85 351.12 351.12 430.85 254.13 MHz
Notes:
1. The timing report shows all of these parameters as TRCKO_DO.
2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
Table 34: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 40
DSP48E1 Switching Characteristics
Table 35: DSP48E1 Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_AREG/
TDSPCKD_A_AREG
A input to A register CLK 0.24/
0.12
0.27/
0.14
0.31/
0.16
0.33/
0.18
0.27/
0.14
0.38/
0.12
ns
TDSPDCK_B_BREG/
TDSPCKD_B_BREG
B input to B register CLK 0.28/
0.13
0.32/
0.14
0.39/
0.15
0.41/
0.18
0.32/
0.14
0.51/
0.16
ns
TDSPDCK_C_CREG/
TDSPCKD_C_CREG
C input to C register CLK 0.15/
0.15
0.17/
0.17
0.20/
0.20
0.20/
0.22
0.17/
0.17
0.31/
0.21
ns
TDSPDCK_D_DREG/
TDSPCKD_D_DREG
D input to D register CLK 0.21/
0.19
0.27/
0.22
0.35/
0.26
0.35/
0.27
0.27/
0.22
0.46/
0.20
ns
TDSPDCK_ACIN_AREG/
TDSPCKD_ACIN_AREG
ACIN input to A register CLK 0.21/
0.12
0.24/
0.14
0.27/
0.16
0.30/
0.16
0.24/
0.14
0.31/
0.12
ns
TDSPDCK_BCIN_BREG/
TDSPCKD_BCIN_BREG
BCIN input to B register CLK 0.22/
0.13
0.25/
0.14
0.30/
0.15
0.32/
0.15
0.25/
0.14
0.34/
0.16
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, B}_MREG_MULT/
TDSPCKD_{A, B}_MREG_MULT
{A, B} input to M register CLK
using multiplier
2.04/
–0.01
2.34/
–0.01
2.79/
–0.01
2.79/
–0.01
2.34/
–0.01
3.66/
–0.06
ns
TDSPDCK_{A, D}_ADREG/
TDSPCKD_{A, D}_ADREG
{A, D} input to AD register CLK 1.09/
–0.02
1.25/
–0.02
1.49/
–0.02
1.49/
–0.02
1.25/
–0.02
1.94/
–0.23
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT/
TDSPCKD_{A, B} _PREG_MULT
{A, B,} input to P register CLK
using multiplier
3.41/
–0.24
3.90/
–0.24
4.64/
–0.24
4.64/
–0.24
3.90/
–0.24
5.89/
–0.41
ns
TDSPDCK_D_PREG_MULT/
TDSPCKD_D_PREG_MULT
D input to P register CLK
using multiplier
3.33/
–0.62
3.81/
–0.62
4.53/
–0.62
4.53/
–0.62
3.81/
–0.62
5.70/
–1.42
ns
TDSPDCK_{A, B} _PREG/
TDSPCKD_{A, B} _PREG
A or B input to P register CLK
not using multiplier
1.47/
–0.24
1.68/
–0.24
2.00/
–0.24
2.00/
–0.24
1.68/
–0.24
2.37/
–0.41
ns
TDSPDCK_C_PREG/
TDSPCKD_C_PREG
C input to P register CLK not
using multiplier
1.30/
–0.22
1.49/
–0.22
1.78/
–0.22
1.78/
–0.22
1.49/
–0.22
2.11/
–0.36
ns
TDSPDCK_PCIN_PREG/
TDSPCKD_PCIN_PREG
PCIN input to P register CLK 1.12/
–0.13
1.28/
–0.13
1.52/
–0.13
1.52/
–0.13
1.28/
–0.13
1.81/
–0.21
ns
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA;CEB}_{AREG;BREG}/
TDSPCKD_{CEA;CEB}_{AREG;BREG}
{CEA; CEB} input to {A; B}
register CLK
0.30/
0.05
0.36/
0.06
0.44/
0.09
0.44/
0.09
0.36/
0.06
0.55/
0.09
ns
TDSPDCK_CEC_CREG/
TDSPCKD_CEC_CREG
CEC input to C register CLK 0.24/
0.08
0.29/
0.09
0.36/
0.11
0.36/
0.11
0.29/
0.09
0.43/
0.11
ns
TDSPDCK_CED_DREG/
TDSPCKD_CED_DREG
CED input to D register CLK 0.31/
–0.02
0.36/
–0.02
0.44/
–0.02
0.44/
0.02
0.36/
–0.02
0.58/
0.12
ns
TDSPDCK_CEM_MREG/
TDSPCKD_CEM_MREG
CEM input to M register CLK 0.26/
0.15
0.29/
0.17
0.33/
0.20
0.33/
0.20
0.29/
0.17
0.39/
0.25
ns
TDSPDCK_CEP_PREG/
TDSPCKD_CEP_PREG
CEP input to P register CLK 0.31/
0.01
0.36/
0.01
0.45/
0.01
0.45/
0.01
0.36/
0.01
0.54/
0.00
ns
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 41
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/
TDSPCKD_{RSTA; RSTB}_{AREG; BREG}
{RSTA, RSTB} input to {A, B}
register CLK
0.34/
0.10
0.39/
0.11
0.47/
0.13
0.47/
0.14
0.39/
0.11
0.53/
0.34
ns
TDSPDCK_RSTC_CREG/
TDSPCKD_RSTC_CREG
RSTC input to C register CLK 0.06/
0.22
0.07/
0.24
0.08/
0.26
0.08/
0.26
0.07/
0.24
0.08/
0.31
ns
TDSPDCK_RSTD_DREG/
TDSPCKD_RSTD_DREG
RSTD input to D register CLK 0.37/
0.06
0.42/
0.06
0.50/
0.07
0.50/
0.07
0.42/
0.06
0.57/
0.07
ns
TDSPDCK_RSTM_MREG/
TDSPCKD_RSTM_MREG
RSTM input to M register CLK 0.18/
0.18
0.20/
0.21
0.23/
0.24
0.23/
0.24
0.20/
0.21
0.24/
0.29
ns
TDSPDCK_RSTP_PREG/
TDSPCKD_RSTP_PREG
RSTP input to P register CLK 0.24/
0.01
0.26/
0.01
0.30/
0.01
0.30/
0.11
0.26/
0.01
0.37/
0.00
ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output
using multiplier
3.21 3.69 4.39 4.39 3.69 5.60 ns
TDSPDO_D_P_MULT D input to P output using
multiplier
3.15 3.61 4.30 4.30 3.61 5.44 ns
TDSPDO_A_P A input to P output not using
multiplier
1.30 1.48 1.76 1.76 1.48 2.10 ns
TDSPDO_C_P C input to P output 1.13 1.30 1.55 1.55 1.30 1.84 ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT,
BCOUT} output
0.47 0.53 0.63 0.63 0.53 0.75 ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to
CARRYCASCOUT output
using multiplier
3.44 3.94 4.69 4.69 3.94 5.96 ns
TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT
output using multiplier
3.36 3.85 4.58 4.58 3.85 5.77 ns
TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to
CARRYCASCOUT output not
using multiplier
1.50 1.72 2.04 2.04 1.72 2.44 ns
TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT
output
1.34 1.53 1.83 1.83 1.53 2.18 ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT ACIN input to P output using
multiplier
3.09 3.55 4.24 4.24 3.55 5.42 ns
TDSPDO_ACIN_P ACIN input to P output not
using multiplier
1.16 1.33 1.59 1.59 1.33 2.07 ns
TDSPDO_ACIN_ACOUT ACIN input to ACOUT output 0.32 0.37 0.45 0.45 0.37 0.53 ns
TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to
CARRYCASCOUT output
using multiplier
3.30 3.79 4.52 4.52 3.79 5.76 ns
TDSPDO_ACIN_CARRYCASCOUT ACIN input to
CARRYCASCOUT output not
using multiplier
1.37 1.57 1.87 1.87 1.57 2.40 ns
TDSPDO_PCIN_P PCIN input to P output 0.94 1.08 1.29 1.29 1.08 1.54 ns
TDSPDO_PCIN_CARRYCASCOUT PCIN input to
CARRYCASCOUT output
1.15 1.32 1.57 1.57 1.32 1.88 ns
Table 35: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 42
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG CLK PREG to P output 0.33 0.35 0.39 0.39 0.35 0.45 ns
TDSPCKO_CARRYCASCOUT_PREG CLK PREG to
CARRYCASCOUT output
0.44 0.50 0.59 0.59 0.50 0.71 ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG CLK MREG to P output 1.42 1.64 1.96 1.96 1.64 2.31 ns
TDSPCKO_CARRYCASCOUT_MREG CLK MREG to
CARRYCASCOUT output
1.63 1.87 2.24 2.24 1.87 2.65 ns
TDSPCKO_P_ADREG_MULT CLK ADREG to P output using
multiplier
2.30 2.63 3.13 3.13 2.63 3.90 ns
TDSPCKO_CARRYCASCOUT_
ADREG_MULT
CLK ADREG to
CARRYCASCOUT output
using multiplier
2.51 2.87 3.41 3.41 2.87 4.23 ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT CLK AREG to P output using
multiplier
3.34 3.83 4.55 4.55 3.83 5.80 ns
TDSPCKO_P_BREG CLK BREG to P output not
using multiplier
1.39 1.59 1.88 1.88 1.59 2.24 ns
TDSPCKO_P_CREG CLK CREG to P output not
using multiplier
1.43 1.64 1.95 1.95 1.64 2.32 ns
TDSPCKO_P_DREG_MULT CLK DREG to P output using
multiplier
3.32 3.80 4.51 4.51 3.80 5.74 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}
_{AREG; BREG}
CLK (ACOUT, BCOUT) to
{A,B} register output
0.55 0.62 0.74 0.74 0.62 0.87 ns
TDSPCKO_CARRYCASCOUT_
{AREG, BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output
using multiplier
3.55 4.06 4.84 4.84 4.06 6.13 ns
TDSPCKO_CARRYCASCOUT_ BREG CLK BREG to
CARRYCASCOUT output not
using multiplier
1.60 1.82 2.16 2.16 1.82 2.58 ns
TDSPCKO_CARRYCASCOUT
_ DREG_MULT
CLK DREG to
CARRYCASCOUT output
using multiplier
3.52 4.03 4.79 4.79 4.03 6.07 ns
TDSPCKO_CARRYCASCOUT_ CREG CLK CREG to
CARRYCASCOUT output
1.64 1.88 2.23 2.23 1.88 2.65 ns
Maximum Frequency
FMAX With all registers used 741.84 650.20 547.95 547.95 650.20 429.37 MHz
FMAX_PATDET With pattern detector 627.35 549.75 463.61 463.61 549.75 365.90 MHz
FMAX_MULT_NOMREG Two register multiply without
MREG
412.20 360.75 303.77 303.77 360.75 248.32 MHz
FMAX_MULT_NOMREG_PATDET Two register multiply without
MREG with pattern detect
374.25 327.65 276.01 276.01 327.65 225.73 MHz
FMAX_PREADD_MULT_NOADREG Without ADREG 468.82 408.66 342.70 342.70 408.66 263.44 MHz
FMAX_PREADD_MULT_
NOADREG_PATDET
Without ADREG with pattern
detect
468.82 408.66 342.70 342.70 408.66 263.44 MHz
Table 35: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 43
Clock Buffers and Networks
FMAX_NOPIPELINEREG Without pipeline registers
(MREG, ADREG)
306.84 267.81 225.02 225.02 267.81 177.15 MHz
FMAX_NOPIPELINEREG_PATDET Without pipeline registers
(MREG, ADREG) with pattern
detect
285.23 249.13 209.38 209.38 249.13 165.32 MHz
Table 36: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
TBCCCK_CE/
TBCCKC_CE(1)
CE pins Setup/Hold 0.12/0.30 0.14/0.38 0.26/0.38 0.26/0.92 0.14/0.38 0.23/0.40 ns
TBCCCK_S/
TBCCKC_S(1) S pins Setup/Hold 0.12/0.30 0.14/0.38 0.26/0.38 0.26/0.92 0.14/0.38 0.23/0.40 ns
TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O 0.08 0.10 0.12 0.12 0.10 0.10 ns
Maximum Frequency
FMAX_BUFG Global clock tree (BUFG) 741.00 710.00 625.00 625.00 710.00 560.00 MHz
Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 37: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
TBIOCKO_O Clock to out delay from I to O 1.04 1.14 1.32 1.32 1.14 1.48 ns
Maximum Frequency
FMAX_BUFIO I/O clock tree (BUFIO) 800.00 800.00 710.00 710.00 800.00 710.00 MHz
Table 38: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
TBRCKO_O Clock to out delay from
I to O
0.60 0.65 0.77 0.77 0.65 1.06 ns
TBRCKO_O_BYP Clock to out delay from I to O with
Divide Bypass attribute set
0.30 0.32 0.38 0.38 0.32 0.57 ns
TBRDO_O Propagation delay from CLR to O 0.71 0.75 0.96 0.96 0.75 0.93 ns
Table 35: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 44
Maximum Frequency
FMAX_BUFR(1) Regional clock tree (BUFR) 600.00 540.00 450.00 450.00 540.00 450.00 MHz
Notes:
1. The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency except for the BUFMR in the -2LE at 0.9V, which has
a maximum input frequency of 667 MHz.
Table 39: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
TBHCKO_O BUFH delay from I to O 0.10 0.11 0.13 0.13 0.11 0.12 ns
TBHCCK_CE/
TBHCKC_CE CE pin Setup and Hold 0.20/0.16 0.23/0.20 0.38/0.21 0.38/0.79 0.23/0.20 0.28/0.09 ns
Maximum Frequency
FMAX_BUFH Horizontal clock buffer (BUFH) 741.00 710.00 625.00 625.00 710.00 560.00 MHz
Table 40: Duty Cycle Distortion and Clock-Tree Skew
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
TDCD_CLK Global Clock Tree Duty Cycle
Distortion(1)
All 0.20 0.20 0.20 0.20 All 0.25 ns
TCKSKEW Global Clock Tree Skew(2) XC7K70T 0.29 0.40 0.40 N/A N/A 0.47 ns
XC7K160T 0.42 0.53 0.57 N/A 0.53 0.59 ns
XC7K325T 0.59 0.74 0.79 N/A 0.74 0.91 ns
XC7K355T 0.45 0.57 0.59 N/A 0.57 0.69 ns
XC7K410T 0.60 0.74 0.79 N/A 0.74 0.91 ns
XC7K420T 0.60 0.74 0.79 N/A 0.74 0.91 ns
XC7K480T 0.60 0.74 0.79 N/A 0.74 0.91 ns
XQ7K325T N/A 0.74 0.79 0.79 0.74 0.91 ns
XQ7K410T N/A 0.74 0.79 0.79 0.74 0.91 ns
TDCD_BUFIO I/O clock tree duty cycle
distortion
All 0.12 0.12 0.12 0.12 0.12 0.12 ns
TBUFIOSKEW I/O clock tree skew across
one clock region
All 0.02 0.02 0.02 0.02 0.02 0.03 ns
TDCD_BUFR Regional clock tree duty cycle
distortion
All 0.15 0.15 0.15 0.15 0.15 0.15 ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to
calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate clock skew specific to your application.
Table 38: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 45
MMCM Switching Characteristics
Table 41: MMCM Specification
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
MMCM_FINMAX Maximum Input Clock
Frequency
1066.00 933.00 800.00 800.00 933.00 800.00 MHz
MMCM_FINMIN Minimum Input Clock
Frequency
10.00 10.00 10.00 10.00 10.00 10.00 MHz
MMCM_FINJITTER Maximum Input Clock Period
Jitter
< 20% of clock input period or 1 ns Max
MMCM_FINDUTY Allowable Input Duty Cycle:
10–49 MHz
25.00 25.00 25.00 25.00 25.00 25.00 %
Allowable Input Duty Cycle:
50–199 MHz
30.00 30.00 30.00 30.00 30.00 30.00 %
Allowable Input Duty Cycle:
200–399 MHz
35.00 35.00 35.00 35.00 35.00 35.00 %
Allowable Input Duty Cycle:
400–499 MHz
40.00 40.00 40.00 40.00 40.00 40.00 %
Allowable Input Duty Cycle:
>500 MHz
45.00 45.00 45.00 45.00 45.00 45.00 %
MMCM_FMIN_PSCLK Minimum Dynamic Phase Shift
Clock Frequency
0.01 0.01 0.01 0.01 0.01 0.01 MHz
MMCM_FMAX_PSCLK Maximum Dynamic Phase
Shift Clock Frequency
550.00 500.00 450.00 450.00 500.00 450.00 MHz
MMCM_FVCOMIN Minimum MMCM VCO
Frequency
600.00 600.00 600.00 600.00 600.00 600.00 MHz
MMCM_FVCOMAX Maximum MMCM VCO
Frequency
1600.00 1440.00 1200.00 1200.00 1440.00 1200.00 MHz
MMCM_FBANDWIDTH Low MMCM Bandwidth at
Typical(1)
1.00 1.00 1.00 1.00 1.00 1.00 MHz
High MMCM Bandwidth at
Typical(1) 4.00 4.00 4.00 4.00 4.00 4.00 MHz
MMCM_TSTATPHAOFFSET Static Phase Offset of the
MMCM Outputs(2)
0.12 0.12 0.12 0.12 0.12 0.12 ns
MMCM_TOUTJITTER MMCM Output Jitter Note 3
MMCM_TOUTDUTY MMCM Output Clock Duty
Cycle Precision(4)
0.20 0.20 0.20 0.20 0.20 0.25 ns
MMCM_TLOCKMAX MMCM Maximum Lock Time 100.00 100.00 100.00 100.00 100.00 100.00 µs
MMCM_FOUTMAX MMCM Maximum Output
Frequency
1066.00 933.00 800.00 800.00 933.00 800.00 MHz
MMCM_FOUTMIN MMCM Minimum Output
Frequency(5)(6)
4.69 4.69 4.69 4.69 4.69 4.69 MHz
MMCM_TEXTFDVAR External Clock Feedback
Variation
< 20% of clock input period or 1 ns Max
MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00 5.00 5.00 5.00 5.00 5.00 ns
MMCM_FPFDMAX Maximum Frequency at the
Phase Frequency Detector
550.00 500.00 450.00 450.00 500.00 450.00 MHz
MMCM_FPFDMIN Minimum Frequency at the
Phase Frequency Detector
10.00 10.00 10.00 10.00 10.00 10.00 MHz
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 46
MMCM_TFBDELAY Maximum Delay in the
Feedback Path
3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN/
TMMCMCKD_PSEN
Setup and Hold of Phase Shift
Enable
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
TMMCMDCK_PSINCDEC/
TMMCMCKD_PSINCDEC
Setup and Hold of Phase Shift
Increment/Decrement
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
TMMCMCKO_PSDONE Phase Shift Clock-to-Out of
PSDONE
0.59 0.68 0.81 0.81 0.68 0.78 ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
TMMCMDCK_DADDR/
TMMCMCKD_DADDR
DADDR Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min
TMMCMDCK_DI/
TMMCMCKD_DI
DI Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min
TMMCMDCK_DEN/
TMMCMCKD_DEN
DEN Setup/Hold 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 1.97/0.00 2.40/0.00 ns, Min
TMMCMDCK_DWE/
TMMCMCKD_DWE
DWE Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min
TMMCMCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.99 0.72 0.70 ns, Max
FDCK DCLK frequency 200.00 200.00 200.00 200.00 200.00 100.00 MHz, Max
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
6. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.
Table 41: MMCM Specification (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 47
PLL Switching Characteristics
Table 42: PLL Specification
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
PLL_FINMAX Maximum Input Clock Frequency 1066.00 933.00 800.00 800.00 933.00 800.00 MHz
PLL_FINMIN Minimum Input Clock Frequency 19.00 19.00 19.00 19.00 19.00 19.00 MHz
PLL_FINJITTER Maximum Input Clock Period
Jitter
< 20% of clock input period or 1 ns Max
PLL_FINDUTY Allowable Input Duty Cycle:
19–49 MHz
25.00 25.00 25.00 25.00 25.00 25.00 %
Allowable Input Duty Cycle:
50–199 MHz
30.00 30.00 30.00 30.00 30.00 30.00 %
Allowable Input Duty Cycle:
200–399 MHz
35.00 35.00 35.00 35.00 35.00 35.00 %
Allowable Input Duty Cycle:
400–499 MHz
40.00 40.00 40.00 40.00 40.00 40.00 %
Allowable Input Duty Cycle:
>500 MHz
45.00 45.00 45.00 45.00 45.00 45.00 %
PLL_FVCOMIN Minimum PLL VCO Frequency 800.00 800.00 800.00 800.00 800.00 800.00 MHz
PLL_FVCOMAX Maximum PLL VCO Frequency 2133.00 1866.00 1600.00 1600.00 1866.00 1600.00 MHz
PLL_FBANDWIDTH Low PLL Bandwidth at Typical(1) 1.00 1.00 1.00 1.00 1.00 1.00 MHz
High PLL Bandwidth at Typical(1) 4.00 4.00 4.00 4.00 4.00 4.00 MHz
PLL_TSTATPHAOFFSET Static Phase Offset of the PLL
Outputs(2)
0.12 0.12 0.12 0.12 0.12 0.12 ns
PLL_TOUTJITTER PLL Output Jitter Note 3
PLL_TOUTDUTY PLL Output Clock Duty Cycle
Precision(4)
0.20 0.20 0.20 0.20 0.20 0.25 ns
PLL_TLOCKMAX PLL Maximum Lock Time 100 100 100 100 100 100 µs
PLL_FOUTMAX PLL Maximum Output Frequency 1066.00 933.00 800.00 800.00 933.00 800.00 MHz
PLL_FOUTMIN PLL Minimum Output
Frequency(5)
6.25 6.25 6.25 6.25 6.25 6.25 MHz
PLL_TEXTFDVAR External Clock Feedback
Variation
< 20% of clock input period or 1 ns Max
PLL_RSTMINPULSE Minimum Reset Pulse Width 5.00 5.00 5.00 5.00 5.00 5.00 ns
PLL_FPFDMAX Maximum Frequency at the
Phase Frequency Detector
550.00 500.00 450.00 450.00 500.00 450.00 MHz
PLL_FPFDMIN Minimum Frequency at the Phase
Frequency Detector
19.00 19.00 19.00 19.00 19.00 19.00 MHz
PLL_TFBDELAY Maximum Delay in the Feedback
Path
3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
TPLLCCK_DADDR/
TPLLCKC_DADDR
Setup and hold of D address 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min
TPLLCCK_DI/
TPLLCKC_DI
Setup and hold of D input 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min
TPLLCCK_DEN/
TPLLCKC_DEN
Setup and hold of D enable 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 1.97/0.00 2.40/0.00 ns, Min
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 48
TPLLCCK_DWE/
TPLLCKC_DWE
Setup and hold of D write enable 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.40/0.15 1.43/0.00 ns, Min
TPLLCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.99 0.72 0.70 ns, Max
FDCK DCLK frequency 200.00 200.00 200.00 200.00 200.00 100.00 MHz, Max
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
Table 42: PLL Specification (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 49
Device Pin-to-Pin Output Parameter Guidelines
Table 43: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOF Clock-capable clock input and
OUTFF at pins/banks closest to
the BUFGs without MMCM/PLL
(near clock region)
XC7K70T 4.98 5.49 6.17 N/A N/A 7.04 ns
XC7K160T 5.23 5.77 6.48 N/A 5.77 7.38 ns
XC7K325T 5.72 6.31 7.09 N/A 6.31 8.07 ns
XC7K355T 5.34 5.87 6.57 N/A 5.87 7.51 ns
XC7K410T 5.84 6.44 7.22 N/A 6.44 8.21 ns
XC7K420T 5.50 6.04 6.77 N/A 6.04 7.73 ns
XC7K480T 5.50 6.04 6.77 N/A 6.04 7.73 ns
XQ7K325T N/A 6.31 7.09 7.09 6.31 8.07 ns
XQ7K410T N/A 6.44 7.22 7.22 6.44 8.21 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475).
Table 44: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOFFAR Clock-capable clock input and
OUTFF at pins/banks farthest
from the BUFGs without
MMCM/PLL (far clock region)
XC7K70T 5.29 5.83 6.55 N/A N/A 7.47 ns
XC7K160T 5.84 6.45 7.24 N/A 6.45 8.24 ns
XC7K325T 6.33 6.99 7.84 N/A 6.99 8.92 ns
XC7K355T 5.95 6.55 7.32 N/A 6.55 8.36 ns
XC7K410T 6.45 7.12 7.97 N/A 7.12 9.07 ns
XC7K420T 6.41 7.06 7.90 N/A 7.06 9.01 ns
XC7K480T 6.41 7.06 7.90 N/A 7.06 9.01 ns
XQ7K325T N/A 6.99 7.84 7.84 6.99 8.92 ns
XQ7K410T N/A 7.12 7.97 7.97 7.12 9.07 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475).
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 50
Table 45: Clock-Capable Clock Input to Output Delay With MMCM
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
TICKOFMMCMCC Clock-capable clock input and
OUTFF with MMCM
XC7K70T 0.95 0.95 0.95 N/A N/A 1.74 ns
XC7K160T 0.96 0.96 0.96 N/A 0.96 1.78 ns
XC7K325T 1.00 1.00 1.00 N/A 1.00 1.82 ns
XC7K355T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7K410T 1.00 1.00 1.00 N/A 1.00 1.82 ns
XC7K420T 1.07 1.07 1.07 N/A 1.07 1.82 ns
XC7K480T 1.07 1.07 1.07 N/A 1.07 1.82 ns
XQ7K325T N/A 1.00 1.00 1.00 1.00 1.82 ns
XQ7K410T N/A 1.00 1.00 1.00 1.00 1.82 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
Table 46: Clock-Capable Clock Input to Output Delay With PLL
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
TICKOFPLLCC Clock-capable clock input and
OUTFF with PLL
XC7K70T 0.84 0.84 0.84 N/A N/A 1.45 ns
XC7K160T 0.89 0.89 0.89 N/A 0.89 1.54 ns
XC7K325T 0.89 0.89 0.89 N/A 0.89 1.54 ns
XC7K355T 0.89 0.89 0.89 N/A 0.89 1.50 ns
XC7K410T 0.89 0.89 0.89 N/A 0.89 1.54 ns
XC7K420T 0.96 0.96 0.96 N/A 0.96 1.54 ns
XC7K480T 0.96 0.96 0.96 N/A 0.96 1.54 ns
XQ7K325T N/A 0.89 0.89 0.89 0.89 1.54 ns
XQ7K410T N/A 0.89 0.89 0.89 0.89 1.54 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
Table 47: Pin-to-Pin, Clock-to-Out using BUFIO
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.
TICKOFCS Clock-to-Out of I/O clock for HR I/O banks 4.93 5.52 6.20 6.20 5.52 6.97 ns
Clock-to-Out of I/O clock for HP I/O banks 4.85 5.44 6.11 6.11 5.44 6.90 ns
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 51
Device Pin-to-Pin Input Parameter Guidelines
Table 48: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSFD/TPHFD Full Delay (Legacy
Delay or Default Delay)
Global Clock Input and
IFF(2) without
MMCM/PLL with
ZHOLD_DELAY on HR
I/O Banks
XC7K70T 2.83/–0.29 2.95/–0.29 3.15/–0.29 N/A N/A 4.96/–0.33 ns
XC7K160T 3.17/–0.35 3.29/–0.35 3.55/–0.35 N/A 3.29/–0.35 5.54/–0.49 ns
XC7K325T 2.83/–0.06 2.94/–0.06 3.15/–0.06 N/A 2.94/–0.06 5.18/–0.14 ns
XC7K355T 3.26/–0.32 3.41/–0.32 3.67/–0.32 N/A 3.41/–0.32 5.84/–0.49 ns
XC7K410T 3.43/–0.34 3.59/–0.34 3.88/–0.34 N/A 3.59/–0.34 6.21/–0.54 ns
XC7K420T 3.37/–0.27 3.48/–0.27 3.76/–0.27 N/A 3.48/–0.27 6.00/–0.52 ns
XC7K480T 3.37/–0.27 3.48/–0.27 3.76/–0.27 N/A 3.48/–0.27 6.00/–0.52 ns
XQ7K325T N/A 2.94/–0.06 3.15/–0.06 3.15/–0.06 2.94/–0.06 5.18/–0.14 ns
XQ7K410T N/A 3.59/–0.34 3.88/–0.34 3.88/–0.34 3.59/–0.34 6.21/–0.54 ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch.
Table 49: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSMMCMCC/
TPHMMCMCC
No Delay clock-
capable clock input and
IFF(2) with MMCM
XC7K70T 2.39/–0.22 2.65/–0.22 2.94/–0.22 N/A N/A 2.21/–0.44 ns
XC7K160T 2.49/–0.20 2.77/–0.20 3.07/–0.20 N/A 2.77/–0.20 2.38/–0.47 ns
XC7K325T 2.55/–0.16 2.85/–0.16 3.14/–0.16 N/A 2.85/–0.16 2.60/–0.47 ns
XC7K355T 2.43/–0.16 2.73/–0.16 3.00/–0.16 N/A 2.73/–0.16 2.47/–0.43 ns
XC7K410T 2.55/–0.16 2.84/–0.16 3.14/–0.16 N/A 2.84/–0.16 2.58/–0.47 ns
XC7K420T 2.47/–0.09 2.73/–0.09 3.02/–0.09 N/A 2.73/–0.09 2.40/–0.41 ns
XC7K480T 2.47/–0.09 2.73/–0.09 3.02/–0.09 N/A 2.73/–0.09 2.40/–0.41 ns
XQ7K325T N/A 2.85/–0.16 3.14/–0.16 3.14/–0.16 2.85/–0.16 2.60/–0.47 ns
XQ7K410T N/A 2.84/–0.16 3.14/–0.16 3.14/–0.16 2.84/–0.16 2.58/–0.47 ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 52
Table 50: Clock-Capable Clock Input Setup and Hold With PLL
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)
TPSPLLCC/
TPHPLLCC
No Delay clock-capable
clock input and IFF(2)
with PLL
XC7K70T 2.75/–0.32 3.04/–0.32 3.33/–0.32 N/A N/A 2.42/–0.54 ns
XC7K160T 2.85/–0.31 3.16/–0.31 3.46/–0.31 N/A 3.16/–0.31 2.59/–0.56 ns
XC7K325T 2.91/–0.27 3.24/–0.27 3.54/–0.27 N/A 3.24/–0.27 2.80/–0.56 ns
XC7K355T 2.79/–0.27 3.12/–0.27 3.40/–0.27 N/A 3.12/–0.27 2.67/–0.52 ns
XC7K410T 2.91/–0.27 3.24/–0.27 3.53/–0.27 N/A 3.24/–0.27 2.78/–0.56 ns
XC7K420T 2.83/–0.20 3.12/–0.20 3.41/–0.20 N/A 3.12/–0.20 2.61/–0.50 ns
XC7K480T 2.83/–0.20 3.12/–0.20 3.41/–0.20 N/A 3.12/–0.20 2.61/–0.50 ns
XQ7K325T N/A 3.24/–0.27 3.54/–0.27 3.54/–0.27 3.24/–0.27 2.80/–0.56 ns
XQ7K410T N/A 3.24/–0.27 3.53/–0.27 3.53/–0.27 3.24/–0.27 2.78/–0.56 ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 51: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
TPSCS/TPHCS Setup/Hold of I/O clock for HR I/O
banks
–0.36/1.36 –0.36/1.50 –0.36/1.70 –0.36/1.70 0.36/1.50 –0.44/1.87 ns
Setup/Hold of I/O clock for HP I/O
banks
–0.34/1.39 –0.34/1.53 –0.34/1.73 –0.34/1.73 0.34/1.53 –0.44/1.87 ns
Table 52: Sample Window
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1LM -2LI -2LE
TSAMP Sampling Error at Receiver Pins(1) 0.51 0.56 0.61 0.61 0.56 0.56 ns
TSAMP_BUFIO Sampling Error at Receiver Pins using
BUFIO(2)
0.30 0.35 0.40 0.40 0.35 0.35 ns
Notes:
1. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 53
Additional Package Parameter Guidelines
The parameters in this section provide the necessary values for calculating timing budgets for Kintex-7 FPGA clock
transmitter and receiver data-valid windows.
Table 53: Package Skew
Symbol Description Device Package Value Units
TPKGSKEW Package Skew(1) XC7K70T FBG484 108 ps
FBG676 135 ps
XC7K160T FBG484 118 ps
FBG676 136 ps
FFG676 161 ps
XC7K325T FBG676 146 ps
FFG676 154 ps
FBG900 163 ps
FFG900 161 ps
XC7K355T FFG901 149 ps
XC7K410T FBG676 165 ps
FFG676 168 ps
FBG900 151 ps
FFG900 146 ps
XC7K420T FFG901 149 ps
FFG1156 145 ps
XC7K480T FFG901 149 ps
FFG1156 145 ps
XQ7K325T RF676 154 ps
RF900 161 ps
XQ7K410T RF676 168 ps
RF900 146 ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die
pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 54
GTX Transceiver Specifications
GTX Transceiver DC Input and Output Levels
Table 54 summarizes the DC output specifications of the GTX transceivers in Kintex-7 FPGAs. Consult the 7Series FPGAs
GTX/GTH Transceivers User Guide (UG476) for further details.
Note: In Figure 4, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2.
Table 54: GTX Transceiver DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
DVPPOUT Differential peak-to-peak output
voltage(1)
Transmitter output swing is set to
maximum setting
1000 – mV
VCMOUTDC DC common mode output
voltage.
Equation based VMGTAVTT –DV
PPOUT/4 mV
ROUT Differential output resistance 100 Ω
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew 2 12 ps
DVPPIN
Differential peak-to-peak input
voltage (external AC coupled)
>10.3125 Gb/s 150 1250 mV
6.6 Gb/s to 10.3125 Gb/s 150 1250 mV
6.6 Gb/s 150 2000 mV
VIN Single-ended input voltage(2) DC coupled VMGTAVTT = 1.2V –200 VMGTAVTT mV
VCMIN Common mode input voltage DC coupled VMGTAVTT = 1.2V 2/3 VMGTAVTT –mV
RIN Differential input resistance 100 Ω
CEXT Recommended external AC coupling capacitor(3) –100 –nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in the 7 Series FPGAs GTX/GTH Transceivers
User Guide (UG476) and can result in values lower than reported in this table.
2. Voltage measured at the pin referenced to ground.
3. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 3
Figure 3: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 4
Figure 4: Differential Peak-to-Peak Voltage
0
+V P
N
DS182_01_071014
Single-Ended
Peak-to-Peak
Voltage
0
+V
–V
P–N
DS182_02_071014
Differential
Peak-to-Peak
Voltage
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 55
Table 55 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the 7 Series FPGAs GTX/GTH
Transceivers User Guide (UG476) for further details.
GTX Transceiver Switching Characteristics
Consult the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further information.
Table 55: GTX Transceiver Clock DC Input Level Specification
Symbol DC Parameter Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 250 2000 mV
RIN Differential input resistance 100 Ω
CEXT Required external AC coupling capacitor 100 nF
Table 56: GTX Transceiver Performance
Symbol Description Output
Divider
Speed Grade(1)
Units
-3 (1.0V)
-2 (1.0V)
-2LE (1.0V)
-2LI (0.95V)
-1 (1.0V)(2)
-1M (1.0V)(2)
-1LM (1.0V)(2) -2LE (0.9V)(3)
Package Type
FF FBG484 FBG676
FBG900
FF
RF
FBG484
FBG676
FBG900
FF
RF FB FF
RF FB
FGTXMAX(4) Maximum GTX transceiver
data rate
12.5(5) 10.3125(6) 6.6 10.3125(6) 6.6 8.0 6.6 6.6 6.6 Gb/s
FGTXMIN(4) Minimum GTX transceiver
data rate
0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.500 Gb/s
FGTXCRANGE CPLL line rate range
1 3.2–6.6 Gb/s
2 1.6–3.3 Gb/s
40.81.65Gb/s
8 0.5–0.825 Gb/s
16 N/A Gb/s
FGTXQRANGE1 QPLL line rate
range 1
15.93–
8.0
5.93–
8.0
5.93–
6.6
5.93–
8.0
5.93–
6.6
5.93–
8.0
5.93–
6.6
5.93–6.6 Gb/s
2 2.965–4.0 2.965–4.0 2.965–4.0 2.965–3.3 Gb/s
4 1.4825–2.0 1.4825–2.0 1.4825–2.0 1.4825–1.65 Gb/s
8 0.74125–1.0 0.74125–1.0 0.74125–1.0 0.74125–0.825 Gb/s
16 N/A N/A N/A N/A Gb/s
FGTXQRANGE2 QPLL line rate
range 2(7)
19.8–
12.5
9.8–
10.3125
N/A 9.8–
10.3125
N/A N/A N/A Gb/s
2 4.9–6.25 4.9–5.15625 N/A N/A Gb/s
4 2.45–3.125 2.45–2.578125 N/A N/A Gb/s
8 1.225–1.5625 1.225–1.2890625 N/A N/A Gb/s
16 0.6125–0.78125 0.6125–
0.64453125
N/A N/A Gb/s
FGCPLLRANGE GTX transceiver CPLL
frequency range
1.6–3.3 1.6–3.3 1.6–3.3 1.6–3.3 GHz
FGQPLLRANGE1 GTX transceiver QPLL
frequency range 1
5.93–8.0 5.93–8.0 5.93–8.0 5.93–6.6 GHz
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 56
FGQPLLRANGE2 GTX transceiver QPLL
frequency range 2
9.8–12.5 9.8–10.3125 N/A N/A GHz
Notes:
1. Voltages specified for speed grades are VCCINT.
2. The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s.
3. The -2LE (0.9V) speed grade requires a 4-byte internal data width for operation above 3.8 Gb/s.
4. Data rates between 8.0 Gb/s and 9.8 Gb/s are not available.
5. For line rates greater than 10.3125 Gb/s, VMGTAVCC is 1.05V nominal (see Table 2).
6. The FBG484 package supports data rates greater than 6.6 Gb/s in the -2 and -3 speed grades (requires Vivado Design Suite 2017.1 or
later).
7. For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125 Gb/s.
Table 57: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1/-1M/-1LM -2LI -2LE
FGTXDRPCLK GTXDRPCLK maximum frequency 175.01 175.01 156.25 175.01 125.00 MHz
Table 58: GTX Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequency range -3 speed grade 60 700 MHz
All other speed grades 60 670 MHz
TRCLK Reference clock rise time 20% – 80% 200 ps
TFCLK Reference clock fall time 80% – 20% 200 ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 %
X-Ref Target - Figure 5
Figure 5: Reference Clock Timing Parameters
Table 56: GTX Transceiver Performance (Cont’d)
Symbol Description Output
Divider
Speed Grade(1)
Units
-3 (1.0V)
-2 (1.0V)
-2LE (1.0V)
-2LI (0.95V)
-1 (1.0V)(2)
-1M (1.0V)(2)
-1LM (1.0V)(2) -2LE (0.9V)(3)
Package Type
FF FBG484 FBG676
FBG900
FF
RF
FBG484
FBG676
FBG900
FF
RF FB FF
RF FB
ds182_03_042712
80%
20%
T
FCLK
T
RCLK
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS182 (v2.16.1) August 7, 2018 www.xilinx.com
Product Specification 57
Table 59: GTX Transceiver PLL /Lock Time Adaptation
Symbol Description Conditions All Speed Grades Units
Min Typ Max
TLOCK Initial PLL lock 1 ms
TDLOCK
Clock recovery phase acquisition and
adaptation time for decision feedback
equalizer (DFE).
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
50,000 37 x106UI
Clock recovery phase acquisition and
adaptation time for low-power mode
(LPM) when the DFE is disabled.
50,000 2.3 x106UI
Table 60: GTX Transceiver User Clock Switching Characteristics(1)(2)
Symbol Description Conditions
Speed Grade
Units1.0V 0.95V 0.9V
-3(3) -2/-2LE(3) -1/-1M/-1LM(4) -2LI -2LE(5)
FTXOUT TXOUTCLK maximum frequency 412.500 412.500 312.500 412.500 237.500 MHz
FRXOUT RXOUTCLK maximum frequency 412.500 412.500 312.500 412.500 237.500 MHz
FTXIN TXUSRCLK maximum frequency 16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz
32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz
FRXIN RXUSRCLK maximum frequency 16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz
32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz
FTXIN2 TXUSRCLK2 maximum
frequency
16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz
32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz
64-bit data path 195.313 161.133 125.000 161.133 103.125 MHz
FRXIN2 RXUSRCLK2 maximum
frequency
16-bit data path 412.500 412.500 312.500 412.500 237.500 MHz
32-bit data path 390.625 322.266 250.000 322.266 206.250 MHz
64-bit data path 195.313 161.133 125.000 161.133 103.125 MHz
Notes:
1. Clocking must be implemented as described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).