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SiP32401A,402A Datasheet

Vishay Siliconix

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Datasheet

SiP32401A, SiP32402A
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1.1 V to 5.5 V, Slew Rate Controlled Load Switch
DESCRIPTION
SiP32401A and SiP32402A are slew rate controlled load
switches designed for 1.1 V to 5.5 V operation.
The devices guarantee low switch on-resistance at 1.2 V
input. They feature a controlled soft-on slew rate of typical
2.5 ms that limits the inrush current for designs of heavy
capacitive load and minimizes the resulting voltage droop at
the power rails.
These devices feature low voltage control logic interface
(On/Off interface) that can interface with low voltage control
signal without extra level shifting circuit. SiP32402A also
integrates an output discharge switch that enables fast
shutdown load discharge.
Both SiP32401A and SiP32402A have exceptionally low
shutdown current and provide reverse blocking to prevent
high current flowing into the power source.
SiP32401A and SiP32402A are in TDFN4 package of
1.2 mm by 1.6 mm.
FEATURES
1.1 V to 5.5 V operation voltage range
62 mΩ typical from 2 V to 5 V
•Low R
on down to 1.2 V
Slew rate controlled turn-on: 2.5 ms at 3.6 V
Fast shutdown load discharge for SiP32402A
Low quiescent current
< 1 μA when disabled
10.5 μA typical at VIN = 1.2 V
Reverse current blocking when switch is off
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
PDAs / smart phones
Notebook / netbook computers
•Tablet PC
Portable media players
Digital camera
GPS navigation devices
Data storage devices
Optical, industrial, medical, and healthcare devices
TYPICAL APPLICATION CIRCUIT
Fig. 1 - SiP32401A, SiP32402A Typical Application Circuit
Available
SiP32401A, SiP32402A
IN VOUT
OUT
VIN
GND
GND
GND
EN
EN
C
4.7 µF
IN C
0.1 µF
OUT
SiP32401A, SiP32402A
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Notes
•x = Lot code
GE4 denotes halogen-free and RoHS-compliant
Notes
a. Device mounted with all leads and power pad soldered or welded to PC board, see PCB layout.
b. Derate 5.9 mW/°C above TA = 70 °C, see PCB layout.
c. TA = 25 °C, see PCB layout
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
ORDERING INFORMATION
TEMPERATURE RANGE PACKAGE MARKING PART NUMBER
-40 °C to +85 °C TDFN4 1.2 mm x 1.6 mm Gx SiP32401ADNP-T1GE4
Hx SiP32402ADNP-T1GE4
ABSOLUTE MAXIMUM RATINGS
PARAMETER LIMIT UNIT
Supply Input Voltage (VIN) -0.3 to +6
VEnable Input Voltage (VEN) -0.3 to +6
Output Voltage (VOUT)-0.3 to VIN + 0.3
Maximum Continuous Switch Current (Imax.) c2.4 A
Maximum Repetitive Pulsed Current (1 ms, 10 % Duty Cycle) c3
ESD Rating (HBM) 4000 V
Junction Temperature (TJ) -40 to +125 °C
Thermal Resistance (θJA) a170 °C/W
Power Dissipation (PD) a, b 324 mW
RECOMMENDED OPERATING RANGE
PARAMETER LIMIT UNIT
Input Voltage Range (VIN) 1.1 to 5.5 V
Operating Junction Temperature Range (TJ) -40 to +125 °C
SiP32401A, SiP32402A
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Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. For VIN outside this range consult typical EN threshold curve.
d. Not tested, guarantee by design.
SPECIFICATIONS
PARAMETER SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 5 V, TA = -40 °C to +85 °C
(typical values are at TA = 25 °C)
LIMITS
-40 °C to +85 °C UNIT
MIN. a TYP.
bMAX. a
Operating Voltage cVIN 1.1 - 5.5 V
Quiescent Current IQ
VIN = 1.2 V, EN = active - 10.5 17
μA
VIN = 1.8 V, EN = active - 21 30
VIN = 2.5 V, EN = active - 34 50
VIN = 3.6 V, EN = active - 54 90
VIN = 4.3 V, EN = active - 68 110
VIN = 5 V, EN = active - 105 180
Off Supply Current IQ(off) EN = inactive, OUT = open - - 1
Off Switch Current IDS(off) EN = inactive, OUT = GND - - 1
Reverse Blocking Current IRB VOUT = 5 V, VIN = 0 V, VEN = inactive - - 10
On-Resistance RDS(on)
VIN = 1.2 V, IL = 100 mA, TA = 25 °C - 66 76
mΩ
VIN = 1.8 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 2.5 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 3.6 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 4.3 V, IL = 100 mA, TA = 25 °C - 62 72
VIN = 5 V, IL = 100 mA, TA = 25 °C - 62 72
On-Resistance Temp.-Coefficient TCRDS - 4250 - ppm/°C
EN Input Low Voltage cVIL
VIN = 1.2 V - - 0.3
V
VIN = 1.8 V - - 0.4 d
VIN = 2.5 V - - 0.5 d
VIN = 3.6 V - - 0.6 d
VIN = 4.3 V - - 0.7 d
VIN = 5 V - - 0.8 d
EN Input High Voltage cVIH
VIN = 1.2 V 0.9 d--
VIN = 1.8 V 1.2 d--
VIN = 2.5 V 1.4 d--
VIN = 3.6 V 1.6 d--
VIN = 4.3 V 1.7 d--
VIN = 5 V 1.8 - -
EN Input Leakage ISINK VEN = 5.5 V -1 - 1 μA
Output Pulldown Resistance RPD EN = inactive, TA = 25 °C (for SiP32402A only) - 217 280 Ω
Output Turn-On Delay Time td(on)
VIN = 3.6 V, RLOAD = 10 Ω, TA = 25 °C
-1.8-
msOutput Turn-On Rise Time t(on) 1.2 2.5 3.8
Output Turn-Off Delay Time td(off) --0.001
SiP32401A, SiP32402A
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PIN CONFIGURATION
Fig. 2 - TDFN4 1.2 mm x 1.6 mm Package
TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 3 - Quiescent Current vs. Input Voltage
Fig. 4 - Off Supply Current vs. Input Voltage
Fig. 5 - Quiescent Current vs. Temperature
Fig. 6 - Off Supply Current vs. Temperature
PIN DESCRIPTION
PIN NUMBER NAME FUNCTION
1 OUT This is the output pin of the switch
2 GND Ground connection
3 IN This is the input pin of the switch
4 EN Enable input
4
3
1
2
Bottom View
EN
IN
OUT
GND
GND
0
20
40
60
80
100
120
140
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN (V)
IQ - Quiescent Current (μA)
VIN (V)
IQ(OFF) - Off Supply Current (nA)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (°C)
IQ - Quiescent Current (μA)
0
20
40
60
80
100
120
- 40 - 20 0 20 40 60 80 100
VIN = 5 V
VIN = 3.6 V
VIN = 1.2 V
Temperature (°C)
IQ(OFF) - Off Supply Current (nA)
0.001
0.01
0.1
1
10
100
- 40 - 20 0 20 40 60 80 100
VIN = 5 V
VIN = 3.6 V
VIN = 1.2 V
SiP32401A, SiP32402A
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 7 - Off Switch Current vs. Input Voltage
Fig. 8 - RDS(on) vs. VIN
Fig. 9 - Output Pull Down vs. Input Voltage
Fig. 10 - Off Switch Current vs. Temperature
Fig. 11 - RDS(on) vs. Temperature
Fig. 12 - Output Pull Down vs. Temperature
VIN (V)
IDS(off) - Off Switch Current (nA)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V
IN
(V)
RDS - On-Resistance (mΩ)
60
62
64
66
68
70
72
74
76
78
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
IO = 2 A
IO = 1.2 A
IO = 0.1 A
IO = 1 A
IO = 0.2 A
VIN (V)
RPD - Output Pulldown Resistance (Ω)
100
150
200
250
300
350
400
450
500
550
600
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VOUT = VIN
SiP32402A only
Temperature (°C)
IDS(off) - Off Switch Current (nA)
0.0001
0.001
0.01
0.1
1
10
100
1000
- 40 - 20 0 20 40 60 80 100
VIN = 5 V
VIN = 1.2 V
VIN = 3.6 V
Temperature (°C)
RDS - On-Resistance (mΩ)
45
50
55
60
65
70
75
80
85
- 40 - 20 0 20 40 60 80 100
VIN = 5 V
IO = 0.1 mA
Temperature (°C)
RPD - Output Pulldown Resistance (Ω)
160
180
200
220
240
260
280
300
- 40 - 20 0 20 40 60 80 100
VOUT = VIN = 5 V
SiP32402A only
SiP32401A, SiP32402A
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 13 - Reverse Blocking Current vs. Output Voltage
Fig. 14 - Rise Time vs. Temperature
Fig. 15 - EN Threshold Voltage vs. Input Voltage
Fig. 16 - Turn-on Delay Time vs. Temperature
Fig. 17 - Turn-Off Delay Time vs. Temperature
VOUT (V)
IIN - Input Current (nA)
- 12
- 10
- 8
- 6
- 4
- 2
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VIN = 0 V
VEN = 0 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
- 40 - 20 0 20 40 60 80 100
tr - Rise Time (ms)
Temperature (°C)
VIN = 5 V
CL = 0.1 μF
RL = 10 Ω
VIN (V)
EN Threshold Voltage (V)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIH
VIL
0.00
0.05
0.10
0.15
0.20
0.25
0.30
- 40 - 20 0 20 40 60 80 100
td(off) - Turn Off Delay Time (μs)
Temperature (°C)
VIN = 5 V
CL = 0.1 μF
RL = 10 Ω
SiP32401A, SiP32402A
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TYPICAL CHARACTERISTICS (internally regulated, 25 °C, unless otherwise noted)
Fig. 18 - Typical Turn-on Delay, Rise Time
COUT = 0.1 μF, CIN = 4.7 μF, IOUT = 1.5 A
Fig. 19 - Typical Turn-on Delay, Rise Time
COUT = 0.1 μF, CIN = 4.7 μF, ROUT = 10 Ω
Fig. 20 - Typical Turn-on Delay, Rise Time
COUT = 200 μF, CIN = 4.7 μF, IOUT = 1.5 A
Fig. 21 - Typical Fall Time
COUT = 0.1 μF, CIN = 4.7 μF, IOUT = 1.5 A
Fig. 22 - Typical Fall Time
COUT = 0.1 μF, CIN = 4.7 μF, ROUT = 10 Ω
Fig. 23 - Typical Fall Time
COUT = 200 μF, CIN = 4.7 μF, IOUT = 1.5 A
EN
5V
OUT
3.6V
OUT
1.5V
OUT
I
OUT
for 5V
OUT
I
OUT
for 3.6V
OUT
I
OUT
for 1.5V
OUT
2 V/Div, 2 A/Div, 2 ms/Div
5V
OUT
EN
1.5V
OUT
I
OUT
for 5V
OUT
I
OUT
for 3.6V
OUT
I
OUT
for 1.5V
OUT
3.6V
OUT
2 V/Div, 0.25 A/Div, 2 ms/Div
EN
5V
OUT
I
OUT
for 5V
OUT
3.6V
OUT
I
OUT
for 3.6V
OUT
1.5V
OUT
I
OUT
for 1.5V
OUT
2 V/Div, 2 A/Div, 2 ms/Div
EN
5V
OUT
3.6V
OUT
1.5V
OUT
I
OUT
for 5V
OUT
I
OUT
for 3.6V
OUT
I
OUT
for 1.5V
OUT
EN
5V
OUT
3.6V
OUT
1.5V
OUT
I
OUT
for 5V
OUT
I
OUT
for 3.6V
OUT
I
OUT
for 1.5V
OUT
EN
5V
OUT
I
OUT
for 5V
OUT
3.6V
OUT
I
OUT
for 3.6V
OUT
1.5V
OUT
I
OUT
for 1.5V
OUT
2 V/Div, 2 A/Div, 2 ms/Div
SiP32401A, SiP32402A
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Fig. 24 - Typical Turn-on Delay, Rise Time
COUT = 200 μF, CIN = 4.7 μF, ROUT = 10 Ω
Fig. 25 - Typical Fall Time
COUT = 200 μF, CIN = 4.7 μF, ROUT = 10 Ω
BLOCK DIAGRAM
Fig. 26 - Functional Block Diagram
EN
5VOUT
IOUT for 5VOUT
3.6VOUT
IOUT for 3.6VOUT
1.5VOUT
IOUT for 1.5VOUT
2 V/Div, 0.25 A/Div, 2 ms/Div
EN
5VOUT
IOUT for 5VOUT
3.6VOUT
IOUT for 3.6VOUT
1.5VOUT
IOUT for 1.5VOUT
2 V/Div, 0.25 A/Div, 2 ms/Div
Control
Logic
Turn On
Slew Rate Control
GND
EN
OUT
IN
Reverse
Blocking
Charge
Pump
Note: for SiP32402A only
SiP32401A, SiP32402A
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PCB LAYOUT
Fig. 27 - PCB Layout for TDFN4 1.2 mm x 1.6 mm (type: FR4, size: 1" x 1", thickness: 0.062", copper thickness: 2 oz.)
DETAILED DESCRIPTION
SiP32401A and SiP32402A are advanced slew rate
controlled high side load switch consisted of a n-channel
power switch. When the device is enable the gate of the
power switch is turned on at a controlled rate to avoid
excessive in-rush current. Once fully on the gate to source
voltage of the power switch is biased at a constant level. The
design gives a flat on resistance throughout the operating
voltages. When the device is off, the reverse blocking
circuitry prevents current from flowing back to input if output
is raised higher than input. The reverse blocking mechanism
also works in case of no input applied. The SiP32402A also
integrates an output discharge switch which allows fast
output discharge.
APPLICATION INFORMATION
Input Capacitor
The SiP32401A and SiP32402A do not require an input
capacitor. To limit the voltage drop on the input supply
caused by transient inrush currents, an input bypass
capacitor is recommended. A 2.2 μF ceramic capacitor
placed as close to the VIN and GND should be enough.
Higher values capacitor can help to further reduce the
voltage drop. Ceramic capacitors are recommended for
their ability to withstand input current surge from low
impedance sources such as batteries in portable devices.
Output Capacitor
While these devices works without an output capacitor,
an 0.1 μF or larger capacitor across VOUT and GND is
recommended to accommodate load transient condition. It
also help to prevent parasitic inductance forces VOUT below
GND when switching off. Output capacitor has minimal
affect on device’s turn on slew rate time. There is no
requirement on capacitor type and its ESR.
Enable
The EN pin is compatible with both TTL and CMOS logic
voltage levels.
Protection Against Reverse Voltage Condition
Both SiP32401A and SiP32402A contain reverse blocking
circuitry to protect the current from going to the input from
the output in case where the output voltage is higher than
the input voltage when the main switch is off. Reverse
blocking works for input voltage as low as 0 V.
Thermal Considerations
SiP32401A and SiP32402A are designed to maintain a
constant output load current. Due to physical limitations of
the layout and assembly of the device the maximum switch
current is 2.8 A, as stated in the Absolute Maximum Ratings
table. However, another limiting characteristic for the safe
operating load current is the thermal power dissipation of
the package. To obtain the highest power dissipation (and a
thermal resistance of 170 °C/W) the power pad of the device
should be connected to a heat sink on the printed circuit
board. Figure 23 shows a typical PCB layout. All copper
traces and vias for the IN and OUT pins should be sized
adequately to carry the maximum continuous current.
The maximum power dissipation in any application is
dependant on the maximum junction temperature,
TJ (max.) = 125 °C, the junction-to-ambient thermal
resistance for the TDFN4 1.2 mm x 1.6 mm package, θJ-A =
170 °C/W, and the ambient temperature, TA, which may be
formulaically expressed as:
Top Bottom
170
125
(max.)
(max.)
A
A
J
A
J T
TT
P
-
=
-
=
-
θ
SiP32401A, SiP32402A
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It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to
about 324 mW.
So long as the load current is below the 2.8 A limit, the
maximum continuous switch current becomes a function of
two things: the package power dissipation and the RDS(on) at
the ambient temperature.
As an example let us calculate the worst case maximum
load current at TA = 70 °C. The worst case RDS(on) at 25 °C
occurs at an input voltage of 1.2 V and is equal to 76 mΩ.
The RDS(on) at 70 °C can be extrapolated from this data using
the following formula:
RDS(on) (at 70 °C) = RDS(on) (at 25 °C) x (1 + TC x DT)
Where TC is 4250 ppm/°C. Continuing with the calculation
we have
RDS(on) (at 70 °C) = 76 mΩ x (1 + 0.00425 x (70 °C - 25 °C))
= 90.5 mΩ
The maximum current limit is then determined by
which in case is 1.9 A. Under the stated input voltage
condition, if the 1.9 A current limit is exceeded the internal
die temperature will rise and eventually, possibly damage
the device.
Recommended Board Layout
For the best performance, all traces should be as short as
possible to minimize the inductance and parasitic effects.
The input and output capacitors should be kept as close
as possible to the input and output pins respectively.
Connecting the central exposed pad to GND, using wide
traces for input, output, and GND help reducing the case to
ambient thermal impedance.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63705.
(
on)
(max.)
(max.)
DS
LOAD
R
P
I<
Package Information
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Revision: 18-Apr-16 1Document Number: 65734
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TDFN4 1.2 x 1.6 Case Outline
Note
(1) The dimension depends on the leadframe that assembly house used.
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.45 0.55 0.60 0.017 0.022 0.024
A1 0.00 - 0.05 0.00 - 0.002
A3 0.15 REF. or 0.127 REF. (1) 0.006 or 0.005 (1)
b 0.20 0.25 0.30 0.008 0.010 0.012
D 1.15 1.20 1.25 0.045 0.047 0.049
D2 0.81 0.86 0.91 0.032 0.034 0.036
e 0.50 BSC 0.020
E 1.55 1.60 1.65 0.061 0.063 0.065
E2 0.45 0.50 0.55 0.018 0.020 0.022
K 0.25 typ. 0.010 typ.
L 0.25 0.30 0.35 0.010 0.012 0.014
ECN: T16-0143-Rev. C, 18-Apr-16
DWG: 5995
Top View Bottom View
Side View
21
43
34
12
D
E
A
A1
b
e
L
A3
E2
D2
K
Index Area
(D/2 x E/2)
Pin #1 ID
(Optional)
Document Number: 66558 www.vishay.com
Revision: 05-Mar-10 1
PAD Pattern
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TDFN4 1.2 x 1.6
Recommended Minimum Pads
Dimensions in mm
12
3
4
0.30
0.50
0.86
0.20 0.50
2.0
0.20
0.55 0.55
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consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED

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