Date Version Changes
• Updated HPS I/O for U484 (19 mm) in Table 11 with '151' for A2, A4, A5
• Updated Memory (Kb) for Maximum Resource Counts for Cyclone V SE A4
and A6, SX C4 and C6, ST D6 devices.
• Updated FPGA PLL for Maximum Resource Counts for Cyclone V SE A2, SX
• Removed '36 x 36' from the Variable-Precision DSP Block.
• Updated Variable-precision DSP Blocks and 18 x 18 Multiplier for
Maximum Resource Counts for Cyclone V SX C4 device.
• Updated the HPS I/O counts for Cyclone V SE, SX, and ST devices.
• Updated Figure 7 which shows the I/O vertical migration table.
• Updated Table 17 for Cyclone V SX C4 device.
• Updated Embedded Memory Capacity and Distribution table for Cyclone V
SE A4 and A6, SX C4 and C6, ST D6 devices.
• Removed 'Counter reconfiguration' from the PLL Features.
• Updated Low-Power Serial Transceivers by replacing 5 Gbps with
• Removed 'Distributed Memory' symbol.
• Updated the Capability in Table 22 of Backplane support to '6.144 Gbps'.
• Updated Capability in Table 22 of Ring oscillator transmit PLLs with
• Updated the PCS Support in Table 23 from 5 Gbps to '6 Gbps'.
• Updated the Data Rates (Gbps) in Table 23 of 3 Gbps and 6 Gbps Basic to
• Updated the Data Rates (Gbps) in Table 23 of CPRI 4.1 to '6.144 Gbps'.
• Clarified that partial reconfiguration is an advanced feature. Contact Altera
for support of the feature.
December 2012 2012.12.28 • Updated the pin counts for the MBGA packages.
• Updated the GPIO and transceiver counts for the MBGA packages.
• Updated the GPIO counts for the U484 package of the Cyclone V E A9, GX
C9, and GT D9 devices.
• Updated the vertical migration table for vertical migration of the U484
• Updated the MLAB supported programmable widths at 32 bits depth.
November 2012 2012.11.19 • Added new MBGA packages and additional U484 packages for Cyclone V E,
GX, and GT.
• Added ordering code for five-transceiver devices for Cyclone V GT and ST.
• Updated the vertical migration table to add MBGA packages.
• Added performance information for HPS memory controller.
• Removed DDR3U support.
• Updated Cyclone V ST speed grade information.
• Added information on maximum transceiver channel usage restrictions for
PCI Gen2 and CPRI at 4.9152 Gbps transmit jitter compliance.
• Added note on the differences between GPIO reported in Overview with
User I/O numbers shown in the Quartus II software.
• Updated template.
July 2012 2.1 Added support for PCIe Gen2 x4 lane configuration (PCIe-compatible)
June 2012 2.0 • Restructured the document.
• Added the “Embedded Memory Capacity” and “Embedded Memory
• Added Table 1, Table 3, Table 16, Table 19, and Table 20.
• Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table
10, Table 11, Table 12, Table 13, Table 14, Table 17, and Table 18.
Cyclone V Device Overview
CV-51001 | 2018.05.07
Cyclone V Device Overview