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ESP8266 Datasheet

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Datasheet

1 | P a g e Espressif Systems Oct 12, 2013
ESP8266 802.11bgn Smart Device
ESPRESSIF SMART
CONNECTIVITY
PLATFORM: ESP8266
2 | P a g e Espressif Systems Oct 12, 2013
ESP8266 802.11bgn Smart Device
Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice.
THIS DOCUMENT IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT,
FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. All liability, including
liability for infringement of any proprietary rights, relating to use of information in this
document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any
intellectual property rights are granted herein.
The Wi-Fi Alliance Member Logo is a trademark of the Wi-Fi Alliance.
All trade names, trademarks and registered trademarks mentioned in this document are property
of their respective owners, and are hereby acknowledged.
Copyright © 2013 Espressif Systems Inc. All rights reserved.
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ESP8266 802.11bgn Smart Device
Table of Contents
1 INTRODUCTION 4
2 TECHNOLOGY OVERVIEW 5
3 FEATURES 6
4 APPLICATION DIAGRAM 7
5 ULTRA LOW POWER TECHNOLOGY 8
5.1 HIGHEST LEVEL OF INTEGRATION 8
6 ESP8266 APPLICATIONS 9
7 SPECIFICATIONS 10
7.1 CURRENT CONSUMPTION 10
7.2 RF PERFORMANCE 11
8 CPU, MEMORY AND INTERFACES 12
8.1 CPU 12
8.2 MEMORY CONTROLLER 12
8.3 AHB AND AHB BLOCKS 12
8.4 INTERFACES 13
8.4.1 Master SI / SPI Control (Optional) 13
8.4.2 General Purpose IO 14
8.4.3 Digital IO Pads 14
9 FIRMWARE & SOFTWARE DEVELOPMENT KIT 16
9.1 FEATURES 16
10 POWER MANAGEMENT 18
11 CLOCK MANAGEMENT 19
11.1 HIGH FREQUENCY CLOCK 19
11.2 EXTERNAL REFERENCE REQUIREMENTS 20
12 RADIO 21
12.1 CHANNEL FREQUENCIES 21
12.2 2.4GHZ RECEIVER 21
12.3 2.4GHZ TRANSMITTER 22
12.4 CLOCK GENERATOR 22
APP. QFN32 PACKAGE DRAWING 23
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ESP8266 802.11bgn Smart Device
1 Introduction
Espressif Systems’ Smart Connectivity Platform (ESCP) of high performance wireless SOCs, for
mobile platform designers, provides unsurpassed ability to embed Wi-Fi capabilities within other
systems, at the lowest cost with the greatest functionality.
RF
receive Analog
receive
RF
transmit Analog
transmit
RF balun
PLL
Digital baseband
PMUSRAM
Registers
CPU
Sequencers
Accelerator
MAC
SDIO
SPI
GPIO
I2C
Interface
Bias circuits
Switch
VCO 1/2 PLL
PMU Crystal
Figure 1: ESP8266 Block Diagram
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ESP8266 802.11bgn Smart Device
2 Technology Overview
ESP8266 offers a complete and self-contained Wi-Fi networking solution, allowing it to either
host the application or to offload all Wi-Fi networking functions from another application
processor.
When ESP8266 hosts the application, and when it is the only application processor in the device,
it is able to boot up directly from an external flash. It has integrated cache to improve the
performance of the system in such applications, and to minimize the memory requirements.
Alternately, serving as a Wi-Fi adapter, wireless internet access can be added to any
microcontroller-based design with simple connectivity through UART interface or the CPU
AHB bridge interface.
ESP8266 on-board processing and storage capabilities allow it to be integrated with the sensors
and other application specific devices through its GPIOs with minimal development up-front and
minimal loading during runtime. With its high degree of on-chip integration, which includes the
antenna switch balun, power management converters, it requires minimal external circuitry, and
the entire solution, including front-end module, is designed to occupy minimal PCB area.
Sophisticated system-level features include fast sleep/wake context switching for energy-
efficient VoIP, adaptive radio biasing for low-power operation, advance signal processing, and
spur cancellation and radio co-existence features for common cellular, Bluetooth, DDR, LVDS,
LCD interference mitigation.
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ESP8266 802.11bgn Smart Device
3 Features
802.11 b/g/n protocol
Wi-Fi Direct (P2P), soft-AP
Integrated TCP/IP protocol stack
Integrated TR switch, balun, LNA, power amplifier and matching network
Integrated PLL, regulators, and power management units
+19.5dBm output power in 802.11b mode
Integrated temperature sensor
Supports antenna diversity
Power down leakage current of < 10uA
Integrated low power 32-bit CPU could be used as application processor
SDIO 2.0, SPI, UART
STBC, 1×1 MIMO, 2×1 MIMO
A-MPDU & A-MSDU aggregation & 0.4s guard interval
Wake up and transmit packets in < 2ms
Standby power consumption of < 1.0mW (DTIM3)
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ESP8266 802.11bgn Smart Device
4 Application Diagram
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ESP8266 802.11bgn Smart Device
5 Ultra Low Power Technology
ESP8266 has been designed for mobile, wearable electronics and Internet of Things applications
with the aim of achieving the lowest power consumption with a combination of several
proprietary techniques. The power saving architecture operates in 3 modes: active mode, sleep
mode and deep sleep mode.
By using advance power management techniques and logic to power-down functions not
required and to control switching between sleep and active modes, ESP8266 consumes less than
12uA in sleep mode and less than 1.0mW (DTIM=3) or less than 0.5mW (DTIM=10) to stay
connected to the access point.
When in sleep mode, only the calibrated real-time clock and watchdog remains active. The real-
time clock can be programmed to wake up the ESP8266 at any required interval.
The ESP8266 can be programmed to wake up when a specified condition is detected. This
minimal wake-up time feature of the ESP8266 can be utilized by mobile device SOCs, allowing
them to remain in the low-power standby mode until Wi-Fi is needed.
In order to satisfy the power demand of mobile and wearable electronics, ESP8266 can be
programmed to reduce the output power of the PA to fit various application profiles, by trading
off range for power consumption.
5.1 Highest Level of Integration
By integrating the costliest components such as power management unit, TR switch, RF balun,
high power PA capable of delivering +25dBm (peak), ESP8266 ensures that the BOM cost is the
lowest possible, and ease of integration into any system.
With ESP8266, the only external BOM are resistors, capacitors, and crystal.
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ESP8266 802.11bgn Smart Device
6 ESP8266 Applications
Smart power plugs
Home automation
Mesh network
Industrial wireless control
Baby monitors
IP Cameras
Sensor networks
Wearable electronics
Wi-Fi location-aware devices
Security ID tags
Wi-Fi position system beacons
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ESP8266 802.11bgn Smart Device
7 Specifications
7.1 Current Consumption
The following current consumption is based on 3.3V supply, and 25C ambient, using internal
regulators. Measurements are done at antenna port without SAW filter. All the transmitter’s
measurements are based on 90% duty cycle, continuous transmit mode.
Mode
Typ
Max
Unit
Transmit 802.11b, CCK 1Mbps, POUT=+19.5dBm
215
mA
Transmit 802.11b, CCK 11Mbps, POUT=+18.5dBm
197
mA
Transmit 802.11g, OFDM 54Mbps, POUT =+16dBm
145
mA
Transmit 802.11n, MCS7, POUT=+14dBm
135
mA
Receive 802.11b, packet length=1024 byte, -80dBm
60
mA
Receive 802.11g, packet length=1024 byte, -70dBm
60
mA
Receive 802.11n, packet length=1024 byte, -65dBm
62
mA
Standby
0.9
mA
Deep sleep
10
uA
Power save mode DTIM 1
1.2
mA
Power save mode DTIM 3
0.86
mA
Total shutdown
0.5
uA
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ESP8266 802.11bgn Smart Device
7.2 RF Performance
The following are measured under room temperature conditions with 3.3V and 1.1V power
supplies.
Description
Min
Typical
Max
Unit
Input frequency
2412
2484
MHz
Input impedance
50
Input reflection
-10
dB
Output power of PA for 72.2Mbps
14
15
16
dBm
Output power of PA for 11b mode
17.5
18.5
19.5
dBm
Sensitivity
CCK, 1Mbps
-98
dBm
CCK, 11Mbps
-91
dBm
6Mbps (1/2 BPSK)
-93
dBm
54Mbps (3/4 64-QAM)
-75
dBm
HT20, MCS7 (65Mbps, 72.2Mbps)
-71
dBm
Adjacent Channel Rejection
OFDM, 6Mbps
37
dB
OFDM, 54Mbps
21
dB
HT20, MCS0
37
dB
HT20, MCS7
20
dB
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ESP8266 802.11bgn Smart Device
8 CPU, Memory and Interfaces
8.1 CPU
This chip embeds an ultra low power Micro 32-bit CPU, with 16-bit thumb mode. This CPU can
be interfaced using:
code RAM/ROM interface (iBus) that goes to the memory controller, that can also be
used to access external flash memory,
data RAM interface (dBus), that also goes to the memory controller
AHB interface, for register access, and
JTAG interface for debugging
8.2 Memory Controller
The memory controller contains ROM, and SRAM. It is accessed by the CPU using the iBus,
dBus and AHB interface. Any of these interfaces can request access to the ROM or RAM
modules, and the memory controller arbiters serve these 3 interfaces on a first-come-first-serve
basis.
8.3 AHB and AHB Blocks
The AHB blocks performs the function of an arbiter, controls the AHB interfaces from the MAC,
SDIO (host) and CPU. Depending on the address, the AHB data requests can go into one of the
two slaves:
APB block, or
flash controller (usually for standalone applications).
Data requests to the memory controller are usually high speed requests, and requests to the APB
block are usually register access.
13 | P a g e Espressif Systems Oct 12, 2013
ESP8266 802.11bgn Smart Device
The APB block acts as a decoder. It is meant only for access to programmable registers within
ESP8266’s main blocks. Depending on the address, the APB request can go to the radio, SI/SPI,
SDIO (host), GPIO, UART, real-time clock (RTC), MAC or digital baseband.
8.4 Interfaces
The ESP8266 contains several analog and digital interfaces described in the following sections.
8.4.1 Master SI / SPI Control (Optional)
The master serial interface (SI) can operate in two, three or four-wire bus configurations to
control the EEPROM or other I2C/SPI devices. Multiple I2C devices with different device
addresses are supported by sharing the 2-wire bus.
Multiple SPI devices are supported by sharing the clock and data signals, using separate software
controlled GPIO pins as chip selects.
The SPI can be used for controlling external devices such as serial flash memories, audio
CODECs, or other slave devices. It is set up as a standard master SPI device with 3 different
enable pins:
SPI_EN0,
SPI_EN1,
SPI_EN2.
Both SPI master and SPI slave are supported with the latter being used as a host interface.
SPI_EN0 is used as an enable signal to an external serial flash memory for downloading patch
code and/or MIB-data to the baseband in an embedded application. In a host based application,
patch code and MIB-data can alternatively be downloaded via the host interface. This pin is
active low and should be left open if not used.
SPI_EN1 is usually used for a user application, e.g. to control an external audio codec or sensor
ADC, in an embedded application. This pin is active low and should be left open if not used.
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ESP8266 802.11bgn Smart Device
SPI_EN2 usually controls an EEPROM to store individual data, such as MIB information, MAC
address, and calibration data, or for general use. This pin is active low and should be left open if
not used.
Figure 2: SPI timing characteristics
8.4.2 General Purpose IO
There are up to 16 GPIO pins. They can be assigned to various functions by the firmware. Each
GPIO can be configured with internal pull-up/down, input available for sampling by a software
register, input triggering an edge or level CPU interrupt, input triggering a level wakeup interrupt,
open-drain or push-pull output driver, or output source from a software register, or a sigma-delta
PWM DAC.
These pins are multiplexed with other functions such as host interface, UART, SI, Bluetooth
coexistence, etc.
8.4.3 Digital IO Pads
The digital IO pads are bidirectional, non-inverting and tri-state. It includes input and an output
buffer with tristate control inputs. Besides this, for low power operations, the IO can also be set
to hold. For instance, when we power down the chip, all output enable signals can be set to hold
low.
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ESP8266 802.11bgn Smart Device
Optional hold functionality can be built into the IO if requested. When the IO is not driven by the
internal or external circuitry, the hold functionality can be used to hold the state to the last used
state.
The hold functionality introduces some positive feedback into the pad. Hence, the external driver
that drives the pad must be stronger than the positive feedback. The required drive strength is
however small in the range of 5uA.
Parameter
Symbol
Min
Max
Unit
Input low voltage
VIL
-0.3
0.25VIO
V
Input high voltage
VIH
0.75VIO
3.6
V
Input leakage current
IIL
50
nA
Output low voltage
VOL
0.1VIO
V
Output high voltage
VOH
0.8VIO
V
Input pin capacitance
Cpad
2
pF
VDDIO
VIO
1.7
3.6
V
Maximum drive capability
IMAX
12
mA
Temperature
Tamb
-20
100
C
All digital IO pins are protected from over-voltage with a snap-back circuit connected between
the pad and ground. The snap back voltage is typically about 6V, and the holding voltage is 5.8V.
This provides protection from over-voltages and ESD. The output devices are also protected
from reversed voltages with diodes.
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ESP8266 802.11bgn Smart Device
9 Firmware & Software Development Kit
The application and firmware is executed in on-chip ROM and SRAM, which loads the
instructions during wake-up, through the SDIO interface, from the external flash.
The firmware implements TCP/IP, the full 802.11 b/g/n/e/i WLAN MAC protocol and Wi-Fi
Direct specification. It supports not only basic service set (BSS) operations under the distributed
control function (DCF) but also P2P group operation compliant with the latest Wi-Fi P2P
protocol. Low level protocol functions are handled automatically by ESP8266:
RTS/CTS,
acknowledgement,
fragmentation and defragmentation,
aggregation,
frame encapsulation (802.11h/RFC 1042),
automatic beacon monitoring / scanning, and
P2P Wi-Fi direct,
Passive or active scanning, as well as P2P discovery procedure is performed autonomously once
initiated by the appropriate command. Power management is handled with minimum host
interaction to minimize active duty period.
9.1 Features
The SDK includes the following library functions:
802.11 b/g/n/d/e/i/k/r support;
Wi-Fi Direct (P2P) support:
P2P Discovery, P2P Group Owner mode, P2P Power Management
Infrastructure BSS Station mode / P2P mode / softAP mode support;
Hardware accelerators for CCMP (CBC-MAC, counter mode), TKIP (MIC, RC4), WAPI
(SMS4), WEP (RC4), CRC;
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ESP8266 802.11bgn Smart Device
WPA/WPA2 PSK, and WPS driver;
Additional 802.11i security features such as pre-authentication, and TSN;
Open Interface for various upper layer authentication schemes over EAP such as TLS,
PEAP, LEAP, SIM, AKA, or customer specific;
802.11n support (2.4GHz / 5GHz);
Supports MIMO 11 and 21, STBC, A-MPDU and A-MSDU aggregation and 0.4s
guard interval;
WMM power save U-APSD;
Multiple queue management to fully utilize traffic prioritization defined by 802.11e
standard;
UMA compliant and certified;
802.1h/RFC1042 frame encapsulation;
Scattered DMA for optimal CPU off load on Zero Copy data transfer operations;
Antenna diversity and selection (software managed hardware);
Clock/power gating combined with 802.11-compliant power management dynamically
adapted to curent connection condition providing minimal power consumption;
Adaptive rate fallback algorithm sets the optimium transmission rate and Tx power based
on actual SNR and packet loss information;
Automatic retransmission and response on MAC to avoid packet discarding on slow host
environment;
Seamless roaming support;
Configurable packet traffic arbitration (PTA) with dedicated slave processor based design
provides flexible and exact timing Bluetooth co-existence supoport for a wide range of
Bluetooth Chip vendors;
Dual and single antenna Bluetooth co-existence support with optional simultaneous
receive (Wi-Fi/Bluetooth) capability.
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ESP8266 802.11bgn Smart Device
10 Power Management
The chip can be put into the following states:
OFF: CHIP_PD pin is low. The RTC is
disabled. All registers are cleared.
DEEP_SLEEP: Only RTC is powered on
the rest of the chip is powered off.
Recovery memory of RTC can keep basic
Wi-Fi connecting information.
SLEEP: Only the RTC is operating. The
crystal oscillator is disabled. Any wakeup
events (MAC, host, RTC timer, external
interrupts) will put the chip into the
WAKEUP state.
WAKEUP: In this state, the system goes
from the sleep states to the PWR state. The
crystal oscillator and PLLs are enabled.
ON state: the high speed clock is
operational and sent to each block enabled by the clock control register. Lower level
clock gating is implemented at the block level, including the CPU, which can be gated off
using the WAITI instruction, while the system is on.
Off
On
Deep Sleep
Sleep
XTAL Off
WAKEUP
events
SLEEP criteria
XTAL_SETTLE
CHIP_PWD
Wakeup
~CHIP_PWD
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ESP8266 802.11bgn Smart Device
11 Clock Management
11.1 High Frequency Clock
The high frequency clock on ESP8266 is used to drive both the Tx and Rx mixers. This clock is
generated from the internal crystal oscillator and an external crystal. The crystal frequency can
range from 26MHz to 52MHz.
While internal calibration of the crystal oscillator ensures that a wide range of crystals can be
used, in general, the quality of the crystal is still a factor to consider, to obtain reasonable phase
noise. When the crystal selected is sub-optimal due to large frequency drifts or poor Q-factor, the
maximum throughput and sensitivity of the Wi-Fi system is degraded. Please refer to the
application notes on how the frequency offset can be measured.
Parameter
Symbol
Min
Max
Unit
Frequency
FXO
26
52
MHz
Loading capacitance
CL
32
pF
Motional capacitance
CM
2
5
pF
Series resistance
RS
0
65
Frequency tolerance
FXO
-15
15
ppm
Frequency vs temperature (-25C ~ 75C)
FXO,Temp
-15
15
ppm
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ESP8266 802.11bgn Smart Device
11.2 External Reference Requirements
For an externally generated clock, the frequency can range from 26MHz to 52MHz can be used.
For good performance of the radio, the following characteristics are expected of the clock:
Parameter
Symbol
Min
Max
Unit
Clock amplitude
VXO
0.2
1
Vpp
External clock accuracy
FXO,EXT
-15
15
ppm
Phase noise @1kHz offset, 40MHz clock
-120
dBc/Hz
Phase noise @10kHz offset, 40MHz clock
-130
dBc/Hz
Phase noise @100kHz offset, 40MHz clock
-138
dBc/Hz
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ESP8266 802.11bgn Smart Device
12 Radio
The ESP8266 radio consists of the following main blocks:
2.4GHz receiver
2.4GHz transmitter
High speed clock generators and crystal oscillator
Real time clock
Bias and regulators
Power management
12.1 Channel Frequencies
The RF transceiver supports the following channels according to the IEEE802.11bgn standards.
Channel
No
Frequency
(MHz)
Channel
No
Frequency
(MHz)
1
2412
8
2447
2
2417
9
2452
3
2422
10
2457
4
2427
11
2462
5
2432
12
2467
6
2437
13
2472
7
2442
14
2484
12.2 2.4GHz Receiver
The 2.4GHz receiver downconverts the RF signal to quadrature baseband signals and converts
them to the digital domain with 2 high resolution high speed ADCs. To adapt to varying signal
channel conditions, RF filters, automatic gain control, DC offset cancelation circuits and
baseband filters are integrated within the radio.
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ESP8266 802.11bgn Smart Device
12.3 2.4GHz Transmitter
The 2.4GHz transmitter upconverts the quadrature baseband signals to 2.4GHz, and drives the
antenna with a high powered CMOS power amplifier. The use of digital calibration further
improves the linearity of the power amplifier, enabling a state of art performance of delivering
+19dBm average power for 802.11b transmission and +16dBm for 802.11n transmission.
Additional calibrations are integrated to cancel any imperfections of the radio, such as:
carrier leakage,
I/Q phase matching, and
baseband nonlinearities
This reduces the amount of time required and test equipment required for production testing.
12.4 Clock Generator
The clock generator generates quadrature 2.4GHz clock signals for the receiver and transmitter.
All components of the clock generator are integrated on-chip, including:
inductor,
varactor, and
loop filter.
The clock generator has built-in calibration and self test circuits. Quadrature clock phases and
phase noise are optimized on-chip with patented calibration algorithms to ensure the best
receiver and transmitter performance.
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ESP8266 802.11bgn Smart Device
App. QFN32 Package Drawing

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