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NUP4114, SZNUP4114 Series Datasheet

ON Semiconductor

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Datasheet

© Semiconductor Components Industries, LLC, 2014
July, 2018 − Rev. 6 1Publication Order Number:
NUP4114/D
NUP4114 Series
ESD Protection Diode
Low Clamping Voltage
The NUP4114 ESD protection diode array is designed to protect
high speed data lines from ESD. Ultra−low capacitance and high level
of ESD protection make these devices well suited for use in USB 2.0
high speed applications.
Features
Low Clamping Voltage
Low Capacitance (<0.6 pF Typical, I/O to GND)
Low Leakage
Response Time is Typically < 1.0 ns
IEC61000−4−2 Level 4 ESD Protection
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
LVDS
USB 2.0 High Speed Data Line and Power Line Protection
Digital Video Interface (DVI) and HDMI
Gigabit Ethernet
Monitors and Flat Panel Displays
Notebook Computers
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ40 to +125 °C
Storage Temperature Range Tstg 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds) TL260 °C
IEC 61000−4−2 Contact
IEC 61000−4−2 Air
ISO 10605 330 pF / 330 W Contact
ISO 10605 330 pF / 2 kW Contact
ISO 10605 150 pF / 2 kW Contact
ESD ±8
±15
±10
±21
±30
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of survivability specs.
www.onsemi.com
MARKING
DIAGRAMS
X2 MG
G
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
1
6
1
SC−88
W1 SUFFIX
CASE 419B
(Note: Microdot may be in either location)
5
3
6
2
14
X4 MG
G
1
6
1
SC−88
W1 SUFFIX
CASE 419B
P4H MG
G
1
6
TSOP−6
CASE 318G
STYLE 12
1
SOT−563
CASE 463A P4MG
G
1
1
6
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
NUP4114 Series
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
IFForward Current
VFForward Voltage @ IF
Ppk Peak Power Dissipation
CCapacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Uni−Directional
IPP
IF
V
I
IR
IT
VRWM
VCVBR VF
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM 5.5 V
Breakdown Voltage VBR IT = 1 mA, (Note 1) 5.5 6.5 V
Reverse Leakage Current IRVRWM = 5.5 V 1.0 mA
Clamping Voltage VCIPP = 1 A (Note 2) 8.3 10 V
IPP = 5 A (Note 3) 8.5 9.0 V
IPP = 8 A (Note 3) 9.2 10 V
ESD Clamping Voltage VCPer IEC61000−4−2 (Note 4) See Figures 1 & 2
Maximum Peak Pulse Current IPP 8/20 ms Waveform (Note 3) 12 A
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND 0.6 pF
VR = 0 V, f = 1 MHz between I/O Pins 0.3 pF
1. VBR is measured at pulse test current IT.
2. Nonrepetitive current pulse (I/O to GND).
3. Nonrepetitive current pulse (Pin 5 to Pin 2)
4. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
NUP4114 Series
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3
IEC 61000−4−2 Spec.
Level Test Volt-
age (kV)
First Peak
Current
(A) Current at
30 ns (A) Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Figure 4. Diagram of ESD Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8/20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
NUP4114 Series
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4
Figure 6. 500 MHz Data Pattern
ORDERING INFORMATION
Device Marking Package Shipping
NUP4114UCLW1T2G X2
SC−88
(Pb−Free) 3000 / Tape & Reel
SZNUP4114UCLW1T2G X2
NUP4114UCW1T2G X4
NUP4114UPXV6T1G P4 SOT−563
(Pb−Free) 4000 / Tape & Reel
NUP4114UPXV6T2G
NUP4114HMR6T1G P4H TSOP−6
(Pb−Free) 3000 / Tape & Reel
SZNUP4114HMR6T1G P4H
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NUP4114 Series
www.onsemi.com
5
APPLICATIONS INFORMATION
The new NUP4114 is a low capacitance ESD diode array
designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the NUP4114 offers low capacitance steering
diodes and an ESD diode integrated in a single package
(TSOP−6). If a transient condition occurs, the steering
diodes will drive the transient to the positive rail of the
power supply or to ground. This device protects the power
line against overvoltage conditions to avoid damage to the
power supply and any downstream components.
NUP4114 Configuration Options
The NUP4114 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or
VCC + Vf). The diodes will force the transient current to
bypass the sensitive circuit.
Data lines are connected at pins 1, 3, 4 and 6. The negative
reference is connected at pin 2. This pin must be connected
directly to ground by using a ground plane to minimize the
PCB’s ground inductance. It is very important to reduce the
PCB trace lengths as much as possible to minimize parasitic
inductances.
Option 1
Protection of four data lines and the power supply using
VCC as reference.
I/O 1
I/O 2
I/O 3
I/O 4
VCC
6
5
4
1
2
3
For this configuration, connect pin 5 directly to the
positive supply rail (VCC), the data lines are referenced to
the supply voltage. The internal ESD diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.
Option 2
Protection of four data lines with bias and power supply
isolation resistor.
VCC
10 k
I/O 1
I/O 2
I/O 3
I/O 4
6
5
4
1
2
3
The NUP4114 can be isolated from the power supply by
connecting a series resistor between pin 5 and VCC. A 10 kW
resistor is recommended for this application. This will
maintain a bias on the internal ESD and steering diodes,
reducing their capacitance.
Option 3
Protection of four data lines using the internal ESD diode
as reference.
I/O 1
I/O 2
I/O 3
I/O 4
NC
6
5
4
1
2
3
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal ESD can be used as the reference. For
these applications, pin 5 is not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
the ESD plus one diode drop (VC = Vf + VESD).
ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
NUP4114 Series
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6
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
VCC
D1
D2
Data Line
IESDpos
IESDneg
VF + VCC
−VF
IESDpos
IESDneg
Power
Supply
Protected
Device
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:
For positive pulse conditions:
Vc = VCC + VfD1
For negative pulse conditions:
Vc = −VfD2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.
VCC
D1
D2
Data Line
IESDpos
IESDneg
VC = VCC + Vf + (L diESD/d
t)
IESDpos
IESDneg
Power
Supply
Protected
Device
V
C
= −Vf − (L diESD/dt
)
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = VCC + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = −Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
L diESD/dt factor. A relatively small trace inductance can
result in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board
layout. Taking care to minimize the effects of parasitic
inductance will provide significant benefits in transient
immunity.
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD
events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
therefore higher capacitance. This capacitance becomes
problematic as transmission frequencies increase. Reducing
capacitance generally requires reducing die size. These
small die will have higher forward voltage characteristics at
typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.
The ON Semiconductor NUP4114 was developed to
overcome the disadvantages encountered when using
discrete diodes for ESD protection. This device integrates an
ESD diode within a network of steering diodes.
Figure 7. NUP4114 Equivalent Circuit
5
3
6
2
14
During an ESD condition, the ESD current will be driven
to ground through the ESD diode as shown below.
VCC
D1
D2
Data Line
IESDpos
Power
Supply
Protected
Device
The resulting clamping voltage on the protected IC will
be:
Vc = VF + VESD.
The clamping voltage of the ESD diode depends on the
magnitude of the ESD current. The steering diodes are fast
switching devices with unique forward voltage and low
capacitance characteristics.
NUP4114 Series
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7
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
23
456
D
1
eb
E1
A1
A
0.05
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
c
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DIM
AMIN NOM MAX
MILLIMETERS
0.90 1.00 1.10
A1 0.01 0.06 0.10
b0.25 0.38 0.50
c0.10 0.18 0.26
D2.90 3.00 3.10
E2.50 2.75 3.00
e0.85 0.95 1.05
L0.20 0.40 0.60
0.25 BSC
L2
0°10°
1.30 1.50 1.70
E1
E
RECOMMENDED
NOTE 5
LC
M
H
L2
SEATING
PLANE
GAUGE
PLANE
DETAIL Z
DETAIL Z
0.60
6X
3.20 0.95
6X
0.95
PITCH
DIMENSIONS: MILLIMETERS
M
NUP4114 Series
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8
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
Cddd M
123
A1
A
c
654
E
b
6X DIM MIN NOM MAX
MILLIMETERS
A 1.10
A1 0.00 0.10
ddd
b0.15 0.20 0.25
C0.08 0.15 0.22
D1.80 2.00 2.20
0.043
0.000 0.004
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
MIN NOM MAX
INCHES
0.10 0.004
E1 1.15 1.25 1.35
e0.65 BSC
L0.26 0.36 0.46
2.00 2.10 2.20 0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.078 0.082 0.086
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.66
6X
DIMENSIONS: MILLIMETERS
0.30
PITCH
2.50
6X
RECOMMENDED
TOP VIEW
SIDE VIEW END VIEW
bbb H
B
SEATING
PLANE
DETAIL A E
A2 0.70 0.90 1.00 0.027 0.035 0.039
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
ccc 0.10 0.004
A-B D
aaa C
2X 3 TIPS
D
E1
D
e
A
2X
aaa H D
2X
D
L
PLANE
DETAIL A
H
GAGE
L2
C
ccc C
A2
6X
NUP4114 Series
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9
PACKAGE DIMENSIONS
HE
DIM MIN NOM MAX
MILLIMETERS
A0.50 0.55 0.60
b0.17 0.22 0.27
C
D1.50 1.60 1.70
E1.10 1.20 1.30
e0.5 BSC
L0.10 0.20 0.30
1.50 1.60 1.70
0.020 0.021 0.023
0.007 0.009 0.011
0.059 0.062 0.066
0.043 0.047 0.051
0.02 BSC
0.004 0.008 0.012
0.059 0.062 0.066
MIN NOM MAX
INCHES
SOT−563, 6 LEAD
CASE 463A
ISSUE G
eM
0.08 (0.003) X
b6 5 PL
A
C
−X−
−Y−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
D
E
Y
12 3
45
L
6
1.35
0.0531
0.5
0.0197
ǒmm
inchesǓ
SCALE 20:1
0.5
0.0197
1.0
0.0394
0.45
0.0177
0.3
0.0118
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
HE
0.08 0.12 0.18 0.003 0.005 0.007
NUP4114/D
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