LTC6655 Datasheet

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Datasheet

LTC6655/LTC6655LN
1
Rev. G
For more information www.analog.com
TYPICAL APPLICATION
DESCRIPTION
0.25ppm Noise, Low Drift
Precision References
The LTC
®
6655 is a complete family of precision bandgap
voltage references, offering exceptional noise and drift
performance. This low noise and drift is ideally suited
for the high resolution measurements required by instru-
mentation and test equipment. In addition, the LTC6655
is fully specified over the temperature range of 40°C
to 125°C, ensuring its suitability for demanding auto-
motive and industrial applications. Advanced curvature
compensation allows this bandgap reference to achieve a
drift of less than 2ppm/°C with a predictable temperature
characteristic and an output voltage accurate to ±0.025%,
reducing or eliminating the need for calibration.
The LTC6655LN Low Noise comes with a noise reduction
pin that enables reduction of wideband noise with the
addition of a single capacitor.
The LTC6655 can be powered from as little as 500mV
above the output voltage to as much as 13.2V. Superior
load regulation with source and sink capability, coupled
with exceptional line rejection, ensures consistent per-
formance over a wide range of operating conditions. A
shutdown mode is provided for low power applications.
The LTC6655 references are offered in an 8-lead MSOP
package and an 8-lead LS8 package. The LS8 is a
5mm × 5mm surface mount hermetic package that pro-
vides outstanding stability.
All registered trademarks and trademarks are the property of their respective owners.
Basic Connection
Basic Connection with Noise Reduction
FEATURES
APPLICATIONS
n Low Noise:
n 0.25ppmP-P (0.1Hz to 10Hz) 625nVP-P for the
LTC6655-2.5
n 0.21ppmRMS (10Hz to 10kHz) for the
LTC6655LN-2.5 CNR = 100µF
n Low Drift: 2ppm/°C Max
n High Accuracy: ±0.025% Max
n No Humidity Sensitivity (LS8 Package)
n Thermal Hysteresis (LS8): 30ppm (–40°C to 85°C)
n Long-Term Drift (LS8): 20ppm/√kHr
n 100% Tested at –40°C, 25°C and 125°C
n Load Regulation: <10ppm/mA
n Sinks and Sources Current: ±5mA
n Low Dropout: 500mV
n Maximum Supply Voltage: 13.2V
n Low Power Shutdown: <20µA Max
n Available Output Voltages: 1.25V, 2.048V, 2.5V, 3V,
3.3V, 4.096V, 5V
n Available in an 8-Lead MSOP and High Stability
Hermetic 5mm × 5mm LS8 Packages
n
Instrumentation and Test Equipment
n
High Resolution Data Acquisition Systems
n
Weigh Scales
n
Precision Battery Monitors
n
Precision Regulators
n
Medical Equipment
LTC6655-2.5
VIN
SHDN C
OUT
10µF
V
OUT
6655 TA01a
VOUT_F
VOUT_S
3V < V
IN ≤ 13.2V
GND
CIN
0.1µF
LTC6655LN-2.5
VIN
SHDN C
OUT
10µF
CNR
10µF
V
OUT
6655 TA01c
VOUT
NR
3V < V
IN ≤ 13.2V
GND
CIN
0.1µF
Low Frequency 0.1Hz to 10Hz Noise (LTC6655-2.5)
500nV/DIV
6655 TA01b
1s/DIV
Document Feedback
LTC6655/LTC6655LN
2
Rev. G
For more information www.analog.com
Input Voltage
VIN to GND .......................................... 0.3V to 13.2V
SHDN to GND ........................... 0.3V to (VIN + 0.3V)
Output Voltage:
VOUT_F....................................... –0.3V to (VIN + 0.3V)
VOUT_S ..................................................... 0.3V to 6V
NR ........................................................... 0.3V to 6V
Output Short-Circuit Duration ...................... Indefinite
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Operating Temperature Range (Note 2).. 40°C to 125°C
Storage Temperature Range (Note 2) ..... 65°C to 150°C
Lead Temperature Range (Soldering, 10 sec)
(Note 3) .................................................................300°C
LTC6655 LTC6655LN
1
2
3
4
SHDN
VIN
GND
GND
8
7
6
5
GND
VOUT_F
VOUT_S
GND
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 300°C/W
STAR ALL GND CONNECTIONS AT PIN 4
1
2
3
4
SHDN
VIN
GND
GND
8
7
6
5
GND
VOUT_F
NR
GND
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 300°C/W
STAR ALL GND CONNECTIONS AT PIN 4
LTC6655
1
2
3
SHDN
VIN
GND
7
6
5
VOUT_F
VOUT_S
GND
4
GND
8
GND
TOP VIEW
LS8 PACKAGE
8-PIN LEADLESS CHIP CARRIER (5mm
×
5mm)
TJMAX = 150°C, θJA = 120°C/W
STAR ALL GND CONNECTIONS AT PIN 4
LTC6655/LTC6655LN
3
Rev. G
For more information www.analog.com
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL
PART
MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6655BHMS8-1.25#PBF LTC6655BHMS8-1.25#TRPBF LTFDG 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-1.25#PBF LTC6655CHMS8-1.25#TRPBF LTFDG 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-2.048#PBF LTC6655BHMS8-2.048#TRPBF LTFDH 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-2.048#PBF LTC6655CHMS8-2.048#TRPBF LTFDH 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-2.5#PBF LTC6655BHMS8-2.5#TRPBF LTFCY 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-2.5#PBF LTC6655CHMS8-2.5#TRPBF LTFCY 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-3#PBF LTC6655BHMS8-3#TRPBF LTFDJ 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-3#PBF LTC6655CHMS8-3#TRPBF LTFDJ 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-3.3#PBF LTC6655BHMS8-3.3#TRPBF LTFDK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-3.3#PBF LTC6655CHMS8-3.3#TRPBF LTFDK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-4.096#PBF LTC6655BHMS8-4.096#TRPBF LTFDM 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-4.096#PBF LTC6655CHMS8-4.096#TRPBF LTFDM 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHMS8-5#PBF LTC6655BHMS8-5#TRPBF LTFDN 8-Lead Plastic MSOP –40°C to 125°C
LTC6655CHMS8-5#PBF LTC6655CHMS8-5#TRPBF LTFDN 8-Lead Plastic MSOP –40°C to 125°C
LTC6655LNBHMS8-2.5#PBF LTC6655LNBHMS8-2.5#TRPBF LTHFK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655LNCHMS8-2.5#PBF LTC6655LNCHMS8-2.5#TRPBF LTHFK 8-Lead Plastic MSOP –40°C to 125°C
LTC6655BHLS8-2.5 #PBFN/A 665525 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655CHLS8-2.5 #PBFN/A 665525 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655BHLS8-4.096#PBFN/A 554096 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655CHLS8-4.096#PBFN/A 554096 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655BHLS8-5 #PBFN/A 66555 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
LTC6655CHLS8-5 #PBFN/A 66555 8-Lead Ceramic LCC (5mm × 5mm) –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
This product is only offered in trays.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LTC6655/LTC6655LN
4
Rev. G
For more information www.analog.com
AVAILABLE OPTIONS
OUTPUT VOLTAGE INITIAL ACCURACY TEMPERATURE COEFFICIENT PART NUMBER
1.250 0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHMS8-1.25
LTC6655CHMS8-1.25
2.048 0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHMS8-2.048
LTC6655CHMS8-2.048
2.500 0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHMS8-2.5
LTC6655CHMS8-2.5
0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHLS8-2.5
LTC6655CHLS8-2.5
0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655LNBHMS8-2.5
LTC6655LNCHMS8-2.5
3.000 0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHMS8-3.0
LTC6655CHMS8-3.0
3.300 0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHMS8-3.3
LTC6655CHMS8-3.3
4.096 0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHMS8-4.096
LTC6655CHMS8-4.096
0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHLS8-4.096
LTC6655CHLS8-4.096
5.000 0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHMS8-5
LTC6655CHMS8-5
0.025%
0.05% 2ppm/°C
5ppm/°C LTC6655BHLS8-5
LTC6655CHLS8-5
See Order Information section for complete part number listing.
LTC6655/LTC6655LN
5
Rev. G
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT + 0.5V, VOUT_S connected to VOUT_F , unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage LTC6655B
LTC6655C –0.025
–0.05 0.025
0.05 %
%
Output Voltage Temperature Coefficient
(Note 4) LTC6655B
LTC6655C
l
l
1
2.5 2
5ppm/°C
ppm/°C
Line Regulation VOUT + 0.5V ≤ VIN ≤ 13.2V, SHDN = 2V
l
5 25
40 ppm/V
ppm/V
Load Regulation (Note 5) ISOURCE = 5mA LTC6655MS8
l
3
15 ppm/mA
ppm/mA
LTC6655LS8
l
3
15 ppm/mA
ppm/mA
LTC6655LNMS8
l
6
20 ppm/mA
ppm/mA
ISINK = 5mA LTC6655MS8
l
10
30 ppm/mA
ppm/mA
LTC6655LS8
l
20
45 ppm/mA
ppm/mA
LTC6655LNMS8
l
14
35 ppm/mA
ppm/mA
Operating Voltage (Note 6) LTC6655-1.25, LTC6655-2.048, LTC6655-2.5
ISOURCE = 5mA, VOUT Error ≤ 0.1%
l
3
13.2
V
LTC6655-3, LTC6655-3.3, LTC6655-4.096, LTC6655-5
ISOURCE = ±5mA, VOUT Error ≤ 0.1%
IOUT = 0mA, VOUT Error ≤ 0.1%
l
l
VOUT + 0.5
VOUT + 0.2
13.2
13.2
V
V
Output Short-Circuit Current Short VOUT to GND
Short VOUT to VIN
20
20 mA
mA
Shutdown Pin (SHDN) Logic High Input Voltage
Logic High Input Current, SHDN = 2V
l
l
2.0
12 V
µA
Logic Low Input Voltage
Logic Low Input Current, SHDN = 0.8V
l
l
0.8
15 V
µA
Supply Current No Load
l
5 7
7.5 mA
mA
Shutdown Current SHDN Tied to GND l20 µA
LTC6655/LTC6655LN
6
Rev. G
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT + 0.5V, VOUT_S connected to VOUT_F , unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage Noise (Note 7) LTC6655
0.1Hz ≤ f ≤ 10Hz
10Hz ≤ f ≤ 1kHz
0.25
0.67
ppmP-P
ppmRMS
LTC6655LN
0.1Hz ≤ f ≤ 10Hz, CNR = 100µF
10Hz ≤ f ≤ 1kHz, CNR = 100µF
0.12
0.21
ppmP-P
ppmRMS
Turn-On Time 0.1% Settling, COUT = 2.7µF 400 µs
Long-Term Drift of Output Voltage (Note 8) LTC6655MS8
LTC6655LS8 60
20 ppm/√kHr
ppm/√kHr
Hysteresis (Note 9) LTC6655MS8
∆T = 0°C to 70°C
∆T = –40°C to 85°C
∆T = –40°C to 125°C
20
30
60
ppm
ppm
ppm
LTC6655LS8
∆T = 0°C to 70°C
∆T = –40°C to 85°C
∆T = –40°C to 125°C
5
30
80
ppm
ppm
ppm
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Precision may be affected if the parts are stored outside of the
specified temperature range. Large temperature changes may cause
changes in device performance due to thermal hysteresis. For best
performance, extreme temperatures should be avoided whenever possible.
Note 3: The stated temperature is typical for soldering of the leads during
manual rework. For detailed IR reflow recommendations, refer to the
Applications Information section.
Note 4: Temperature coefficient is measured by dividing the maximum
change in output voltage by the specified temperature range.
Note 5: Load regulation is measured on a pulse basis from no load to
the specified load current. Load current does not include the 2mA sense
current. Output changes due to die temperature change must be taken into
account separately.
Note 6: Excludes load regulation errors. Minimum supply for the
LTC6655-1.25, LTC6655-2.048 and LTC6655-2.5 is set by internal
circuitry supply requirements, regardless of load condition. Minimum
supply for the LTC6655-3, LTC6655-3.3, LTC6655-4.096 and LTC6655-5
is specified by load current.
Note 7: Peak-to-peak noise is measured with a 2-pole highpass filter at
0.1Hz and 3-pole lowpass filter at 10Hz. The unit is enclosed in a still-air
environment to eliminate thermocouple effects on the leads, and the
test time is 10 seconds. Due to the statistical nature of noise, repeating
noise measurements will yield larger and smaller peak values in a given
measurement interval. By repeating the measurement for 1000 intervals,
each 10 seconds long, it is shown that there are time intervals during
which the noise is higher than in a typical single interval, as predicted by
statistical theory. In general, typical values are considered to be those for
which at least 50% of the units may be expected to perform similarly or
better. For the 1000 interval test, a typical unit will exhibit noise that is
less than the typical value listed in the Electrical Characteristics table in
more than 50% of its measurement intervals. See Application Note 124 for
noise testing details. RMS noise is measured with a spectrum analyzer in a
shielded environment.
Note 8: Long-term stability typically has a logarithmic characteristic and
therefore, changes after 1000 hours tend to be much smaller than before
that time. Total drift in the second thousand hours is normally less than
one-third that of the first thousand hours with a continuing trend toward
reduced drift with time. Long-term stability is also affected by differential
stresses between the IC and the board material created during board
assembly.
Note 9: Hysteresis in output voltage is created by mechanical stress
that differs depending on whether the IC was previously at a higher or
lower temperature. Output voltage is always measured at 25°C, but
the IC is cycled to the hot or cold temperature limit before successive
measurements. Hysteresis is roughly proportional to the square of the
temperature change. For instruments that are stored at well controlled
temperatures (within 20 or 30 degrees of operational temperature),
hysteresis is usually not a significant error source. Typical hysteresis is the
worst case of 25°C to cold to 25°C or 25°C to hot to 25°C, preconditioned
by one thermal cycle.
LTC6655/LTC6655LN
7
Rev. G
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.
1.25V Load Regulation (Sinking)
1.25V Output Voltage Noise
Spectrum
1.25V Sinking Current with a
3.3µF Output Capacitor
1.25V Sourcing Current with a
3.3µF Output Capacitor
1.25V Shutdown Supply Current
vs Input Voltage 1.25V VOUT Distribution
1.25V Low Frequency
0.1Hz to 10Hz Noise
1.25V Output Voltage
Temperature Drift 1.25V Load Regulation (Sourcing)
200nV/
DIV
6655 G01
1s/DIV
TEMPERATURE (°C)
–50 –25
1.2496
OUTPUT VOLTAGE (V)
1.2498
1.2504
050 75
6655 G02
1.2502
1.2500
25 100 125
3 TYPICAL UNITS
OUTPUT CURRENT (mA)
–20
OUTPUT VOLTAGE CHANGE (ppm)
0
20
–30
–10
10
0.001 0.1 1 10
6655 G03
–40
0.01
125°C
25°C
–40°C
OUTPUT CURRENT (mA)
40
80
120
160
200
0.001 0.1 1 10
6655 G04
00.01
125°C
25°C
–40°C
FREQUENCY (kHz)
10
NOISE VOLTAGE (nV/√Hz)
15
25
35
40
0.01 1 10 1000
6655 G05
5
0.1 100
30
20
0
2.7µF
10µF
100µF
IOUT 0mA
5mA
VOUT
10mV/DIV
COUT = 3.3µF 200µs/DIV 6655 G06
IOUT
–5mA
0mA
VOUT
10mV/DIV
COUT = 3.3µF 200µs/DIV 6655 G07
INPUT VOLTAGE (V)
0
8
10
14
6 10
6655 G08
6
4
2 4 8 12 14
2
0
12
SUPPLY CURRENT (µA)
125°C
25°C
–40°C
VOUT (V)
1.2495
0
NUMBER OF PARTS
10
20
30
40
50
60
TA = 25°C
1.2498 1.2500 1.2503 1.2505
6655 G09
LTC6655/LTC6655LN
8
Rev. G
For more information www.analog.com
2.5V Load Regulation (Sinking)
2.5V Supply Current
vs Input Voltage
2.5V Shutdown Supply Current
vs Input Voltage
2.5V Minimum VIN – VOUT
Differential (Sourcing)
2.5V Minimum VIN – VOUT
Differential (Sinking)
2.5V Output Voltage Noise
Spectrum
2.5V Low Frequency
0.1Hz to 10Hz Noise
2.5V Output Voltage
Temperature Drift 2.5V Load Regulation (Sourcing)
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.
500nV/
DIV
6655 G10
1s/DIV
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
6655 G11
2.4990
2.4995
2.5000
2.5005
2.5010
–50 0 50 100 150
3 TYPICAL UNITS
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE CHANGE (ppm)
6655 G12
–50
–40
–30
–20
–10
0
10
0.001 0.01 0.1 1 10
125°C
25°C
–40°C
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE CHANGE (ppm)
6655 G13
–20
0
40
80
120
20
60
100
140
160
0.001 0.01 0.1 1 10
125°C
25°C
–40°C
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
6655 G14
0
1
2
3
4
5
6
7
8
0 2 4 6 8 10 12 14
125°C
25°C
–40°C
INPUT VOLTAGE (V)
SUPPLY CURRENT (µA)
6655 G15
0
2
4
6
8
10
12
14
0 2 4 6 8 10 12 14
125°C
25°C
–40°C
INPUT – OUTPUT VOLTAGE (V) 6655 G16
0.01
0.1
1
10
0.01 0.1 1
OUTPUT CURRENT (mA)
125°C
25°C
–40°C
6655 G17
0.01
0.1
1
10
–0.15 –0.05 0.05 0.15
OUTPUT CURRENT (mA)
INPUT – OUTPUT VOLTAGE (V)
125°C
25°C
–40°C
COUT = 100µF
FREQUENCY (kHz)
60
NOISE VOLTAGE (nV√Hz)
100
0.01 10 100 1000
0
20
0.1 1
120
80
40
6655 F01
COUT = 2.7µF
COUT = 10µF
LTC6655/LTC6655LN
9
Rev. G
For more information www.analog.com
2.5V Power Supply Rejection
Ratio vs Frequency
2.5V Output Impedance
vs Frequency 2.5V Line Regulation
2.5V VOUT Distribution
2.5V Temperature Drift
Distribution
2.5V SHDN Input Voltage
Thresholds vs VIN
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.
VOUT (V)
2.4992
0
NUMBER OF PARTS
20
40
60
2.4996 2.5000 2.5004 2.5008
80
100
10
30
50
70
90
6655 G19
TA = 25°C
DRIFT (ppm/C)
0
NUMBER OF PARTS
8
10
12
2.8
6
4
0.8 1.6
0.4 1.2 2 2.4
2
0
14 –40°C TO 125°C
6655 G20
VIN (V)
V
TRIP
(V)
6655 G21
VTH_UP
VTH_DN
0.0
0.5
1.0
1.5
2.0
2.5
2 4 6 8 10 12 14
FREQUENCY (kHz)
POWER SUPPLY REJECTION RATIO (dB)
40
60
100
80
20
0
120
6655 G22
10.1 10 1000.010.001
COUT = 2.7µF
COUT = 10µF
COUT = 100µF
FREQUENCY (kHz)
OUTPUT IMPEDENCE (Ω)
101 1000.10.001 0.01 1000
6655 G23
0.01
0.1
1
10
COUT = 2.7µF
COUT = 10µF
COUT = 100µF
INPUT VOLTAGE (V)
0
OUTPUT VOLTAGE (V)
2.501
2.500
48
2610 12 14
2.499
2.498
2.502
6655 G24
125°C
25°C
–40°C
LTC6655/LTC6655LN
10
Rev. G
For more information www.analog.com
5V Load Regulation (Sinking)
5V Supply Current
vs Input Voltage
5V Output Voltage Noise
Spectrum
5V Minimum VIN-VOUT
Differential (Sourcing)
5V Minimum VIN-VOUT
Differential (Sinking)
5V Start-Up Response with a
3.3µF Output Capacitor
5V Low Frequency
0.1Hz to 10Hz Noise
5V Output Voltage
Temperature Drift 5V Load Regulation (Sourcing)
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves are similar for most voltage options of the LTC6655. Curves from the LTC6655-1.25, LTC6655-2.5 and the
LTC6655-5 represent the range of performance across the entire family of references. Characteristic curves for other output voltages
fall between these curves and can be estimated based on their voltage output.
TEMPERATURE (°C)
–50
4.9985
OUTPUT VOLTAGE (V)
4.9990
4.9995
5.0000
5.0010
5.0005
–25 0 25 50
6655 G26
75 100 125
3 TYPICAL UNITS
500nV/
DIV
6655 G25
1s/DIV
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE CHANGE (ppm)
0.01
–50
–10
0
10
0.1 1 10
6655 G27
–20
–30
–40 125°C
25°C
–40°C
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE CHANGE (ppm)
0.01
–20
60
80
100
0.1 1 10
6655 G28
40
20
0
125°C
25°C
–40°C
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
4
5
6
6 10
6655 G29
3
2
2 4 8 12 14
1
0
125°C
25°C
–40°C
FREQUENCY (kHz)
0.01
80
NOISE VOLTAGE (nV/√Hz)
100
120
140
160
0.1 1 10 100 1000
6655 G30
60
40
20
0
180
200
2.7µF
10µF
100µF
INPUT-OUTPUT VOLTAGE (V)
0.01
0.01
OUTPUT CURRENT (mA)
1
10
0.1 1
6655 G31
0.1
125°C
25°C
–40°C
INPUT-OUTPUT VOLTAGE (V)
–0.3
0.01
OUTPUT CURRENT (mA)
0.1
1
10
–0.2 –0.1 0 0.1
6655 G32
125°C
25°C
–40°C
VIN
2V/DIV
VOUT
2V/DIV
COUT = 3.3µF 400µs/DIV 6655 G33
LTC6655/LTC6655LN
11
Rev. G
For more information www.analog.com
LTC6655LN-2.5 Effect of NR Pin
Leakage on VOUT
LTC6655LN-2.5 Output Voltage
Noise Spectrum
LTC6655LN-2.5 Output
Integrated Noise
TYPICAL PERFORMANCE CHARACTERISTICS
Characteristic curves shown below are the LTC6655NL option.
C
OUT
= 2.7µF
C
NR
= 0.1µF
C
NR
= 1µF
C
NR
= 10µF
C
NR
= 100µF
FREQUENCY (kHz)
0.01
0.1
1
10
100
1k
0
10
20
30
40
50
60
70
NOISE VOLTAGE (nV/√
Hz
)
6655 G34
C
OUT
= 2.7µF
C
NR
= 0.1µF
C
NR
= 1µF
C
NR
= 10µF
C
NR
= 100µF
FREQUENCY (kHz)
0.01
0.1
1
10
0
1
2
3
4
5
INTEGRATED NOISE (µV
RMS
)
6655 G35
CURRENT INJECTED INTO THE NR PIN (nA)
–1000
–750
–500
–250
0
250
500
750
1000
–1000
–800
–600
–400
–200
0
200
400
600
800
1000
CHANGE IN V
OUT
V)
6655 G36
LTC6655/LTC6655LN
12
Rev. G
For more information www.analog.com
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. This active low input
powers down the device to <20µA. If left open, an internal
pull-up resistor puts the part in normal operation. It is
recommended to tie this pin high externally for best
performance during normal operation.
VIN (Pin 2): Power Supply. Bypass VIN with a 0.1µF, or
larger, capacitor to GND.
GND (Pin 4): Device Ground. This pin is the main ground
and must be connected to a noise-free ground plane.
VOUT_S (Pin 6 LTC6655): VOUT Sense Pin. Connect
this pin at the load and route with a wide metal trace
to minimize load regulation errors. This pin sinks 2mA.
Output error is RTRACE 2mA, regardless of load current.
For load currents <100µA, tie directly to VOUT_F pin.
NR (Pin 6 – LTC6655LN): Noise Reduction Pin. To band
limit noise, connect a capacitor between this pin and
ground. See Applications Information section.
VOUT_F (Pin 7 LTC6655): VOUT Force Pin. This pin
sources and sinks current to the load. An output capacitor
of 2.7µF to 100µF is required.
VOUT_F (Pin 7 LTC6655LN): VOUT Pin. This pin sources
and sinks current to the load. An output capacitor of 2.7µF
to 100µF is required.
GND (Pins 3, 5, 8): Internal Function. Ground these pins.
BLOCK DIAGRAM
+VOUT_F 7
2
VOUT_S
6655 BD
6
BANDGAP
V
IN
1
4
SHDN
GND
GND
3,5,8
+VOUT_F 7
2
6655LN BD
NR
6
BANDGAP
VIN
1
4
SHDN
GND
GND
3,5,8
LTC6655
LTC6655LN
LTC6655/LTC6655LN
13
Rev. G
For more information www.analog.com
APPLICATIONS INFORMATION
Bypass and Load Capacitors
The LTC6655 voltage references require a 0.1µF or larger
input capacitor located close to the part to improve power
supply rejection. An output capacitor with a value between
2.7µF and 100µF is also required.
The output capacitor has a direct effect on the stability,
turn-on time and settling behavior. Choose a capacitor
with low ESR to insure stability. Resistance in series
with the output capacitor (ESR) introduces a zero in the
output buffer transfer function and could cause instabil-
ity. The 2.7μF to 100μF range includes several types of
capacitors that are readily available as through-hole and
surface mount components. It is recommended to keep
ESR less than or equal to 0.1Ω. Capacitance and ESR are
both frequency dependent. At higher frequencies capaci-
tance drops and ESR increases. To insure stable operation
the output capacitor should have the required values at
100kHz.
In order to achieve the best performance, caution should
be used when choosing a capacitor. X7R ceramic capaci-
tors are small, come in appropriate values and are rela-
tively stable over a wide temperature range. However,
for a low noise application X7R capacitors may not be
suitable since they may exhibit a piezoelectric effect. The
mechanical vibrations cause a charge displacement in the
ceramic dielectric and the resulting perturbation can look
like noise. If X7R capacitors are necessary, a thorough
bench evaluation should be completed to verify proper
performance.
For very low noise applications where every nanovolt
counts, film capacitors should be considered for their
low noise and lack of piezoelectric effects. Film capaci-
tors such as polyester, polystyrene, polycarbonate, and
polypropylene have good temperature stability. Additional
care must be taken as polystyrene and polypropylene have
an upper temperature limit of 85°C to 105°C. Above these
temperatures, the working voltages need to be derated
according to manufacturers specifications. Another type
of film capacitor is polyphenylene sulfide (PPS). These
devices work over a wide temperature range, are stable,
and have large capacitance values beyond 1μF. In general,
film capacitors are found in surface mount and leaded
packages. Table1 is a partial list of capacitor companies
and some of their available products.
In voltage reference applications, film capacitor lifetime is
affected by temperature and applied voltage. When poly-
ester capacitors are operated beyond their rated tempera-
tures (some capacitors are not rated for operation above
85°C) they need to be derated. Voltage derating is usually
accomplished as a ratio of applied voltage to rated volt-
age limit. Contact specific film capacitor manufacturers to
determine exact lifetime and derating information.
The lifetime of X7R capacitors is long, especially for refer-
ence applications. Capacitor lifetime is degraded by oper
-
ating near or exceeding the rated voltage, at high tem-
perature, with AC ripple or some combination of these.
Most reference applications have AC ripple only during
transient events.
Table1. Film Capacitor Companies
COMPANY DIELECTRIC AVAILABLE CAPACITANCE TEMPERATURE RANGE TYPE
Cornell Dublier Polyester 0.5µF to 10µF –55°C to 125°C DME
Dearborn Electronics Polyester 0.1µF to 12µF –55°C to 125°C 218P, 430P, 431P, 442P, and 410P
Tecate Polyester 0.01µF to 18µF –40°C to 105°C 901, 914, and 914D
Wima Polyester 10µF to 22µF –55°C to 100°C MKS 4, MKS 2-XL
Vishay Polyester 1000pF to 15µF –55°C to 125°C MKT1820
Vishay Polycarbonate 0.01µF to 10µF –55°C to 100°C MKC1862, 632P
Dearborn Electronics Polyphenylene Sulfide (PPS) 0.01µF to 15µF –55°C to 125°C 820P, 832P, 842P, 860P, and 880P
Wima Polyphenylene Sulfide (PPS) 0.01µF to 6.8µF –55°C to 140°C SMD-PPS
LTC6655/LTC6655LN
14
Rev. G
For more information www.analog.com
3.5V
3V
VIN
VOUT
50mV/DIV
C
OUT
= 3.3µF
6655 F04
400µs/DIV
APPLICATIONS INFORMATION
The choice of output capacitor also affects the bandwidth
of the reference circuitry and resultant noise peaking. As
shown in Figure1, the bandwidth is inversely proportional
to the value of the output capacitor.
Noise peaking is related to the phase margin of the out-
put buffer. Higher peaking generally indicates lower phase
margin. Other factors affecting noise peaking are tem-
perature, input voltage, and output load current.
Start-Up and Load Transient Response
Results for the transient response plots (Figures 3 to 8)
were produced with the test circuit shown in Figure2
unless otherwise indicated.
The turn-on time is slew limited and determined by the
short-circuit current, the output capacitor, and output volt-
age as shown in the equation:
tVC
I
ON OUT OUT
SC
=
For example, the LTC6655-2.5V, with a 3.3µF output
capacitor and a typical short-circuit current of 20mA, the
start-up time would be approximately:
25 33 10
002412
6
.•
.•
.
VF
Aµs=
The resulting turn-on time is shown in Figure3. Here the
output capacitor is 3.3µF and the input capacitor is 0.1µF.
Figure4 shows the output response to a 500mV step on
VIN. The output response to a current step sourcing and
sinking is shown in Figures 5 and 6, respectively.
Figure7 shows the output response as the current goes
from sourcing to sinking.
Shutdown Mode
The LTC6655 family of references can be shut down by
tying the SHDN pin to ground. There is an internal pull-up
resistor tied to this pin. If left unconnected this pin rises to
V
IN
and the part is enabled. Due to the low internal pull-up
current, it is recommended that the SHDN pin be pulled
high externally for normal operation to prevent accidental
LTC6655-2.5
100Ω
V
OUT
1,2 7
6
3,4,5,8
CIN
0.1µF
COUT
3.3µF
VGEN
6655 F02
0.5V
V
IN
3V
Figure1. Output Voltage Noise Spectrum
Figure2. Transient Load Test Circuit
Figure3. Start-Up Response
Figure4. Output Response with a 500mV Step On VIN
VIN
2V/DIV
VOUT
1V/DIV
C
OUT
= 3.3µF
6655 F03
200µs/DIV
COUT = 100µF
FREQUENCY (kHz)
60
NOISE VOLTAGE (nV√Hz)
100
0.01 10 100 1000
0
20
0.1 1
120
80
40
6655 F01
COUT = 2.7µF
COUT = 10µF
LTC6655/LTC6655LN
15
Rev. G
For more information www.analog.com
Figure5. Output Response with a 5mA Load Step Sourcing
Figure6. Output Response with 5mA Load Step Sinking
Figure8. Shutdown Response with 5mA Source Load
Figure7. Output Response Showing a
Sinking to Sourcing Transition
C
OUT
= 3.3µF
6655 F08
1ms/DIV
VOUT
1V/DIV
SHDN
2V/DIV
C
OUT
= 3.3µF
6655 F07
200µs/DIV
2mA
–2mA
IOUT
VOUT
10mV/DIV
APPLICATIONS INFORMATION
LTC6655-2.5
VIN
GND
SHDN
2N7002
VOUT_F
VOUT_S
TO µC
3V ≤ VIN ≤ 13.2V
VOUT
C1
F
C2
10µF
6655 F09
shutdown due to system noise or leakage currents. The
turn-on/turn-off response due to shutdown is shown in
Figure8.
To control shutdown from a low voltage source, a MOSFET
can be used as a pull-down device as shown in Figure9.
Note that an external resistor is unnecessary. A MOSFET
with a low drain-to-source leakage over the operating tem-
perature range should be chosen to avoid inadvertently
pulling down the SHDN pin. A resistor may be added from
SHDN to VIN to overcome excessive MOSFET leakage.
The SHDN thresholds have some dependency on VIN
and temperature as shown in the Typical Performance
Characteristics section. Avoid leaving SHDN at a voltage
between the thresholds as this will cause an increase in
supply current due to shoot-through current.
0mA
–5mA
IOUT
VOUT
10mV/DIV
COUT = 3.3µF 6655 F05
200µs/DIV
5mA
0mA
IOUT
VOUT
10mV/DIV
COUT = 3.3µF 6655 F06
200µs/DIV
Long-Term Drift
Long-term drift cannot be extrapolated from accelerated
high temperature testing. This erroneous technique gives
drift numbers that are wildly optimistic. The only way
long-term drift can be determined is to measure it over
the time interval of interest.
The LTC6655 long-term drift data was collected on 80
parts that were soldered into printed circuit boards similar
to a real world application. The boards were then placed
into a constant temperature oven with a TA = 35°C, their
outputs were scanned regularly and measured with an
8.5 digit DVM. Typical long-term drift is illustrated in
Figure10a. The hermetic LS8 package provides additional
stability as shown in Figure10b.
Figure9. Open-Drain Shutdown Circuit
LTC6655/LTC6655LN
16
Rev. G
For more information www.analog.com
APPLICATIONS INFORMATION
Hysteresis
Thermal hysteresis is a measure of change of output
voltage as a result of temperature cycling. Figure11
illustrates the typical hysteresis based on data taken from
the LTC6655-2.5. A proprietary design technique mini-
mizes thermal hysteresis.
Humidity Sensitivity
Plastic mould compounds absorb water. With changes in
relative humidity, plastic packaging materials change the
amount of pressure they apply to the die inside, which
can cause slight changes in the output of a voltage refer-
ence, usually on the order of 100ppm. The LS8 package is
hermetic, so it is not affected by humidity, and is therefore
more stable in environments where humidity may be a
DISTRIBUTION (ppm)
–90
NUMBER OF UNITS
20
25
50
15
10
–50 –10
–70 90
–30 10 70
30
110
5
0
30
6655 F11
HOURS
0
LONG-TERM DRIFT (ppm)
40
80
120
2000
6655 F10a
0
–40
–80 500 1000 1500 2500
4 TYPICAL UNITS
LTC6655-2.5
MS8 PACKAGE
HOURS
0
LONG-TERM DRIFT (ppm)
40
120
200
2400
6655 F10b
–40
–120
0
80
160
–80
–160
–200 600 1200 1800 3000
LTC6655-2.5
LS8 PACKAGE
concern. However, PC board material may absorb water
and apply mechanical stress to the LTC6655LS8. Proper
board materials and layout are essential.
For best stability, the PC board layout is critical. Change
in temperature and position of the PC board, as well as
aging, can alter the mechanical stress applied to compo-
nents soldered to the board. FR4 and similar materials
also absorb water, causing the board to swell. Even con-
formal coating or potting of the board does not always
eliminate this effect, though it may delay the symptoms
by reducing the rate of absorption.
Power and ground planes should be omitted under the
voltage reference IC for best stability. Figure12a shows
a tab cut through the PC board on three sides of an
LTC6655, which significantly reduces stress on the IC,
as described in Application Note 82. For even better per-
formance, Figure12b shows slots cut through the PC
board on all four sides. The slots should be as long as
possible, and the corners just large enough to accom-
modate routing of traces. It has been shown that for PC
boards designed in this way, humidity sensitivity can
be reduced to less than 35ppm for a change in relative
humidity of approximately 60%. Mounting the reference
near the center of the board, with slots on four sides, can
further reduce the sensitivity to less than 10ppm.
An additional advantage of slotting the PC board is that the
LTC6655 is thermally isolated from surrounding circuitry.
This can help reduce thermocouple effects and improve
accuracy.
Figure10a. Long-Term Drift MS8
Figure10b. Long-Term Drift LS8
Figure11. Hysteresis Plot –40°C to 125°C
LTC6655/LTC6655LN
17
Rev. G
For more information www.analog.com
APPLICATIONS INFORMATION
maximum ambient temperature limits for differing V
IN
and
load conditions using a maximum junction temperature
of 125°C.
PC Board Layout
The LTC6655 reference is a precision device that is fac-
tory trimmed to an initial accuracy of ±0.025%, as shown
in the Typical Performance Characteristics section. The
mechanical stress caused by soldering parts to a printed
circuit board may cause the output voltage to shift and
the temperature coefficient to change.
Power Dissipation
Power dissipation for the LTC6655 depends on VIN and
load current. Figure13 illustrates the power consump-
tion versus VIN under a no-load and 5mA load condition
at room temperature for the LTC6655-2.5. Other voltage
options display similar behavior.
The MSOP8 package has a thermal resistance (θJA)
equal to 300°C/W. Under the maximum loaded condition,
the increase in die temperature is over 35°C. If operated
at these conditions with an ambient temperature of 125°C,
the absolute maximum junction temperature rating of
the device would be exceeded. Although the maximum
junction temperature is 150°C, for best performance it
is recommended to not exceed a junction temperature
of 125°C. The plot in Figure14 shows the recommended
VIN (V)
0
105
115
125
12
6655 F14
95
85
3 6 9 15
75
65
55
MAXIMUM AMBIENT
OPERATING TEMPERATURE (°C)
NO LOAD
5mA LOAD
VIN (V)
0
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
6655 F13
510
NO LOAD
15
POWER (W)
5mA LOAD
LS8
6655 F12a
LS8
6655 F12b
Figure12a. 3-Sided PCB Tab Cutout
Figure12b. 4-Sided PCB Cutout
Figure13. LTC6655-2.5 Power Consumption
Figure14. LTC6655-2.5 Maximum
Ambient Operating Temperature
LTC6655/LTC6655LN
18
Rev. G
For more information www.analog.com
APPLICATIONS INFORMATION
To reduce the effects of stress-related shifts, mount the
reference near the short edge of a printed circuit board
or in a corner. In addition, slots can be cut into the board
on two sides of the device to reduce mechanical stress.
A thicker and smaller board is stiffer and less prone to
bend. Finally, use stress relief, such as flexible standoffs,
when mounting the board.
Additional precautions include making sure the solder
joints are clean and the board is flux free to avoid leak-
age paths. Sample PCB layouts are shown in Figures 15a
and 15b.
The VOUT_S pin sinks 2mA, which is unusual for a Kelvin
connection. However, this is required to achieve the
exceptional low noise performance. The I R drop on the
VOUT_S line directly affects load regulation. The VOUT_S
trace should be as short and wide as practical to minimize
series resistance The VOUT_S trace adds error as RTRACE
2mA, so a 0.1Ω trace adds 200µV error. The VOUT_F pin
is not as important as the VOUT_S pin in this regard. An
I R drop on the VOUT_F pin increases the minimum supply
voltage when sourcing current, but does not directly affect
load regulation. For light loading of the output (maximum
output current <100µA), VOUT_S should be tied to VOUT_F
by the shortest possible path to reduce errors caused by
resistance in the sense trace.
Careful attention to grounding is also important, espe-
cially when sourcing current. The return load current can
produce an I R drop causing poor load regulation. Use
a “star” ground connection and minimize the ground to
load metal resistance. Although there are several pins that
are required to be connected to ground, Pin 4 is the actual
ground for return current.
Optimal Noise Performance
The LTC6655 offers extraordinarily low noise for a band-
gap referenceonly 0.25ppm in 0.1Hz to 10Hz. As a
result, system noise performance may be dominated by
system design and physical layout.
Some care is required to achieve the best possible noise
performance. The use of dissimilar metals in compo-
nent leads and PC board traces creates thermocouples.
Variations in thermal resistance, caused by uneven air
flow, create differential lead temperatures, thereby caus-
ing thermoelectric voltage noise at the output of the refer-
ence. Minimizing the number of thermocouples, as well
as limiting airflow, can substantially reduce these errors.
Additional information can be found in Analog Devices
Application Note 82. Position the input and load capaci-
tors close to the part. Although the LTC6655 has a DC
PSRR of over 100dB, the power supply should be as
stable as possible to guarantee optimal performance. A
plot of the 0.1Hz to 10Hz low frequency noise is shown
in the Typical Performance Characteristics section. Noise
6655 F15a
GND VOUT
VIN
6655 F15b
GND
V
OUT
VIN
Load Regulation
To take advantage of the V
OUT
Kelvin force/sense pins,
the VOUT_S pin should be connected separately from the
VOUT_F pin as shown in Figure16.
LTC6655-2.5
2
7
2mA LOAD
STAR
MINIMIZE RESISTANCE
OF METAL
6
4
6655 F16
+
Figure15a. Sample LTC6655 PCB Layout
Figure15b. Sample LTC6655LN PCB Layout
Figure16. Kelvin Connection for Good Load Regulation
LTC6655/LTC6655LN
19
Rev. G
For more information www.analog.com
performance can be further improved by wiring several
LTC6655s in parallel as shown in the Typical Applications
section. With this technique the noise is reduced by N,
where N is the number of LTC6655s in parallel.
Noise Specification
Noise in any frequency band is a random function based
on physical properties such as thermal noise, shot noise,
and flicker noise. The most precise way to specify a ran-
dom error such as noise is in terms of its statistics, for
example as an RMS value. This allows for relatively simple
maximum error estimation, generally involving assump-
tions about noise bandwidth and crest factor. Unlike wide-
band noise, low frequency noise, typically specified in
a 0.1Hz to 10Hz band, has traditionally been specified
in terms of expected error, illustrated as peak-to-peak
error. Low frequency noise is generally measured with
an oscilloscope over a 10 second time frame. This is a
pragmatic approach, given that it can be difficult to mea-
sure noise accurately at low frequencies, and that it can
also be difficult to agree on the statistical characteristics
of the noise, since flicker noise dominates the spectral
density. While practical, a random sampling of 10 second
intervals is an inadequate method for representation of
low frequency noise, especially for systems where this
noise is a dominant limit of system performance. Given
the random nature of noise, the output voltage may be
observed over many time intervals, each giving different
results. Noise specifications that were determined using
this method are prone to subjectivity, and will tend toward
a mean statistical value, rather than the maximum noise
that is likely to be produced by the device in question.
Because the majority of voltage reference data sheets
express low frequency noise as a typical number, and as it
tends to be illustrated with a repeatable plot near the mean
of a distribution of peak-to-peak values, the LTC6655 data
sheet provides a similarly defined typical specification in
order to allow a reasonable direct comparison against
similar products. Data produced with this method gener-
ally suggests that in a series of 10 second output voltage
measurements, at least half the observations should have
a peak-to-peak value that is below this number. For exam-
ple, the LTC6655-2.5 measures less than 0.25ppmP-P in
at least 50% of the 10 second observations.
APPLICATIONS INFORMATION
As mentioned above, the statistical distribution of noise
is such that if observed for long periods of time, the
peak error in output voltage due to noise may be much
larger than that observed in a smaller interval. The likely
maximum error due to noise is often estimated using
the RMS value, multiplied by an estimated crest factor,
assumed to be in the range of 6 to 8.4. This maximum
possible value will only be observed if the output volt-
age is measured for very long periods of time. Therefore,
in addition to the common method, a more thorough
approach to measuring noise has been used for the
LTC6655 (described in detail in Analog Devicess AN124)
that allows more information to be obtained from the
result. In particular, this method characterizes the noise
over a significantly greater length of time, resulting in a
more complete description of low frequency noise. The
peak-to-peak voltage is measured for 10 second intervals
over hundreds of intervals. In addition, an electronic peak-
detect circuit stores an objective value for each interval.
The results are then summarized in terms of the fraction
of measurement intervals for which observed noise is
below a specified level. For example, the LTC6655-2.5
measures less than 0.27ppmP-P in 80% of the measure-
ment intervals, and less than 0.295ppmP-P in 95% of
observation intervals. This statistical variation in noise
is illustrated in Table2 and Figure18. The test circuit is
shown in Figure17.
Table2.
Low Frequency Noise (ppmP-P)
50% 0.246
60% 0.252
70% 0.260
80% 0.268
90% 0.292
This method of testing low frequency noise is superior to
more common methods. The results yield a comprehen-
sive statistical description, rather than a single observa-
tion. In addition, the direct measurement of output voltage
over time gives an actual representation of peak noise,
rather than an estimate based on statistical assumptions
such as crest factor. Additional information can be derived
from a measurement of low frequency noise spectral den-
sity, as shown in Figure19.
LTC6655/LTC6655LN
20
Rev. G
For more information www.analog.com
APPLICATIONS INFORMATION
+
100k100k
SHIELD
SHIELDED CAN
1N4697
10V
AC LINE GROUND
1300µF
9V
100k*
10Ω*
+
1k* 200Ω*
2k
450Ω* 900Ω*
15V
15V
–15V
–15V
1µF
1µF A1
LT1012
A2
LT1097
6655 F17
– INPUT
Q1
5
* = 1% METAL FILM
** = 1% WIREWOUND, ULTRONIX105A
= 1N4148
= 2N4393
= 1/4 LTC202
SEE APPENDIX C FOR POWER, SHIELDING
AND GROUNDING SCHEME
= TANTALUM,WET SLUG
ILEAK < 5nA
SEE TEXT/APPENDIX B
= POLYPROPELENE
A4 330µF OUTPUT CAPACITORS = <200nA LEAKAGE
AT 1VDC AT 25°C
Q1, Q2 = THERMALLY MATED
2SK369 (MATCH VGS 10%)
OR LSK389 DUAL
THERMALLY LAG
SEE TEXT
A = 104
LOW NOISE
PRE-AMP
REFERENCE
UNDER TEST
0.15µF
750Ω*
10k
–15V
Q3
2N2907
Q2 0.022µF
1µF
**1.2k
SD
LTC6655
2.5V
IN S
F
+
1µF
0.1µF
124k* 124k*
+
A3
LT1012
1M*
10k*
100Ω*330Ω*
IN OUT
ROOT-SUM-SQUARE
CORRECTION
SEE TEXT
330µF
16V
330µF
16V
+
+
330µF
16V
330µF
16V
+
A4
LT1012
0.1µF
0.1µF
10k
A = 100 AND
0.1Hz TO 10Hz FILTER
1µF
RST
+
A5
1/4 LT1058
+A7
1/4 LT1058
1k
PEAK TO PEAK
NOISE DETECTOR
O TO 1V =
O TO 1µV
+ PEAK
4.7k
P
P
1µF
RST
15V
0.1µF
+
A6
1/4 LT1058
+A8
1/4 LT1058
1k
– PEAK
4.7k
10k
100k
100k
P
T
T
+
DVM
TO OSCILLOSCOPE INPUT
VIA ISOLATED PROBE,
1V/DIV = 1µV/DIV,
REFERRED TO INPUT,
SWEEP = 1s/DIV
FROM OSCILLOSCOPE
SWEEP GATE OUTPUT
VIA ISOLATION
PULSE TRANSFORMER
RESET PULSE
GENERATOR
0.22µF
C2 RC2
+15V +15V
CLR2
+15V
74C221
RST = Q2 +V
+15V
A2
B2
10k
BAT-85
BAT-85
10k
+
+
0.005µF
–15V 10k
0.005µF
Figure17. Detailed Noise Test Circuitry. See Application Note 124
LTC6655/LTC6655LN
21
Rev. G
For more information www.analog.com
APPLICATIONS INFORMATION
It should be noted from Figure19 that the LTC6655 has
not only a low wideband noise, but an exceptionally low
flicker noise corner of 1Hz! This substantially reduces
low frequency noise, as well as long-term variation in
peak noise.
Noise Reduction and the NR Pin
The LTC6655LN provides access to an internal circuit
node preceding the output buffer so that dynamic per-
formance is not affected. This facilitates the use of a low
pass filter (LPF) to reduce wide band noise.
The Block Diagram section illustrates the LTC6655LN
architectural differences. The Low Noise version trades
out the Kelvin sense pin for the NR pin. Figure20 shows
PEAK-TO-PEAK NOISE (nV)
450
0
NUMBER OF OBSERVATIONS
5
15
20
25
35
6655 F18
10
30
650 950
550 750 850
FREQUENCY (Hz)
0.1
0
NOISE VOLTAGE (nV/√Hz)
120
160
200
1 10 100
6655 F19
80
40
the typical application circuit with a capacitor on the NR
pin. When a capacitor is placed between NR and ground,
a LPF is formed.
The LPF reduces the wide band noise from the bandgap
circuit before it reaches the output buffer. This is very
different from placing a LPF after the reference. A LPF
following the buffer would cause poor load regulation and
slow down the response affecting dynamic performance.
With the LPF internally placed before the low noise buffer,
the buffer response is not impeded by the LPF. Placing
anything between the output buffer and the converter will
likely add noise or cause an error such as a load regulation
error, or a dynamic response error.
The value of resistor R3 is slightly different depending
on the voltage option. Tables 3 and 4 below list the resis-
tance values of R3 for the three available voltage options
along with the 3dB cutoff frequencies for four decades of
capacitor values.
Table3. Resistance Value of R3 for the Three Voltage Options
2.500 4.096 5.000 V
R3 ±15% 5305 4233 3969 Hz
Table4. The 3dB Cutoff Frequencies for Different Values of CNR
CNR 2.500 4.096 5.000 V
0.1µF 5305 4233 3969 Hz
1µF 531 423 397 Hz
10µF 53 423 397 Hz
100µF 5.3 4.2 4.0 Hz
R3
R2
R1
2
7
3, 4, 5, 8
6
2.7µF
V
IN
LTC6655LN
V
OUT
BANDGAP
GND
NR
C
NR
+
6655 F20
Figure18. LTC6655-2.5 Low Frequency Noise Histogram
Figure19. LTC6655-2.5 Low Frequency Noise Spectrum
Figure20. The LTC6655LN Typical Application Circuit
LTC6655/LTC6655LN
22
Rev. G
For more information www.analog.com
APPLICATIONS INFORMATION
Internally the NR pin connects to a sensitive node. Any
leakage to this pin can cause excessive shift and drift.
Leakage of 10nA will cause a shift of 9μV in VOUT. It is
recommended to use high quality, low leakage capacitors.
A guard ring may also be employed to control leakage.
The nominal pin voltage of NR is 1.000V or 1.024V.
The LTC6655LN-2.5 output noise for three conditions is
shown in Figure21. Without a capacitor on the NR pin the
wideband noise extends past 10kHz at 50nV/√Hz. When
a 1μF or 100μF capacitor is included, the wideband noise
is reduced to 16nV/√Hz. The noise corner frequency pro-
duced by the LPF decreases as the capacitor increases.
A plot of the total integrated noise for the same three
conditions is shown in Figure22. A large value of C
NR
can
have a large impact on the total integrated noise.
Start-Up with CNR
The CNR capacitor will require time to charge. The
LTC6655 has an initial accuracy of 0.025%. A single RC
time constant circuit will require approximately 8.3τ to
reach 0.025% settling. For example, assume R3 = 300Ω
and CNR = 10μF; the time constant is R C = 300Ω 10μF
= 3ms. For 0.025% settling multiply 8.3 3ms to get
24.9ms. This is the time required for the signal at the NR
pin to settle to 0.025% of its final value. The output buffer
will follow the NR pin signal with some delay depending
on the capacitive loading on the VOUT pin.
Example start-up measurements are shown in Figures 23a,
23b, and 23c. Figure23a shows the difference between
using no capacitor and a 1μF capacitor on the NR pin.
Figures 23b and 23c show the start-up with CNR = 10μF
and 100μF, respectively.
IR Reflow Shift
The mechanical stress of soldering a part to a board can
cause the output voltage to shift. Moreover, the heat of
an IR reflow or convection soldering oven can also cause
the output voltage to shift. The materials that make up a
semiconductor device and its package have different rates
of expansion and contraction. After a part undergoes the
extreme heat of a lead-free IR reflow profile, like the one
shown in Figure24, the output voltage shifts. After the
device expands, due to the heat, and then contracts, the
stresses on the die have changed position. This shift is
similar, but more extreme than thermal hysteresis.
Experimental results of IR reflow shift are shown below
in Figure25. These results show only shift due to reflow
and not mechanical stress.
C
OUT
= 2.7µF
C
NR
= 0.1µF
C
NR
= 1µF
C
NR
= 10µF
C
NR
= 100µF
FREQUENCY (kHz)
0.01
0.1
1
10
100
1k
0
10
20
30
40
50
60
70
NOISE VOLTAGE (nV/√
Hz
)
6655 F21
C
OUT
= 2.7µF
C
NR
= 0.1µF
C
NR
= 1µF
C
NR
= 10µF
C
NR
= 100µF
FREQUENCY (kHz)
0.01
0.1
1
10
0
1
2
3
4
5
INTEGRATED NOISE (µV
RMS
)
6655 F22
Figure21. The LTC6655LN-2.5 Output Voltage
Noise Spectrum Using the CNR Capacitor
Figure22. Total Integrated Noise of the
LTC6655LN-2.5 Using the CNR Capacitor
LTC6655/LTC6655LN
23
Rev. G
For more information www.analog.com
MINUTES
0
TEMPERATURE (°C)
150
225
8
6655 F24
75
024610
300
T = 150°C
TS = 190°C
TL = 217°C
TP = 260°C
380s
tP
30s
tL
130s
40s
120s
RAMP
DOWN
TS(MAX) = 200°C
RAMP TO
150°C
OUTPUT VOLTAGE SHIFT DUE TO IR REFLOW (%)
–0.029
0
NUMBER OF UNITS
2
4
6
–0.023 –0.017 –0.005–0.011
8
1
3
5
7
6655 F25
APPLICATIONS INFORMATION
C
OUT
= 2.7µF
C
NR
= OPEN
C
NR
= 1µF
1ms/DIV
V
IN
5V/DIV
V
NR
500mV/DIV
V
OUT
1V/DIV
6655 F23a
C
OUT
= 2.7µF
C
NR
= 10µF
10ms/DIV
V
IN
5V/DIV
V
NR
500mV/DIV
V
OUT
1V/DIV
6655 F23b
C
OUT
= 2.7µF
C
NR
= 100µF
50ms/DIV
V
IN
5V/DIV
V
NR
500mV/DIV
V
OUT
1V/DIV
6655 F23c
Figure23a. CNR = Open and 10µF
Figure23b. CNR = 10µF
Figure23c. CNR = 100µF
Figure23. The LTC6655LN-2.5 Start-Up Response with a) No
CNR Capacitor and CNR = 1µF, b) CNR = 10µF, and c) CNR = 100µF
Figure24. Lead-Free Reflow Profile
Figure25. Output Voltage Shift Due to IR Reflow
LTC6655/LTC6655LN
24
Rev. G
For more information www.analog.com
TYPICAL APPLICATIONS
LTC6655-2.5
GND
SHDN
VIN
VOUT_S
VOUT_F VOUT
C1
0.1µF
R1
BZX84C12
4V TO 30V
C2
10µF
6655 TA02
Extended Supply Range Reference Extended Supply Range Reference
LTC6655-2.5
GND
VIN SHDN
VOUT_S
VOUT_F VOUT
6V TO 80V
ON SEMI
MMBT5551
C1
0.1µF
R1
100k
R2
4.7k
BZX84C12
C2
10µF
0.1µF
6655 TA03
Boosted Output Current
LTC6655-2.5
GND
VIN SHDN
VOUT_S
VOUT + 1.8V TO 13.2V
VOUT_F VOUT
C1
F
C3
0.1µF
R1
220Ω
C2
10µF
6655 TA04
2N2905 35mA MAX
R2
1k
C4
F
Q1
2N2222
IMAX SET BY NPN
VOUT
6655 TA05
LTC6655-2.5
GND
SHDN
VIN VOUT_S
VOUT_F
C2
4.7µF
C1
0.1µF
4V TO 13.2V
Boosted Output Current
LTC6655/LTC6655LN
25
Rev. G
For more information www.analog.com
TYPICAL APPLICATIONS
Output Voltage Boost
LTC6655-2.5
GND
SHDN
VIN
VOUT_S
R
R = 0k to 1k
VOUT_F VOUT
2.5V TO 4.5V
C1
F
VIN
VOUT + 0.5V TO 13.2V C2
10µF
6655 TA07
VOUT = VOLTAGE OPTION + 0.002 • R
THIS EXAMPLE USES 2.5V AS THE
VOLTAGE OPTION
FOR R USE A POTENTIOMETER THAT
CAN HANDLE 2mA, IS LOW NOISE AND
HAS A LOW TEMPERATURE COEFFICIENT
Low Noise Precision Voltage Boost Circuit
LTC6655-2.5 LT1677
GND
SHDN
VIN
VOUT_S
VOUT_F VOUT
5V
C1
F
VIN
VOUT + 0.5V TO 13.2V C2
10µF
R1
10k
R3
5k
VIN
6655 TA08
VOUT = VOLTAGE OPTION • (1 + R1/R2)
THIS EXAMPLE USES 2.5V AS THE
VOLTAGE OPTION
FOR R1, R2 AND R3 USE LT5400-1.
WITH A PRECISION ARRAY THE
MATCHING AND LOW TC WILL HELP
PRESERVE LOW DRIFT. R3 = R1||R2
R3 IS MADE WITH TWO PRALLEL 10k
RESISTORS, AVAILABLE IN THE
LT5400-1
+
RLOAD
R2
10k
+
Ultralow 1/f Noise Reference Buffer
4.7µF
4.7µF
49.9k
1k
4.7µF
VIN
6V ±5%
OUT
IN
SET
LT3042
VOUT = 5V
IOUT(MAX)
200mA
100µA
OUTS
EN/UV
ILIM
GND
PG
PGFB
6655 TA08
+
10µF
LTC6655-5
1,2
6,7
3,4,5,8
LTC6655/LTC6655LN
26
Rev. G
For more information www.analog.com
TYPICAL APPLICATIONS
Low Noise Statistical Averaging Reference
eN = eN/√N; Where N is the Number of LTC6655s in Parallel
6655 TA09a
LTC6655-2.5
R1
32.4Ω
GND
SHDN
VIN
VOUT
VOUT_S
VOUT_F
C2
2.7µF
C1
0.1µF
LTC6655-2.5
R2
32.4Ω
GND
SHDN
VIN VOUT_S
VOUT_F
C4
2.7µF
C3
0.1µF
LTC6655-2.5
R3
32.4Ω
GND
SHDN
VIN VOUT_S
VOUT_F
C6
2.7µF
C5
0.1µF
LTC6655-2.5
R4
32.4Ω
GND
SHDN
VIN VOUT_S
VOUT_F
C8
2.7µF
C7
0.1µF
C9
4.7µF
3V TO
13.2V
200nV/
DIV
6655 TA09b
1s/DIV
320nVP-P
0.1Hz to 10Hz
Low Frequency Noise (0.1Hz to 10Hz)
with Four LTC6655-2.5 in Parallel
LTC6655/LTC6655LN
27
Rev. G
For more information www.analog.com
PACKAGE DESCRIPTION
MSOP (MS8) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
LTC6655/LTC6655LN
28
Rev. G
For more information www.analog.com
PACKAGE DESCRIPTION
7
8
1
3
4
2
2.00 REF
R0.20 REF
6
5
7
8
6
5
1
2
3
4
4.20 ±0.10
4.20 SQ ±0.10
2.54 ±0.15
1.00 × 7 TYP
0.64 × 8 TYP
LS8 0113 REV B
R0.20 REF
0.95 ±0.10
1.45 ±0.10
0.10 TYP0.70 TYP
1
4
7
8
6
1.4
0.5
1.50 ±0.15
2.50 ±0.15
2.54 ±0.15
0.70 ±0.05 × 8
PACKAGE OUTLINE
0.5
5.00 SQ ±0.15
5.00 SQ ±0.15
5.00 SQ ±0.15
5.80 SQ ±0.15
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS PACKAGE DO NOT INCLUDE PLATING BURRS
PLATING BURRS, IF PRESENT, SHALL NOT EXCEED 0.30mm ON ANY SIDE
4. PLATING—ELECTO NICKEL MIN 1.25UM, ELECTRO GOLD MIN 0.30UM
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(SEE NOTE 5)
2
3
LS8 Package
8-Pin Leadless Chip Carrier (5mm × 5mm)
(Reference LTC DWG # 05-08-1852 Rev B)
ABCDEF
XYY ZZ
e4
Q12345
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1
1.4
LTC6655/LTC6655LN
29
Rev. G
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 02/10 Voltage Options Added (1.250, 2.048, 3.000, 3.300, 4.096, 5.000), Reflected Throughout the Data Sheet 1 to 22
B 12/12 Addition of 5mm x 5mm hermetic LS8 package
Update to Electrical Characteristics to include LS8 package
Addition of long-term drift and hysteresis plots for LS8 package
Addition of Humidity Sensitivity information
Addition of Related Parts
1, 2, 3, 12, 22
3, 4
13
13
22
C 06/13 TJMAX changed from 125°C to 150°C
Addition of 5V Option in the LS8 package
Addition of PC board layout guidance
2
3, 4
14, 15
D 01/14 Addition of 4.096V option in the LS8 package
Changed Line Regulation Condition to SHDN = 2V
Updated PC board layout guidance
Corrected Polarity of 9V battery in Figure17
Updated captions for Figures 10, 12, 18
Updated note for circuit “Low Noise Precision Voltage Boost Circuit”
3, 4
4
14
18
14, 15, 19
21
E 9/14 Corrected LS8-4.096 part marking 3
F 08/17 Trademark information updated.
Web links updated.
Addition of Ultralow 1/f Noise Reference Buffer schematic.
1
3, 23, 24
21
G 02/19 Addition of LTC6655LN Specifications and Features. 1 to 6, 11, 12,
18, 22, 23
LTC6655/LTC6655LN
30
Rev. G
For more information www.analog.com
ANALOG DEVICES, INC. 2009-2019
2/19
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
Low Noise Precision 24-Bit Analog-to-Digital Converter Application
–2.5V
7.5V
SPI INTERFACE
THERMOCOUPLE
10µF
0.1µF
LTC6655
VIN
SHDN
VOUT_F
VOUT_S
GND GND
3,5,8 4
1
2
6
7
VCC
5V
6655 TA10
1nF
1nF
0.01µF0.01µF
50Ω
2.5k
50Ω
2.5k
+
+
1/2
LTC6241
1/2
LTC6241
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
COM
REF+
REF
GND
GND
GND
GND
GND
GND
GND
MUXOUTN
ADCINN
MUXOUTP
ADCINP
SDI
SCK
SDO
CS
BUSY
EXT
fO
LTC2449
5k
RREF
400Ω
VREF
RTD
VREF
PART NUMBER DESCRIPTION COMMENTS
LT
®
1236 Precision Low Drift Low Noise Reference 0.05% Max, 5ppm/°C Max, 1ppm (Peak-to-Peak) Noise
LT1236LS8 Precision Low Noise, Low Profile Hermetic Voltage Reference 0.05% Max, 5ppm/°C Max, 0.3µVP-P Noise, 5mm × 5mm Hermetic
Package
LT1460 Micropower Series References 0.075% Max, 10ppm/°C Max, 20mA Output Current
LT1461 Micropower Series Low Dropout 0.04% Max, 3ppm/°C Max, 50mA Output Current
LT1790 Micropower Precision Series References 0.05% Max, 10ppm/°C Max, 60mA Supply, SOT23 Package
LT6650 Micropower Reference with Buffer Amplifier 0.5% Max, 5.6µA Supply, SOT23 Package
LTC6652 Precision Low Drift Low Noise Reference 0.05% Max, 5ppm/°C Max, –40°C to 125°C, MSOP8
LT6660 Tiny Micropower Series Reference 0.2% Max, 20ppm/°C Max, 20mA Output Current, 2mm × 2mm DFN
LTC6652LS8 High Precision, Buffered Voltage Reference Family in
5mm × 5mm Hermetic QFN Package 0.05% Max Initial Error, 5ppm/°C Max Drift, Shutdown Current <2µA,
–40°C to 125°C Operation
LT6654LS8 Precision, Low Noise, High Output Drive Voltage Reference
Family in 5mm × 5mm Hermetic QFN Package 1.6ppm Peak-to-Peak Noise (0.1Hz to 10Hz, Sink/Source ±10mA,
5ppm/°C Max Drift, –40°C to 125°C Operation

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