iCE40™ LP/HX Family Datasheet

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Datasheet

iCE40™ LP/HX Family Data Sheet
DS1040 Version 3.4, October 2017
www.latticesemi.com 1-1 DS1040 Introduction_01.7
March 2017 Data Sheet DS1040
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
Flexible Logic Architecture
Five devices with 384 to 7,680 LUT4s and
10 to 206 I/Os
Ultra Low Power Devices
Advanced 40 nm low power process
As low as 21 µA standby power
Programmable low swing differential I/Os
Embedded and Distributed Memory
Up to 128 kbits sysMEM™ Embedded Block
RAM
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
High Current LED Drivers
Three High Current Drivers used for three differ-
ent LEDs or one RGB LED
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8
LVDS25E, subLVDS
Schmitt trigger inputs, to 200 mV typical
hysteresis
Programmable pull-up mode
Flexible On-Chip Clocking
Eight low-skew global clock resources
Up to two analog PLLs per device
Flexible Device Configuration
SRAM is configured through:
Standard SPI Interface
Internal Nonvolatile Configuration Memory
(NVCM)
Broad Range of Package Options
WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA,
and csBGA package options
Small footprint package options
As small as 1.40 mm x 1.48 mm
Advanced halogen-free packaging
iCE40 LP/HX Family Data Sheet
Introduction
Table 1-1. iCE40 Family Selection Guide
Part Number LP384 LP640 LP1K LP4K LP8K HX1K HX4K HX8K
Logic Cells (LUT + Flip-Flop) 384 640 1,280 3,520 7,680 1,280 3,520 7,680
RAM4K Memory Blocks 0 8 16 20 32 16 20 32
RAM4K RAM bits 0 32K 64K 80K 128K 64K 80K 128K
Phase-Locked Loops (PLLs) 0 0 1122221122
Maximum Programmable I/O Pins 63 25 95 167 178 95 95 206
Maximum Differential Input Pairs 8 3 122023111226
High Current LED Drivers 03300000
Package Code Programmable I/O: Max Inputs (LVDS25)
16 WLCSP
(1.40 mm x 1.48 mm, 0.35
mm)
SWG16 10(0)110(0)1
32 QFN
(5 mm x 5 mm, 0.5 mm) SG32 21(3)
36 ucBGA
(2.5 mm x 2.5 mm, 0.4 mm) CM36 25(3) 25(3)1
49 ucBGA
(3 mm x 3 mm, 0.4 mm) CM49 37(6) 35(5)1
81 ucBGA
(4 mm x 4 mm, 0.4 mm) CM81 63(8) 63(9)263(9)2
81 csBGA
(5 mm x 5 mm, 0.5 mm) CB81 62(9)1
1-2
Introduction
iCE40 LP/HX Family Data Sheet
Table 1-1. iCE40 Family Selection Guide (continued)
Introduction
The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680
Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded
Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features
allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer
High-Current drivers that are ideal to drive three white LEDs, or one RGB LED.
The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several fea-
tures such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These
features help manage static and dynamic power consumption, resulting in low static power for all members of the
family. The iCE40 devices are available in two versions – ultra low power (LP) and high performance (HX) devices.
The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space
saving 1.40x1.48 mm WLCSP to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities, package
and I/O options, along with other key parameters.
The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a
“per-pin” basis.
The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can
also configure themselves from external SPI Flash or be configured by an external master such as a CPU.
Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40
family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use
the synthesis tool output along with the user-specified preferences and constraints to place and route the design in
the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing ver-
ification.
Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,
licensed free of charge, optimized for the iCE40 FPGA family. By using these configurable soft core IP cores as
standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productiv-
ity.
84 QFN
(7 mm x 7 mm, 0.5 mm) QN84 67(7)1
100 VQFP
(14 mm x 14 mm, 0.5 mm) VQ100 72(9)1
121 ucBGA
(5 mm x 5 mm, 0.4 mm) CM121 95(12) 93(13) 93(13)
121 csBGA
(6 mm x 6 mm, 0.5 mm) CB121 92(12)
121 caBGA
(9 mm x 9 mm, 0.8 mm) BG121 93(13) 93(13)
132 csBGA
(8 mm x 8 mm, 0.5 mm) CB132 95(11) 95(12) 95(12)
144 TQFP
(20 mm x 20 mm, 0.5 mm) TQ144 96(12) 107(14)
225 ucBGA
(7 mm x 7 mm, 0.4 mm) CM225 178(23) 178(23) 178(23)
256-ball caBGA
(14 mm x 14 mm, 0.8 mm) CT256 206(26)
1. No PLL available on the 16 WLCSP, 36 ucBGA, 81 csBGA, 84 QFN and 100 VQFP packages.
2. Only one PLL available on the 81 ucBGA package.
3. High Current I/Os only available on the 16 WLCSP package.
www.latticesemi.com 2-1 DS1040 Architecture_01.4
March 2017 Data Sheet DS1040
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Architecture Overview
The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Non-
volatile Programmable Configuration Memory (NVCM) and blocks of sysMEM™ Embedded Block RAM (EBR) sur-
rounded by Programmable I/O (PIO). Figure 2-1 shows the block diagram of the iCE40LP/HX1K device.
Figure 2-1. iCE40LP/HX1K Device, Top View
The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional
grid with rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the
periphery of the device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register
functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of
interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The
place and route software tool automatically allocates these routing resources.
In the iCE40 family, there are up to four independent sysIO banks. Note on some packages VCCIO banks are tied
together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this
document. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as
RAM, ROM or FIFO.
The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have mul-
tiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the
clocks.
Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40
includes on-chip, Nonvolatile Configuration Memory (NVCM).
Programmable
Logic Block (PLB)
I/O Bank 0
I/O Bank 3
Programmable Interconnect
Programmable Interconnect
Programmable Interconnect
I/O Bank 1
I/O Bank 2
NVCM
Flip-flop with Enable
and Reset Controls
Non-volatile
Configuration Memory
(NVCM)
Phase-Locked
Loop
Carry Logic
4-Input Look-up
Table (LUT4)
8 Logic Cells = Programmable Logic Block
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
4 kbit RAM 4 kbit RAM
PLB
PLB
PLB
PLB
PLB
PLL
SPI
Bank
iCE40 LP/HX Family Data Sheet
Architecture
2-2
Architecture
iCE40 LP/HX Family Data Sheet
PLB Blocks
The core of the iCE40 device consists of Programmable Logic Blocks (PLB) which can be programmed to perform
logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 2-2.
Each LC contains one LUT and one register.
Figure 2-2. PLB Block Diagram
Logic Cells
Each Logic Cell includes three primary logic elements shown in Figure 2-2.
A four-input Look-Up Table (LUT4) builds any combinational logic function, of any complexity, requiring up to
four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and cas-
cade multiple LUT4s to create wider logic functions.
A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic func-
tions. Each DFF also connects to a global reset signal that is automatically asserted immediately following
device configuration.
Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtractors,
comparators, binary counters and some wide, cascaded logic functions.
Table 2-1. Logic Cell Signal Descriptions
Function Type Signal Names Description
Input Data signal I0, I1, I2, I3 Inputs to LUT4
Input Control signal Enable Clock enable shared by all LCs in the PLB
Input Control signal Set/Reset1 Asynchronous or synchronous local set/reset shared by all LCs in
the PLB.
Input Control signal Clock Clock one of the eight Global Buffers, or from the general-purpose
interconnects fabric shared by all LCs in the PLB
Input Inter-PLB signal FCIN Fast carry in
Output Data signals O LUT4 or registered output
Output Inter-PFU signal FCOUT Fast carry out
1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
= Statically defined by configuration program
LUT4
Carry Logic
Logic Cell
SR
EN
DQ
DFF
Flip-flop with
optional enable and
set or reset controls
Four-input
Look-Up Table
(LUT4)
Clock
Enable
FCOUT
FCIN
Set/Reset
Shared Block-Level Controls
Programmable Logic
Block (PLB)
8 Logic Cells (LCs)
I0
I1
I2
I3
O
1
0
2-3
Architecture
iCE40 LP/HX Family Data Sheet
Routing
There are many resources provided in the iCE40 devices to route signals individually with related control signals.
The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4
(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient
connections in the diagonal, horizontal and vertical directions.
The design tool takes the output of the synthesis tool and places and routes the design.
Clock/Control Distribution Network
Each iCE40 device has eight global inputs, two pins on each side of the device. Note that not all GBINs are avail-
able in all packages.
These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are
identified as GBIN[7:0] and the global buffers are identified as-GBUF[7:0]. These eight inputs may be used as gen-
eral purpose I/O if they are not used to drive the clock nets. Global buffer GBUF7 in I/O Bank 3 also provides an
optional direct LVDS25 or subLVDS differential clock input.
Table 2-2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally
connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered
global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the
PLB clock-enable input.
Table 2-2. Global Buffer (GBUF) Connections to Programmable Logic Blocks
The maximum frequency for the global buffers are shown in the iCE40 External Switching Characteristics tables
later in this document.
Global Hi-Z Control
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 device. This GHIZ signal is
automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance
state.
Global Buffer LUT Inputs Clock Reset Clock Enable
GBUF0
Yes, any 4 of 8
GBUF Inputs
Ye s Ye s
GBUF1 Yes Yes
GBUF2 Yes Yes
GBUF3 Yes Yes
GBUF4 Yes Yes
GBUF5 Yes Yes
GBUF6 Yes Yes
GBUF7 Yes Yes
2-4
Architecture
iCE40 LP/HX Family Data Sheet
Global Reset Control
The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 device. The global reset signal is
automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For
PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 devices have one or more sys-
CLOCK PLLs. REFERENCECLK is the reference frequency input to the PLL and its source can come from an
external I/O pin or from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from
internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus
synthesize a higher frequency clock output.
The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output.
The output divider can have a value from 1 to 6. The PLLOUT outputs can all be used to drive the iCE40 global
clock network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is
detected. A block diagram of the PLL is shown in Figure 2-3.
The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock
which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be
either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock
after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has
been satisfied.
For more details on the PLL, see TN1251, iCE40 sysCLOCK PLL Design and Usage Guide.
Figure 2-3. PLL Diagram
Table 2-3 provides signal descriptions of the PLL block.
Input
Divider
DIVR
Low-Pass
Filter
Voltage
Controlled
Oscillator
(VCO)
VCO
Divider
DIVQ
Feedback
Divider
DIVF
RANGE
Phase
Detector
Feedback_Path
Fine Delay
Adjustment
Feedback
Phase
Shifter
LATCHINPUTVALUE
REFERENCECLK
DYNAMICDELAY[7:0]
BYPASS
RESET
EXTFEEDBACK
PLLOUTCORE
PLLOUTGLOBAL
LOCK
BYPASS
Low Power mode
(iCEgate enabled)
SIMPLE
EXTERNAL
VCCPLLGNDPLL
Fine Delay
Adjustment
Output Port
2-5
Architecture
iCE40 LP/HX Family Data Sheet
Table 2-3. PLL Signal Descriptions
sysMEM Embedded Block RAM Memory
Larger iCE40 device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each 4
kbit in size. This memory can be used for a wide variety of purposes including data buffering, and FIFO.
sysMEM Memory Block
The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic
resources. Each block can be used in a variety of depths and widths as shown in Table 2-4.
Table 2-4. sysMEM Block Configurations1
Signal Name Direction Description
REFERENCECLK Input Input reference clock
BYPASS Input
When FEEDBACK_PATH is set to SIMPLE, the BYPASS control selects which clock sig-
nal connects to the PLLOUT output.
0 = PLL generated signal
1 = REFERENCECLK
EXTFEEDBACK Input
External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set to
EXTERNAL.
DYNAMICDELAY[3:0] Input
Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE is
set to DYNAMIC.
LATCHINPUTVALUE Input
When enabled, forces the PLL into low-power mode; PLL output is held static at the last
input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‘1’ to enable.
PLLOUTGLOBAL Output Output from the Phase-Locked Loop (PLL). Drives a global clock network on the FPGA.
The port has optimal connections to global clock buffers GBUF4 and GBUF5.
PLLOUTCORE Output
Output clock generated by the PLL, drives regular FPGA routing. The frequency gener-
ated on this output is the same as the frequency of the clock signal generated on the
PLLOUTLGOBAL port.
LOCK Output When High, indicates that the PLL output is phase aligned or locked to the input refer-
ence clock.
RESET Input Active low reset.
Block RAM
Configuration
Block RAM
Configuration
and Size
WADDR Port
Size (Bits)
WDATA Port
Size (Bits)
RADDR Port
Size (Bits)
RDATA Port
Size (Bits)
MASK Port
Size (Bits)
SB_RAM256x16
SB_RAM256x16NR
SB_RAM256x16NW
SB_RAM256x16NRNW
256x16 (4K) 8 [7:0] 16 [15:0] 8 [7:0] 16 [15:0] 16 [15:0]
SB_RAM512x8
SB_RAM512x8NR
SB_RAM512x8NW
SB_RAM512x8NRNW
512x8 (4K) 9 [8:0] 8 [7:0] 9 [8:0] 8 [7:0] No Mask Port
SB_RAM1024x4
SB_RAM1024x4NR
SB_RAM1024x4NW
SB_RAM1024x4NRNW
1024x4 (4K) 10 [9:0] 4 [3:0] 10 [9:0] 4 [3:0] No Mask Port
SB_RAM2048x2
SB_RAM2048x2NR
SB_RAM2048x2NW
SB_RAM2048x2NRNW
2048x2 (4K) 11 [10:0] 2 [1:0] 11 [10:0] 2 [1:0] No Mask Port
1. For iCE40 EBR primitives with a negative-edged Read or Write clock, the base primitive name is appended with a ‘N’ and a ‘R’ or ‘W’
depending on the clock that is affected.
2-6
Architecture
iCE40 LP/HX Family Data Sheet
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration.
By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block
can also be utilized as a ROM.
Note the sysMEM Embedded Block RAM Memory address 0 cannot be initialized.
Memory Cascading
Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.
RAM4k Block
Figure 2-4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes,
the input data and addresses for the ports are registered at the input of the memory array.
Figure 2-4. sysMEM Memory Primitives
Table 2-5. EBR Signal Descriptions
For further information on the sysMEM EBR block, please refer to TN1250, Memory Usage Guide for iCE40 De-
vices.
Signal Name Direction Description
WDATA[15:0] Input Write Data input.
MASK[15:0] Input Masks write operations for individual data bit-lines.
0 = write bit; 1 = don’t write bit
WADDR[7:0] Input Write Address input. Selects one of 256 possible RAM locations.
WE Input Write Enable input.
WCLKE Input Write Clock Enable input.
WCLK Input Write Clock input. Default rising-edge, but with falling-edge option.
RDATA[15:0] Output Read Data output.
RADDR[7:0] Input Read Address input. Selects one of 256 possible RAM locations.
RE Input Read Enable input.
RCLKE Input Read Clock Enable input.
RCLK Input Read Clock input. Default rising-edge, but with falling-edge option.
WCLK
WERE
WCLKE RCLKE
RCLK
WDATA[15:0] RDATA[15:0]
MASK[15:0]
WADDR[7:0] RADDR[7:0]
Write Port Read Port
RAM4K
RAM Block
(256x16)
2-7
Architecture
iCE40 LP/HX Family Data Sheet
sysIO
Buffer Banks
iCE40 devices have up to four I/O banks with independent VCCIO rails with an additional configuration bank
VCC_SPI for the SPI I/Os.
Programmable I/O (PIO)
The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respec-
tive sysIO buffers and pads. The PIOs are placed on all four sides of the device.
Figure 2-5. I/O Bank and Programmable I/O Cell
The PIO contains three blocks: an input register block, output register block iCEgate™ and tri-state register block.
To save power, the optional iCEgateTM latch can selectively freeze the state of individual, non-registered inputs
within an I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of
modes along with the necessary clock and selection logic.
Input Register Block
The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed inter-
face signals before they are passed to the device core. In Generic DDR mode, two registers are used to sample the
data on the positive and negative edges of the system clock signal, creating two data streams.
Output Register Block
The output register block can optionally register signals from the core of the device before they are passed to the
sysIO buffers. In Generic DDR mode, two registers are used to capture the data on the positive and negative edge
of the system clock and then muxed creating one data stream.
Figure 2-6 shows the input/output register block for the PIOs.
I/O Bank 0
I/O Bank 2
I/O Bank 1
I/O Bank 3
PIO OUT
OE
VCCIO
I/O Bank 0, 1, 2, or 3
Voltage Supply
= Statically defined by configuration program
0 = Hi-Z
1 = Output
Enabled
PAD
HD
iCEGATE
HOLD
Disabled ‘0’
OUTCLK
OUTCLK
INCLK
Enabled ‘1’
Latch inhibits
switching for
lowest power
IN
VCCIO_0
VCCIO_2
VCCIO_3
VCC
Internal Core
VCC_SPI
Special/LVDS I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
Programmable Input/Output
SPI
Bank
Pull-up
Enable
Pull-up
VCCIO_1
GBIN pins optionally
connect directly to an
associated GBUF global
buffer
IN
2-8
Architecture
iCE40 LP/HX Family Data Sheet
Figure 2-6. iCE I/O Register Block Diagram
Table 2-6. PIO Signal List
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of
standards that are found in today’s systems including LVCMOS and LVDS25.
High Current LED Drivers combine three sysIO buffers together. This allows for programmable drive strength. This
also allows for high current drivers that are ideal to drive three white LEDs, or one RGB LED. Each bank is capable
of supporting multiple I/O standards including single-ended LVCMOS buffers and differential LVDS25E output buf-
Pin Name I/O Type Description
OUTPUT_CLK Input Output register clock
CLOCK_ENABLE Input Clock enable
INPUT_CLK Input Input register clock
OUTPUT_ENABLE Input Output enable
D_OUT_0/1 Input Data from the core
D_IN_0/1 Output Data to the core
LATCH_INPUT_VALUE Input Latches/holds the Input Value
(1,0)
(1,0)
(1,0)
0
1
(1,0)
Pad
Pad
CLOCK_ENABLE
OUTPUT_ENABLE
OUTPUT_ENABLE
OUTPUT_CLK
INPUT_CLK
LATCH_INPUT_VALUE
LATCH_INPUT_VALUE
D_IN_1
D_IN_0
D_OUT_1
D_OUT_0
D_IN_1
D_IN_0
D_OUT_1
D_OUT_0
PIO Pair
0
1
= Statically defined by configuration program.
2-9
Architecture
iCE40 LP/HX Family Data Sheet
fers. Bank 3 additionally supports differential LVDS25 input buffers. Each sysIO bank has its own dedicated power
supply.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO_2, VPP_2V5, and VCC_SPI have reached
the level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data
sheet. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to
ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all
the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to config-
uration is tri-stated with a weak pull-up to VCCIO. The I/O pins will maintain the pre-configuration state until VCC and
VCCIO (for I/O banks containing configuration I/Os) have reached levels, at which time the I/Os will take on the soft-
ware user-configured settings only after a proper download/configuration. Unused IOs are automatically blocked
and the pullup termination is disabled.
Supported Standards
The iCE40 sysIO buffer supports both single-ended and differential input standards. The single-ended standard
supported is LVCMOS. The buffer supports the LVCMOS 1.8, 2.5, and 3.3 V standards. The buffer has individually
configurable options for bus maintenance (weak pull-up or none). The High Current output buffer have individually
configurable options for drive strength.
Table 2-7 and Table 2-8 show the I/O standards (together with their supply and reference voltages) supported by
the iCE40 devices.
Table 2-7. Supported Input Standards
Table 2-8. Supported Output Standards
Non-Volatile Configuration Memory
All iCE40 devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the
device.
For more information on the NVCM, please refer to TN1248, iCE40 Programming and Configuration Usage Guide.
Input Standard VCCIO (Typical)
3.3 V 2.5 V 1.8 V
Single-Ended Interfaces
LVCMOS33 Yes
LVCMOS25 Yes
LVCMOS18 Ye s
Differential Interfaces
LVDS251Ye s
subLVDS1Ye s
1. Bank 3 only.
Output Standard VCCIO (Typical)
Single-Ended Interfaces
LVCMOS33 3.3
LVCMOS25 2.5
LVCMOS18 1.8
Differential Interfaces
LVDS25E12.5
subLVDSE1 1.8
1. These interfaces can be emulated with external resistors in all devices.
2-10
Architecture
iCE40 LP/HX Family Data Sheet
Power On Reset
iCE40 devices have power-on reset circuitry to monitor VCC, VCCIO_2, VPP_2V5, and VCC_SPI voltage levels during
power-up and operation. At power-up, the POR circuitry monitors VCC, VCCIO_2, VPP_2V5, and VCC_SPI (controls
configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after
reaching the power-up levels specified in the Power-On-Reset Voltage table in the DC and Switching Characteris-
tics section of this data sheet. Before and during configuration, the I/Os are held in tri-state. I/Os are released to
user functionality once the device has finished configuration.
Programming and Configuration
This section describes the programming and configuration of the iCE40 family.
Device Programming
The NVCM memory can be programmed through the SPI port.
Device Configuration
There are various ways to configure the Configuration RAM (CRAM) including:
1. Internal NVCM Download
2. From a SPI Flash (Master SPI mode)
3. System microprocessor to drive a Serial Slave SPI port (SSPI mode)
The image to configure the CRAM can be selected by the user on power up (Cold Boot) or once powered up
(Warm Boot).
For more details on programming and configuration, see TN1248, iCE40 Programming and Configuration Usage
Guide.
Power Saving Options
iCE40 devices are available in two options for maximum flexibility: LP and HX devices. The LP devices have ultra
low static and dynamic power consumption. HX devices are designed to provide high performance. Both the LP
and the HX devices operate at 1.2 V VCC.
iCE40 devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic power
requirements of their applications. While these features are available in both device types, these features are
mainly intended for use with iCE40 LP devices to manage power consumption.
Table 2-9. iCE40 Power Saving Features Description
Device Subsystem Feature Description
PLL When LATCHINPUTVALUE is enabled, forces the PLL into low-power mode; PLL output held static
at last input clock value.
iCEGate
To save power, the optional iCEgate latch can selectively freeze the state of individual, non-regis-
tered inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or
clock-enable control.
www.latticesemi.com 3-1 DS1040 DC and Switching_02.0
October 2015 Data Sheet DS1040
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Absolute Maximum Ratings1, 2, 3, 4
iCE40 LP/HX
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.42 V
Output Supply Voltage VCCIO, VCC_SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
NVCM Supply Voltage VPP_2V5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
PLL Supply Voltage VCCPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 1.30 V
I/O Tri-state Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
Dedicated Input Voltage Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.60 V
Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 °C to 150 °C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 °C to 125 °C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. IOs can support a 200 mV Overshoot above the Recommend Operating Conditions VCCIO (Max) and -200mV Undershoot below VIL (Min).
Overshoot and Undershoot is permitted for 25% duty cycle but must not exceed 1.6 ns.
Recommended Operating Conditions1
Symbol Parameter Min. Max. Units
VCC1Core Supply Voltage 1.14 1.26 V
VPP_2V5 VPP_2V5 NVCM Programming and
Operating Supply Voltage
Slave SPI Configuration 1.71 3.46 V
Master SPI Configuration 2.30 3.46 V
Configure from NVCM 2.30 3.46 V
NVCM Programming 2.30 3.00 V
VPP_FAST4Optional fast NVCM programming supply. Leave unconnected. N/A N/A V
VCCPLL5, 6 PLL Supply Voltage 1.14 1.26 V
VCCIO1, 2, 3 I/O Driver Supply Voltage VCCIO0-3 1.71 3.46 V
VCC_SPI 1.71 3.46 V
tJIND Junction Temperature Industrial Operation 40 100 °C
tPROG Junction Temperature NVCM Programming 10 30 °C
1. Like power supplies must be tied together. For example, if VCCIO and VCC_SPI are both the same voltage, they must also be the same sup-
ply.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. VPP_FAST
, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 pack-
ages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
5. No PLL available on the iCE40LP384 and iCE40LP640 device.
6. VCCPLL is tied to VCC internally in packages without PLLs pins.
iCE40 LP/HX Family Data Sheet
DC and Switching Characteristics
3-2
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Power Supply Ramp Rates1, 2
Power-On-Reset Voltage Levels1
ESD Performance
Please refer to the iCE40 Product Family Qualification Summary for complete qualification data, including ESD per-
formance.
Symbol Parameter Min. Max. Units
tRAMP Power supply ramp rates for all
power supplies.
All configuration modes. No power
supply sequencing.
0.40 10 V/ms
Configuring from Slave SPI. No
power supply sequencing,
0.01 10 V/ms
Configuring from NVCM. VCC and
VPP_2V5 to be powered 0.25 ms
before VCC_SPI.
0.01 10 V/ms
Configuring from MSPI. VCC and
VPP_SPI to be powered 0.25 ms
before VPP_2V5.
0.01 10 V/ms
1. Assumes monotonic ramp rates.
2. iCE40LP384 requires VCC to be greater than 0.7V when VCCIO and VCC_SPI are above GND.
Symbol Device Parameter Min. Max. Units
VPORUP iCE40LP384 Power-On-Reset ramp-up trip point
(band gap based circuit monitoring
VCC, VCCIO_2, VCC_SPI and
VPP_2V5)
VCC 0.67 0.99 V
VCCIO_2 0.70 1.59 V
VCC_SPI 0.70 1.59 V
VPP_2V5 0.70 1.59 V
iCE40LP640,
iCE40LP/HX1K,
iCE40LP/HX4K,
iCE40LP/HX8K
Power-On-Reset ramp-up trip point
(band gap based circuit monitoring
VCC, VCCIO_2, VCC_SPI and
VPP_2V5)
VCC 0.55 0.75 V
VCCIO_2 0.86 1.29 V
VCC_SPI 0.86 1.29 V
VPP_2V5 0.86 1.33 V
VPORDN iCE40LP384 Power-On-Reset ramp-down trip
point (band gap based circuit moni-
toring VCC, VCCIO_2, VCC_SPI
and VPP_2V5)
VCC 0.64 V
VCCIO_2 1.59 V
VCC_SPI 1.59 V
VPP_2V5 1.59 V
iCE40LP640,
iCE40LP/HX1K,
iCE40LP/HX4K,
iCE40LP/HX8K
Power-On-Reset ramp-down trip
point (band gap based circuit moni-
toring VCC, VCCIO_2, VCC_SPI
and VPP_2V5)
VCC 0.75 V
VCCIO_2 1.29 V
VCC_SPI 1.29 V
VPP_2V5 1.33 V
1. These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages specified under rec-
ommended operating conditions.
3-3
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Static Supply Current – LP Devices1, 2, 3, 4
Symbol Parameter Condition Min. Typ. Max. Units
IIL, IIH1, 3, 4, 5, 6, 7 Input or I/O Leakage 0V < VIN < VCCIO + 0.2 V +/10 µA
C16, 7
I/O Capacitance2VCCIO = 3.3 V, 2.5 V, 1.8 V
VCC = Typ., VIO = 0 to VCCIO + 0.2 V —6—pf
C26, 7 Global Input Buffer
Capacitance2
VCCIO = 3.3 V, 2.5 V, 1.8 V
VCC = Typ., VIO = 0 to VCCIO + 0.2 V —6—pf
VHYST Input Hysteresis VCCIO = 1.8 V, 2.5 V, 3.3 V 200 mV
IPU6, 7 Internal PIO Pull-up
Current
VCCIO = 1.8 V, 0=<VIN<=0.65 VCCIO 3—31 µA
VCCIO = 2.5 V, 0=<VIN<=0.65 VCCIO 8—72 µA
VCCIO = 3.3 V, 0=<VIN<=0.65 VCCIO 11 128 µA
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Internal pull-up resistors are disabled.
2. TJ 25°C, f = 1.0 MHz.
3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document.
4. Only applies to IOs in the SPI bank following configuration.
5. Some products are clamped to a diode when VIN is larger than VCCIO.
6. High current IOs has three sysIO buffers connected together.
7. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysIO buffer are connected together.
Symbol Parameter Device Typ. VCC4Units
ICC Core Power Supply
iCE40LP384 21 µA
iCE40LP640 100 µA
iCE40LP1K 100 µA
iCE40LP4K 250 µA
iCE40LP8K 250 µA
ICCPLL5, 6 PLL Power Supply All devices 0.5 µA
IPP_2V5 NVCM Power Supply All devices 1.0 µA
ICCIO, ICC_SPI Bank Power Supply4
VCCIO = 2.5 V All devices 3.5 µA
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO
or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI con-
figuration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25 °C, power supplies at nominal voltage.
4. Does not include pull-up.
5. No PLL available on the iCE40LP384 and iCE40LP640 device.
6. VCCPLL is tied to VCC internally in packages without PLLs pins.
3-4
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Static Supply Current – HX Devices1, 2, 3, 4
Programming NVCM Supply Current – LP Devices1, 2, 3, 4
Symbol Parameter Device Typ. VCC4Units
ICC Core Power Supply
iCE40HX1K 296 µA
iCE40HX4K 1140 µA
iCE40HX8K 1140 µA
ICCPLL5PLL Power Supply All devices 0.5 µA
IPP_2V5 NVCM Power Supply All devices 1.0 µA
ICCIO, ICC_SPI Bank Power Supply4
VCCIO = 2.5 V All devices 3.5 µA
1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO
or GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified with master SPI config-
uration mode. Other modes may be up to 25% higher.
2. Frequency = 0 MHz.
3. TJ = 25 °C, power supplies at nominal voltage.
4. Does not include pull-up.
5. VCCPLL is tied to VCC internally in packages without PLLs pins.
Symbol Parameter Device Typ. VCC5Units
ICC Core Power Supply
iCE40LP384 60 µA
iCE40LP640 120 µA
iCE40LP1K 120 µA
iCE40LP4K 350 µA
iCE40LP8K 350 µA
ICCPLL6, 7 PLL Power Supply All devices 0.5 µA
IPP_2V5 NVCM Power Supply All devices 2.5 mA
ICCIO8, ICC_SPI Bank Power Supply5All devices 3.5 mA
1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
2. Typical user pattern.
3. SPI programming is at 8 MHz.
4. TJ = 25 °C, power supplies at nominal voltage.
5. Per bank. VCCIO = 2.5 V. Does not include pull-up.
6. No PLL available on the iCE40-LP384 and iCE40-LP640 device.
7. VCCPLL is tied to VCC internally in packages without PLLs pins.
8. VPP_FAST
, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 pack-
ages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
3-5
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Programming NVCM Supply Current – HX Devices1, 2, 3, 4
Peak Startup Supply Current – LP Devices
Symbol Parameter Device Typ. VCC5Units
ICC Core Power Supply
iCE40HX1K 278 µA
iCE40HX4K 1174 µA
iCE40HX8K 1174 µA
ICCPLL6PLL Power Supply All devices 0.5 µA
IPP_2V5 NVCM Power Supply All devices 2.5 mA
ICCIO7, ICC_SPI Bank Power Supply5All devices 3.5 mA
1. Assumes all inputs are held at VCCIO or GND and all outputs are tri-stated.
2. Typical user pattern.
3. SPI programming is at 8 MHz.
4. TJ = 25 °C, power supplies at nominal voltage.
5. Per bank. VCCIO = 2.5 V. Does not include pull-up.
6. VCCPLL is tied to VCC internally in packages without PLLs pins.
7. VPP_FAST
, used only for fast production programming, must be left floating or unconnected in applications.
Symbol Parameter Device Max Units
ICCPEAK Core Power Supply
iCE40LP384 7.7 mA
iCELP640 6.4 mA
iCE40LP1K 6.4 mA
iCE40LP4K 15.7 mA
iCE40LP8K 15.7 mA
ICCPLLPEAK1, 2, 4 PLL Power Supply
iCE40LP1K 1.5 mA
iCELP640 1.5 mA
iCE40LP4K 8.0 mA
iCE40LP8K 8.0 mA
IPP_2V5PEAK NVCM Power Supply
iCE40LP384 3.0 mA
iCELP640 7.7 mA
iCE40LP1K 7.7 mA
iCE40LP4K 4.2 mA
iCE40LP8K 4.2 mA
IPP_FASTPEAK3NVCM Programming Supply
iCE40LP384 5.7 mA
iCELP640 8.1 mA
iCE40LP1K 8.1 mA
ICCIOPEAK5, ICC_SPIPEAK Bank Power Supply
iCE40LP384 8.4 mA
iCELP640 3.3 mA
iCE40LP1K 3.3 mA
iCE40LP4K 8.2 mA
iCE40LP8K 8.2 mA
1. No PLL available on the iCE40LP384 and iCE40LP640 device.
2. VCCPLL is tied to VCC internally in packages without PLLs pins.
3. VPP_FAST
, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 pack-
ages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
4. While no PLL is available in the iCE40-LP640 the ICCPLLPEAK is additive to ICCPEAK.
5. iCE40LP384 requires VCC to be greater than 0.7 V when VCCIO and VCC_SPI are above GND.
3-6
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Peak Startup Supply Current – HX Devices
sysIO Recommended Operating Conditions
sysIO Single-Ended DC Electrical Characteristics
Symbol Parameter Device Max Units
ICCPEAK Core Power Supply
iCE40HX1K 6.9 mA
iCE40HX4K 22.3 mA
iCE40HX8K 22.3 mA
ICCPLLPEAK1PLL Power Supply
iCE40HX1K 1.8 mA
iCE40HX4K 6.4 mA
iCE40HX8K 6.4 mA
IPP_2V5PEAK NVCM Power Supply
iCE40HX1K 2.8 mA
iCE40HX4K 4.1 mA
iCE40HX8K 4.1 mA
ICCIOPEAK, ICC_SPIPEAK Bank Power Supply
iCE40HX1K 6.8 mA
iCE40HX4K 6.8 mA
iCE40HX8K 6.8 mA
1. VCCPLL is tied to VCC internally in packages without PLLs pins.
Standard
VCCIO (V)
Min. Typ. Max.
LVCMOS 3.3 3.14 3.3 3.46
LVCMOS 2.5 2.37 2.5 2.62
LVCMOS 1.8 1.71 1.8 1.89
LV D S 2 5 E 1, 2 2.37 2.5 2.62
subLVDSE1, 2 1.71 1.8 1.89
1. Inputs on-chip. Outputs are implemented with the addition of external resistors.
2. Does not apply to Configuration Bank VCC_SPI.
Input/
Output
Standard
VIL VIH1
VOL Max.
(V)
VOH Min.
(V)
IOL Max.
(mA) IOH Max. (mA)Min. (V) Max. (V) Min. (V) Max. (V)
LVCMOS 3.3 0.3 0.8 2.0 VCCIO + 0.2 V 0.4 VCCIO 0.4 8, 162, 242 8, 162, 242
0.2 VCCIO 0.2 0.1 0.1
LVCMOS 2.5 0.3 0.7 1.7 VCCIO + 0.2 V 0.4 VCCIO 0.4 6, 122, 182 6, 122, 182
0.2 VCCIO 0.2 0.1 0.1
LVCMOS 1.8 0.3 0.35VCCIO 0.65VCCIO VCCIO + 0.2 V 0.4 VCCIO 0.4 4, 82, 122 4, 82, 122
0.2 VCCIO 0.2 0.1 0.1
1. Some products are clamped to a diode when VIN is larger than VCCIO.
2. Only for High Drive LED outputs.
3-7
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
sysIO Differential Electrical Characteristics
The LVDS25E/subLVDSE differential output buffers are available on all banks but the LVDS/subLVDS input buffers
are only available on Bank 3 of iCE40 devices.
LVDS 25
Over Recommended Operating Conditions
subLVDS
Over Recommended Operating Conditions
Parameter
Symbol Parameter Description Test Conditions Min. Typ. Max. Units
VINP, VINM Input Voltage VCCIO1 = 2.5 0 2.5 V
VTHD Differential Input Threshold 250 350 450 mV
VCM Input Common Mode Voltage VCCIO1 = 2.5 (VCCIO/2) - 0.3 VCCIO/2 (VCCIO/2) + 0.3 V
IIN Input Current Power on ±10 µA
1. Typical.
Parameter
Symbol Parameter Description Test Conditions Min. Typ. Max. Units
VINP, VINM Input Voltage VCCIO1 = 1.8 0 1.8 V
VTHD Differential Input Threshold 100 150 200 mV
VCM Input Common Mode Voltage VCCIO1 = 1.8 (VCCIO/2) - 0.25 VCCIO/2 (VCCIO/2) + 0.25 V
IIN Input Current Power on ±10 µA
1. Typical.
3-8
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
LVDS25E Emulation
iCE40 devices can support LVDSE outputs via emulation on all banks. The output is emulated using complemen-
tary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in
Figure 3-1 is one possible solution for LVDS25E standard implementation. Resistor values in Figure 3-1 are indus-
try standard values for 1% resistors.
Figure 3-1. LVDS25E Using External Resistors
Table 3-1. LVDS25E DC Conditions
Over Recommended Operating Conditions
Parameter Description Typ. Units
ZOUT Output impedance 20 Ohms
RSDriver series resistor 150 Ohms
RPDriver parallel resistor 140 Ohms
RTReceiver termination 100 Ohms
VOH Output high voltage 1.43 V
VOL Output low voltage 1.07 V
VOD Output differential voltage 0.30 V
VCM Output common mode voltage 1.25 V
ZBACK Back impedance 100.5 Ohms
IDC DC output current 6.03 mA
3-9
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
SubLVDS Emulation
The iCE40 family supports the differential subLVDS standard. The output standard is emulated using complemen-
tary LVCMOS outputs in conjunction with resistors across the driver outputs on all banks of the devices. The sub-
LVDS input standard is supported by the LVDS25 differential input buffer. The scheme shown in Figure 3-2 is one
possible solution for subLVDSE output standard implementation. Use LVDS25E mode with suggested resistors for
subLVDSE operation. Resistor values in Figure 3-2 are industry standard values for 1% resistors.
Figure 3-2. subLVDSE
Table 3-2. subLVDSE DC Conditions
Over Recommended Operating Conditions
Parameter Description Typ. Units
ZOUT Output impedance 20 Ohms
RSDriver series resistor 270 Ohms
RPDriver parallel resistor 120 Ohms
RTReceiver termination 100 Ohms
VOH Output high voltage 1.43 V
VOL Output low voltage 1.07 V
VOD Output differential voltage 0.35 V
VCM Output common mode voltage 0.9 V
ZBACK Back impedance 100.5 Ohms
IDC DC output current 2.8 mA
3-10
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Typical Building Block Function Performance – LP Devices1, 2
Pin-to-Pin Performance (LVCMOS25)
Register-to-Register Performance
Typical Building Block Function Performance – HX Devices1, 2
Pin-to-Pin Performance (LVCMOS25)
Register-to-Register Performance
Function Timing Units
Basic Functions
16-bit decoder 11.0 ns
4:1 MUX 12.0 ns
16:1 MUX 13.0 ns
Function Timing Units
Basic Functions
16:1 MUX 190 MHz
16-bit adder 160 MHz
16-bit counter 175 MHz
64-bit counter 65 MHz
Embedded Memory Functions
256x16 Pseudo-Dual Port RAM 240 MHz
1. The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with
device and tool version. The tool uses internal parameters that have been characterized but are not tested on
every device.
2. Using a VCC of 1.14 V at Junction Temp 85 °C.
Function Timing Units
Basic Functions
16-bit decoder 10.0 ns
4:1 MUX 9.0 ns
16:1 MUX 9.5 ns
Function Timing Units
Basic Functions
16:1 MUX 305 MHz
16-bit adder 220 MHz
16-bit counter 255 MHz
64-bit counter 105 MHz
Embedded Memory Functions
256x16 Pseudo-Dual Port RAM 403 MHz
1. The above timing numbers are generated using the iCECube2 design tool. Exact performance may vary with
device and tool version. The tool uses internal parameters that have been characterized but are not tested on
every device.
2. Using a VCC of 1.14 V at Junction Temp 85 °C.
3-11
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Derating Logic Timing
Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case num-
bers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing num-
bers at a particular temperature and voltage.
Maximum sysIO Buffer Performance2
iCE40 Family Timing Adders
Over Recommended Commercial Operating Conditions - LP Devices1, 2, 3, 4, 5
I/O Standard Max. Speed Units
Inputs
LVDS251400 MHz
subLVDS181400 MHz
LVCMOS33 250 MHz
LVCMOS25 250 MHz
LVCMOS18 250 MHz
Outputs
LVDS25E 250 MHz
subLVDS18E 155 MHz
LVCMOS33 250 MHz
LVCMOS25 250 MHz
LVCMOS18 155 MHz
1. Supported in Bank 3 only.
2. Measured with a toggling pattern
Buffer Type Description Timing Units
Input Adjusters
LVD S 2 5 LVD S, V CCIO = 2.5 V 0.18 ns
subLVDS subLVDS, VCCIO = 1.8 V 0.82 ns
LVC M O S33 LVC M O S, VCCIO = 3.3 V 0.18 ns
LVC M O S25 LVC M O S, VCCIO = 2.5 V 0.00 ns
LVC M O S18 LVC M O S, VCCIO = 1.8 V 0.19 ns
Output Adjusters
LVDS25E LVDS, Emulated, VCCIO = 2.5 V 0.00 ns
subLVDSE subLVDS, Emulated, VCCIO = 1.8 V 1.32 ns
LVC M O S33 LVC M O S, VCCIO = 3.3 V 0.12 ns
LVC M O S25 LVC M O S, VCCIO = 2.5 V 0.00 ns
LVC M O S18 LVC M O S, VCCIO = 1.8 V 1.32 ns
1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. All other standards tested according to the appropriate specifications.
4. Commercial timing numbers are shown.
5. Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
3-12
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Over Recommended Commercial Operating Conditions - HX Devices1, 2, 3, 4, 5
Buffer Type Description Timing Units
Input Adjusters
LVD S 2 5 LVD S, V CCIO = 2.5 V 0.13 ns
subLVDS subLVDS, VCCIO = 1.8 V 1.03 ns
LVC M O S33 LVC M O S, VCCIO = 3.3 V 0.16 ns
LVC M O S25 LVC M O S, VCCIO = 2.5 V 0.00 ns
LVC M O S18 LVC M O S, VCCIO = 1.8 V 0.23 ns
Output Adjusters
LVDS25E LVDS, Emulated, VCCIO = 2.5 V 0.00 ns
subLVDSE subLVDS, Emulated, VCCIO = 1.8 V 1.76 ns
LVC M O S33 LVC M O S, VCCIO = 3.3 V 0.17 ns
LVC M O S25 LVC M O S, VCCIO = 2.5 V 0.00 ns
LVC M O S18 LVC M O S, VCCIO = 1.8 V 1.76 ns
1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. All other standards tested according to the appropriate specifications.
4. Commercial timing numbers are shown.
5. Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
3-13
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
iCE40 External Switching Characteristics – LP Devices 1, 2
Over Recommended Operating Conditions
Parameter Description Device Min. Max. Units
Clocks
Global Clocks
fMAX_GBUF Frequency for Global Buffer Clock network All iCE40LP devices 275 MHz
tW_GBUF Clock Pulse Width for Global Buffer All iCE40LP devices 0.92 ns
tSKEW_GBUF Global Buffer Clock Skew Within a Device
iCE40LP384 370 ps
iCE40LP640 230 ps
iCE40LP1K 230 ps
iCE40LP4K 340 ps
iCE40LP8K 340 ps
Pin-LUT-Pin Propagation Delay
tPD Best case propagation delay through one
LUT-4 All iCE40LP devices 9.36 ns
General I/O Pin Parameters (Using Global Buffer Clock without PLL)3
tSKEW_IO Data bus skew across a bank of IOs
iCE40LP384 300 ps
iCE40LP640 200 ps
iCE40LP1K 200 ps
iCE40LP4K 280 ps
iCE40LP8K 280 ps
tCO Clock to Output - PIO Output Register
iCE40LP384 — 6.33 ns
iCE40LP640 — 5.91 ns
iCE40LP1K — 5.91 ns
iCE40LP4K — 6.58 ns
iCE40LP8K — 6.58 ns
tSU Clock to Data Setup - PIO Input Register
iCE40LP384 0.08 — ns
iCE40LP640 0.33 — ns
iCE40LP1K 0.33 — ns
iCE40LP4K 0.63 — ns
iCE40LP8K 0.63 — ns
tHClock to Data Hold - PIO Input Register
iCE40LP384 1.99 — ns
iCE40LP640 2.81 — ns
iCE40LP1K 2.81 — ns
iCE40LP4K 3.48 — ns
iCE40LP8K 3.48 — ns
General I/O Pin Parameters (Using Global Buffer Clock with PLL)3
tCOPLL Clock to Output - PIO Output Register
iCE40LP1K — 2.20 ns
iCE40LP4K — 2.30 ns
iCE40LP8K — 2.30 ns
tSUPLL Clock to Data Setup - PIO Input Register
iCE40LP1K 5.23 — ns
iCE40LP4K 6.13 — ns
iCE40LP8K 6.13 — ns
3-14
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
tHPLL Clock to Data Hold - PIO Input Register
iCE40LP1K 0.90 — ns
iCE40LP4K 0.80 — ns
iCE40LP8K 0.80 — ns
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V. Other
operating conditions can be extracted from the iCECube2 software.
2. General I/O timing numbers based on LVCMOS 2.5, 0pf load.
3. Supported on devices with a PLL.
iCE40 External Switching Characteristics – LP Devices (Continued)1, 2
Over Recommended Operating Conditions
Parameter Description Device Min. Max. Units
3-15
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
iCE40 External Switching Characteristics – HX Devices 1, 2
Over Recommended Operating Conditions
Parameter Description Device Min. Max. Units
Clocks
Primary Clocks
fMAX_GBUF Frequency for Global Buffer Clock network All iCE40HX devices 275 MHz
tW_GBUF Clock Pulse Width for Global Buffer All iCE40HX devices 0.88 ns
tSKEW_GBUF Global Buffer Clock Skew Within a Device
iCE40HX1K 727 ps
iCE40HX4K 300 ps
iCE40HX8K 300 ps
Pin-LUT-Pin Propagation Delay
tPD Best case propagation delay through one
LUT-4 All iCE40 HX devices 7.30 ns
General I/O Pin Parameters (Using Global Buffer Clock without PLL)
tSKEW_IO Data bus skew across a bank of IOs
iCE40HX1K 696 ps
iCE40HX4K 290 ps
iCE40HX8K 290 ps
tCO Clock to Output - PIO Output Register
iCE40HX1K 5.00 ns
iCE40HX4K 5.41 ns
iCE40HX8K 5.41 ns
tSU Clock to Data Setup - PIO Input Register
iCE40HX1K 0.23 — ns
iCE40HX4K 0.43 — ns
iCE40HX8K 0.43 — ns
tHClock to Data Hold - PIO Input Register
iCE40HX1K 1.92 — ns
iCE40HX4K 2.38 — ns
iCE40HX8K 2.38 — ns
General I/O Pin Parameters (Using Global Buffer Clock with PLL)3
tCOPLL Clock to Output - PIO Output Register
iCE40HX1K 2.96 ns
iCE40HX4K 2.51 ns
iCE40HX8K 2.51 ns
tSUPLL Clock to Data Setup - PIO Input Register
iCE40HX1K 3.10 — ns
iCE40HX4K 4.16 — ns
iCE40HX8K 4.16 — ns
tHPLL Clock to Data Hold - PIO Input Register
iCE40HX1K 0.60 — ns
iCE40HX4K 0.53 — ns
iCE40HX8K 0.53 — ns
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85 °C and 1.14 V. Other
operating conditions, including industrial, can be extracted from the iCECube2 software.
2. General I/O timing numbers based on LVCMOS 2.5, 0pf load.
3. Supported on devices with a PLL.
3-16
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter Descriptions Conditions Min. Max. Units
fIN Input Clock Frequency
(REFERENCECLK, EXTFEEDBACK) 10 133 MHz
fOUT Output Clock Frequency (PLLOUT) 16 275 MHz
fVCO PLL VCO Frequency 533 1066 MHz
fPFD Phase Detector Input Frequency 10 133 MHz
AC Characteristics
tDT Output Clock Duty Cycle fOUT < 175 MHz 40 50 %
175 MHz < fOUT < 275 MHz 35 65 "%
tPH Output Phase Accuracy +/12 deg
tOPJIT1, 5
Output Clock Period Jitter fOUT <= 100 MHz 450 ps p-p
fOUT > 100 MHz 0.05 UIPP
Output Clock Cycle-to-cycle Jitter fOUT <= 100 MHz 750 ps p-p
fOUT > 100 MHz 0.10 UIPP
Output Clock Phase Jitter fPFD <= 25 MHz 275 ps p-p
fPFD > 25 MHz 0.05 UIPP
tWOutput Clock Pulse Width At 90% or 10% 1.3 ns
tLOCK2, 3 PLL Lock-in Time 50 us
tUNLOCK PLL Unlock Time 50 ns
tIPJIT4Input Clock Period Jitter fPFD 20 MHz 1000 ps p-p
fPFD < 20 MHz 0.02 UIPP
tFDTAP Fine Delay adjustment, per Tap 147 195 ps
tSTABLE3LATCHINPUTVALUE LOW to PLL Stable 500 ns
tSTABLE_PW3LATCHINPUTVALUE Pulse Width 100 ns
tRST RESET Pulse Width 10 ns
tRSTREC RESET Recovery Time 10 us
tDYNAMIC_WD DYNAMICDELAY Pulse Width 100 VCO
Cycles
tPDBYPASS Propagation delay with the PLL in bypass
mode
iCE40LP 1.18 4.68 ns
iCE40HX 1.73 4.07 ns
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over
1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed.
4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table.
5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise.
3-17
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
SPI Master or NVCM Configuration Time1, 2
Symbol Parameter Conditions Typ. Units
tCONFIG POR/CRESET_B to
Device I/O Active
iCE40LP384 - Low Frequency (Default) 25 ms
iCE40LP384 - Medium Frequency 15 ms
iCE40LP384 - High Frequency 11 ms
iCE40LP640 - Low Frequency (Default) 53 ms
iCE40LP640 - Medium Frequency 25 ms
iCE40LP640 - High Frequency 13 ms
iCE40LP/HX1K - Low Frequency (Default) 53 ms
iCE40LP/HX1K - Medium Frequency 25 ms
iCE40LP/HX1K - High Frequency 13 ms
iCE40LP/HX4K - Low Frequency (Default) 230 ms
iCE40LP/HX4K - Medium Frequency 110 ms
iCE40LP/HX4K - High Frequency 70 ms
iCE40LP/HX8K - Low Frequency (Default) 230 ms
iCE40LP/HX8K - Medium Frequency 110 ms
iCE40LP/HX8K - High Frequency 70 ms
1. Assumes sysMEM Block is initialized to an all zero pattern if they are used.
2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point.
3-18
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
sysCONFIG Port Timing Specifications1
Symbol Parameter Min. Typ. Max. Units
All Configuration Modes
tCRESET_B
Minimum CRESET_B Low pulse
width required to restart configu-
ration, from falling edge to rising
edge
200 — ns
tDONE_IO
Number of configuration clock
cycles after CDONE goes High
before the PIO pins are activated
49 ——Clock
Cycles
Slave SPI
tCR_SCK
Minimum time from a rising edge
on CRESET_B until the first SPI
write operation, first SPI_SCK.
During this time, the iCE40
device is clearing its internal con-
figuration memory
iCE40LP384 600 - us
iCE40LP640,
iCE40LP/HX1K
800 - us
iCE40LP/HX4K 1200 - us
iCE40LP/HX8K 1200 - us
fMAX1CCLK clock frequency
Write 1 - 25 MHz
Read iCE40LP3842- 15 - MHz
Read iCE40LP640,
iCE40LP/HX1K2
- 15 - MHz
Read iCE40LP/
HX4K2
- 15 - MHz
Read iCE40LP/
HX8K2
- 15 - MHz
tCCLKH CCLK clock pulse width high 20 ns
tCCLKL CCLK clock pulse width low 20 ns
tSTSU CCLK setup time 12 ns
tSTH CCLK hold time 12 ns
tSTCO CCLK falling edge to valid output 13 ns
Master SPI
fMCLK MCLK clock frequency
Off 0 MHz
Low Frequency
(Default)
7.5 MHz
Medium Frequency3 24 MHz
High Frequency3 40 MHz
3-19
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
tMCLK CRESET_B high to first MCLK
edge
iCE40LP384 - Low
Frequency (Default)
600 us
iCE40LP384 -
Medium Frequency
600 us
iCE40LP384 - High
Frequency
600 us
iCE40LP640,
iCE40LP/HX1K -
Low Frequency
(Default)
800 us
iCE40LP640,
iCE40LP/HX1K -
Medium Frequency
800 us
iCE40LP640,
iCE40LP/HX1K -
High Frequency
800 us
iCE40LP/HX1K -Low
Frequency (Default)
800 us
iCE40LP/HX1K -
Medium Frequency
800 us
iCE40LP/HX1K -
High Frequency
800 us
iCE40LP/HX4K -
Low Frequency
(Default)
1200 us
iCE40LP/HX4K -
Medium Frequency
1200 us
iCE40LP/HX4K -
high frequency
1200 us
iCE40LP/HX8K -
Low Frequency
(Default)
1200 us
iCE40LP/HX8K -
Medium Frequency
1200 us
iCE40LP/HX8K -
High Frequency
1200 us
1. Does not apply for NVCM.
2. Supported only with 1.2 V VCC and at 25 °C.
3. Extended range fMAX Write operations support up to 53 MHz only with 1.2 V VCC and at 25 °C.
sysCONFIG Port Timing Specifications1 (Continued)
Symbol Parameter Min. Typ. Max. Units
3-20
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Switching Test Conditions
Figure 3-3 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage,
and other test conditions are shown in Table 3-3.
Figure 3-3. Output Test Load, LVCMOS Standards
Table 3-3. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition R1CLTiming Reference VT
LVCMOS settings (L -> H, H -> L) 0 pF
LVCMOS 3.3 = 1.5 V
LVCMOS 2.5 = VCCIO/2 —
LVCMOS 1.8 = VCCIO/2 —
LVCMOS 3.3 (Z -> H)
188 0 pF
1.5 VOL
LVCMOS 3.3 (Z -> L) 1.5 VOH
Other LVCMOS (Z -> H) VCCIO/2 VOL
Other LVCMOS (Z -> L) VCCIO/2 VOH
LVCMOS (H -> Z) VOH - 0.15 VOL
LVCMOS (L -> Z) VOL - 0.15 VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
DUT
V
T
R1
CL
Test Poi n t
www.latticesemi.com 4-1 DS1040 Pinout Information_01.8
October 2017 Data Sheet DS1040
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Signal Descriptions
Signal Name I/O Descriptions
General Purpose
IO[Bank]_[Row/Column
Number][A/B] I/O [Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number on the device.
IO[Bank]_[Row/Column
Number][A/B] I/O
[Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number on the device.
[A/B] indicates the differential I/O. 'A' = negative input. 'B' = positive input.
HCIO[Bank]_[Number] I/O High Current IO. [Bank] indicates the bank of the device on which the pad is located.
[Number] indicates IO number.
NC No connect
GND GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together.
VCC VCC – The power supply pins for core logic. Dedicated pins. It is recommended that
all VCCs are tied to the same supply.
VCCIO_x VCCIO – The power supply pins for I/O Bank x. Dedicated pins. All VCCIOs located
in the same bank are tied to the same supply.
PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)
VCCPLLx PLL VCC – Power. Dedicated pins. The PLL requires a separate power and ground
that is quiet and stable to reduce the output clock jitter of the PLL.
GNDPLLx —
PLL GND – Ground. Dedicated pins. The sysCLOCK PLL has the DC ground con-
nection made on the FPGA, so the external PLL ground connection (GNDPLL) must
NOT be connected to the board’s ground.
GBINx Global pads. Two per side.
Programming and Configuration
CBSEL[0:1] I/O Dual function pins. I/Os when not used as CBSEL. Optional ColdBoot configuration
SELect input, if ColdBoot mode is enabled.
CRESET_B I Configuration Reset, active Low. Dedicated input. No internal pull-up resistor. Either
actively drive externally or connect a 10 KOhm pull-up resistor to VCCIO_2.
CDONE I/O
Configuration Done. Includes a permanent weak pull-up resistor to VCCIO_2. If driv-
ing external devices with CDONE output, an external pull-up resistor to VCCIO_2
may be required. Refer to the TN1248, iCE40 Programming and Configuration for
more details. Following device configuration the iCE40LP640 and iCE40LP1K in the
SWG16 package CDONE pin can be used as a user output.
VCC_SPI SPI interface voltage supply input. Must have a valid voltage even if configuring from
NVCM.
SPI_SCK I/O Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Config-
uration Clock for configuring an FPGA configuration modes.
SPI_SS_B I/O
SPI Slave Select. Active Low. Includes an internal weak pull-up resistor to VCC_SPI
during configuration. During configuration, the logic level sampled on this pin deter-
mines the configuration mode used by the iCE40 device. An input when sampled at
the start of configuration. An input when in SPI Peripheral configuration mode
(SPI_SS_B = Low). An output when in Master SPI Flash configuration mode.
SPI_SI I/O Slave SPI serial data input and master SPI serial data output
SPI_SO I/O Slave SPI serial data output and master SPI serial data input
iCE40 LP/HX Family Data Sheet
Pinout Information
4-2
Pinout Information
iCE40 LP/HX Family Data Sheet
VPP_FAST —
Optional fast NVCM programming supply. VPP_FAST
, used only for fast production pro-
gramming, must be left floating or unconnected in applications, except CM36 and
CM49 packages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
VPP_2V5 VPP_2V5 NVCM programming and operating supply
Signal Descriptions (Continued)
Signal Name I/O Descriptions
4-3
Pinout Information
iCE40 LP/HX Family Data Sheet
Pin Information Summary
iCE40LP384 iCE40LP640 iCE40LP1K
SG32 CM362CM492SWG16 SWG16 CM361, 2 CM491, 2 CM81 CB81 QN84 CM121 CB121
General Purpose I/O per Bank
Bank 0 6 4 10 3 3 4 10 17 17 17 24 24
Bank 1 5 7 7 0 0 7 7 15 16 17 25 21
Bank 2 044 1 144118111819
Bank 3 6 6 12 2 2 6 10 16 17 18 24 24
Configuration 444 4 444444 4 4
Total General Purpose Single
Ended I/O 21 25 37 10 10 25 35 63 62 67 95 92
High Current Outputs per Bank
Bank 0 000 3 300000 0 0
Bank 1 000 0 000000 0 0
Bank 2 000 0 000000 0 0
Bank 3 000 0 000000 0 0
Total Current Outputs 000 3 300000 0 0
Differential Inputs per Bank
Bank 0 000 0 000000 0 0
Bank 1 000 0 000000 0 0
Bank 2 000 0 000000 0 0
Bank 3 336 1 1358971212
Total Differential Inputs 336 1 1358971212
Dedicated Inputs per Bank
Bank 0 000 0 000000 0 0
Bank 1 000 0 000000 0 0
Bank 2 222 1 122222 2 2
Bank 3 000 0 000000 0 0
Configuration 000 0 000000 0 0
Total Dedicated Inputs 222 1 122222 2 2
Vccio Pins
Bank 0 111 1 111111 2 1
Bank 1 111 0 000111 2 1
Bank 2 111 1 111111 2 1
Bank 3 100 0 000111 2 2
VCC 112 1 112334 4 4
VCC_SPI 111 0 011111 1 1
VPP_2V5 1 1 1 0 011111 1 1
VPP_FAST3000 0 011101 1 1
VCCPLL 000 0 001100 1 1
GND 233 2 234584 8 11
NC 000 0 000000 0 3
Total Count of Bonded Pins 32 36 49 16 16 36 49 81 81 84 121 121
1. VCCIO0 and VCCIO1 are connected together.
2. VCCIO2 and VCCIO3 are connected together.
3. VPP_FAST
, used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 pack-
ages MUST have the VPP_FAST ball connected to VCCIO_0 ball externally.
4-4
Pinout Information
iCE40 LP/HX Family Data Sheet
Pin Information Summary (Continued)
iCE40LP4K iCE40LP8K iCE40HX1K
CM81 CM121 CM225 CM81 CM121 CM225 VQ100 CB132 TQ144
General Purpose I/O per Bank
Bank 0 172346172346192423
Bank 1 152142152142192525
Bank 2 9 1940 9 1940122020
Bank 3 182646182646182224
Configuration 444444444
Total General Purpose
Single Ended I/O 63 93 178 63 93 178 72 95 96
High Current Outputs per Bank
Bank 0 000000000
Bank 1 000000000
Bank 2 000000000
Bank 3 000000000
Total Differential Inputs 000000000
Differential Inputs per Bank
Bank 0 000000000
Bank 1 000000000
Bank 2 000000000
Bank 3 9 13 23 9 13 23 9 11 12
Total Differential Inputs 9 13 23 9 13 23 9 11 12
Dedicated Inputs per Bank
Bank 0 000000000
Bank 1 001001000
Bank 2 222222222
Bank 3 000000000
Configuration 000000000
Total Dedicated Inputs223223222
Vccio Pins
Bank 0 113113222
Bank 1 113113222
Bank 2 113113222
Bank 3 124124332
VCC 348348454
VCC_SPI 111111111
VPP_2V5 111111111
VPP_FAST1111111111
VCCPLL 122122011
GND 5 1218 5 1218101410
NC 0000000219
Total Count of Bonded
Pins 81 121 225 81 121 225 100 132 144
1. VPP_FAST
, used only for fast production programming, must be left floating or unconnected in applications.
4-5
Pinout Information
iCE40 LP/HX Family Data Sheet
Pin Information Summary (Continued)
iCE40HX4K iCE40HX8K
BG121 CB132 TQ144 BG121 CB132 CM225 CT256
General Purpose I/O per Bank
Bank 0 23 24 27 23 24 46 52
Bank 1 21 25 29 21 25 42 52
Bank 2 19 18 19 19 18 40 46
Bank 3 26 24 28 26 24 46 52
Configuration 4444444
Total General Purpose Single Ended I/O 93 95 107 93 95 178 206
High Current Outputs per Bank
Bank 0 0000000
Bank 1 0000000
Bank 2 0000000
Bank 3 0000000
Total Differential Inputs 0 0 0 0 0 0 0
Differential Inputs per Bank
Bank 0 0000000
Bank 1 0000000
Bank 2 0000000
Bank 3 13121413122326
Total Differential Inputs 13 12 14 13 12 23 26
Dedicated Inputs per Bank
Bank 0 0000000
Bank 1 0000000
Bank 2 2222222
Bank 3 0000000
Configuration 0 0 0 0 0 0 0
Total Dedicated Inputs 2 2 2 2 2 2 2
Vccio Pins
Bank 0 1221234
Bank 1 1221234
Bank 2 1221234
Bank 3 2322344
VCC 4544586
VCC_SPI 1111111
VPP_2V5 1111111
VPP_FAST11111111
VCCPLL 2222222
GND 12 15 11 12 15 18 20
NC 0060000
Total Count of Bonded Pins 121 132 144 121 132 225 256
1. VPP_FAST
, used only for fast production programming, must be left floating or unconnected in applications.
www.latticesemi.com 5-1 DS1040 Order Info_01.6
March 2017 Data Sheet DS1040
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
iCE40 Part Number Description
Ultra Low Power (LP) Devices
ICE40LPXXX XXXXXXX
Series
LP = Low Power Series
Logic Cells
384 = 384 Logic Cells
640 = 640 Logic Cells
1K = 1,280 Logic Cells
4K = 3,520 Logic Cells
8K = 7,680 Logic Cells
Package
SWG16 = 16-Ball WLCSP (0.35 mm Pitch)
CM36 = 36-Ball ucBGA (0.4 mm Pitch)
CM49 = 49-Ball ucBGA (0.4 mm Pitch)
CM81 = 81-Ball ucBGA (0.4 mm Pitch)
CB81 = 81-Ball csBGA (0.5 mm Pitch)
CM121 = 121-Ball ucBGA (0.4 mm Pitch)
CB121 = 121-Ball csBGA (0.5 mm Pitch)
CM225 = 225-Ball ucBGA (0.4 mm Pitch)
SG32 = 32-Pin QFN (0.5 mm Pitch)
QN84 = 84-Pin QFN (0.5 mm Pitch)
Device Family
iCE40 FPGA
Shipping Method
TR = Tape and Reel
TR50 = Tape and Reel 50 units
TR1K = Tape and Reel 1,000 units
High Performance (HX) Devices
ICE40HXXX XXXXXXX
Series
HX = High-Performance Series
Logic Cells
1K = 1,280 Logic Cells
4K = 3,520 Logic Cells
8K = 7,680 Logic Cells
Package
CB132 = 132-Ball csBGA (0.5 mm Pitch)
CM225 = 225-Ball ucBGA (0.4 mm Pitch)
CT256 = 256-Ball caBGA (0.8 mm Pitch)
TQ144 = 144-Pin TQFP (0.5 mm Pitch)
VQ100 = 100-Pin VQFP (0.5 mm Pitch)
BG121 = 121-Ball caBGA (0.8 mm Pitch)
Device Family
iCE40 mobileFPGA
Shipping Method
TR = Tape and Reel
All parts shipped in trays unless noted.
Ordering Information
iCE40 devices have top-side markings as shown below:
Note: Markings are abbreviated for small packages.
Industrial
iCE40HX8K
CM225
Datecode
iCE40 LP/HX Family Data Sheet
Ordering Information
5-2
Ordering Information
iCE40 LP/HX Family Data Sheet
Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging
Part Number LUTs Supply Voltage Package Leads Temp.
ICE40LP384-CM36 384 1.2 V Halogen-Free ucBGA 36 IND
ICE40LP384-CM36TR 384 1.2 V Halogen-Free ucBGA 36 IND
ICE40LP384-CM36TR1K 384 1.2 V Halogen-Free ucBGA 36 IND
ICE40LP384-CM49 384 1.2 V Halogen-Free ucBGA 49 IND
ICE40LP384-CM49TR 384 1.2 V Halogen-Free ucBGA 49 IND
ICE40LP384-CM49TR1K 384 1.2 V Halogen-Free ucBGA 49 IND
ICE40LP384-SG32 384 1.2 V Halogen-Free QFN 32 IND
ICE40LP384-SG32TR 384 1.2 V Halogen-Free QFN 32 IND
ICE40LP384-SG32TR1K 384 1.2 V Halogen-Free QFN 32 IND
ICE40LP640-SWG16TR 640 1.2 V Halogen-Free WLCSP 16 IND
ICE40LP640-SWG16TR50 640 1.2 V Halogen-Free WLCSP 16 IND
ICE40LP640-SWG16TR1K 640 1.2 V Halogen-Free WLCSP 16 IND
ICE40LP1K-SWG16TR 1280 1.2 V Halogen-Free WLCSP 16 IND
ICE40LP1K-SWG16TR50 1280 1.2 V Halogen-Free WLCSP 16 IND
ICE40LP1K-SWG16TR1K 1280 1.2 V Halogen-Free WLCSP 16 IND
ICE40LP1K-CM36 1280 1.2 V Halogen-Free ucBGA 36 IND
ICE40LP1K-CM36TR 1280 1.2 V Halogen-Free ucBGA 36 IND
ICE40LP1K-CM36TR1K 1280 1.2 V Halogen-Free ucBGA 36 IND
ICE40LP1K-CM49 1280 1.2 V Halogen-Free ucBGA 49 IND
ICE40LP1K-CM49TR 1280 1.2 V Halogen-Free ucBGA 49 IND
ICE40LP1K-CM49TR1K 1280 1.2 V Halogen-Free ucBGA 49 IND
ICE40LP1K-CM81 1280 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP1K-CM81TR 1280 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP1K-CM81TR1K 1280 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP1K-CB81 1280 1.2 V Halogen-Free csBGA 81 IND
ICE40LP1K-CB81TR 1280 1.2 V Halogen-Free csBGA 81 IND
ICE40LP1K-CB81TR1K 1280 1.2 V Halogen-Free csBGA 81 IND
ICE40LP1K-CM121 1280 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP1K-CM121TR 1280 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP1K-CM121TR1K 1280 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP1K-CB121 1280 1.2 V Halogen-Free csBGA 121 IND
ICE40LP1K-QN84 1280 1.2 V Halogen-Free QFN 84 IND
ICE40LP4K-CM81 3520 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP4K-CM81TR 3520 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP4K-CM81TR1K 3520 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP4K-CM121 3520 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP4K-CM121TR 3520 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP4K-CM121TR1K 3520 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP4K-CM225 3520 1.2 V Halogen-Free ucBGA 225 IND
ICE40LP8K-CM81 7680 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP8K-CM81TR 7680 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP8K-CM81TR1K 7680 1.2 V Halogen-Free ucBGA 81 IND
ICE40LP8K-CM121 7680 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP8K-CM121TR 7680 1.2 V Halogen-Free ucBGA 121 IND
5-3
Ordering Information
iCE40 LP/HX Family Data Sheet
High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging
ICE40LP8K-CM121TR1K 7680 1.2 V Halogen-Free ucBGA 121 IND
ICE40LP8K-CM225 7680 1.2 V Halogen-Free ucBGA 225 IND
Part Number LUTs Supply Voltage Package Leads Temp.
ICE40HX1K-CB132 1280 1.2 V Halogen-Free csBGA 132 IND
ICE40HX1K-VQ100 1280 1.2 V Halogen-Free VQFP 100 IND
ICE40HX1K-TQ144 1280 1.2 V Halogen-Free TQFP 144 IND
ICE40HX4K-BG121 3520 1.2 V Halogen-Free caBGA 121 IND
ICE40HX4K-BG121TR 3520 1.2 V Halogen-Free caBGA 121 IND
ICE40HX4K-CB132 3520 1.2 V Halogen-Free csBGA 132 IND
ICE40HX4K-TQ144 3520 1.2 V Halogen-Free TQFP 144 IND
ICE40HX8K-BG121 7680 1.2 V Halogen-Free caBGA 121 IND
ICE40HX8K-BG121TR 7680 1.2 V Halogen-Free caBGA 121 IND
ICE40HX8K-CB132 7680 1.2 V Halogen-Free csBGA 132 IND
ICE40HX8K-CM225 7680 1.2 V Halogen-Free ucBGA 225 IND
ICE40HX8K-CT256 7680 1.2 V Halogen-Free caBGA 256 IND
Part Number LUTs Supply Voltage Package Leads Temp.
March 2017 Data Sheet DS1040
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 6-1 DS1040 Further Info_01.1
For Further Information
A variety of technical notes for the iCE40 family are available on the Lattice web site.
TN1248, iCE40 Programming and Configuration
TN1250, Memory Usage Guide for iCE40 Devices
TN1251, iCE40 sysCLOCK PLL Design and Usage Guide
TN1252, iCE40 Hardware Checklist
TN1253, Using Differential I/O (LVDS, Sub-LVDS) in iCE40 Devices
TN1074, PCB Layout Recommendations for BGA Packages
iCE40 Pinout Files
Thermal Management document
Lattice design tools
•IBIS
Package Diagrams Data Sheet
Schematic Symbols
iCE40 LP/HX Family Data Sheet
Supplemental Information
October 2017 Data Sheet DS1040
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 7-1 DS1040 Revision History
Date Version Section Change Summary
October 2017 3.4 Pinout Information Updated Pin Information Summary section.
Modified the dedicated inputs for Bank 1 of iCE40HX1K (CB132,
TQ144), iCE40HX4K (CB132, TQ144) and iCE40HX8K (CB132,
CM225, CT256).
March 2017 3.3 Introduction Updated Features section. Added 121-ball caBGA package for ICE40
HX4K/8K to Table 1-1, iCE40 Family Selection Guide.
Architecture Updated PLB Blocks section. Changed “subtracters” to “subtractors” in
the Carry Logic description.
Updated Clock/Control Distribution Network section. Switched the
“Clock Enable“ and the “Reset” headings in Table 2-2, Global Buffer
(GBUF) Connections to Programmable Logic Blocks.
Pinout Information Updated Pin Information Summary section. Added BG121information
under iCE40HX4K and iCE40HX8K.
Ordering Information Updated iCE40 Part Number Description section. Added Shipping
Method and BG121 package under High Performance (HX) Devices.
Updated Ordering Information section. Added part numbers for BG121
under High-Performance Industrial Grade Devices, Halogen Free
(RoHS) Packaging.
Supplemental
Information
Corrected reference to “Package Diagrams Data Sheet”.
October 2015 3.2 Introduction Updated Features section. Added footnote to 16 WLCSP Programma-
ble I/O: Max Inputs (LVDS25) in Table 1-1, iCE40 Family Selection
Guide.
DC and Switching
Characteristics
Updated sysCLOCK PLL Timing section. Changed tDT conditions.
Updated Programming NVCM Supply Current – LP Devices section.
Changed IPP_2V5 and ICCIO, ICC_SPI units.
March 2015 3.1 DC and Switching
Characteristics
Updated sysIO Single-Ended DC Electrical Characteristics section.
Changed LVCMOS 3.3 and LVCMOS 2. 5 VOH Min. (V) from 0.5 to 0.4.
July 2014 3.0 DC and Switching
Characteristics
Revised and/or added Typ. VCC data in the following sections.
Static Supply Current – LP Devices
Static Supply Current – HX Devices
Programming NVCM Supply Current – LP Devices
Programming NVCM Supply Current – HX Devices
In each section table, the footnote indicating Advanced device status
was removed.
Pinout Information Updated Pin Information Summary section. Added footnote 1 to CM49
under iCE40LP1K.
April 2014 02.9 Ordering Information Changed “i” to “I” in part number description and ordering part numbers.
Added part numbers to the Ultra Low Power Industrial Grade Devices,
Halogen Free (RoHS) Packaging table.
iCE40 LP/HX Family Data Sheet
Revision History
7-2
Revision History
iCE40 LP/HX Family Data Sheet
February 2014 02.8 Introduction Updated Features section.
Corrected standby power units.
Included High Current LED Drivers
Updated Table 1-1, iCE40 Family Selection Guide.
Removed LP384 Programmable I/O for 81 ucBGA package.
Architecture Updated Supported Standards section. Added information on High Cur-
rent LED drivers.
DC and Switching
Characteristics
Corrected typos.
Added footnote to the Peak Startup Supply Current – LP Devices table.
Ordering Information Updated part number description in the Ultra Low Power (LP) Devices
section.
Added part numbers to the Ultra Low Power Industrial Grade Devices,
Halogen Free (RoHS) Packaging table.
October 2013 02.7 Introduction Updated Features list and iCE40 Family Selection Guide table.
Architecture Revised iCE40-1K device to iCE40LP/HX1K device.
DC and Switching
Characteristics
Added iCE40LP640 device information.
Pinout Information Added iCE40LP640 and iCE40LP1K information.
Ordering Information Added iCE40LP640 and iCE40LP1K information.
September 2013 02.6 DC and Switching
Characteristics
Updated Absolute Maximum Ratings section.
Updated sysCLOCK PLL Timing – Preliminary table.
Pinout Information Updated Pin Information Summary table.
August 2013 02.5 Introduction Updated the iCE40 Family Selection Guide table.
DC and Switching
Characteristics
Updated the following tables:
Absolute Maximum Ratings
Power-On-Reset Voltage Levels
Static Supply Current – LP Devices
Static Supply Current – HX Devices
Programming NVCM Supply Current – LP Devices
Programming NVCM Supply Current – HX Devices
Peak Startup Supply Current – LP Devices
sysIO Recommended Operating Conditions
Typical Building Block Function Performance – HX Devices
iCE40 External Switching Characteristics – HX Devices
sysCLOCK PLL Timing – Preliminary
SPI Master or NVCM Configuration Time
Pinout Information Updated the Pin Information Summary table.
July 2013 02.4 Introduction Updated the iCE40 Family Selection Guide table.
DC and Switching
Characteristics
Updated the sysCONFIG Port Timing Specifications table.
Updated footnote in DC Electrical Characteristics table.
GDDR tables removed. Support to be provided in a technical note.
Pinout Information Updated the Pin Information Summary table.
Ordering Information Updated the top-side markings figure.
Updated the Ultra Low Power Industrial Grade Devices, Halogen Free
(RoHS) Packaging table.
May 2013 02.3 DC and Switching
Characteristics
Added new data from Characterization.
Date Version Section Change Summary
7-3
Revision History
iCE40 LP/HX Family Data Sheet
April 2013 02.2 Introduction Added the LP8K 81 ucBGA.
Architecture Corrected typos.
DC and Switching
Characteristics
Corrected typos.
Added 7:1 LVDS waveforms.
Pinout Information Corrected typos in signal descriptions.
Added the LP8K 81 ucBGA.
Ordering Information Added the LP8K 81 ucBGA.
March 2013 02.1 DC and Switching
Characteristics
Recommended operating conditions added requirement for Master SPI.
Updated Recommended Operating Conditions for VPP_2V5.
Updated Power-On-Reset Voltage Levels and sequence requirements.
Updated Static Supply Current conditions.
Changed unit for tSKEW_IO from ns to ps.
Updated range of CCLK fMAX.
Ordering Information Updated ordering information to include tape and reel part numbers.
September 2012 02.0 Merged SiliconBlue iCE40 LP and HX data sheets and updated to Lat-
tice format.
01.31 Updated Table 1.
01.3 Production release.
Updated notes on Table 3: Recommended Operating Conditions.
Updated values in Table 4, Table 5, Table 12, Table 13 and Table 17.
01.21 Updated Figure 3 and Figure 4 to specify iCE40.
Aug 2012 01.2 Updated company name.
July 2011 01.1 Moved package specifications to iCE40 pinout Excel files.
Updated Table 1 maximum I/Os.
01.01 Added 640, 1K and 4K to Table 13 configuration times. Updated Table 1
maximum I/Os.
01.0 Initial release.
Date Version Section Change Summary

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