Cyclone IV Device Handbook

Intel FPGAs/Altera

View All Related Products | Download PDF Datasheet

Datasheet

101 Innovation Drive
San Jose, CA 95134
www.altera.com
CYIV-5V1-2.2
Volume 1
Cyclone IV Device Handbook,
Cyclone IV Device Handbook, Volume 1
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
ISO
9001:2008
Registered
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Section I. Device Core
Chapter 1. Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Package Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Cyclone IV Device Family Speed Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Cyclone IV Device Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
FPGA Core Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
High-Speed Transceivers (Cyclone IV GX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Hard IP for PCI Express (Cyclone IV GX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Reference and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13
Chapter 2. Logic Elements and Logic Array Blocks in Cyclone IV Devices
Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
LE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Chapter 3. Memory Blocks in Cyclone IV Devices
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Mixed-Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Single-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
iv Contents
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Shift Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
FIFO Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Input or Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Read or Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Single-Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Read-During-Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16
Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17
Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18
Chapter 4. Embedded Multipliers in Cyclone IV Devices
Embedded Multiplier Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Multiplier Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
18-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9-Bit Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Chapter 5. Clock Networks and PLLs in Cyclone IV Devices
Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
GCLK Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
GCLK Network Clock Source Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
GCLK Network Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
clkena Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
PLLs in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Cyclone IV PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
External Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23
Source-Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23
No Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24
Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–25
Deterministic Latency Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26
Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26
Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26
Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28
Automatic Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28
Manual Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29
Contents v
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Manual Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30
Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30
Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32
Phase Shift Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32
PLL Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–33
PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34
PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–34
Post-Scale Counters (C0 to C4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–36
Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–37
Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–38
Bypassing a PLL Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Dynamic Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Spread-Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–41
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–41
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–42
Section II. I/O Interfaces
Chapter 6. I/O Features in Cyclone IV Devices
Cyclone IV I/O Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
I/O Element Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
PCI-Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
OCT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
On-Chip Series Termination Without Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Termination Scheme for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Voltage-Referenced I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Differential I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22
External Memory Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Pad Placement and DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Pad Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
Clock Pins Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23
High-Speed I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24
High-Speed I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–28
High Speed Serial Interface (HSSI) Input Reference Clock Support . . . . . . . . . . . . . . . . . . . . . . . . . 6–28
LVDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–29
Designing with LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–30
BLVDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–30
Designing with BLVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–31
RSDS, Mini-LVDS, and PPDS I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . 6–32
Designing with RSDS, Mini-LVDS, and PPDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–32
LVPECL I/O Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–34
Differential SSTL I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35
vi Contents
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Differential HSTL I/O Standard Support in Cyclone IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35
True Differential Output Buffer Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35
Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35
High-Speed I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36
Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
Differential Pad Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37
Board Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38
Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–39
Chapter 7. External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
Data and Data Clock/Strobe Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Optional Parity, DM, and Error Correction Coding Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11
Address and Control/Command Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
Memory Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
Cyclone IV Devices Memory Interfaces Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
DDR Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
DDR Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14
OCT with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16
Section III. System Integration
Chapter 8. Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
Configuration Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power-On Reset (POR) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
Configuration File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
Configuration and JTAG Pin I/O Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6
Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7
Configuration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8
AS Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
Single-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10
Multi-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13
Configuring Multiple Cyclone IV Devices with the Same Design . . . . . . . . . . . . . . . . . . . . . . . . . 8–14
Guidelines for Connecting a Serial Configuration Device to Cyclone IV Devices for an AS Interface
8–18
Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19
AP Configuration (Supported Flash Memories) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–21
AP Configuration Supported Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–22
Single-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–23
Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–25
Byte-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–26
Contents vii
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Word-Wide Multi-Device AP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–26
Guidelines for Connecting Parallel Flash to Cyclone IV E Devices for an AP Interface . . . . . . . 8–28
Configuring With Multiple Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–28
Estimating AP Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–30
Programming Parallel Flash Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31
PS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–32
PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33
PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36
PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–37
FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–40
FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–40
FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–44
JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–45
Configuring Cyclone IV Devices with Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–52
Configuring Cyclone IV Devices with the JRunner Software Driver . . . . . . . . . . . . . . . . . . . . . . 8–52
Combining JTAG and AS Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–53
Programming Serial Configuration Devices In-System with the JTAG Interface . . . . . . . . . . . . 8–55
JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–57
Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–62
Remote System Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–69
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–69
Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–70
Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–70
Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–71
Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–71
Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–74
Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–75
Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–78
User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–79
Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–80
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–80
Chapter 9. SEU Mitigation in Cyclone IV Devices
Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
Automated SEU Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
CRC_ERROR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5
Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6
Accessing Error Detection Block Through User Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
Recovering from CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
Chapter 10. JTAG Boundary-Scan Testing for Cyclone IV Devices
IEEE Std. 1149.6 Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
EXTEST_PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
EXTEST_TRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7
viii Contents
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Chapter 11. Power Requirements for Cyclone IV Devices
External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Devices Driven Before Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
I/O Pins Remain Tri-stated During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Hot-socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Chapter Revision Dates
The chapters in this document, Cyclone IV Device Handbook,, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1. Cyclone IV FPGA Device Family Overview
Revised: March 2016
Part Number: CYIV-51001-2.0
Chapter 2. Logic Elements and Logic Array Blocks in Cyclone IV Devices
Revised: November 2009
Part Number: CYIV-51002-1.0
Chapter 3. Memory Blocks in Cyclone IV Devices
Revised: November 2011
Part Number: CYIV-51003-1.1
Chapter 4. Embedded Multipliers in Cyclone IV Devices
Revised: February 2010
Part Number: CYIV-51004-1.1
Chapter 5. Clock Networks and PLLs in Cyclone IV Devices
Revised: October 2012
Part Number: CYIV-51005-2.4
Chapter 6. I/O Features in Cyclone IV Devices
Revised: March 2016
Part Number: CYIV-51006-2.7
Chapter 7. External Memory Interfaces in Cyclone IV Devices
Revised: March 2016
Part Number: CYIV-51007-2.6
Chapter 8. Configuration and Remote System Upgrades in Cyclone IV Devices
Revised: May 2013
Part Number: CYIV-51008-1.7
Chapter 9. SEU Mitigation in Cyclone IV Devices
Revised: May 2013
Part Number: CYIV-51009-1.3
Chapter 10. JTAG Boundary-Scan Testing for Cyclone IV Devices
Revised: December 2013
Part Number: CYIV-51010-1.3
Chapter 11. Power Requirements for Cyclone IV Devices
Revised: May 2013
Part Number: CYIV-51011-1.3
xChapter Revision Dates
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Additional Information
This chapter provides additional information about the document and Altera.
About this Handbook
This handbook provides comprehensive information about the Altera® Cyclone®IV
family of devices.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Typographic Conventions
The following table shows the typographic conventions this document uses.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training Website www.altera.com/training
Email custrain@altera.com
Product literature Website www.altera.com/literature
Nontechnical support (general) Email nacomp@altera.com
(software licensing) Email authorization@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
Visual Cue Meaning
Bold Type with Initial Capital
Letters
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.
italic type
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
“Subheading Title” Quotation marks indicate references to sections in a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Info–2 Additional Information
Typographic Conventions
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Courier type
Indicates signal, port, register, bit, block, and primitive names. For example,
data1
,
tdi
, and
input
. The suffix
n
denotes an active-low signal. For example,
resetn
.
Indicates command line commands and anything that must be typed exactly as it
appears. For example,
c:\qdesigns\tutorial\chiptrip.gdf
.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword
SUBDESIGN
), and logic function names (for
example,
TRI
).
r An angled arrow instructs you to press the Enter key.
1., 2., 3., and
a., b., c., and so on
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
Bullets indicate a list of items when the sequence of the items is not important.
1The hand points to information that requires special attention.
h The question mark directs you to a software help system with related information.
f The feet direct you to another document or website with related information.
m The multimedia icon directs you to a related multimedia presentation.
cA caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
w A warning calls attention to a condition or possible situation that can cause you
injury.
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
Visual Cue Meaning
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Section I. Device Core
This section provides a complete overview of all features relating to the Cyclone®IV
device family, which is the most architecturally advanced, high-performance,
low-power FPGA in the marketplace. This section includes the following chapters:
Chapter 1, Cyclone IV FPGA Device Family Overview
Chapter 2, Logic Elements and Logic Array Blocks in Cyclone IV Devices
Chapter 3, Memory Blocks in Cyclone IV Devices
Chapter 4, Embedded Multipliers in Cyclone IV Devices
Chapter 5, Clock Networks and PLLs in Cyclone IV Devices
Revision History
Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the complete handbook.
I–2 Section I: Device Core
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
CYIV-51001-2.0
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Cyclone IV Device Handbook,
Volume 1
March 2016
Feedback Subscribe
ISO
9001:2008
Registered
1. Cyclone IV FPGA Device Family
Overview
Altera’s new Cyclone®IV FPGA device family extends the Cyclone FPGA series
leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a
transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive
applications, enabling system designers to meet increasing bandwidth requirements
while lowering costs.
Built on an optimized low-power process, the Cyclone IV device family offers the
following two variants:
Cyclone IV E—lowest power, high functionality with the lowest cost
Cyclone IV GXlowest power and lowest cost FPGAs with 3.125 Gbps
transceivers
1Cyclone IV E devices are offered in core voltage of 1.0 V and 1.2 V.
fFor more information, refer to the Power Requirements for Cyclone IV Devices
chapter.
Providing power and cost savings without sacrificing performance, along with a
low-cost integrated transceiver option, Cyclone IV devices are ideal for low-cost,
small-form-factor applications in the wireless, wireline, broadcast, industrial,
consumer, and communications industries.
Cyclone IV Device Family Features
The Cyclone IV device family offers the following features:
Low-cost, low-power FPGA fabric:
6K to 150K logic elements
Up to 6.3 Mb of embedded memory
Up to 360 18 × 18 multipliers for DSP processing intensive applications
Protocol bridging applications for under 1.5 W total power
March 2016
CYIV-51001-2.0
1–2 Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Features
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Cyclone IV GX devices offer up to eight high-speed transceivers that provide:
Data rates up to 3.125 Gbps
8B/10B encoder/decoder
8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer
(PCS) interface
Byte serializer/deserializer (SERDES)
Word aligner
Rate matching FIFO
TX bit slipper for Common Public Radio Interface (CPRI)
Electrical idle
Dynamic channel reconfiguration allowing you to change data rates and
protocols on-the-fly
Static equalization and pre-emphasis for superior signal integrity
150 mW per channel power consumption
Flexible clocking structure to support multiple protocols in a single transceiver
block
Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe)
Gen 1:
×1, ×2, and ×4 lane configurations
End-point and root-port configurations
Up to 256-byte payload
One virtual channel
2 KB retry buffer
4 KB receiver (Rx) buffer
Cyclone IV GX devices offer a wide range of protocol support:
PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)
Gigabit Ethernet (1.25 Gbps)
CPRI (up to 3.072 Gbps)
XAUI (3.125 Gbps)
Triple rate serial digital interface (SDI) (up to 2.97 Gbps)
Serial RapidIO (3.125 Gbps)
Basic mode (up to 3.125 Gbps)
V-by-One (up to 3.0 Gbps)
DisplayPort (2.7 Gbps)
Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)
OBSAI (up to 3.072 Gbps)
Chapter 1: Cyclone IV FPGA Device Family Overview 1–3
Device Resources
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Up to 532 user I/Os
LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx
Support for DDR2 SDRAM interfaces up to 200 MHz
Support for QDRII SRAM and DDR SDRAM up to 167 MHz
Up to eight phase-locked loops (PLLs) per device
Offered in commercial and industrial temperature grades
Device Resources
Table 11 lists Cyclone IV E device resources.
Table 1–1. Resources for the Cyclone IV E Device Family
Resources
EP4CE6
EP4CE10
EP4CE15
EP4CE22
EP4CE30
EP4CE40
EP4CE55
EP4CE75
EP4CE115
Logic elements (LEs) 6,272 10,320 15,408 22,320 28,848 39,600 55,856 75,408 114,480
Embedded memory
(Kbits) 270 414 504 594 594 1,134 2,340 2,745 3,888
Embedded 18 × 18
multipliers 15 23 56 66 66 116 154 200 266
General-purpose PLLs22444444 4
Global Clock Networks 10 10 20 20 20 20 20 20 20
User I/O Banks 88888888 8
Maximum user I/O (1) 179 179 343 153 532 532 374 426 528
Note to Table 1–1:
(1) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
1–4 Chapter 1: Cyclone IV FPGA Device Family Overview
Device Resources
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Table 12 lists Cyclone IV GX device resources.
Table 1–2. Resources for the Cyclone IV GX Device Family
Resources
EP4CGX15
EP4CGX22
EP4CGX30
(1)
EP4CGX30
(2)
EP4CGX50
(3)
EP4CGX75
(3)
EP4CGX110
(3)
EP4CGX150
(3)
Logic elements (LEs) 14,400 21,280 29,440 29,440 49,888 73,920 109,424 149,760
Embedded memory (Kbits) 540 756 1,080 1,080 2,502 4,158 5,490 6,480
Embedded 18 × 18 multipliers 0 40 80 80 140 198 280 360
General purpose PLLs 1 2 2 4 (4) 4 (4) 4 (4) 4 (4) 4 (4)
Multipurpose PLLs 2 (5) 2 (5) 2 (5) 2 (5) 4 (5) 4 (5) 4 (5) 4 (5)
Global clock networks 20 20 20 30 30 30 30 30
High-speed transceivers (6) 24448888
Transceiver maximum data rate
(Gbps) 2.5 2.5 2.5 3.125 3.125 3.125 3.125 3.125
PCIe (PIPE) hard IP blocks 11111111
User I/O banks 9 (7) 9 (7) 9 (7) 11 (8) 11 (8) 11 (8) 11 (8) 11 (8)
Maximum user I/O (9) 72 150 150 290 310 310 475 475
Notes to Table 1–2:
(1) Applicable for the F169 and F324 packages.
(2) Applicable for the F484 package.
(3) Only two multipurpose PLLs for F484 package.
(4) Two of the general purpose PLLs are able to support transceiver clocking. For more information, refer to the Clock Networks and PLLs in
Cyclone IV Devices chapter.
(5) You can use the multipurpose PLLs for general purpose clocking when they are not used to clock the transceivers. For more information, refer
to the Clock Networks and PLLs in Cyclone IV Devices chapter.
(6) If PCIe 1, you can use the remaining transceivers in a quad for other protocols at the same or different data rates.
(7) Including one configuration I/O bank and two dedicated clock input I/O banks for HSSI reference clock input.
(8) Including one configuration I/O bank and four dedicated clock input I/O banks for HSSI reference clock input.
(9) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
Chapter 1: Cyclone IV FPGA Device Family Overview 1–5
Package Matrix
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Package Matrix
Table 1–3 lists Cyclone IV E device package offerings.
Table 1–3. Package Offerings for the Cyclone IV E Device Family (1), (2)
Package E144 M164 M256 U256 F256 F324 U484 F484 F780
Size (mm) 22 × 22 8 × 8 9 x 9 14 × 14 17 × 17 19 x 19 19 × 19 23 × 23 29 × 29
Pitch (mm) 0.5 0.5 0.5 0.8 1.0 1.0 0.8 1.0 1.0
Device
User I/O
LVDS (3)
User I/O
LVDS (3)
User I/O
LVDS (3)
User I/O
LVDS (3)
User I/O
LVDS (3)
User I/O
LVDS (3)
User I/O
LVDS (3)
User I/O
LVDS (3)
User I/O
LVDS (3)
EP4CE6 91 21 — — — — 179 66 179 66 — — — — — — — —
EP4CE10 91 21 — — — — 179 66 179 66 — — — — — — — —
EP4CE15 81 18 89 21 165 53 165 53 165 53 — 343 137 —
EP4CE22 79 17 — — — — 153 52 153 52 — — — — — — — —
EP4CE30 — — — — — — — — — 193 68 — — 328 124 532 224
EP4CE40 193 68 328 124 328 124 532 224
EP4CE55 — — — — — — — — — — — 324 132 324 132 374 160
EP4CE75 — — — — — — — — — — — 292 110 292 110 426 178
EP4CE115 — — — — — — — — — — — — — — 280 103 528 230
Notes to Table 1–3:
(1) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane of your PCB. Use this exposed pad for electrical
connectivity and not for thermal purposes.
(2) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more information, refer to the I/O
Management chapter in volume 2 of the Quartus II Handbook.
(3) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter.
1–6 Chapter 1: Cyclone IV FPGA Device Family Overview
Package Matrix
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Table 1–4 lists Cyclone IV GX device package offerings, including I/O and transceiver counts.
Table 1–4. Package Offerings for the Cyclone IV GX Device Family (1)
Package F169 F324 F484 F672 F896
Size (mm) 14 × 14 19 × 19 23 × 23 27 × 27 31 × 31
Pitch (mm) 1.0 1.0 1.0 1.0 1.0
Device
User I/O
LVDS (2)
XCVRs
User I/O
LVDS (2)
XCVRs
User I/O
LVDS (2)
XCVRs
User I/O
LVDS (2)
XCVRs
User I/O
LVDS (2)
XCVRs
EP4CGX15 72 25 2 — — — —
EP4CGX22 72 25 2 150 64 4 — — — —
EP4CGX30 72 25 2 150 64 4 290 130 4 — — — —
EP4CGX50 — — 290 130 4 310 140 8 — —
EP4CGX75 — — 290 130 4 310 140 8 — —
EP4CGX110 — — — — 270 120 4 393 181 8 475 220 8
EP4CGX150 — — — — 270 120 4 393 181 8 475 220 8
Note to Table 1–4:
(1) Use the Pin Migration View window in Pin Planner of the Quartus II software to verify the pin migration compatibility when you perform device migration. For more
information, refer to the I/O Management chapter in volume 2 of the Quartus II Handbook.
(2) This includes both dedicated and emulated LVDS pairs. For more information, refer to the I/O Features in Cyclone IV Devices chapter.
Chapter 1: Cyclone IV FPGA Device Family Overview 1–7
Cyclone IV Device Family Speed Grades
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Cyclone IV Device Family Speed Grades
Table 15 lists the Cyclone IV GX devices speed grades.
Table 16 lists the Cyclone IV E devices speed grades.
Table 1–5. Speed Grades for the Cyclone IV GX Device Family
Device F169 F324 F484 F672 F896
EP4CGX15 C6, C7, C8, I7
EP4CGX22 C6, C7, C8, I7 C6, C7, C8, I7
EP4CGX30 C6, C7, C8, I7 C6, C7, C8, I7 C6, C7, C8, I7
EP4CGX50 C6, C7, C8, I7 C6, C7, C8, I7
EP4CGX75 C6, C7, C8, I7 C6, C7, C8, I7
EP4CGX110 C7, C8, I7 C7, C8, I7 C7, C8, I7
EP4CGX150 C7, C8, I7 C7, C8, I7 C7, C8, I7
Table 1–6. Speed Grades for the Cyclone IV E Device Family (1),(2)
Device E144 M164 M256 U256 F256 F324 U484 F484 F780
EP4CE6
C8L, C9L, I8L
C6, C7, C8, I7,
A7
——I7N
C8L, C9L, I8L
C6, C7, C8, I7,
A7
—— —
EP4CE10
C8L, C9L, I8L
C6, C7, C8, I7,
A7
——I7N
C8L, C9L, I8L
C6, C7, C8, I7,
A7
—— —
EP4CE15 C8L, C9L, I8L
C6, C7, C8, I7 I7NC7N, I7NI7N
C8L, C9L, I8L
C6, C7, C8, I7,
A7
——
C8L, C9L, I8L
C6, C7, C8, I7,
A7
EP4CE22
C8L, C9L, I8L
C6, C7, C8, I7,
A7
——I7N
C8L, C9L, I8L
C6, C7, C8, I7,
A7
—— —
EP4CE30 A7N —
C8L, C9L, I8L
C6, C7, C8, I7,
A7
C8L, C9L, I8L
C6, C7, C8, I7
EP4CE40 A7N I7N
C8L, C9L, I8L
C6, C7, C8, I7,
A7
C8L, C9L, I8L
C6, C7, C8, I7
EP4CE55 — — — — — I7N C8L, C9L, I8L
C6, C7, C8, I7
C8L, C9L, I8L
C6, C7, C8, I7
EP4CE75 — — — — — I7N C8L, C9L, I8L
C6, C7, C8, I7
C8L, C9L, I8L
C6, C7, C8, I7
EP4CE115 — — — — — C8L, C9L, I8L
C7, C8, I7
C8L, C9L, I8L
C7, C8, I7
Notes to Table 1–6:
(1) C8L, C9L, and I8L speed grades are applicable for the 1.0-V core voltage.
(2) C6, C7, C8, I7, and A7 speed grades are applicable for the 1.2-V core voltage.
1–8 Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Architecture
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Cyclone IV Device Family Architecture
This section describes Cyclone IV device architecture and contains the following
topics:
“FPGA Core Fabric”
“I/O Features”
“Clock Management”
“External Memory Interfaces”
“Configuration”
“High-Speed Transceivers (Cyclone IV GX Devices Only)”
“Hard IP for PCI Express (Cyclone IV GX Devices Only)”
FPGA Core Fabric
Cyclone IV devices leverage the same core fabric as the very successful Cyclone series
devices. The fabric consists of LEs, made of 4-input look up tables (LUTs), memory
blocks, and multipliers.
Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAM
memory. You can configure the M9K blocks as single port, simple dual port, or true
dual port RAM, as well as FIFO buffers or ROM. They can also be configured to
implement any of the data widths in Table 17.
The multiplier architecture in Cyclone IV devices is the same as in the existing
Cyclone series devices. The embedded multiplier blocks can implement an 18 × 18 or
two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP
including finite impulse response (FIR), fast Fourier transform (FFT), and numerically
controlled oscillator (NCO) functions for use with the multiplier blocks. The
Quartus®II design software’s DSP Builder tool integrates MathWorks Simulink and
MATLAB design environments for a streamlined DSP design flow.
fFor more information, refer to the Logic Elements and Logic Array Blocks in Cyclone IV
Devices, Memory Blocks in Cyclone IV Devices, and Embedded Multipliers in Cyclone IV
Devices chapters.
Table 1–7. M9K Block Data Widths for Cyclone IV Device Family
Mode Data Width Configurations
Single port or simple dual port ×1, ×2, ×4, ×8/9, ×16/18, and ×32/36
True dual port ×1, ×2, ×4, ×8/9, and ×16/18
Chapter 1: Cyclone IV FPGA Device Family Overview 1–9
Cyclone IV Device Family Architecture
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
I/O Features
Cyclone IV device I/O supports programmable bus hold, programmable pull-up
resistors, programmable delay, programmable drive strength, programmable
slew-rate control to optimize signal integrity, and hot socketing. Cyclone IV devices
support calibrated on-chip series termination (Rs OCT) or driver impedance matching
(Rs) for single-ended I/O standards. In Cyclone IV GX devices, the high-speed
transceiver I/Os are located on the left side of the device. The top, bottom, and right
sides can implement general-purpose user I/Os.
Table 18 lists the I/O standards that Cyclone IV devices support.
The LVDS SERDES is implemented in the core of the device using logic elements.
fFor more information, refer to the I/O Features in Cyclone IV Devices chapter.
Clock Management
Cyclone IV devices include up to 30 global clock (GCLK) networks and up to eight
PLLs with five outputs per PLL to provide robust clock management and synthesis.
You can dynamically reconfigure Cyclone IV device PLLs in user mode to change the
clock frequency or phase.
Cyclone IV GX devices support two types of PLLs: multipurpose PLLs and general-
purpose PLLs:
Use multipurpose PLLs for clocking the transceiver blocks. You can also use them
for general-purpose clocking when they are not used for transceiver clocking.
Use general purpose PLLs for general-purpose applications in the fabric and
periphery, such as external memory interfaces. Some of the general purpose PLLs
can support transceiver clocking.
fFor more information, refer to the Clock Networks and PLLs in Cyclone IV Devices
chapter.
External Memory Interfaces
Cyclone IV devices support SDR, DDR, DDR2 SDRAM, and QDRII SRAM interfaces
on the top, bottom, and right sides of the device. Cyclone IV E devices also support
these interfaces on the left side of the device. Interfaces may span two or more sides of
the device to allow more flexible board design. The Altera® DDR SDRAM memory
interface solution consists of a PHY interface and a memory controller. Altera supplies
the PHY IP and you can use it in conjunction with your own custom memory
controller or an Altera-provided memory controller. Cyclone IV devices support the
use of error correction coding (ECC) bits on DDR and DDR2 SDRAM interfaces.
Table 1–8. I/O Standards Support for the Cyclone IV Device Family
Type I/O Standard
Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X
Differential I/O SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS
1–10 Chapter 1: Cyclone IV FPGA Device Family Overview
Cyclone IV Device Family Architecture
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
fFor more information, refer to the External Memory Interfaces in Cyclone IV Devices
chapter.
Configuration
Cyclone IV devices use SRAM cells to store configuration data. Configuration data is
downloaded to the Cyclone IV device each time the device powers up. Low-cost
configuration options include the Altera EPCS family serial flash devices and
commodity parallel flash configuration options. These options provide the flexibility
for general-purpose applications and the ability to meet specific configuration and
wake-up time requirements of the applications.
Table 19 lists which configuration schemes are supported by Cyclone IV devices.
IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pins
support IEEE 1149.1 (JTAG) for boundary scan testing.
fFor more information, refer to the JTAG Boundary-Scan Testing for Cyclone IV Devices
chapter.
For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you
must use passive serial (PS) configuration mode for the EP4CGX15/22/30 devices
and use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 and
EP4CGX50/75/110/150 devices.
fFor more information, refer to the Configuration and Remote System Upgrades in
Cyclone IV Devices chapter.
The cyclical redundancy check (CRC) error detection feature during user mode is
supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only
supported for the devices with the core voltage of 1.2 V.
fFor more information about CRC error detection, refer to the SEU Mitigation in
Cyclone IV Devices chapter.
High-Speed Transceivers (Cyclone IV GX Devices Only)
Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that
can operate independently. These blocks support multiple industry-standard
communication protocols, as well as Basic mode, which you can use to implement
your own proprietary protocols. Each transceiver channel has its own pre-emphasis
and equalization circuitry, which you can set at compile time to optimize signal
integrity and reduce bit error rates. Transceiver blocks also support dynamic
reconfiguration, allowing you to change data rates and protocols on-the-fly.
Table 1–9. Configuration Schemes for Cyclone IV Device Family
Devices Supported Configuration Scheme
Cyclone IV GX AS, PS, JTAG, and FPP (1)
Cyclone IV E AS, AP, PS, FPP, and JTAG
Note to Table 1–9:
(1) The FPP configuration scheme is only supported by the EP4CGX30F484 and EP4CGX50/75/110/150 devices.
Chapter 1: Cyclone IV FPGA Device Family Overview 1–11
Cyclone IV Device Family Architecture
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Figure 1–1 shows the structure of the Cyclone IV GX transceiver.
fFor more information, refer to the Cyclone IV Transceivers Architecture chapter.
Hard IP for PCI Express (Cyclone IV GX Devices Only)
Cyclone IV GX devices incorporate a single hard IP block for ×1, ×2, or ×4 PCIe (PIPE)
in each device. This hard IP block is a complete PCIe (PIPE) protocol solution that
implements the PHY-MAC layer, Data Link Layer, and Transaction Layer
functionality. The hard IP for the PCIe (PIPE) block supports root-port and end-point
configurations. This pre-verified hard IP block reduces risk, design time, timing
closure, and verification. You can configure the block with the Quartus II software’s
PCI Express Compiler, which guides you through the process step by step.
fFor more information, refer to the PCI Express Compiler User Guide.
Figure 1–1. Transceiver Channel for the Cyclone IV GX Device
RX Phase
Compensation
FIFO
TX Phase
Compensation
FIFO
Byte Ordering
Byte Deserializer
Byte Serializer
8B10B Decoder
8B10B Encoder
Rate Match FIFO
Receiver Channel PCS Receiver Channel
PMA
Word Aligner
rx_datain
Deserializer
CDR
Transmitter Channel PCS Transceiver Channel
PMA
tx_dataout
Serializer
PCI Express hard IP
FPGA
Fabric
PIPE Interface
1–12 Chapter 1: Cyclone IV FPGA Device Family Overview
Reference and Ordering Information
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
Reference and Ordering Information
Figure 1–2 shows the ordering codes for Cyclone IV GX devices.
Figure 1–3 shows the ordering codes for Cyclone IV E devices.
Figure 1–2. Packaging Ordering Information for the Cyclone IV GX Device
Family Signature
Transceiver Count
Package Type
Package Code
Operating Temperature
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
GX : 3-Gbps transceivers
EP4C : Cyclone IV
15 : 14,400 logic elements
22 : 21,280 logic elements
30 : 29,440 logic elements
50 : 49,888 logic elements
75 : 73,920 logic elements
110 : 109,424 logic elements
150 : 149,760 logic elements
B : 2
C : 4
D : 8
F : FineLine BGA (FBGA)
N : Quad Flat Pack No Lead (QFN)
FBGA Package Type
14 : 169 pins
19 : 324 pins
23 : 484 pins
27 : 672 pins
31 : 896 pins
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
6 (fastest)
7
8
N : Lead-free packaging
ES : Engineering sample
EP4C GX 30 C F 19 C 7N
Member Code
Family Variant
Figure 1–3. Packaging Ordering Information for the Cyclone IV E Device
Family Signature
Package Type
Package Code
Operating Temperature
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
E : Enhanced logic/memory
EP4C : Cyclone IV
6 : 6,272 logic elements
10 : 10,320 logic elements
15 : 15,408 logic elements
22 : 22,320 logic elements
30 : 28,848 logic elements
40 : 39,600 logic elements
55 : 55,856 logic elements
75 : 75,408 logic elements
115 : 114,480 logic elements
F : FineLine BGA (FBGA)
E : Enhanced Thin Quad Flat Pack (EQFP)
U : Ultra FineLine BGA (UBGA)
M : Micro FineLine BGA (MBGA)
FBGA Package Type
17 : 256 pins
19 : 324 pins
23 : 484 pins
29 : 780 pins
EQFP Package Type
22 : 144 pins
UBGA Package Type
14 : 256 pins
19 : 484 pins
MBGA Package Type
8 : 164 pins
9 : 256 pins
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
Extended industrial temperature (TJ = -40° C to 125° C)
A : Automotive temperature (TJ = -40° C to 125° C)
6 (fastest)
7
8
9
N : Lead-free packaging
ES : Engineering sample
L : Low-voltage device
EP4C E 40 F 29 C 8 N
Member Code
Family Variant
Chapter 1: Cyclone IV FPGA Device Family Overview 1–13
Document Revision History
March 2016 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Document Revision History
Table 11 0 lists the revision history for this chapter.
Table 1–10. Document Revision History
Date Version Changes
March 2016 2.0
Updated Table 1–4 and Table 15 to remove support for the N148 package.
Updated Figure 1–2 to remove support for the N148 package.
April 2014 1.9 Updated “Packaging Ordering Information for the Cyclone IV E Device”.
May 2013 1.8 Updated Table 1–3, Table 1–6 and Figure 1–3 to add new device options and
packages.
February 2013 1.7 Updated Table 1–3, Table 1–6 and Figure 1–3 to add new device options and
packages.
October 2012 1.6 Updated Table 1–3 and Table 1–4.
November 2011 1.5
Updated “Cyclone IV Device Family Features” section.
Updated Figure 1–2 and Figure 1–3.
December 2010 1.4
Updated for the Quartus II software version 10.1 release.
Added Cyclone IV E new device package information.
Updated Table 1–1, Table 1–2, Table 1–3, Table 1–5, and Table 1–6.
Updated Figure 1–3.
Minor text edits.
July 2010 1.3 Updated Table 1–2 to include F484 package information.
March 2010 1.2
Updated Table 1–3 and Table 1–6.
Updated Figure 1–3.
Minor text edits.
February 2010 1.1
Added Cyclone IV E devices in Table 1–1, Table 1–3, and Table 1–6 for the
Quartus II software version 9.1 SP1 release.
Added the “Cyclone IV Device Family Speed Grades” and “Configuration”
sections.
Added Figure 1–3 to include Cyclone IV E Device Packaging Ordering
Information.
Updated Table 1–2, Table 1–4, and Table 1–5 for Cyclone IV GX devices.
Minor text edits.
November 2009 1.0 Initial release.
1–14 Chapter 1: Cyclone IV FPGA Device Family Overview
Document Revision History
Cyclone IV Device Handbook, March 2016 Altera Corporation
Volume 1
CYIV-51002-1.0
© 2009 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Cyclone IV Device Handbook,
Volume 1
November 2009
Feedback Subscribe
ISO
9001:2008
Registered
2. Logic Elements and Logic Array Blocks
in Cyclone IV Devices
This chapter contains feature definitions for logic elements (LEs) and logic array
blocks (LABs). Details are provided on how LEs work, how LABs contain groups of
LEs, and how LABs interface with the other blocks in Cyclone®IV devices.
Logic Elements
Logic elements (LEs) are the smallest units of logic in the Cyclone IV device
architecture. LEs are compact and provide advanced features with efficient logic
usage. Each LE has the following features:
A four-input look-up table (LUT), which can implement any function of four
variables
A programmable register
A carry chain connection
A register chain connection
The ability to drive the following interconnects:
Local
Row
Column
Register chain
Direct link
Register packing support
Register feedback support
November 2009
CYIV-51002-1.0
2–2 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
Logic Elements
Cyclone IV Device Handbook, November 2009 Altera Corporation
Volume 1
Figure 2–1 shows the LEs for Cyclone IV devices.
LE Features
You can configure the programmable register of each LE for D, T, JK, or SR flipflop
operation. Each register has data, clock, clock enable, and clear inputs. Signals that
use the global clock network, general-purpose I/O pins, or any internal logic can
drive the clock and clear control signals of the register. Either general-purpose I/O
pins or the internal logic can drive the clock enable. For combinational functions, the
LUT output bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources. The
LUT or register output independently drives these three outputs. Two LE outputs
drive the column or row and direct link routing connections, while one LE drives the
local interconnect resources. This allows the LUT to drive one output while the
register drives another output. This feature, called register packing, improves device
utilization because the device can use the register and the LUT for unrelated
functions. The LAB-wide synchronous load control signal is not available when using
register packing. For more information about the synchronous load control signal,
refer to “LAB Control Signals” on page 2–6.
The register feedback mode allows the register output to feed back into the LUT of the
same LE to ensure that the register is packed with its own fan-out LUT, providing
another mechanism for improved fitting. The LE can also drive out registered and
unregistered versions of the LUT output.
Figure 2–1. Cyclone IV Device LEs
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices 2–3
LE Operating Modes
November 2009 Altera Corporation Cyclone IV Device Handbook,
Volume 1
In addition to the three general routing outputs, LEs in an LAB have register chain
outputs, which allows registers in the same LAB to cascade together. The register
chain output allows the LUTs to be used for combinational functions and the registers
to be used for an unrelated shift register implementation. These resources speed up
connections between LABs while saving local interconnect resources.
LE Operating Modes
Cyclone IV LEs operate in the following modes:
Normal mode
Arithmetic mode
The Quartus®II software automatically chooses the appropriate mode for common
functions, such as counters, adders, subtractors, and arithmetic functions, in
conjunction with parameterized functions such as the library of parameterized
modules (LPM) functions. You can also create special-purpose functions that specify
which LE operating mode to use for optimal performance, if required.
Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In normal mode, four data inputs from the LAB local interconnect are inputs to a
four-input LUT (Figure 2–2). The Quartus II Compiler automatically selects the
carry-in (
cin
) or the
data3
signal as one of the inputs to the LUT. LEs in normal mode
support packed registers and register feedback.
Figure 2–2 shows LEs in normal mode.
Figure 2–2. Cyclone IV Device LEs in Normal Mode
data1
Four-Input
LUT
data2
data3
cin (from cout
of previous LE)
data4
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
CLRN
D
Q
ENA
sclear
(LAB Wide)
sload
(LAB Wide)
Register Chain
Connection
Register
Chain Output
Row, Column, and
Direct Link Routing
Row, Column, and
Direct Link Routing
Local Routing
Register Bypass
Packed Register Input
Register Feedback
2–4 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
LE Operating Modes
Cyclone IV Device Handbook, November 2009 Altera Corporation
Volume 1
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, and
comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry
chain (Figure 2–3). LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output. Register feedback and register packing are supported
when LEs are used in arithmetic mode.
Figure 2–3 shows LEs in arithmetic mode.
The Quartus II Compiler automatically creates carry chain logic during design
processing. You can also manually create the carry chain logic during design entry.
Parameterized functions, such as LPM functions, automatically take advantage of
carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 LEs by automatically
linking LABs in the same column. For enhanced fitting, a long carry chain runs
vertically, which allows fast horizontal connections to M9K memory blocks or
embedded multipliers through direct link interconnects. For example, if a design has a
long carry chain in an LAB column next to a column of M9K memory blocks, any LE
output can feed an adjacent M9K memory block through the direct link interconnect.
If the carry chains run horizontally, any LAB which is not next to the column of M9K
memory blocks uses other row or column interconnects to drive a M9K memory
block. A carry chain continues as far as a full column.
Figure 2–3. Cyclone IV Device LEs in Arithmetic Mode
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
CLRN
D
Q
ENA
sclear
(LAB Wide)
sload
(LAB Wide)
Register
Chain Output
Row, Column, and
Direct link routing
Row, Column, and
Direct link routing
Local Routing
Register Feedback
Three-Input
LUT
Three-Input
LUT
cin (from cout
of previous LE)
data2
data1
cout
Register Bypass
data4
data3
Register Chain
Connection
Packed Register Input
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices 2–5
Logic Array Blocks
November 2009 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Logic Array Blocks
Logic array blocks (LABs) contain groups of LEs.
Topology
Each LAB consists of the following features:
16 LEs
LAB control signals
LE carry chains
Register chains
Local interconnect
The local interconnect transfers signals between LEs in the same LAB. Register chain
connections transfer the output of one LE register to the adjacent LE register in an
LAB. The Quartus II Compiler places associated logic in an LAB or adjacent LABs,
allowing the use of local and register chain connections for performance and area
efficiency.
Figure 2–4 shows the LAB structure for Cyclone IV devices.
Figure 2–4. Cyclone IV Device LAB Structure
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Row Interconnect
Column
Interconnect
Local Interconnect
LAB
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
2–6 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
LAB Control Signals
Cyclone IV Device Handbook, November 2009 Altera Corporation
Volume 1
LAB Interconnects
The LAB local interconnect is driven by column and row interconnects and LE
outputs in the same LAB. Neighboring LABs, phase-locked loops (PLLs), M9K RAM
blocks, and embedded multipliers from the left and right can also drive the local
interconnect of a LAB through the direct link connection. The direct link connection
feature minimizes the use of row and column interconnects, providing higher
performance and flexibility. Each LE can drive up to 48 LEs through fast local and
direct link interconnects.
Figure 2–5 shows the direct link connection.
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs. The control
signals include:
Two clocks
Two clock enables
Two asynchronous clears
One synchronous clear
One synchronous load
You can use up to eight control signals at a time. Register packing and synchronous
load cannot be used simultaneously.
Each LAB can have up to four non-global control signals. You can use additional LAB
control signals as long as they are global signals.
Synchronous clear and load signals are useful for implementing counters and other
functions. The synchronous clear and synchronous load signals are LAB-wide signals
that affect all registers in the LAB.
Figure 2–5. Cyclone IV Device Direct Link Connection
LAB
Direct link
interconnect
to right
Direct link interconnect from
right LAB, M9K memory
block, embedded multiplier,
PLL, or IOE output
Direct link interconnect from
left LAB, M9K memory
block, embedded multiplier,
PLL, or IOE output
Local
Interconnect
Direct link
interconnect
to left
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices 2–7
Document Revision History
November 2009 Altera Corporation Cyclone IV Device Handbook,
Volume 1
Each LAB can use two clocks and two clock enable signals. The clock and clock enable
signals of each LAB are linked. For example, any LE in a particular LAB using the
labclk1
signal also uses the
labclkena1
. If the LAB uses both the rising and falling
edges of a clock, it also uses both LAB-wide clock signals. Deasserting the clock
enable signal turns off the LAB-wide clock.
The LAB row clocks
[5..0]
and LAB local interconnect generate the LAB-wide
control signals. The MultiTrack interconnect inherent low skew allows clock and
control signal distribution in addition to data distribution.
Figure 2–6 shows the LAB control signal generation circuit.
LAB-wide signals control the logic for the clear signal of the register. The LE directly
supports an asynchronous clear function. Each LAB supports up to two asynchronous
clear signals (
labclr1
and
labclr2
).
A LAB-wide asynchronous load signal to control the logic for the preset signal of the
register is not available. The register preset is achieved with a NOT gate push-back
technique. Cyclone IV devices only support either a preset or asynchronous clear
signal.
In addition to the clear port, Cyclone IV devices provide a chip-wide reset pin
(
DEV_CLRn
) that resets all registers in the device. An option set before compilation in
the Quartus II software controls this pin. This chip-wide reset overrides all other
control signals.
Document Revision History
Table 21 shows the revision history for this chapter.
Figure 2–6. Cyclone IV Device LAB-Wide Control Signals
labclkena1
labclk2labclk1
labclkena2 labclr1
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
syncload
synclr
labclr2
6
Table 2–1. Document Revision History
Date Version Changes
November 2009 1.0 Initial release.
2–8 Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
Document Revision History
Cyclone IV Device Handbook, November 2009 Altera Corporation
Volume 1
CYIV-51003-1.1
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Cyclone IV Device Handbook,
Volume 1
November 2011
Feedback Subscribe
ISO
9001:2008
Registered
3. Memory Blocks in Cyclone IV Devices
Cyclone®IV devices feature embedded memory structures to address the on-chip
memory needs of Altera® Cyclone IV device designs. The embedded memory
structure consists of columns of M9K memory blocks that you can configure to
provide various memory functions, such as RAM, shift registers, ROM, and FIFO
buffers.
This chapter contains the following sections:
“Memory Modes” on page 3–7
“Clocking Modes” on page 3–14
“Design Considerations” on page 3–15
Overview
M9K blocks support the following features:
8,192 memory bits per block (9,216 bits per block including parity)
Independent read-enable (
rden
) and write-enable (
wren
) signals for each port
Packed mode in which the M9K memory block is split into two 4.5 K single-port
RAMs
Variable port configurations
Single-port and simple dual-port modes support for all port widths
True dual-port (one read and one write, two reads, or two writes) operation
Byte enables for data input masking during writes
Two clock-enable control signals for each port (port A and port B)
Initialization file to pre-load memory content in RAM and ROM modes
November 2011
CYIV-51003-1.1
3–2 Chapter 3: Memory Blocks in Cyclone IV Devices
Overview
Cyclone IV Device Handbook, November 2011 Altera Corporation
Volume 1
Table 31 lists the features supported by the M9K memory.
fFor information about the number of M9K memory blocks for Cyclone IV devi