S25FL512S Datasheet

Cypress Semiconductor Corp

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Datasheet

S25FL512S
512 Mbit (64 Mbyte), 3.0 V SPI Flash Memory
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-98284 Rev. *O Revised March 21, 2018
Features
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface with Multi-I/O
Density
512 Mbits (64 Mbytes)
Serial Peripheral Interface (SPI)
SPI Clock polarity and phase modes 0 and 3
Double Data Rate (DDR) option
Extended Addressing: 32-bit address
Serial Command set and footprint compatible with
S25FL-A,
S25FL-K, and S25FL-P SPI families
Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
AutoBoot - power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
Common Flash Interface (CFI) data for configuration
information.
Programming (1.5 MB/s)
512-byte Page Programming buffer
Quad-Input Page Programming (QPP) for slow clock
systems
Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 MB/s)
Uniform 256-kbyte sectors
Cycling Endurance
100,000 Program-Erase Cycles, minimum
Data Retention
20 Year Data Retention, minimum
Security features
One Time Program (OTP) array of 1024 bytes
Block Protection:
Status Register bits to control protection against
program or erase of a contiguous range of sectors.
Hardware and software control options
Advanced Sector Protection (ASP)
Individual sector protection controlled by boot code or
password
Cypress® 65 nm MirrorBit® Technology with Eclipse
Architecture
Core Supply Voltage: 2.7 V to 3.6 V
I/O Supply Voltage: 1.65 V to 3.6 V
SO16 and FBGA packages
Temperature Range:
Industrial (–40 °C to +85 °C)
Industrial Plus (–40 °C to +105 °C)
Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C)
Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C)
Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C)
Packages (all Pb-free)
16-lead SOIC (300 mil)
BGA-24 6 × 8 mm
5 × 5 ball (FAB024) and 4 × 6 ball (FAC024) footprint
options
Known Good Die and Known Tested Die
Logic Block Diagram
SRAM
MirrorBit Array
Control
Logic
Data Path
X Decoders
CS#
SCK
SI/IO0
SO/IO1
HOLD#/IO3
WP#/IO2
RESET#
I/O Y Decoders
Data Latch
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S25FL512S
Performance Summary
Maximum Read Rates with the Same Core and I/O Voltage (VIO = VCC = 2.7 V to 3.6 V)
Command Clock Rate (MHz) Mbps
Read 50 6.25
Fast Read 133 16.6
Dual Read 104 26
Quad Read 104 52
Maximum Read Rates with Lower I/O Voltage (VIO = 1.65 V to 2.7 V, VCC = 2.7 V to 3.6 V)
Command Clock Rate (MHz) Mbps
Read 50 6.25
Fast Read 66 8.25
Dual Read 66 16.5
Quad Read 66 33
Maximum Read Rates DDR (VIO = VCC = 3 V to 3.6 V)
Command Clock Rate (MHz) Mbps
Fast Read DDR 80 20
Dual Read DDR 80 40
Quad Read DDR 80 80
Typical Program and Erase Rates
Operation kbytes/s
Page Programming (512-byte page buffer - Uniform Sector Option) 1500
256-kbyte Logical Sector Erase (Uniform Sector Option) 500
Current Consumption
Operation Clock Rate (MHz)
Serial Read 50 MHz 16 (max)
Serial Read 133 MHz 33 (max)
Quad Read 104 MHz 61 (max)
Program 100 (max)
Erase 100 (max)
Standby 0.07 (typ)
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S25FL512S
Contents
1. Overview ....................................................................... 4
1.1 General Description ....................................................... 4
1.2 Migration Notes.............................................................. 4
1.3 Glossary......................................................................... 7
1.4 Other Resources............................................................ 7
Hardware Interface
2. Signal Descriptions ..................................................... 8
2.1 Input/Output Summary................................................... 8
2.2 Address and Data Configuration.................................... 9
2.3 RESET# ......................................................................... 9
2.4 Serial Clock (SCK)......................................................... 9
2.5 Chip Select (CS#) .......................................................... 9
2.6 Serial Input (SI) / I/O0 .................................................. 10
2.7 Serial Output (SO) / I/O1.............................................. 10
2.8 Write Protect (WP#) / I/O2 ........................................... 10
2.9 Hold (HOLD#) / I/O3 .................................................... 10
2.10 Core Voltage Supply (VCC) .......................................... 11
2.11 Versatile I/O Power Supply (VIO) ................................. 11
2.12 Supply and Signal Ground (VSS) ................................. 11
2.13 Not Connected (NC) .................................................... 11
2.14 Reserved for Future Use (RFU)................................... 11
2.15 Do Not Use (DNU) ....................................................... 11
2.16 Block Diagrams............................................................ 12
3. Signal Protocols......................................................... 13
3.1 SPI Clock Modes ......................................................... 13
3.2 Command Protocol ...................................................... 14
3.3 Interface States............................................................ 17
3.4 Configuration Register Effects on the Interface ........... 22
3.5 Data Protection ............................................................ 22
4. Electrical Specifications............................................ 24
4.1 Absolute Maximum Ratings ......................................... 24
4.2 Thermal Resistance..................................................... 24
4.3 Operating Ranges........................................................ 24
4.4 Power-Up and Power-Down ........................................ 25
4.5 DC Characteristics....................................................... 27
5. Timing Specifications................................................ 28
5.1 Key to Switching Waveforms ....................................... 28
5.2 AC Test Conditions...................................................... 29
5.3 Reset............................................................................ 30
5.4 SDR AC Characteristics............................................... 32
5.5 DDR AC Characteristics .............................................. 36
6. Physical Interface ...................................................... 39
6.1 SOIC 16-Lead Package ............................................... 39
6.2 FAB024 24-Ball BGA Package .................................... 41
6.3 FAC024 24-Ball BGA Package.................................... 43
Software Interface
7. Address Space Maps................................................. 45
7.1 Overview ...................................................................... 45
7.2 Flash Memory Array..................................................... 45
7.3 ID-CFI Address Space................................................. 45
7.4 JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space............................................................... 46
7.5 OTP Address Space ..................................................... 46
7.6 Registers....................................................................... 48
8. Data Protection ........................................................... 58
8.1 Secure Silicon Region (OTP)........................................ 58
8.2 Write Enable Command................................................ 58
8.3 Block Protection............................................................ 59
8.4 Advanced Sector Protection ......................................... 60
9. Commands .................................................................. 64
9.1 Command Set Summary............................................... 65
9.2 Identification Commands .............................................. 71
9.3 Register Access Commands......................................... 73
9.4 Read Memory Array Commands .................................. 82
9.5 Program Flash Array Commands ................................. 96
9.6 Erase Flash Array Commands...................................... 99
9.7 One Time Program Array Commands ........................ 103
9.8 Advanced Sector Protection Commands.................... 104
9.9 Reset Commands ....................................................... 109
9.10 Embedded Algorithm Performance Tables................. 110
10. Data Integrity ............................................................. 111
10.1 Erase Endurance ........................................................ 111
10.2 Data Retention............................................................ 111
11. Software Interface Reference .................................. 112
11.1 Command Summary................................................... 112
11.2 Serial Flash Discoverable Parameters (SFDP) Address
Map............................................................................. 114
11.3 Device ID and Common Flash Interface (ID-CFI) Address
Map............................................................................. 118
11.4 Registers..................................................................... 136
11.5 Initial Delivery State .................................................... 140
12 Ordering Information................................................ 141
13. Revision History........................................................ 143
Document History Page ....................................................143
Sales, Solutions, and Legal Information .........................146
Worldwide Sales and Design Support ..........................146
Products .......................................................................146
PSoC® Solutions ......................................................... 146
Cypress Developer Community ....................................146
Technical Support ........................................................146
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S25FL512S
1. Overview
1.1 General Description
The Cypress S25FL512S device is a flash nonvolatile memory product using:
MirrorBit technology - that stores two data bits in each memory array transistor
Eclipse architecture - that dramatically improves program and erase performance
65 nm process lithography
This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single
I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple
width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands
for SIO, DIO, and QIO that transfer address and read data on both edges of the clock.
The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) to be programmed in one
operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.
Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates
supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,
asynchronous, NOR flash memories while reducing signal count dramatically.
The S25FL512S product offers high densities coupled with the flexibility and fast performance required by a variety of embedded
applications. It is ideal for code shadowing, XIP, and data storage.
1.2 Migration Notes
1.2.1 Features Comparison
The S25FL512S device is command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1. FL Generations Comparison
Parameter FL-K FL-P FL-S
Technology Node 90 nm 90 nm 65 nm
Architecture Floating Gate MirrorBit MirrorBit Eclipse
Release Date In Production In Production In Production
Density 4 Mb - 128 Mb 32 Mb - 256 Mb 512 Mb
Bus Width x1, x2, x4 x1, x2, x4 x1, x2, x4
Supply Voltage 2.7 V - 3.6 V 2.7 V - 3.6 V 2.7 V - 3.6 V / 1.65 V - 3.6V V
IO
Normal Read Speed (SDR) 6 MB/s (50 MHz) 5 MB/s (40 MHz) 6 MB/s (50 MHz)
Fast Read Speed (SDR) 13 MB/s (104 MHz) 13 MB/s (104 MHz) 17 MB/s (133 MHz)
Dual Read Speed (SDR) 26 MB/s (104 MHz) 20 MB/s (80 MHz) 26 MB/s (104 MHz)
Quad Read Speed (SDR) 52 MB/s (104 MHz) 40 MB/s (80 MHz) 52 MB/s (104 MHz)
Fast Read Speed (DDR) 20 MB/s (80 MHz)
Dual Read Speed (DDR) 40 MB/s (80 MHz)
Quad Read Speed (DDR) 80 MB/s (80 MHz)
Program Buffer Size 256B 256B 512B
Erase Sector Size 4 kB / 32 kB / 64 kB 64 kB / 256 kB 256 kB
Parameter Sector Size 4 kB 4 kB
Sector Erase Time (typ.) 30 ms (4 kB), 150 ms (64 kB) 500 ms (64 kB) 520 ms (256 kB)
Page Programming Time (typ.) 700 µs (256B) 1500 µs (256B) 340 µs (512B)
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S25FL512S
Notes
1. 256B program page option only for 128-Mb and 256-Mb density FL-S devices.
2. FL-P column indicates FL129P MIO SPI device (for 128-Mb density).
3. 64 kB sector erase option only for 128-Mb/256-Mb density FL-P and FL-S devices.
4. FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
5. Refer to individual data sheets for further details.
1.2.2 Known Differences from Prior Generations
1.2.2.1 Error Reporting
Prior generation FL memories either do not have error status bits or do not set them if program or erase is attempted on a protected
sector. The FL-S family does have error reporting status bits for program and erase operations. These can be set when there is an
internal failure to program or erase or when there is an attempt to program or erase a protected sector. In either case the program or
erase operation did not complete as requested by the command.
1.2.2.2 Secure Silicon Region (OTP)
The size and format (address map) of the One Time Program area is different from prior generations. The method for protecting
each portion of the OTP area is different. For additional details see Secure Silicon Region (OTP) on page 58.
1.2.2.3 Configuration Register Freeze Bit
The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior generations. In the FL-S family it
also locks the state of the configuration register TBPARM bit CR1[2], TBPROT bit CR1[5], and the Secure Silicon Region (OTP)
area.
1.2.2.4 Sector Erase Commands
The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.
The command for erasing a 4-kbyte sector is not supported in the 512-Mbit density FL-S device.
The erase command for 64-kbyte sectors is not supported in the 512-Mbit density FL-S device.
1.2.2.5 Deep Power Down
The Deep Power Down (DPD) function is not supported in FL-S family devices.
The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the former DPD
command, to access a new bank address register. The bank address register allows SPI memory controllers that do not support
more than 24 bits of address, the ability to provide higher order address bits for commands, as needed to access the larger address
space of the 256-Mbit density FL-S device. For additional information see Extended Address on page 45.
OTP 768B (3 x 256B) 506B 1024B
Advanced Sector Protection No No Yes
Auto Boot Mode No No Yes
Erase Suspend/Resume Yes No Yes
Program Suspend/Resume Yes No Yes
Operating Temperature –40 °C to +85 °C –40 °C to +85 °C / +105 °C –40 °C to +85 °C / +105 °C
Table 1. FL Generations Comparison (Continued)
Parameter FL-K FL-P FL-S
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S25FL512S
1.2.2.6 New Features
The FL-S family introduces several new features to SPI category memories:
Extended address for access to higher memory density.
AutoBoot for simpler access to boot code following power up.
Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO instructions when
repeating the same type of read command.
Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read
commands.
DDR read commands for SIO, DIO, and QIO.
Automatic ECC for enhanced data integrity.
Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the Advanced
Sector Protection feature found in several other Cypress parallel interface NOR memory families.
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S25FL512S
1.3 Glossary
1.4 Other Resources
1.4.1 Cypress Flash Memory Roadmap
www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap
1.4.2 Links to Software
www.cypress.com/software-and-drivers-cypress-flash-memory
1.4.3 Links to Application Notes
www.cypress.com/cypressappnotes
Command
All information transferred between the host system and memory during one period while CS# is low.
This includes the instruction (sometimes called an operation code or opcode) and any required
address, mode bits, latency cycles, or data.
DDP
(Dual Die Package)
Two die stacked within the same package to increase the memory capacity of a single package.
Often also referred to as a Multi-Chip Package (MCP).
DDR
(Double Data Rate) When input and output are latched on every edge of SCK.
ECC ECC Unit = 16 byte aligned and length data groups in the main Flash array and OTP array, each of
which has its own hidden ECC syndrome to enable error correction on each group.
Flash The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases
large blocks of memory bits in parallel, making the erase operation much faster than early EEPROM.
High A signal voltage level ≥ VIH or a logic level representing a binary one (1).
Instruction
The 8 bit code indicating the function to be performed by a command (sometimes called an
operation code or opcode). The instruction is always the first 8 bits transferred from host system to
the memory in any command.
Low A signal voltage level V
IL or a logic level representing a binary zero (0).
LSB
(Least Significant Bit)
Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a
register or data value.
MSB
(Most Significant Bit)
Generally the left most bit, with the highest order of magnitude value, within a group of bits of a
register or data value.
Nonvolatile No power is needed to maintain data stored in the memory.
OPN
(Ordering Part Number)
The alphanumeric string specifying the memory device type, density, package, factory nonvolatile
configuration, etc. used to select the desired device.
Page 512 bytes aligned and length group of data.
PCB Printed Circuit Board.
Register Bit References Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB: bit_range_LSB].
SDR
(Single Data Rate) When input is latched on the rising edge and output on the falling edge of SCK.
Sector Erase unit size 256 kbytes.
Write
An operation that changes data within volatile or nonvolatile registers bits or nonvolatile flash
memory. When changing nonvolatile data, an erase and reprogramming of any unchanged
nonvolatile data is done, as part of the operation, such that the nonvolatile data is modified by the
write operation, in the same way that volatile data is modified – as a single operation. The
nonvolatile data appears to the host system to be updated by the single write command, without the
need for separate commands for erase and reprogram of adjacent, but unaffected data.
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S25FL512S
Hardware Interface
Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)
Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large
number of signal connections and larger package size. The large number of connections increase power consumption due to so
many signals switching and the larger package increases cost.
The S25FL512S device reduces the number of signals for connection to the host system by serially transferring all control, address,
and data information over 4 to 6 signals. This reduces the cost of the memory package, reduces signal switching power, and either
reduces the host connection count or frees host connectors for use in providing other features.
The S25FL512S device uses the industry standard single bit Serial Peripheral Interface (SPI) and also supports optional extension
commands for two bit (Dual) and four bit (Quad) wide serial transfers. This multiple width interface is called SPI Multi-I/O or SPI-MIO.
2. Signal Descriptions
2.1 Input/Output Summary
Table 2. Signal List
Signal Name Type Description
RESET# Input
Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used.
SCK Input Serial Clock.
CS# Input Chip Select.
SI / IO0 I/O Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1 I/O Serial Output for single bit data commands. IO1 for Dual or Quad commands.
WP# / IO2 I/O Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up
resistor and may be left unconnected in the host system if not used for Quad commands.
HOLD# / IO3 I/O
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The
signal has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad commands.
VCC Supply Core Power Supply.
VIO Supply Versatile I/O Power Supply.
VSS Supply Ground.
NC Unused
Not Connected. No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for routing
space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC
must not have voltage levels higher than VIO.
RFU Reserved
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use of the connector for a signal. It is recommended to not
use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.
DNU Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for connection
to any host system signal. Any DNU signal related function will be inactive when the signal is at
VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system
or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not
connect any host system signal to this connection.
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S25FL512S
2.2 Address and Data Configuration
Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the SI signal. Data
may be sent back to the host serially on the Serial Output (SO) signal.
Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will be returned to the
host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.
Dual or Quad Input/Output (I/O) commands send information from the host to the memory as bit pairs on IO0 and IO1 or four bit
(nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups
on IO0, IO1, IO2, and IO3.
2.3 RESET#
The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a command. When
RESET# is driven to logic low (VIL) for at least a period of tRP, the device:
terminates any operation in progress,
tristates all outputs,
resets the volatile bits in the Configuration Register,
resets the volatile bits in the Status Registers,
resets the Bank Address Register to zero,
loads the Program Buffer with all ones,
reloads all internal configuration information necessary to bring the device to standby mode,
and resets the internal Control Unit to standby state.
RESET# causes the same initialization process as is performed when power comes up and requires tPU time.
RESET# may be asserted low at any time. To ensure data integrity any operation that was interrupted by a hardware reset should
be reinitiated once the device is ready to accept a command sequence.
When RESET# is first asserted Low, the device draws ICC1 (50 MHz value) during tPU. If RESET# continues to be held at VSS the
device draws CMOS standby current (ISB).
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.
The RESET# input is not available on all packages options. When not available the RESET# input of the device is tied to the inactive
state, inside the package.
2.4 Serial Clock (SCK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on
the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR commands, and after every edge in
DDR commands.
2.5 Chip Select (CS#)
The chip select signal indicates when a command for the device is in process and the other signals are relevant for the memory
device. When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output
signals are high impedance. Unless an internal Program, Erase or Write Registers (WRR) embedded operation is in progress, the
device will be in the Standby Power mode. Driving the CS# input to logic low state enables the device, placing it in the Active Power
mode. After Power-up, a falling edge on CS# is required prior to the start of any command.
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S25FL512S
2.6 Serial Input (SI) / I/O0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed.
Values are latched on the rising edge of serial SCK clock signal.
SI becomes I/O0 - an input and output during Dual and Quad commands for receiving instructions, addresses, and data to be
programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in
SDR commands, and on every edge of SCK, in DDR commands).
2.7 Serial Output (SO) / I/O1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock
signal.
SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to be programmed
(values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR commands,
and on every edge of SCK, in DDR commands).
2.8 Write Protect (WP#) / I/O2
When WP# is driven Low (VIL), during a WRR command and while the Status Register Write Disable (SRWD) bit of the Status
Register is set to a 1, it is not possible to write to the Status and Configuration Registers. This prevents any alteration of the Block
Protect (BP2, BP1, BP0) and TBPROT bits of the Status Register. As a consequence, all the data bytes in the memory area that are
protected by the Block Protect and TBPROT bits, are also hardware protected against data modification if WP# is Low during a
WRR command.
The WP# function is not available when the Quad mode is enabled (CR[1]=1). The WP# function is replaced by IO2 for input and
output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal)
as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
WP# has an internal pull-up resistor; when unconnected, WP# is at VIH and may be left unconnected in the host system if not used
for Quad mode.
2.9 Hold (HOLD#) / I/O3
The Hold (HOLD#) signal is used to pause any serial communications with the device without deselecting the device or stopping the
serial clock.
To enter the Hold condition, the device must be selected by driving the CS# input to the logic low state. It is recommended that the
user keep the CS# input low state during the entire duration of the Hold condition. This is to ensure that the state of the interface
logic remains unchanged from the moment of entering the Hold condition. If the CS# input is driven to the logic high state while the
device is in the Hold condition, the interface logic of the device will be reset. To restart communication with the device, it is
necessary to drive HOLD# to the logic high state while driving the CS# signal into the logic low state. This prevents the device from
going back into the Hold condition.
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this coincides with SCK being at the logic low
state. If the falling edge does not coincide with the SCK signal being at the logic low state, the Hold condition starts whenever the
SCK signal reaches the logic low state. Taking the HOLD# signal to the logic low state does not terminate any Write, Program or
Erase operation that is currently in progress.
During the Hold condition, SO is in high impedance and both the SI and SCK input are Don't Care.
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided that this coincides with the SCK signal being at the
logic low state. If the rising edge does not coincide with the SCK signal being at the logic low state, the Hold condition ends
whenever the SCK signal reaches the logic low state.
The HOLD# function is not available when the Quad mode is enabled (CR1[1] =1). The Hold function is replaced by I/O3 for input
and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK
signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).
The HOLD# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode.
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S25FL512S
Figure 1. HOLD Mode Operation
2.10 Core Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read,
program, and erase. The voltage may vary from 2.7V to 3.6V.
2.11 Versatile I/O Power Supply (VIO)
The Versatile I/O (VIO) supply is the voltage source for all device input receivers and output drivers and allows the host system to set
the voltage levels that the device tolerates on all inputs and drives on outputs (address, control, and I/O signals). The VIO range is
1.65V to VCC. VIO cannot be greater than VCC.
For example, a VIO of 1.65V - 3.6V allows for I/O at the 1.8V, 2.5V or 3V levels, driving and receiving signals to and from other 1.8V,
2.5V or 3V devices on the same data bus. VIO may be tied to VCC so that interface signals operate at the same voltage as the core
of the device. VIO is not available in all package options, when not available the VIO supply is tied to VCC internal to the package.
During the rise of power supplies the VIO supply voltage must remain less than or equal to the VCC supply voltage.
This supply is not available in all package options. For a backward compatible SO16 footprint, the VIO supply is tied to VCC inside the
package; thus, the I/O will function at VCC level.
2.12 Supply and Signal Ground (VSS)
VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.
2.13 Not Connected (NC)
No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The
connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an
NC must not have voltage levels higher than VIO.
2.14 Reserved for Future Use (RFU)
No device internal signal is currently connected to the package connector but is there potential future use of the connector. It is
recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced
features in compatible footprint devices.
2.15 Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other
purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the
signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.
Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
CS#
SCK
HOLD#
SI_or_IO_(during_input)
SO_or_IO_(internal)
SO_or_IO_(external)
Valid Input Don't Care Valid Input Don't Care Valid Input
ABCDE
AB B C D E
Hold Condition
Standard Use
Hold Condition
Non-standard Use
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S25FL512S
2.16 Block Diagrams
Figure 2. Bus Master and Memory Devices on the SPI Bus — Single Bit Data Path
Figure 3. Bus Master and Memory Devices on the SPI Bus — Dual Bit Data Path
Figure 4. Bus Master and Memory Devices on the SPI Bus — Quad Bit Data Path
SPI
Bus Master
HOLD#
WP#
SO
SI
SCK
CS2#
CS1#
FL-S
Flash
FL-S
Flash
HOLD#
WP#
SO
SI
SCK
CS2#
CS1#
SPI
Bus Master
HOLD#
WP#
IO1
IO0
SCK
CS2#
CS1#
FL-S
Flash
FL-S
Flash
HOLD#
WP#
IO0
IO1
SCK
CS2#
CS1#
SPI
Bus Master
IO3
IO2
IO1
IO0
SCK
CS2#
CS1#
FL-S
Flash
FL-S
Flash
IO3
IO2
IO0
IO1
SCK
CS2#
CS1#
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S25FL512S
3. Signal Protocols
3.1 SPI Clock Modes
3.1.1 Single Data Rate (SDR)
The S25FL512S device can be driven by an embedded microcontroller (bus master) in either of the two following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data into the device is always latched in on the rising edge of the SCK signal and the output data is
always available from the falling edge of the SCK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring any data.
SCK will stay at logic low state with CPOL = 0, CPHA = 0
SCK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 5. SPI SDR Modes Supported
Timing diagrams throughout the remainder of the document are generally shown as both mode 0 and 3 by showing SCK as both
high and low at the fall of CS#. In some cases a timing diagram may show only mode 0 with SCK low at the fall of CS#. In such a
case, mode 3 timing simply means clock is high at the fall of CS# so no SCK rising edge set up or hold time to the falling edge of
CS# is needed for mode 3.
SCK cycles are measured (counted) from one falling edge of SCK to the next falling edge of SCK. In mode 0 the beginning of the
first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge of SCK because SCK is already low
at the beginning of a command.
3.1.2 Double Data Rate (DDR)
Mode 0 and Mode 3 are also supported for DDR commands. In DDR commands, the instruction bits are always latched on the rising
edge of clock, the same as in SDR commands. However, the address and input data that follow the instruction are latched on both
the rising and falling edges of SCK. The first address bit is latched on the first rising edge of SCK following the falling edge at the end
of the last instruction bit. The first bit of output data is driven on the falling edge at the end of the last access latency (dummy) cycle.
SCK cycles are measured (counted) in the same way as in SDR commands, from one falling edge of SCK to the next falling edge of
SCK. In mode 0 the beginning of the first SCK cycle in a command is measured from the falling edge of CS# to the first falling edge
of SCK because SCK is already low at the beginning of a command.
Figure 6. SPI DDR Modes Supported
CPOL=0_CPHA=0_SCK
CPOL=1_CPHA=1_SCK
CS#
SI
SO
MSB
MSB
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3.2 Command Protocol
All communication between the host system and S25FL512S memory device is in the form of units called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands
may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All
instruction, address, and data information is transferred serially between the host system and memory device.
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to the host serially on
the SO signal.
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be returned to the host as a
sequence of bit pairs on I/O0 and I/O1 or four bit (nibble) groups on I/O0, I/O1, I/O2, and I/O3.
Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on I/O0 and I/O1 or, four-bit (nibble)
groups on I/O0, I/O1, I/O2, and I/O3. Data is returned to the host similarly as bit pairs on I/O0 and I/O1 or, four bit (nibble) groups on
I/O0, I/O1, I/O2, and I/O3.
Commands are structured as follows:
Each command begins with CS# going low and ends with CS# returning high. The memory device is selected by the host
driving the Chip Select (CS#) signal low throughout a command.
The serial clock (SCK) marks the transfer of each bit or group of bits between the host and memory.
Each command begins with an 8-bit (byte) instruction. The instruction is always presented only as a single bit serial
sequence on the Serial Input (SI) signal with one bit transferred to the memory device on each SCK rising edge. The
instruction selects the type of information transfer or device operation to be performed.
The instruction may be stand alone or may be followed by address bits to select a location within one of several address
spaces in the device. The instruction determines the address space used. The address may be either a 24-bit or a 32-bit
byte boundary, address. The address transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in
DDR commands.
The width of all transfers following the instruction are determined by the instruction sent. Following transfers may continue
to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in 2-bit groups per (dual) transfer on
the I/O0 and I/O1 signals, or they may be done in 4-bit groups per (quad) transfer on the I/O0-I/O3 signals. Within the dual
or quad groups the least significant bit is on I/O0. More significant bits are placed in significance order on each higher
numbered I/O signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
Some instructions send an instruction modifier called mode bits, following the address, to indicate that the next command
will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an
instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the same
command type is repeated in a sequence of commands. The mode bit transfers occur on SCK rising edge, in SDR
commands, or on every SCK edge, in DDR commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period
before read data is returned to the host.
Write data bit transfers occur on SCK rising edge, in SDR commands, or on every SCK edge, in DDR commands.
SCK continues to toggle during any read access latency period. The latency may be zero to several SCK cycles (also
referred to as dummy cycles). At the end of the read latency cycles, the first read data bits are driven from the outputs on
SCK falling edge at the end of the last read latency cycle. The first read data bits are considered transferred to the host on
the following SCK rising edge. Each following transfer occurs on the next SCK rising edge, in SDR commands, or on every
SCK edge, in DDR commands.
If the command returns read data to the host, the device continues sending data transfers until the host takes the CS#
signal high. The CS# signal can be driven high after any transfer in the read data sequence. This will terminate the
command.
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S25FL512S
At the end of a command that does not return data, the host drives the CS# input high. The CS# signal must go high after
the eighth bit, of a stand alone instruction or, of the last write data byte that is transferred. That is, the CS# signal must be
driven high when the number of clock cycles after CS# signal was driven low is an exact multiple of eight cycles. If the CS#
signal does not go high exactly at the eight SCK cycle boundary of the instruction or write data, the command is rejected
and not executed.
All instruction, address, and mode bits are shifted into the device with the Most Significant Bits (MSB) first. The data bits are
shifted in and out of the device MSB first. All data is transferred in byte units with the lowest address byte sent first.
Following bytes of data are sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored.
The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during
an embedded operation. These are discussed in the individual command descriptions.
Depending on the command, the time for execution varies. A command to read status information from an executing
command is available to determine when the command completes execution and whether the command was successful.
3.2.1 Command Sequence Examples
Figure 7. Stand Alone Instruction Command
Figure 8. Single Bit Wide Input Command
Figure 9. Single Bit Wide Output Command
Figure 10. Single Bit Wide I/O Command without Latency
CS#
SCK
SI
SO
Phase
76543210
Instruction
CS#
SCK
SI
SO
Phase
7654321076543210
Instruction Input Data
CS#
SCK
SI
SO
Phase
76543210
7654321076543210
Instruction Data 1 Data 2
CS#
SCK
SI
SO
Phase
7 6 5 4 3 2 1 0 31 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction Address Data 1 Data 2
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S25FL512S
Figure 11. Single Bit Wide I/O Command with Latency
Figure 12. Dual Output Command
Figure 13. Quad Output Command without Latency
Figure 14. Dual I/O Command
Figure 15. Quad I/O Command
CS#
SCK
SI
SO
Phase
7 6 5 4 3 2 1 0 31 1 0
7 6 5 4 3 2 1 0
Instruction Dummy Cycles Data 1Address
CS#
SCK
IO0
IO1
Phase
7 6 5 4 3 2 1 0 30 28 26 0 6 4 2 0 6 4 2 0
31 29 27 1 7 5 3 1 7 5 3 1
Instruction 6 Dummy Data 1 Data 2Address
CS#
SCK
IO0
IO1
IO2
IO3
Phase
7 6 5 4 3 2 1 0 31 1 0 4 0 4 0 4 0 4 0 4 0 4
5 1 5 1 5 1 5 1 5 1 5
6 2 6 2 6 2 6 2 6 2 6
7 3 7 3 7 3 7 3 7 3 7
Instruction Address Data 1 Data 2 Data 3 Data 4 Data 5 ...
CS#
SCK
IO0
IO1
Phase
7 6 5 4 3 2 1 0 30 2 0 6 4 2 0 6 4 2 0
31 3 1 7 5 3 1 7 5 3 1
Instruction Address Dummy Data 1 Data 2
CS#
SCK
IO0
IO1
IO2
IO3
Phase
7 6 5 4 3 2 1 0 28 4 0 4 4 0 4 0 4 0 4 0
29 5 1 5 5 1 5 1 5 1 5 1
30 6 2 6 6 2 6 2 6 2 6 2
31 7 3 7 7 3 7 3 7 3 7 3
Instruction Address Mode Dummy D1 D2 D3 D4
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S25FL512S
Figure 16. DDR Fast Read with EHPLC = 00b
Figure 17. DDR Dual I/O Read with EHPLC = 01b and DLP
Figure 18. DDR Quad I/O Read
Additional sequence diagrams, specific to each command, are provided in Commands onpage64.
3.3 Interface States
This section describes the input and output signal levels as related to the SPI interface behavior.
Table 3. Interface States Summary
Interface State VCC VIO RESET# SCK CS# HOLD# /
I/O3
WP# /
z
I/O2
SO /
I/O1
SI /
I/O0
Power-Off <V
CC (low) VCC XXXXXZX
Low Power
Hardware Data Protection <V
CC (cut-off) VCC XXXXXZX
Power-On (Cold) Reset VCC (min) VIO (min)
VCC
XXXXXZX
Hardware (Warm) Reset VCC (min) VIO (min)
VCC
HL X X X X Z X
Interface Standby VCC (min) VIO (min)
VCC
HH X HH X X Z X
Instruction Cycle VCC (min) VIO (min)
VCC
HH HT HL HH HV Z HV
CS#
SCK
SI
SO
Phase
7 6 5 4 3 2 1 0 3130 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Instruction Address Mode Dummy Data 1 Data 2
CS#
SCK
IO0
IO1
Phase
7 6 5 4 3 2 1 0 30 28 0 6 4 2 0 7 6 5 4 3 2 1 0 6 4 2 0 6
31 29 1 7 5 3 1 7 6 5 4 3 2 1 0 7 5 3 1 7
Instruction Mode Dum DLP Data 1Address
CS#
SCK
IO0
IO1
IO2
IO3
Phase
7 6 5 4 3 2 1 0
2824201612
8 4 0 4 0 7 6 5 4 3 2 1 0 4 0 4 0
2925211713
9 5 1 5 1 7 6 5 4 3 2 1 0 5 1 5 1
302622181410
6 2 6 2 7 6 5 4 3 2 1 0 6 2 6 2
312723191511
7 3 7 3 7 6 5 4 3 2 1 0 7 3 7 3
Instruction Address Dummy DLP D1 D2
Mode
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S25FL512S
Legend:
Z = no driver - floating signal
HL = Host driving VIL
HH = Host driving VIH
HV = either HL or HH
X = HL or HH or Z
HT = Toggling between HL and HH
ML = Memory driving VIL
MH = Memory driving VIH
MV = either ML or MH
Hold Cycle VCC (min) VIO (min)
VCC
HH HV or HT HL HL X X X
Single Input Cycle
Host to Memory Transfer VCC (min) VIO (min)
VCC
HH HT HL HH X Z HV
Single Latency (Dummy)
Cycle VCC (min) VIO (min)
VCC
HH HT HL HH X Z X
Single Output Cycle
Memory to Host Transfer VCC (min) VIO (min)
VCC
HH HT HL HH X MV X
Dual Input Cycle
Host to Memory Transfer VCC (min) VIO (min)
VCC
HH HT HL HH X HV HV
Dual Latency (Dummy)
Cycle VCC (min) VIO (min)
VCC
HH HT HL HH X X X
Dual Output Cycle
Memory to Host Transfer VCC (min) VIO (min)
VCC
HH HT HL HH X MV MV
QPP Address Input Cycle
Host to Memory Transfer VCC (min) VIO (min)
VCC
HH HT HL X X X HV
Quad Input Cycle
Host to Memory Transfer VCC (min) VIO (min)
VCC
HH HT HL HV HV HV HV
Quad Latency (Dummy)
Cycle VCC (min) VIO (min)
VCC
HH HT HL X X X X
Quad Output Cycle
Memory to Host Transfer VCC (min) VIO (min)
VCC
HH HT HL MV MV MV MV
DDR Single Input Cycle
Host to Memory Transfer VCC (min) VIO (min)
VCC
HH HT HL X X X HV
DDR Dual Input Cycle
Host to Memory Transfer VCC (min) VIO (min)
VCC
HH HT HL X X HV HV
DDR Quad Input Cycle
Host to Memory Transfer VCC (min) VIO (min)
VCC
HH HT HL HV HV HV HV
DDR Latency (Dummy)
Cycle VCC (min) VIO (min)
VCC
HH HT HL MV or Z MV or
Z
MV or
Z
MV or
Z
DDR Single Output Cycle
Memory to Host Transfer VCC (min) VIO (min)
VCC
HH HT HL Z Z MV X
DDR Dual Output Cycle
Memory to Host Transfer VCC (min) VIO (min)
VCC
HH HT HL Z Z MV MV
DDR Quad Output Cycle
Memory to Host Transfer VCC (min) VIO (min)
VCC
HH HT HL MV MV MV MV
Table 3. Interface States Summary (Continued)
Interface State VCC VIO RESET# SCK CS# HOLD# /
I/O3
WP# /
z
I/O2
SO /
I/O1
SI /
I/O0
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3.3.1 Power-Off
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not
react to external signals, and is prevented from performing any program or erase operation.
3.3.2 Low Power Hardware Data Protection
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not
start when the core supply voltage is out of the operating range.
3.3.3 Power-On (Cold) Reset
When the core voltage supply remains at or below the VCC (low) voltage for tPD time, then rises to VCC (Minimum) the device will
begin its Power-On Reset (POR) process. POR continues until the end of tPU. During tPU the device does not react to external input
signals nor drive any outputs. Following the end of tPU the device transitions to the Interface Standby state and can accept
commands. For additional information on POR see Power-On (Cold) Reset on page 30.
3.3.4 Hardware (Warm) Reset
Some of the device package options provide a RESET# input. When RESET# is driven low for tRP time the device starts the
hardware reset process. The process continues for tRPH time. Following the end of both tRPH and the reset hold time following the
rise of RESET# (tRH) the device transitions to the Interface Standby state and can accept commands. For additional information on
hardware reset see POR followed by Hardware Reset on page 30.
3.3.5 Interface Standby
When CS# is high the SPI interface is in standby state. Inputs other than RESET# are ignored. The interface waits for the beginning
of a new command. The next interface state is Instruction Cycle when CS# goes low to begin a new command.
While in interface standby state the memory device draws standby current (ISB) if no embedded algorithm is in progress. If an
embedded algorithm is in progress, the related current is drawn until the end of the algorithm when the entire device returns to
standby current draw.
3.3.6 Instruction Cycle
When the host drives the MSB of an instruction and CS# goes low, on the next rising edge of SCK the device captures the MSB of
the instruction that begins the new command. On each following rising edge of SCK the device captures the next lower significance
bit of the 8 bit instruction. The host keeps RESET# high, CS# low, HOLD# high, and drives Write Protect (WP#) signal as needed for
the instruction. However, WP# is only relevant during instruction cycles of a WRR command and is otherwise ignored.
Each instruction selects the address space that is operated on and the transfer format used during the remainder of the command.
The transfer format may be Single, Dual output, Quad output, Dual I/O, Quad I/O, DDR Single I/O, DDR Dual I/O, or DDR Quad I/O.
The expected next interface state depends on the instruction received.
Some commands are stand alone, needing no address or data transfer to or from the memory. The host returns CS# high after the
rising edge of SCK for the eighth bit of the instruction in such commands. The next interface state in this case is Interface Standby.
3.3.7 Hold
When Quad mode is not enabled (CR[1]=0) the HOLD# / I/O3 signal is used as the HOLD# input. The host keeps RESET# high,
HOLD# low, SCK may be at a valid level or continue toggling, and CS# is low. When HOLD# is low a command is paused, as though
SCK were held low. SI / I/O0 and SO / I/O1 ignore the input level when acting as inputs and are high impedance when acting as
outputs during hold state. Whether these signals are input or output depends on the command and the point in the command
sequence when HOLD# is asserted low.
When HOLD# returns high the next state is the same state the interface was in just before HOLD# was asserted low.
When Quad mode is enabled the HOLD# / I/O3 signal is used as I/O3.
During DDR commands the HOLD# and WP# inputs are ignored.
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3.3.8 Single Input Cycle - Host to Memory Transfer
Several commands transfer information after the instruction on the single serial input (SI) signal from host to the memory device. The
dual output, and quad output commands send address to the memory using only SI but return read data using the I/O signals. The
host keeps RESET# high, CS# low, HOLD# high, and drives SI as needed for the command. The memory does not drive the Serial
Output (SO) signal.
The expected next interface state depends on the instruction. Some instructions continue sending address or data to the memory
using additional Single Input Cycles. Others may transition to Single Latency, or directly to Single, Dual, or Quad Output.
3.3.9 Single Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before
transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During
the latency cycles, the host keeps RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The host
may drive the SI signal during these cycles or the host may leave SI floating. The memory does not use any data driven on SI / I/O0
or other I/O signals during the latency cycles. In dual or quad read commands, the host must stop driving the I/O signals on the
falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during latency cycles so that
there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This prevents
driver conflict between host and memory when the signal direction changes. The memory does not drive the Serial Output (SO) or I/
O signals during the latency cycles.
The next interface state depends on the command structure i.e. the number of latency cycles, and whether the read is single, dual,
or quad width.
3.3.10 Single Output Cycle - Memory to Host Transfer
Several commands transfer information back to the host on the single Serial Output (SO) signal. The host keeps RESET# high, CS#
low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory ignores the Serial Input (SI) signal. The memory
drives SO with data.
The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the command.
3.3.11 Dual Input Cycle - Host to Memory Transfer
The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host keeps RESET# high, CS#
low, HOLD# high. The Write Protect (WP#) signal is ignored. The host drives address on SI / I/O0 and SO / I/O1.
The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are latency cycles needed or
Dual Output Cycle if no latency is required.
3.3.12 Dual Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before
transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During
the latency cycles, the host keeps RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The host
may drive the SI / I/O0 and SO / I/O1 signals during these cycles or the host may leave SI / I/O0 and SO / I/O1 floating. The memory
does not use any data driven on SI / I/O0 and SO / I/O1 during the latency cycles. The host must stop driving SI / I/O0 and SO / I/O1
on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency cycles so
that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. This
prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the SI / I/O0 and
SO / I/O1 signals during the latency cycles.
The next interface state following the last latency cycle is a Dual Output Cycle.
3.3.13 Dual Output Cycle - Memory to Host Transfer
The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps RESET# high, CS# low, and
HOLD# high. The Write Protect (WP#) signal is ignored. The memory drives data on the SI / I/O0 and SO / I/O1 signals during the
dual output cycles.
The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the command.
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3.3.14 QPP or QOR Address Input Cycle
The Quad Page Program and Quad Output Read commands send address to the memory only on I/O0. The other I/O signals are
ignored because the device must be in Quad mode for these commands thus the Hold and Write Protect features are not active. The
host keeps RESET# high, CS# low, and drives I/O0.
For QPP the next interface state following the delivery of address is the Quad Input Cycle.
For QOR the next interface state following address is a Quad Latency Cycle if there are latency cycles needed or Quad Output
Cycle if no latency is required.
3.3.15 Quad Input Cycle - Host to Memory Transfer
The Quad I/O Read command transfers four address or mode bits to the memory in each cycle. The Quad Page Program command
transfers four data bits to the memory in each cycle. The host keeps RESET# high, CS# low, and drives the I/O signals.
For Quad I/O Read the next interface state following the delivery of address and mode bits is a Quad Latency Cycle if there are
latency cycles needed or Quad Output Cycle if no latency is required. For Quad Page Program the host returns CS# high following
the delivery of data to be programmed and the interface returns to standby state.
3.3.16 Quad Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash memory array before
transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). During
the latency cycles, the host keeps RESET# high, CS# low. The host may drive the I/O signals during these cycles or the host may
leave the I/O floating. The memory does not use any data driven on I/O during the latency cycles. The host must stop driving the I/O
signals on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them during all latency
cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency
cycles. This prevents driver conflict between host and memory when the signal direction changes. The memory does not drive the
I/O signals during the latency cycles.
The next interface state following the last latency cycle is a Quad Output Cycle.
3.3.17 Quad Output Cycle - Memory to Host Transfer
The Quad Output Read and Quad I/O Read return data to the host four bits in each cycle. The host keeps RESET# high, and CS#
low. The memory drives data on I/O0-I/O3 signals during the Quad output cycles.
The next interface state continues to be Quad Output Cycle until the host returns CS# to high ending the command.
3.3.18 DDR Single Input Cycle - Host to Memory Transfer
The DDR Fast Read command sends address, and mode bits to the memory only on the I/O0 signal. One bit is transferred on the
rising edge of SCK and one bit on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The other I/O signals
are ignored by the memory.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
3.3.19 DDR Dual Input Cycle - Host to Memory Transfer
The DDR Dual I/O Read command sends address, and mode bits to the memory only on the I/O0 and I/O1 signals. Two bits are
transferred on the rising edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.
The I/O2 and I/O3 signals are ignored by the memory.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
3.3.20 DDR Quad Input Cycle - Host to Memory Transfer
The DDR Quad I/O Read command sends address, and mode bits to the memory on all the I/O signals. Four bits are transferred on
the rising edge of SCK and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.
The next interface state following the delivery of address and mode bits is a DDR Latency Cycle.
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3.3.21 DDR Latency Cycle
DDR Read commands may have one to several latency cycles during which read data is read from the main flash memory array
before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]).
During the latency cycles, the host keeps RESET# high and CS# low. The host may not drive the I/O signals during these cycles. So
that there is sufficient time for the host drivers to turn off before the memory begins to drive. This prevents driver conflict between
host and memory when the signal direction changes. The memory has an option to drive all the I/O signals with a Data Learning
Pattern (DLP) during the last 4 latency cycles. The DLP option should not be enabled when there are fewer than five latency cycles
so that there is at least one cycle of high impedance for turn around of the I/O signals before the memory begins driving the DLP.
When there are more than 4 cycles of latency the memory does not drive the I/O signals until the last four cycles of latency.
The next interface state following the last latency cycle is a DDR Single, Dual, or Quad Output Cycle, depending on the instruction.
3.3.22 DDR Single Output Cycle - Memory to Host Transfer
The DDR Fast Read command returns bits to the host only on the SO / I/O1 signal. One bit is transferred on the rising edge of SCK
and one bit on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The other I/O signals are not driven by the
memory.
The next interface state continues to be DDR Single Output Cycle until the host returns CS# to high ending the command.
3.3.23 DDR Dual Output Cycle - Memory to Host Transfer
The DDR Dual I/O Read command returns bits to the host only on the I/O0 and I/O1 signals. Two bits are transferred on the rising
edge of SCK and two bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low. The I/O2 and I/O3 signals
are not driven by the memory.
The next interface state continues to be DDR Dual Output Cycle until the host returns CS# to high ending the command.
3.3.24 DDR Quad Output Cycle - Memory to Host Transfer
The DDR Quad I/O Read command returns bits to the host on all the I/O signals. Four bits are transferred on the rising edge of SCK
and four bits on the falling edge in each cycle. The host keeps RESET# high, and CS# low.
The next interface state continues to be DDR Quad Output Cycle until the host returns CS# to high ending the command.
3.4 Configuration Register Effects on the Interface
The configuration register bits 7 and 6 (CR1[7:6]) select the latency code for all read commands. The latency code selects the
number of mode bit and latency cycles for each type of instruction.
The configuration register bit 1 (CR1[1]) selects whether Quad mode is enabled to ignore HOLD# and WP# and allow Quad Page
Program, Quad Output Read, and Quad I/O Read commands. Quad mode must also be selected to allow Read DDR Quad I/O
commands.
3.5 Data Protection
Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These
are described below. Other software managed protection methods are discussed in the software section (page 45) of this document.
3.5.1 Power-Up
When the core supply voltage is at or below the VCC (low) voltage, the device is considered to be powered off. The device does not
react to external signals, and is prevented from performing any program or erase operation. Program and erase operations continue
to be prevented during the Power-on Reset (POR) because no command is accepted until the exit from POR to the Interface
Standby state.
3.5.2 Low Power
When VCC is less than VCC (cut-off) the memory device will ignore commands to ensure that program and erase operations can not
start when the core supply voltage is out of the operating range.
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3.5.3 Clock Pulse Count
The device verifies that all program, erase, and Write Registers (WRR) commands consist of a clock pulse count that is a multiple of
eight before executing them. A command not having a multiple of 8 clock pulse count is ignored and no error status is set for the
command.
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4. Electrical Specifications
4.1 Absolute Maximum Ratings
Notes
1. VIO must always be less than or equal VCC + 200 mV.
2. See Input Signal Overshoot on page 25 for allowed maximums during signal transition.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
4.2 Thermal Resistance
4.3 Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
4.3.1 Power Supply Voltages
Some package options provide access to a separate input and output buffer power supply called VIO. Packages which do not
provide the separate VIO connection, internally connect the device VIO to VCC. For these packages the references to VIO are then
also references to VCC.
4.3.2 Temperature Ranges
Note
1. Industrial Plus operating and performance parameters will be determined by device characterization and may vary from standard industrial temperature range devices
as currently shown in this specification.
Table 4. Absolute Maximum Ratings
Storage Temperature Plastic Packages –65°C to +150°C
Ambient Temperature with Power Applied –65°C to +125°C
VCC –0.5V to +4.0V
VIO (Note 1) –0.5V to +4.0V
Input Voltage with Respect to Ground (VSS) (Note 2) –0.5V to +(VIO + 0.5V)
Output Short Circuit Current (Note 3) 100 mA
Table 5. Thermal Resistance
Parameter Description SO3016 FAB024 FAC024 Unit
Theta JA Thermal resistance
(junction to ambient) 30.6 36 36.5 °C/W
VCC 2.7V to 3.6V
VIO 1.65V to VCC +200 mV
Parameter Symbol Device Spec Unit
Min Max
Ambient Temperature TA
Industrial (I) –40 +85
°C
Industrial Plus (V) –40 +105
Automotive, AEC-Q100 Grade 3 (A) –40 +85
Automotive, AEC-Q100 Grade 2 (B) –40 +105
Automotive, AEC-Q100 Grade 1 (M) –40 +125
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4.3.3 Input Signal Overshoot
During DC conditions, input or I/O signals should remain equal to or between VSS and VIO. During voltage transitions, inputs or I/Os
may overshoot VSS to –2.0V or overshoot to VIO +2.0V, for periods up to 20 ns.
Figure 19. Maximum Negative Overshoot Waveform
Figure 20. Maximum Positive Overshoot Waveform
4.4 Power-Up and Power-Down
The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VCC) until VCC reaches
the correct value as follows:
VCC (min) at power-up, and then for a further delay of tPU
VSS at power-down
A simple pull-up resistor (generally of the order of 100 k) on Chip Select (CS#) can usually be used to insure safe and proper
power-up and power-down.
The device ignores all instructions until a time delay of tPU has elapsed after the moment that VCC rises above the minimum VCC
threshold. See Figure 21. However, correct operation of the device is not guaranteed if VCC returns below VCC (min) during tPU. No
command should be sent to the device until the end of tPU.
After power-up (tPU), the device is in Standby mode (not Deep Power Down mode), draws CMOS standby current (ISB), and the
WEL bit is reset.
During power-down or voltage drops below VCC (cut-off), the voltage must drop below VCC (low) for a period of tPD for the part to
initialize correctly on power-up. See Figure 22. If during a voltage drop the VCC stays above VCC (cut-off) the part will stay initialized
and will work correctly when VCC is again above VCC (min). In the event Power-on Reset (POR) did not complete correctly after
power up, the assertion of the RESET# signal or receiving a software reset command (RESET) will restart the POR process.
Normal precautions must be taken for supply rail decoupling to stabilize the VCC supply at the device. Each device in a system
should have the VCC rail decoupled by a suitable capacitor close to the package supply connection (this capacitor is generally of the
order of 0.1 µf).
VIL
- 2.0V
20 ns
20 ns 20 ns
VIH
VIO + 2.0V
20 ns
20 ns 20 ns
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Figure 21. Power-Up
Figure 22. Power-Down and Voltage Drop
Table 6. Power-Up / Power-Down Voltage and Timing
Symbol Parameter Min Max Unit
VCC (min) VCC (minimum operation voltage) 2.7 V
VCC (cut-off) VCC (Cut 0ff where re-initialization is needed) 2.4 V
VCC (low) VCC (low voltage for initialization to occur)
VCC (Low voltage for initialization to occur at embedded)
1.6
2.3 V
tPU V
CC (min) to Read operation 300 µs
tPD V
CC (low) time 10.0 µs
(max)
(min)
VCC
tPU Full Device Access
Time
VCC
VCC
tPD
(max)
(min)
V
CC
t
PU
Device Access
Allowed
Time
V
CC
V
CC
No Device Access Allowed
(cut-off)
V
CC
(low)
V
CC
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4.5 DC Characteristics
Applicable within operating ranges.
Notes
1. Typical values are at TAI = 25°C and VCC = VIO = 3V.
2. Output switching current is not included.
3. Industrial temperature range / Industrial Plus temperature range.
4.5.1 Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the device is disabled, but
may still be in an Active Power mode until all program, erase, and write operations have completed. The device then goes into the
Standby Power mode, and power consumption drops to ISB.
Table 7. DC Characteristics
Symbol Parameter Test Conditions Min Typ (1) Max Unit
VIL Input Low Voltage -0.5 0.2 x VIO V
VIH Input High Voltage 0.7 x VIO V
IO+0.4 V
VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min 0.15 x VIO V
VOH Output High Voltage IOH = –0.1 mA 0.85 x VIO V
ILI Input Leakage
Current VCC = VCC Max, VIN = VIH or VIL ±2 µA
ILO Output Leakage
Current VCC = VCC Max, VIN = VIH or VIL ±2 µA
ICC1 Active Power Supply
Current (READ)
Serial SDR@50 MHz
Serial SDR@133 MHz
Quad SDR @ 80 MHz
Quad SDR @104 MHz
Quad DDR @ 66 MHz
Quad DDR @80 MHz
Outputs unconnected during read data
return(2)
16
33/35 (3)
50
61
75
90
mA
ICC2
Active Power Supply
Current (Page
Program)
CS# = VIO 100 mA
ICC3 Active Power Supply
Current (WRR) CS# = VIO 100 mA
ICC4
Active Power Supply
Current (SE) CS# = VIO 100 mA
ICC5
Active Power Supply
Current (BE) CS# = VIO 100 mA
ISB (Industrial) Standby Current RESET#, CS# = VIO; SI, SCK = VIO or
VSS, Industrial Temp 70 100 µA
ISB (Industrial
Plus) Standby Current RESET#, CS# = VIO; SI, SCK = VIO or
VSS, Industrial Plus Temp 70 300 µA
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5. Timing Specifications
5.1 Key to Switching Waveforms
Figure 23. Waveform Element Meanings
Figure 24. Input, Output, and Timing Reference Levels
Input
Symbol
Output
Valid at logic high or low High Impedance Any change permitted Logic High Logic Low
Changing, state unknown
Valid at logic high or low High Impedance Logic High Logic Low
VIO + 0.4V
0.7 x VIO
0.2 x VIO
- 0.5V
Timing Reference Level
0.5 x VIO
0.85 x VIO
0.15 x VIO
Input Levels Output Levels
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5.2 AC Test Conditions
Figure 25. Test Setup
Notes
1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).
4. DDR Operation.
5.2.1 Capacitance Characteristics
Note
1. For more information on capacitance, please consult the IBIS models.
Table 8. AC Measurement Conditions
Symbol Parameter Min Max Unit
CL
Load Capacitance 30
15 (4) pF
Input Rise and Fall
Times 2.4 ns
Input Pulse Voltage 0.2 x VIO to 0.8 VIO V
Input Timing Ref Voltage 0.5 VIO V
Output Timing Ref
Voltage 0.5 VIO V
Table 9. Capacitance
Parameter Test Conditions Min Max Unit
CIN Input Capacitance (applies to SCK, CS#, RESET#) 1 MHz, TA = 25°C 8 pF
COUT Output Capacitance (applies to All I/O) 1 MHz, TA = 25°C 8 pF
Device
Under
Test
CL
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5.3 Reset
5.3.1 Power-On (Cold) Reset
The device executes a Power-On Reset (POR) process until a time delay of tPU has elapsed after the moment that VCC rises above
the minimum VCC threshold. See Figure 21 on page 26, Table 6 on page 26, and Table 10 on page 31. The device must not be
selected (CS# to go high with VIO) during power-up (tPU), i.e. no commands may be sent to the device until the end of tPU. RESET#
is ignored during POR. If RESET# is low during POR and remains low through and beyond the end of tPU, CS# must remain high
until tRH after RESET# returns high. RESET# must return high for greater than tRS before returning low to initiate a hardware reset.
Figure 26. Reset Low at the End of POR
Figure 27. Reset High at the End of POR
Figure 28. POR followed by Hardware Reset
5.3.2 Hardware (Warm) Reset
When the RESET# input transitions from VIH to VIL the device will reset register states in the same manner as power-on reset but,
does not go through the full reset process that is performed during POR. The hardware reset process requires a period of tRPH to
complete. If the POR process did not complete correctly for any reason during power-up (tPU), RESET# going low will initiate the full
POR process instead of the hardware reset process and will require tPU to complete the POR process.
The RESET# input provides a hardware method of resetting the flash memory device to standby state.
RESET# must be high for tRS following tPU or tRPH, before going low again to initiate a hardware reset.
When RESET# is driven low for at least a minimum period of time (tRP), the device terminates any operation in progress,
tri-states all outputs, and ignores all read/write commands for the duration of tRPH. The device resets the interface to
standby state.
VCC
VIO
RESET#
CS#
If RESET# is low at tPU end
CS# must be high at tPU end
tPU
tRH
VCC
VIO
RESET#
CS#
If RESET# is high at tPU end
CS# may stay high or go low at tPU end
tPU
tPU
VCC
VIO
RESET#
CS#
tRStPU
tPU
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If CS# is low at the time RESET# is asserted, CS# must return high during tRPH before it can be asserted low again after
tRH.
Hardware Reset is only offered in 16-lead SOIC and BGA packages.
Figure 29. Hardware Reset
Notes
1. RESET# Low is optional and ignored during Power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state and tRH will determine
when CS# may go Low.
2. Sum of tRP and tRH must be equal to or greater than tRPH.
Table 10. Hardware Reset Parameters
Parameter Description Limit Time Unit
tRS Reset Setup - Prior Reset end and RESET# high before RESET# low Min 50 ns
tRPH Reset Pulse Hold - RESET# low to CS# low Min 35 µs
tRP RESET# Pulse Width Min 200 ns
tRH Reset Hold - RESET# high before CS# low Min 50 ns
RESET#
CS#
Any prior reset
tRS
tRP
tRHtRH
tRPHtRPH
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5.4 SDR AC Characteristics
Notes
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Full VCC range (2.7 - 3.6V) and CL = 30 pF.
3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF.
4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF.
5. ±10% duty cycle is supported for frequencies
50 MHz.
6. Maximum value only applies during Program/Erase Suspend/Resume commands.
Table 11. AC Characteristics (Single Die Package, VIO = VCC 2.7V to 3.6V)
Symbol Parameter Min Typ Max Unit
FSCK, R SCK Clock Frequency for READ and 4READ instructions DC 50 MHz
FSCK, C SCK Clock Frequency for single commands as shown in Table 39
on page 67 (4) DC 133 MHz
FSCK, C SCK Clock Frequency for the following dual and quad commands:
DOR, 4DOR, QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR DC 104 MHz
FSCK, QPP SCK Clock Frequency for the QPP, 4QPP commands DC 80 MHz
PSCK SCK Clock Period 1/ FSCK
tWH, tCH Clock High Time (5) 45% PSCK ns
tWL, tCL Clock Low Time (5) 45% PSCK ns
tCRT, tCLCH Clock Rise Time (slew rate) 0.1 V/ns
tCFT, tCHCL Clock Fall Time (slew rate) 0.1 V/ns
tCS CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50 ns
tCSS CS# Active Setup Time (relative to SCK) 3 ns
tCSH CS# Active Hold Time (relative to SCK) 3 ns
tSU Data in Setup Time 1.5 3000 (6) ns
tHD Data in Hold Time 2 ns
tV Clock Low to Output Valid
8.0 (2)
7.65 (3)
6.5 (4) ns
tHO Output Hold Time 2 ns
tDIS Output Disable Time 0 8 ns
tWPS WP# Setup Time 20 (1) ns
tWPH WP# Hold Time 100 (1) ns
tHLCH HOLD# Active Setup Time (relative to SCK) 3 ns
tCHHH HOLD# Active Hold Time (relative to SCK) 3 ns
tHHCH HOLD# Non Active Setup Time (relative to SCK) 3 ns
tCHHL HOLD# Non Active Hold Time (relative to SCK) 3 ns
tHZ HOLD# enable to Output Invalid 8 ns
tLZ HOLD# disable to Output Valid 8 ns
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Notes
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. CL = 30 pF.
3. CL = 15 pF.
4. ±10% duty cycle is supported for frequencies
50 MHz.
5. Maximum value only applies during Program/Erase Suspend/Resume commands.
Table 12. AC Characteristics (Single Die Package, VIO 1.65V to 2.7V, VCC 2.7V to 3.6V)
Symbol Parameter Min Typ Max Unit
FSCK, R SCK Clock Frequency for READ, 4READ instructions DC 50 MHz
FSCK, C SCK Clock Frequency for all others (3) DC 66 MHz
PSCK SCK Clock Period 1/ FSCK
tWH, tCH Clock High Time (4) 45% PSCK ns
tWL, tCL Clock Low Time (4) 45% PSCK ns
tCRT, tCLCH Clock Rise Time (slew rate) 0.1 V/ns
tCFT, tCHCL Clock Fall Time (slew rate) 0.1 V/ns
tCS CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50 ns
tCSS CS# Active Setup Time (relative to SCK) 10 ns
tCSH CS# Active Hold Time (relative to SCK) 3 ns
tSU Data in Setup Time 5 3000 (5) ns
tHD Data in Hold Time 4 ns
tV Clock Low to Output Valid 14.5 (2)
12.0 (3) ns
tHO Output Hold Time 2 ns
tDIS Output Disable Time 0 14 ns
tWPS WP# Setup Time 20 (1) ns
tWPH WP# Hold Time 100 (1) ns
tHLCH HOLD# Active Setup Time (relative to SCK) 5 ns
tCHHH HOLD# Active Hold Time (relative to SCK) 5 ns
tHHCH HOLD# Non Active Setup Time (relative to SCK) 5 ns
tCHHL HOLD# Non Active Hold Time (relative to SCK) 5 ns
tHZ HOLD# enable to Output Invalid 14 ns
tLZ HOLD# disable to Output Valid 14 ns
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5.4.1 Clock Timing
Figure 30. Clock Timing
5.4.2 Input / Output Timing
Figure 31. SPI Single Bit Input Timing
Figure 32. SPI Single Bit Output Timing
VIL max
VIH min
tCH
tCRT tCFT
tCL
VIO / 2
PSCK
CS#
SCK
SI
SO
MSB IN LSB IN
tCSS tCSS
tCSH tCSH
tCS
tSU
tHD
CS#
SCK
SI
SO MSB OUT LSB OUT
tCS
tHO tV tDIStLZ
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Figure 33. SPI SDR MIO Timing
Figure 34. Hold Timing
CS#
SCK
IO
MSB IN LSB IN MSB OUT.LSB OUT
tCSH
tCSS
tCSS
tSU
tHD tLZ tHO
tCS
tDIStV
CS#
SCK
HOLD#
SI_or_IO_(during_input)
SO_or_IO_(during_output) A B B C D E
tHZ tHZtLZ tLZ
tCHHL tCHHL
tHLCH
tHLCHtCHHH
tCHHHtHHCH
Hold Condition
Standard Use
Hold Condition
Non-standard Use
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Figure 35. WP# Input Timing
5.5 DDR AC Characteristics
Notes
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
Table 13. AC Characteristics DDR Operation
Symbol Parameter 66 MHz 80 MHz Unit
Min Typ Max Min Typ Max
FSCK, R SCK Clock Frequency for DDR READ
instruction DC 66 DC 80 MHz
PSCK, R SCK Clock Period for DDR READ
instruction 15 12.5 ns
tWH, tCH Clock High Time 45% PSCK 45% PSCK ns
tWL, tCL Clock Low Time 45% PSCK 45% PSCK ns
tCS CS# High Time (Read Instructions) 10 10 ns
tCSS CS# Active Setup Time (relative to SCK) 3 3 ns
tCSH CS# Active Hold Time (relative to SCK) 3 3 ns
tSU I/O in Setup Time 2 3000 (2) 1.5 3000 (2) ns
tHD I/O in Hold Time 2 1.5 ns
tVClock Low to Output Valid 6.5 (1) 6.5 (1) ns
tHO Output Hold Time 1.5 1.5 ns
tDIS Output Disable Time 8 8 ns
tLZ Clock to Output Low Impedance 0 8 0 8 ns
tIO_SKE
W First Output to last Output data valid time 600 600 ps
CS#
WP#
SCK
SI
SO
Phase
7654321076543210
WRR Instruction Input Data
tWPS tWPH
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5.5.1 DDR Input Timing
Figure 36. SPI DDR Input Timing
5.5.2 DDR Output Timing
Figure 37. SPI DDR Output Timing
CS#
SCK
SI_or_IO
SO
MSB IN LSB IN
tCSS tCSS
tCSH tCSH
tCS
tSU
tSU
tHD
tHD
CS#
SCK
SI
SO_or_IO MSB LSB
tCS
tHO tVtV tDIStLZ
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5.5.3 DDR Data Valid Timing Using DLP
Figure 38. SPI DDR Data Valid Window
The minimum data valid window (tDV) and tV minimum can be calculated as follows:
tDV = Minimum half clock cycle time (tCLH) (1)- tOTT(3) - tIO_SKEW(2)
tV _min = tHO + tIO_SKEW + tOTT
Example:
80 MHz clock frequency = 12.5 ns clock period, DDR operations and duty cycle of 45% or higher
tCLH = 0.45 x PSCK = 0.45 x 12.5 ns = 5.625 ns
Bus impedance of 45 ohm and capacitance of 22 pf, with timing reference of 0.75VCC, the rise time from 0 to 1 or fall time 1 to 0 is
1.4(6) x RC time constant (Tau)(5) = 1.4 x 0.99 ns = 1.39 ns
tOTT = rise time + fall time = 1.39 ns + 1.39 ns = 2.78 ns.
Data Valid Window
tDV = tCLH - tIO_SKEW - tOTT = 5.625 ns - 600 ps - 2.78 ns = 2.24ns
tV Minimum
tV _min = tHO + tIO_SKEW + tOTT = 1.0 ns + 600 ps + 2.78 ns = 4.38 ns
Notes
1. tCLH is the shorter duration of tCL or tCH.
2. tIO_SKEW is the maximum difference (delta) between the minimum and maximum tV (output valid) across all IO signals.
3. tOTT is the maximum Output Transition Time from one valid data value to the next valid data value on each IO. tOTT is dependent on system level considerations
including:
a. Memory device output impedance (drive strength).
b. System level parasitics on the IOs (primarily bus capacitance).
c. Host memory controller input VIH and VIL levels at which 0 to 1 and 1 to 0 transitions are recognized.
d. tOTT is not a specification tested by Cypress, it is system dependent and must be derived by the system designer based on the above considerations.
4. tDV is the data valid window.
5. Tau = R (Output Impedance) x C (Load capacitance)
6. Multiplier of Tau time for voltage to rise to 75% of VCC
SCK
IO Slow
IO Fast
IO_valid
Slow D1
S
.Slow D2
Fast D1 Fast D2
D1 D2
tV
tIO_SKEW
tDV
tCL tCH
tOTT
pSCK
tHO
tV_min
tV
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6. Physical Interface
Note
1. Refer to Table2 onpage8 for signal descriptions.
6.1 SOIC 16-Lead Package
6.1.1 SOIC 16 Connection Diagram
Figure 39. 16-Lead SOIC Package, Top View
Table 14. Model Specific Connections
VIO / RFU
Versatile I/O or RFU — Some device models bond this connector to the device I/O power supply,
other models bond the device I/O supply to Vcc within the package leaving this package connector
unconnected.
RESET# / RFU
RESET# or RFU — Some device models bond this connector to the device RESET# signal, other
models bond the RESET# signal to Vcc within the package leaving this package connector
unconnected.
1
2
3
4
16
15
14
13
HOLD#/IO3
VCC
RESET#/RFU
DNU NC
VIO/RFU
SI/IO0
SCK
5
6
7
8
12
11
10
9WP#/IO2
VSS
DNU
DNU
DNU
RFU
CS#
SO/IO1
Document Number: 001-98284 Rev. *O Page 40 of 146
S25FL512S
6.1.2 SOIC 16 Physical Diagram
Figure 40. SOIC 16-Lead, 300-mil Body Width (SO3016)
0.33 C
0.25 M DCA-B
0.20 C A-B
0.10 C
0.10 C
0.10 C D
2X
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
NOTES:
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
LOWER RADIUS OF THE LEAD FOOT.
IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1
10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
h
0
D
L2
N
e
A1
b
c
E
E1
A
0.75
10.30 BSC
1.27 BSC
0.30
10.30 BSC
0.33
0.25
16
0.20
7.50 BSC
0.10
0.31
0.51
2.65
2.35
A2 2.05 2.55
b1 0.27 0.48
0.30
0.20
c1
L1
0.40
L1.27
1.40 REF
0.25 BSC
015°
0
1
2-
DIMENSIONS
SYMBOL MIN. NOM. MAX.
-
-
-
-
-
-
-
-
-
-
-
-
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
0.25 mm FROM THE LEAD TIP.
PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
THE PLASTIC BODY.
PACKAGE LENGTH.
SEATING PLANE.
Document Number: 001-98284 Rev. *O Page 41 of 146
S25FL512S
6.2 FAB024 24-Ball BGA Package
6.2.1 Connection Diagram
Figure 41. 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View
Note
1. Signal connections are in the same relative positions as FAC024 BGA, allowing a single PCB footprint to use either package.
32541
NCNC NCRESET#/
RFU
B
D
E
A
C
VSSSCK NCVCCDNU
RFUCS# NCWP#/IO2DNU
SI/IO0SO/IO1 NCHOLD#/IO3DNU
NCNC NCVIO/RFUNC
Document Number: 001-98284 Rev. *O Page 42 of 146
S25FL512S
6.2.2 FAB024 Physical Diagram
Figure 42. Ball Grid Array 24-Ball 6x8 mm (FAB024)
METALLIZED MARK INDENTATION OR OTHER MEANS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
e REPRESENTS THE SOLDER BALL GRID PITCH.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
8.
9.
7
ALL DIMENSIONS ARE IN MILLIMETERS.
PARALLEL TO DATUM C.
5.
6
4.
3.
2.
1.
NOTES:
SD
b
eD
eE
ME
N
0.35
0.00 BSC
1.00 BSC
1.00 BSC
0.40
24
5
0.45
D1
MD
E1
E
D
A
A1 0.20
-
4.00 BSC
4.00 BSC
5
6.00 BSC
8.00 BSC
-
-1.20
-
SE 0.00 BSC
DIMENSIONS
SYMBOL MIN. NOM. MAX.
"SE" = eE/2.
Document Number: 001-98284 Rev. *O Page 43 of 146
S25FL512S
6.3 FAC024 24-Ball BGA Package
6.3.1 Connection Diagram
Figure 43. 24-Ball BGA, 4 x 6 Ball Footprint (FAC024), Top View
Note
1. Signal connections are in the same relative positions as FAB024 BGA, allowing a single PCB footprint to use either package.
3241
NCNC RESET#/
RFU
B
D
E
A
C
VSSSCK VCCDNU
RFUCS# WP#/IO2DNU
SI/IO0SO/IO1 HOLD#/IO3DNU
NCNC VIO/RFUNC
NC
NCNC NCNC
F
Document Number: 001-98284 Rev. *O Page 44 of 146
S25FL512S
6.3.2 FAC024 Physical Diagram
Figure 44. Ball Grid Array 24-Ball 6x8 mm (FAC024)
6.3.3 Special Handling Instructions for FBGA Packages
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
METALLIZED MARK INDENTATION OR OTHER MEANS.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
e REPRESENTS THE SOLDER BALL GRID PITCH.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
8.
9.
7
ALL DIMENSIONS ARE IN MILLIMETERS.
PARALLEL TO DATUM C.
5.
6
4.
3.
2.
1.
NOTES:
SD
b
eD
eE
ME
N
0.35
0.50 BSC
1.00 BSC
1.00 BSC
0.40
24
4
0.45
D1
MD
E1
E
D
A
A1 0.25
-
5.00 BSC
3.00 BSC
6
6.00 BSC
8.00 BSC
-
-1.20
-
SE 0.50 BSC
DIMENSIONS
SYMBOL MIN. NOM. MAX.
"SE" = eE/2.
Document Number: 001-98284 Rev. *O Page 45 of 146
S25FL512S
Software Interface
This section discusses the features and behaviors most relevant to host system software that interacts with the S25FL512S memory
device.
7. Address Space Maps
7.1 Overview
7.1.1 Extended Address
The S25FL512S device supports 32-bit addresses to enable higher density devices than allowed by previous generation (legacy)
SPI devices that supported only 24-bit addresses. A 24-bit byte resolution address can access only 16 Mbytes (128 Mbits) of
maximum density. A 32-bit byte resolution address allows direct addressing of up to a 4 Gbytes (32 Gbits) of address space.
Legacy commands continue to support 24-bit addresses for backward software compatibility. Extended 32-bit addresses are
enabled in three ways:
Bank address register — a software (command) loadable internal register that supplies the high order bits of address when
legacy 24-bit addresses are in use.
Extended address mode — a bank address register bit that changes all legacy commands to expect 32 bits of address
supplied from the host system.
New commands — that perform both legacy and new functions, which expect 32-bit address.
The default condition at power-up and after reset, is the Bank address register loaded with zeros and the extended address mode
set for 24-bit addresses. This enables legacy software compatible access to the first 128 Mbits of a device.
7.1.2 Multiple Address Spaces
Many commands operate on the main flash memory array. Some commands operate on address spaces separate from the main
flash array. Each separate address space uses the full 32-bit address but may only define a small portion of the available address
space.
7.2 Flash Memory Array
The main flash array is divided into erase units called sectors. The sectors are organized as uniform 256-kbyte sectors.
Note This is a condensed table that uses a sector as a reference. There are address ranges that are not explicitly listed. All 256-kB
sectors have the pattern XXXX0000h-XXXXFFFFh.
7.3 ID-CFI Address Space
The RDIDJ command (9Fh) reads information from a separate flash memory address space for device identification (ID) and
Common Flash Interface (CFI) information. See Device ID and Common Flash Interface (ID-CFI) Address Map on page118 for the
tables defining the contents of the ID-CFI address space. The ID-CFI address space is programmed by Cypress and read-only for
the host system.
Table 15. S25FL512S Sector and Memory Address Map, Uniform 256-kbyte Sectors
Sector Size (kbyte) Sector Count Sector Range Address Range (8-bit) Notes
256 256
SA00 00000000h-0003FFFFh Sector Starting Address
Sector Ending Address
: :
SA255 03FC0000h-03FFFFFFh
Document Number: 001-98284 Rev. *O Page 46 of 146
S25FL512S
7.4 JEDEC JESD216 Serial Flash Discoverable Parameters (SFDP) Space.
The RSFDP command (5Ah) reads information from a separate Flash memory address space for device identification, feature, and
configuration information, in accord with the JEDEC JESD216B standard for Serial Flash Discoverable Parameters. The ID-CFI
address space is incorporated as one of the SFDP parameters.
See Serial Flash Discoverable Parameters (SFDP) Address Map on page 114 for the table defining the contents of the SFDP
address space. The SFDP address space is programmed by Cypress and is read-only for the host system
7.5 OTP Address Space
Each S25FL512S memory device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash
array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.
In the 32-byte region starting at address zero:
The 16 lowest address bytes are programmed by Cypress with a 128-bit random number. Only Cypress is able to program
these bytes.
The next 4 higher address bytes (OTP Lock Bytes) are used to provide one bit per OTP region to permanently protect each
region from programming. The bytes are erased when shipped from Cypress. After an OTP region is programmed, it can
be locked to prevent further programming, by programming the related protection bit in the OTP Lock Bytes.
The next higher 12 bytes of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU bytes
may be programmed by the host system but it must be understood that a future device may use those bits for protection of
a larger OTP space. The bytes are erased when shipped from Cypress.
The remaining regions are erased when shipped from Cypress, and are available for programming of additional permanent data.
Refer to Figure 45 on page 46 for a pictorial representation of the OTP memory space.
The OTP memory space is intended for increased system security. OTP values, such as the random number programmed by
Cypress, can be used to “mate” a flash component with the system CPU/ASIC to prevent device substitution.
The configuration register FREEZE (CR1[0]) bit protects the entire OTP memory space from programming when set to 1. This allows
trusted boot code to control programming of OTP regions then set the FREEZE bit to prevent further OTP memory space
programming during the remainder of normal power-on system operation.
Figure 45. OTP Address Space
32 Byte OTP Region 31
32 Byte OTP Region 30
32 Byte OTP Region 29
.
.
.
32 Byte OTP Region 3
32 Byte OTP Region 2
32 Byte OTP Region 1
32 Byte OTP Region 0
16 Byte Random NumberReserved Lock Bytes
Lock Bits 31 to 0
...
When programmed to
“0” each lock bit
protects its related 32
byte region from any
further programming
Contents of Region 0
{
Byte 0Byte 10Byte 1F
Document Number: 001-98284 Rev. *O Page 47 of 146
S25FL512S
Table 16. OTP Address Map
Region Byte Address Range (Hex) Contents Initial Delivery State (Hex)
Region 0
000
Least Significant Byte of
Spansion Programmed
Random Number
Spansion Programmed
Random Number
... ...
00F
Most Significant Byte of
Spansion Programmed
Random Number
010 to 013
Region Locking Bits
Byte 10 [bit 0] locks region 0
from programming when = 0
...
Byte 13 [bit 7] locks region 31
from programming when = 0
All bytes = FF
014 to 01F Reserved for Future Use (RFU) All bytes = FF
Region 1 020 to 03F Available for User
Programming All bytes = FF
Region 2 040 to 05F Available for User
Programming All bytes = FF
... ... Available for User
Programming All bytes = FF
Region 31 3E0 to 3FF Available for User
Programming All bytes = FF
Document Number: 001-98284 Rev. *O Page 48 of 146
S25FL512S
7.6 Registers
Registers are small groups of memory cells used to configure how the S25FL512-S memory device operates or to report the status
of device operations. The registers are accessed by specific commands. The commands (and hexadecimal instruction codes) used
for each register are noted in each register description. The individual register bits may be volatile, nonvolatile, or One Time
Programmable (OTP). The type for each bit is noted in each register description. The default state shown for each bit refers to the
state after power-on reset, hardware reset, or software reset if the bit is volatile. If the bit is nonvolatile or OTP, the default state is
the value of the bit when the device is shipped from Cypress. Nonvolatile bits have the same cycling (erase and program) endurance
as the main flash array.
Table 17. Register Descriptions
Register Abbreviation Type Bit Location
Status Register 1 SR1[7:0] Volatile 7:0
Configuration Register 1 CR1[7:0] Volatile 7:0
Status Register 2 SR2[7:0] RFU 7:0
AutoBoot Register ABRD[31:0] Nonvolatile 31:0
Bank Address Register BRAC[7:0] Volatile 7:0
ECC Status Register ECCSR[7:0] Volatile 7:0
ASP Register ASPR[15:1] OTP 15:1
ASP Register ASPR[0] RFU 0
Password Register PASS[63:0] Nonvolatile OTP 63:0
PPB Lock Register PPBL[7:1] Volatile 7:1
PPB Lock Register PPBL[0] Volatile
Read Only 0
PPB Access Register PPBAR[7:0] Nonvolatile 7:0
DYB Access Register DYBAR[7:0] Volatile 7:0
SPI DDR Data Learning Registers NVDLR[7:0] Nonvolatile 7:0
SPI DDR Data Learning Registers VDLR[7:0] Volatile 7:0
Document Number: 001-98284 Rev. *O Page 49 of 146
S25FL512S
7.6.1 Status Register 1 (SR1)
Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN 06h), Write Disable
(WRDI 04h), Clear Status Register (CLSR 30h).
The Status Register contains both status and control bits:
Status Register Write Disable (SRWD) SR1[7]: Places the device in the Hardware Protected mode when this bit is set to 1 and the
WP# input is driven low. In this mode, the SRWD, BP2, BP1, and BP0 bits of the Status Register become read-only bits and the
Write Registers (WRR) command is no longer accepted for execution. If WP# is high the SRWD bit and BP bits may be changed by
the WRR command. If SRWD is 0, WP# has no effect and the SRWD bit and BP bits may be changed by the WRR command. The
SRWD bit has the same nonvolatile endurance as the main flash array.
Program Error (P_ERR) SR1[6]: The Program Error Bit is used as a program operation success or failure indication. When the
Program Error bit is set to a 1 it indicates that there was an error in the last program operation. This bit will also be set when the user
attempts to program within a protected main memory sector or locked OTP region. When the Program Error bit is set to a 1 this bit
can be reset to 0 with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRR command.
Erase Error (E_ERR) SR1[5]: The Erase Error Bit is used as an Erase operation success or failure indication. When the Erase Error
bit is set to a 1 it indicates that there was an error in the last erase operation. This bit will also be set when the user attempts to erase
an individual protected main memory sector. The Bulk Erase command will not set E_ERR if a protected sector is found during the
command execution. When the Erase Error bit is set to a 1 this bit can be reset to 0 with the Clear Status Register (CLSR)
command. This is a read-only bit and is not affected by the WRR command.
Table 18. Status Register-1 (SR1)
Bits Field
Name Function Type Default State Description
7 SRWD Status Register
Write Disable Nonvolatile 0
1 = Locks state of SRWD, BP, and configuration
register bits when WP# is low by ignoring WRR
command
0 = No protection, even when WP# is low
6 P_ERR Programming
Error Occurred Volatile, Read only 0 1 = Error occurred.
0 = No Error
5 E_ERR Erase Error
Occurred Volatile, Read only 0 1 = Error occurred
0 = No Error
4 BP2
Block
Protection
Volatile if CR1[3]=1,
Nonvolatile if
CR1[3]=0
1 if CR1[3]=1,
0 when
shipped from
Cypress
Protects selected range of sectors (Block) from
Program or Erase
3 BP1
2 BP0
1 WEL Write Enable
Latch Volatile 0
1 = Device accepts Write Registers (WRR), program
or erase commands
0 = Device ignores Write Registers (WRR), program
or erase commands
This bit is not affected by WRR, only WREN and
WRDI commands affect this bit
0 WIP Write in
Progress Volatile, Read only 0
1 = Device Busy, a Write Registers (WRR), program,
erase or other operation is in progress
0 = Ready Device is in standby mode and can accept
commands
Document Number: 001-98284 Rev. *O Page 50 of 146
S25FL512S
Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software-protected against program
and erase commands. The BP bits are either volatile or nonvolatile, depending on the state of the BP nonvolatile bit (BPNV) in the
configuration register. When one or more of the BP bits is set to 1, the relevant memory area is protected against program and
erase. The Bulk Erase (BE) command can be executed only when the BP bits are cleared to 0’s. See Block Protection on page 59
for a description of how the BP bit values select the memory array area protected. The BP bits have the same nonvolatile endurance
as the main flash array.
Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to 1 to enable program, write, or erase operations as a means to
provide protection against inadvertent changes to memory or register values. The Write Enable (WREN) command execution sets
the Write Enable Latch to a 1 to allow any program, erase, or write commands to execute afterwards. The Write Disable (WRDI)
command can be used to set the Write Enable Latch to a 0 to prevent all program, erase, and write commands from execution. The
WEL bit is cleared to 0 at the end of any successful program, write, or erase operation. Following a failed operation the WEL bit may
remain set and should be cleared with a WRDI command following a CLSR command. After a power down/power up sequence,
hardware reset, or software reset, the Write Enable Latch is set to a 0 The WRR command does not affect this bit.
Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase operation, or any other
operation, during which a new operation command will be ignored. When the bit is set to a 1 the device is busy performing an
operation. While WIP is 1, only Read Status (RDSR1 or RDSR2), Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status
Register (CLSR), and Software Reset (RESET) commands may be accepted. ERSP and PGSP will only be accepted if memory
array erase or program operations are in progress. The status register E_ERR and P_ERR bits are updated while WIP = 1. When
P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy and unable to receive
new operation commands. A Clear Status Register (CLSR) command must be received to return the device to standby mode. When
the WIP bit is cleared to 0 no operation is in progress. This is a read-only bit.
7.6.2 Configuration Register 1 (CR1)
Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The Configuration Register bits can be
changed using the WRR command with sixteen input cycles.
The configuration register controls certain interface and data protection functions.
Table 19. Configuration Register (CR1)
Bits Field Name Function Type Default
State Description
7 LC1
Latency Code Nonvolatile
0 Selects number of initial read
latency cycles
See Latency Code Tables
6 LC0 0
5 TBPROT Configures Start of Block Protection OTP 0
1 = BP starts at bottom (Low
address)
0 = BP starts at top (High address)
4 DNU DNU DNU 0 Do not Use
3 BPNV Configures BP2-0 in Status Register OTP 0 1 = Volatile
0 = Nonvolatile
2 RFU RFU RFU 0 Reserved for Future Use
1 QUAD Puts the device into Quad I/O
operation Nonvolatile 0 1 = Quad
0 = Dual or Serial
0 FREEZE
Lock current state of BP2-0 bits in
Status Register, TBPROT in
Configuration Register, and OTP
regions
Volatile 0
1 = Block Protection and OTP
locked
0 = Block Protection and OTP un-
locked
Document Number: 001-98284 Rev. *O Page 51 of 146
S25FL512S
Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between the end of address and
the start of read data output for all read commands.
Some read commands send mode bits following the address to indicate that the next command will be of the same type with an
implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte, only a new address and
mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of
commands.
Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can be
returned to the host system. Some read commands require additional latency cycles as the SCK frequency is increased.
The following latency code tables provide different latency settings that are configured by Cypress. The High Performance versus
the Enhanced High Performance settings are selected by the ordering part number.
Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported at the frequency
shown. Read is supported only up to 50 MHz but the same latency value is assigned in each latency code and the command may be
used when the device is operated at 50 MHz with any latency code setting. Similarly, only the Fast Read command is supported
up to 133 MHz but the same 10b latency code is used for Fast Read up to 133 MHz and for the other dual and quad read commands
up to 104 MHz. It is not necessary to change the latency code from a higher to a lower frequency when operating at lower
frequencies where a particular command is supported. The latency code values for a higher frequency can be used for accesses at
lower frequencies.
The High Performance settings provide latency options that are the same or faster than alternate source SPI memories. These
settings provide mode bits only for the Quad I/O Read command.
The Enhanced High Performance settings similarly provide latency options the same or faster than additional alternate source SPI
memories and adds mode bits for the Dual I/O Read, DDR Fast Read, and DDR
Dual I/O Read commands.
Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the start of read data, if
there are 5 or more dummy cycles. See Read Memory Array Commands on page 82 for more information on the DLP.
Table 20. Latency Codes for SDR High Performance
Freq.
(MHz
)
LC
Read Fast Read Read Dual Out Read Quad Out Dual I/O Read Quad I/O Read
(03h, 13h) (0Bh, 0Ch) (3Bh, 3Ch) (6Bh, 6Ch) (BBh, BCh) (EBh, ECh)
Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy
5011000000000421
8000 0808080424
9001 0808080524
10410 0808080625
13310 0 8
Table 21. Latency Codes for DDR High Performance
Freq.
(MHz) LC
DDR Fast Read DDR Dual I/O Read Read DDR Quad I/O
(0Dh, 0Eh) (BDh, BEh) (EDh, EEh)
Mode Dummy Mode Dummy Mode Dummy
5011040413
6600050616
6601060717
6610070818
Document Number: 001-98284 Rev. *O Page 52 of 146
S25FL512S
Note
1. When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides 5 or more dummy cycles should be selected to allow 1
cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP. It is recommended to use LC 10 for DDR Fast Read, LC 01 for
DDR Dual I/O Read, and LC 00 for DDR Quad I/O Read, if the Data Learning Pattern (DLP) for DDR is used.
Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits BP2, BP1, and BP0 in the
Status Register. As described in the status register section, the BP2-0 bits allow the user to optionally protect a portion of the array,
ranging from 1/64, 1/4, 1/2, etc., up to the entire array. When TBPROT is set to a 0 the Block Protection is defined to start from the
top (maximum address) of the array. When TBPROT is set to a 1 the Block Protection is defined to start from the bottom (zero
address) of the array. The TBPROT bit is OTP and set to a 0 when shipped from Cypress. If TBPROT is programmed to 1, an
attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).
The desired state of TBPROT must be selected during the initial configuration of the device during system manufacture; before the
first program or erase operation on the main flash array. TBPROT must not be programmed after programming or erasing is done in
the main flash array.
CR1[4]: Reserved for Future Use
Block Protection Nonvolatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2-0 bits in the Status Register are
volatile or nonvolatile. The BPNV bit is OTP and cleared to a0 with the BP bits cleared to 000 when shipped from Cypress. When
BPNV is set to a 0 the BP2-0 bits in the Status Register are nonvolatile. When BPNV is set to a 1 the BP2-0 bits in the Status
Register are volatile and will be reset to binary 111 after POR, hardware reset, or command reset. If BPNV is programmed to 1, an
attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).
CR1[2]: Reserved for Future Use.
Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit - Quad mode. That is, WP#
becomes I/O2 and HOLD# becomes I/O3. The WP# and HOLD# inputs are not monitored for their normal functions and are
internally set to high (inactive). The commands for Serial, Dual Output, and Dual I/O Read still function normally but, there is no need
to drive WP# and Hold# inputs for those commands when switching between commands using different data path widths. The
QUAD bit must be set to one when using Read Quad Out, Quad I/O Read, Read DDR Quad I/O, and Quad Page Program
commands. The QUAD bit is nonvolatile.
Table 22. Latency Codes for SDR Enhanced High Performance
Freq.
(MHz) LC
Read Fast Read Read Dual Out Read Quad Out Dual I/O Read Quad I/O Read
(03h, 13h) (0Bh, 0Ch) (3Bh, 3Ch) (6Bh, 6Ch) (BBh, BCh) (EBh, ECh)
Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy Mode Dummy
5011000000004021
≤ 80 00 0 8 0 8 0 8 4 0 2 4
≤ 90 01 0 8 0 8 0 8 4 1 2 4
≤104 10 0 8 0 8 0 8 4 2 2 5
≤133 10 0 8
Table 23. Latency Codes for DDR Enhanced High Performance
Freq.
(MHz) LC
DDR Fast Read DDR Dual I/O Read Read DDR Quad I/O
(0Dh, 0Eh) (BDh, BEh) (EDh, EEh)
Mode Dummy Mode Dummy Mode Dummy
5011412213
6600422416
6601442517
6610452618
8000422416
8001442517
8010452618
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Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to 1, locks the current state of the BP2-0 bits in Status Register, the
TBPROT and TBPARM bits in the Configuration Register, and the OTP address space. This prevents writing, programming, or
erasing these areas. As long as the FREEZE bit remains cleared to logic 0 the other bits of the Configuration Register, including
FREEZE, are writable, and the OTP address space is programmable. Once the FREEZE bit has been written to a logic 1 it can only
be cleared to a logic 0 by a power-off to power-on cycle or a hardware reset. Software reset will not affect the state of the FREEZE
bit. The FREEZE bit is volatile and the default state of FREEZE after power-on is 0. The FREEZE bit can be set in parallel with
updating other values in CR1 by a single WRR command.
7.6.3 Status Register 2 (SR2)
Related Commands: Read Status Register 2 (RDSR2 07h).
Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase Suspend mode. This is a
status bit that cannot be written. When Erase Suspend bit is set to 1, the device is in erase suspend mode. When Erase Suspend bit
is cleared to 0, the device is not in erase suspend mode. Refer to Erase Suspend and Resume Commands (75h) (7Ah) for details
about the Erase Suspend/Resume commands.
Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in Program Suspend mode.
This is a status bit that cannot be written. When Program Suspend bit is set to 1, the device is in program suspend mode. When the
Program Suspend bit is cleared to 0, the device is not in program suspend mode. Refer to Program Suspend (PGSP 85h) and
Resume (PGRS 8Ah) on page 98 for details.
7.6.4 AutoBoot Register
Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).
The AutoBoot Register provides a means to automatically read boot code as part of the power on reset, hardware reset, or software
reset process.
Table 24. Status Register-2 (SR2)
Bits Field Name Function Type Default State Description
7 RFU Reserved 0 Reserved for Future Use
6 RFU Reserved 0 Reserved for Future Use
5 RFU Reserved 0 Reserved for Future Use
4 RFU Reserved 0 Reserved for Future Use
3 RFU Reserved 0 Reserved for Future Use
2 RFU Reserved 0 Reserved for Future Use
1 ES Erase Suspend Volatile, Read only 0 1 = In erase suspend mode
0 = Not in erase suspend mode
0 PS Program
Suspend Volatile, Read only 0 1 = In program suspend mode
0 = Not in program suspend mode
Table 25. AutoBoot Register
Bits Field Name Function Type Default State Description
31 to 9 ABSA AutoBoot Start
Address Nonvolatile 000000h 512 byte boundary address for the start of
boot code access
8 to 1 ABSD AutoBoot Start
Delay Nonvolatile 00h
Number of initial delay cycles between
CS# going low and the first bit of boot code
being transferred
0 ABE AutoBoot Enable Nonvolatile 0 1 = AutoBoot is enabled
0 = AutoBoot is not enabled
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7.6.5 Bank Address Register
Related Commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read (BRRD 16h) and Bank
Register Write (BRWR 17h).
The Bank Address register supplies additional high order bits of the main flash array byte boundary address for legacy commands
that supply only the low order 24 bits of address. The Bank Address is used as the high bits of address (above A23) for all 3-byte
address commands when EXTADD=0. The Bank Address is not used when EXTADD = 1 and traditional 3-byte address commands
are instead required to provide all four bytes of address.
Extended Address (EXTADD) BAR[7]: EXTADD controls the address field size for legacy SPI commands. By default (power up
reset, hardware reset, and software reset), it is cleared to 0 for 3 bytes (24 bits) of address. When set to 1, the legacy commands will
require 4 bytes (32 bits) for the address field. This is a volatile bit.
7.6.6 ECC Status Register (ECCSR)
Related Commands: ECC Read (ECCRD 18h). ECCSR does not have user programmable nonvolatile bits. All defined bits are
volatile read only status. The default state of these bits are set by hardware. See Automatic ECC on page 96.
The status of ECC in each ECC unit is provided by the 8-bit ECC Status Register (ECCSR). The ECC Register Read command is
written followed by an ECC unit address. The contents of the status register then indicates, for the selected ECC unit, whether there
is an error in the ECC unit eight bit error correction code, the ECC unit of 16 Bytes of data, or that ECC is disabled for that ECC unit.
ECCSR[2] = 1 indicates an error was corrected in the ECC. ECCSR[1] = 1 indicates an error was corrected in the ECC unit data.
ECCSR[0] = 1 indicates the ECC is disabled. The default state of “0” for all these bits indicates no failures and ECC is enabled.
ECCSR[7:3] are reserved. These have undefined high or low values that can change from one ECC status read to another. These
bits should be treated as “don’t care” and ignored by any software reading status.
Table 26. Bank Address Register (BAR)
Bits Field Name Function Type Default State Description
7 EXTADD Extended Address
Enable Volatile 0b
1 = 4-byte (32-bits) addressing required from command.
0 = 3-byte (24-bits) addressing from command + Bank
Address
6 to 2 RFU Reserved Volatile 00000b Reserved for Future Use
1 BA25 Bank Address Volatile 0 A25 for 512 Mb device
0 BA24 Bank Address Volatile 0 A24 for 512 Mb device
Table 27. ECC Status Register (ECCSR)
Bits Field Name Function Type Default
State Description
7 to 3 RFU Reserved 0 Reserved for Future Use
2 EECC Error in ECC Volatile, Read only 0
1 = Single Bit Error found in the ECC unit eight
bit error correction code
0 = No error.
1 EECCD Error in ECC unit
data Volatile, Read only 0
1 = Single Bit Error corrected in ECC unit
data.
0 = No error.
0 ECCDI ECC Disabled Volatile, Read only 0 1 = ECC is disabled in the selected ECC unit.
0 = ECC is enabled in the selected ECC unit.
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7.6.7 ASP Register (ASPR)
Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh).
The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP)
features.
Note
1. Default value depends on ordering part number, see Initial Delivery State on page 140.
Reserved for Future Use (RFU) ASPR[15:3, 0].
Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password Protection Mode is
permanently selected.
Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent Protection Mode is
permanently selected. PWDMLB and PSTMLB are mutually exclusive, only one may be programmed to zero.
Table 28. ASP Register (ASPR)
Bits Field Name Function Type Default
State Description
15 to 9 RFU Reserved OTP 1 Reserved for Future Use
8 RFU Reserved OTP (Note 1) Reserved for Future Use
7 RFU Reserved OTP (Note 1) Reserved for Future Use
6 RFU Reserved OTP 1 Reserved for Future Use
5 RFU Reserved OTP (Note 1) Reserved for Future Use
4 RFU Reserved OTP (Note 1) Reserved for Future Use
3 RFU Reserved OTP (Note 1) Reserved for Future Use
2 PWDMLB
Password
Protection Mode
Lock Bit
OTP 1 0 = Password Protection Mode permanently enabled.
1 = Password Protection Mode not permanently enabled.
1 PSTMLB
Persistent
Protection Mode
Lock Bit
OTP 1 0 = Persistent Protection Mode permanently enabled.
1 = Persistent Protection Mode not permanently enabled.
0 RFU Reserved OTP 1 Reserved for Future Use
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7.6.8 Password Register (PASS)
Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h).
7.6.9 PPB Lock Register (PPBL)
Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h)
7.6.10 PPB Access Register (PPBAR)
Related Commands: PPB Read (PPBRD E2h)
7.6.11 DYB Access Register (DYBAR)
Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h).
Table 29. Password Register (PASS)
Bits Field
Name Function Type Default State Description
63 to 0 PWD Hidden
Password OTP FFFFFFFF-
FFFFFFFFh
Nonvolatile OTP storage of 64-bit password. The password
is no longer readable after the password protection mode is
selected by programming ASP register bit 2 to zero.
Table 30. PPB Lock Register (PPBL)
Bits Field Name Function Type Default State Description
7 to 1 RFU Reserved Volatile 00h Reserved for Future Use
0 PPBLOCK Protect PPB Array Volatile Persistent Protection Mode = 1
Password Protection Mode = 0
0 = PPB array protected until next power
cycle or hardware reset
1 = PPB array may be programmed or
erased.
Table 31. PPB Access Register (PPBAR)
Bits Field Name Function Type Default
State Description
7 to 0 PPB Read or Program
per sector PPB Nonvolatile FFh
00h = PPB for the sector addressed by the PPBRD or
PPBP command is programmed to 0, protecting that
sector from program or erase operations.
FFh = PPB for the sector addressed by the PPBRD or
PPBP command is erased to 1, not protecting that
sector from program or erase operations.
Table 32. DYB Access Register (DYBAR)
Bits Field Name Function Type Default State Description
7 to 0 DYB Read or Write
per sector DYB Volatile FFh
00h = DYB for the sector addressed by the DYBRD or DYBP
command is cleared to 0, protecting that sector from program or
erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBP
command is set to 1, not protecting that sector from program or
erase operations.
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7.6.12 SPI DDR Data Learning Registers
Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read (DLPRD 41h).
The Data Learning Pattern (DLP) resides in an 8-bit Nonvolatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data
Learning Register (VDLR). When shipped from Cypress, the NVDLR value is 00h. Once programmed, the NVDLR cannot be
reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR. The VDLR can be written to at
any time, but on reset or power cycles the data pattern will revert back to what is in the NVDLR. During the learning phase described
in the SPI DDR modes, the DLP will come from the VDLR. Each I/O will output the same DLP value for every clock edge. For
example, if the DLP is 34h (or binary 00110100) then during the first clock edge all I/O’s will output 0; subsequently, the 2nd clock
edge all I/O’s will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands.
Table 33. Nonvolatile Data Learning Register (NVDLR)
Bits Field Name Function Type Default State Description
7 to 0 NVDLP
Nonvolatile
Data Learning
Pattern
OTP 00h
OTP value that may be transferred to the host during
DDR read command latency (dummy) cycles to
provide a training pattern to help the host more
accurately center the data capture point in the
received data bits.
Table 34. Volatile Data Learning Register (NVDLR)
Bits Field Name Function Type Default State Description
7 to 0 VDLP
Volatile Data
Learning
Pattern
Volatile
Takes the value of
NVDLR during POR or
Reset
Volatile copy of the NVDLP used to enable and deliver
the Data Learning Pattern (DLP) to the outputs. The
VDLP may be changed by the host during system
operation.
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8. Data Protection
8.1 Secure Silicon Region (OTP)
The device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash array. The OTP area is
divided into 32, individually lockable, 32-byte aligned and length regions.
The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with the system CPU/
ASIC to prevent device substitution. See OTP Address Space on page 46, One Time Program Array Commands on page 103, and
OTP Read (OTPR 4Bh) on page 103.
8.1.1 Reading OTP Memory Space
The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-kB OTP address range
will yield indeterminate data.
8.1.2 Programming OTP Memory Space
The protocol of the OTP programming command is the same as Page Program. The OTP Program command can be issued multiple
times to any given OTP address, but this address space can never be erased.
Automatic ECC is programmed on the first programming operation to each 16-byte region. Programming within a 16-byte region
more than once disables the ECC. It is recommended to program each 16-byte portion of each 32-byte region once so that ECC
remains enabled to provide the best data integrity.
The valid address range for OTP Program is depicted in Figure 45 on page 46. OTP Program operations outside the valid OTP
address range will be ignored and the WEL in SR1 will remain high (set to 1). OTP Program operations while FREEZE = 1 will fail
with P_ERR in SR1 set to 1.
8.1.3 Cypress Programmed Random Number
Cypress standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit
random number using the Linear Congruential Random Number Method. The seed value for the algorithm is a random number
concatenated with the day and time of tester insertion.
8.1.4 Lock Bytes
The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the highest address region
related to the byte. The next higher address byte similarly protects the next higher 8 regions. The LSB bit of the lowest address Lock
Byte protects the higher address 16 bytes of the lowest address region. In other words, the LSB of location 0x10 protects all the Lock
Bytes and RFU bytes in the lowest address region from further programming. See OTP Address Space on page 46.
8.2 Write Enable Command
The Write Enable (WREN) command must be written prior to any command that modifies nonvolatile data. The WREN command
sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes) during power-up, hardware reset, or after the
device completes the following commands:
– Reset
Page Program (PP)
Sector Erase (SE)
Bulk Erase (BE)
Write Disable (WRDI)
Write Registers (WRR)
Quad-input Page Programming (QPP)
OTP Byte Programming (OTPP)
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8.3 Block Protection
The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register TBPROT bit can be used
to protect an address range of the main flash array from program and erase operations. The size of the range is determined by the
value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT bit of the configuration register.
When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still be used to protect
sectors not protected by the Block Protection scheme. In the case that both ASP and Block Protection are used on the same sector
the logical OR of ASP and Block Protection related to the sector is used. Recommendation: ASP and Block Protection should not be
used concurrently. Use one or the other, but not both.
8.3.1 Freeze Bit
Bit 0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register 1 and the TBPROT bit
in the Configuration Register to their value at the time the FREEZE bit is set to 1. Once the FREEZE bit has been written to a logic 1
it cannot be cleared to a logic 0 until a power-on-reset is executed. As long as the FREEZE bit is cleared to logic 0 the status register
BP bits and the TBPROT bit of the Configuration Register are writable. The FREEZE bit also protects the entire OTP memory space
from programming when set to 1. Any attempt to change the BP bits with the WRR command while FREEZE = 1 is ignored and no
error status is set.
8.3.2 Write Protect Signal
The Write Protect (WP#) input in combination with the Status Register Write Disable (SRWD) bit provide hardware input signal
controlled protection. When WP# is Low and SRWD is set to 1 the Status and Configuration register is protected from alteration.
This prevents disabling or changing the protection defined by the Block Protect bits.
Table 35. Upper Array Start of Protection (TBPROT = 0)
Status Register Content
Protected Fraction of Memory Array
Protected Memory (kbytes)
FL512S
512 Mb
BP2 BP1 BP0
0 0 0 None 0
0 0 1 Upper 64th 1024
0 1 0 Upper 32nd 2048
0 1 1 Upper 16th 4096
1 0 0 Upper 8th 8192
1 0 1 Upper 4th 16384
1 1 0 Upper Half 32768
1 1 1 All Sectors 65536
Table 36. Lower Array Start of Protection (TBPROT = 1)
Status Register Content
Protected Fraction of Memory Array
Protected Memory (kbytes)
FL512S
512 Mb
BP2 BP1 BP0
0 0 0 None 0
0 0 1 Lower 64th 1024
0 1 0 Lower 32nd 2048
0 1 1 Lower 16th 4096
1 0 0 Lower 8th 8192
1 0 1 Lower 4th 16384
1 1 0 Lower Half 32768
1 1 1 All Sectors 65536
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8.4 Advanced Sector Protection
Advanced Sector Protection (ASP) is the name used for a set of independent hardware and software methods used to disable or
enable programming or erase operations, individually, in any or all sectors. An overview of these methods is shown in Figure 46
on page 60.
Block Protection and ASP protection settings for each sector are logically OR’d to define the protection for each sector, i.e. if either
mechanism is protecting a sector the sector cannot be programmed or erased. Refer to Block Protection on page 59 for full details of
the BP2-0 bits.
Figure 46. Advanced Sector Protection Overview
Every main flash array sector has a nonvolatile (PPB) and a volatile (DYB) protection bit associated with it. When either bit is 0, the
sector is protected from program and erase operations.
The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for managing the state of
the PPB Lock bit, Persistent Protection and Password Protection.
The Persistent Protection method sets the PPB Lock bit to 1 during POR, or Hardware Reset so that the PPB bits are unprotected by
a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB. There is no command in the Persistent
Protection method to set the PPB Lock bit to 1, therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.
The Persistent Protection method allows boot code the option of changing sector protection by programming or erasing the PPB,
then protecting the PPB from further change for the remainder of normal system operation by clearing the PPB Lock bit to 0. This is
sometimes called Boot-code controlled sector protection.
The Password method clears the PPB Lock bit to 0 during POR, or Hardware Reset to protect the PPB. A 64-bit password may be
permanently programmed and hidden for the password method. A command can be used to provide a password for comparison with
the hidden password. If the password matches, the PPB Lock bit is set to 1 to unprotect the PPB. A command can be used to clear
the PPB Lock bit to 0. This method requires use of a password to control PPB protection.
The selection of the PPB Lock bit management method is made by programming OTP bits in the ASP Register so as to permanently
select the method used.
ASP Register
One Time Programmable
Password Method
(ASPR[2]=0)
Persistent Method
(ASPR[1]=0)
64
-
bit Password
(One Time Protect)
PBB Lock Bit
0” = PPBs locked
Sector 0
Memory Array
Sector N
-
2
Sector 1
Sector 2
Sector N
-
1
Sector N
1.) N = Highest Address Sector
PPB 0
Persistent
Protection Bit
(PPB)
PPB N
-
2
PPB 1
PPB 2
PPB N
-
1
PPB N
DYB 0
Dynamic
Protection Bit
(DYB)
DYB N
-
2
DYB 1
DYB 2
DYB N
-
1
DYB N
2.)
3.) DYB are volatile bits
“1”=PPBs unlocked
64
-
bit Password
(One Time Protect)
Sector 0
Memory Array
Sector N
-
2
Sector 1
Sector 2
Sector N
-
1
Sector N
1.) N = Highest Address Sector,
a sector is protected if its PPB =”0”
or its DYB = “0”
PPB 0
Persistent
Protection Bits
(PPB)
PPB N
-
2
PPB 1
PPB 2
PPB N
-
1
PPB N
DYB 0
Dynamic
Protection Bits
(DYB)
DYB N
-
2
DYB 1
DYB 2
DYB N
-
1
DYB N
PPB are programmed individually
but erased as a group
3.) DYB are volatile bits
4.) PPB Lock bit is volatile and
defaults to “1” (persistent
mode).or “0” (password mode)
upon reset
5.) PPB Lock = “0” locks all PPBs
to their current state
6.) Password Method requires a
password to set PPB Lock to “1”
to enable program or erase of
PPB bits
7.) Persistent Method only allows
PPB Lock to be cleared to “0” to
prevent program or erase of PPB
bits. Power off or hardware reset
required to set PPB Lock to “1”
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8.4.1 ASP Register
The ASP register is used to permanently configure the behavior of Advanced Sector Protection (ASP) features. See Table 28
on page 55.
As shipped from the factory, all devices default ASP to the Persistent Protection mode, with all sectors unprotected, when power is
applied. The device programmer or host system must then choose which sector protection method to use. Programming either of
the, one-time programmable, Protection Mode Lock Bits, locks the part permanently in the selected mode:
ASPR[2:1] = 11 = No ASP mode selected, Persistent Protection Mode is the default.
ASPR[2:1] = 10 = Persistent Protection Mode permanently selected.
ASPR[2:1] = 01 = Password Protection Mode permanently selected.
ASPR[2:1] = 00 = Illegal condition, attempting to program both bits to zero results in a programming failure.
ASP register programming rules:
If the password mode is chosen, the password must be programmed prior to setting the Protection Mode Lock Bits.
Once the Protection Mode is selected, the Protection Mode Lock Bits are permanently protected from programming and no
further changes to the ASP register is allowed.
The programming time of the ASP Register is the same as the typical page programming time. The system can determine the status
of the ASP register programming operation by reading the WIP bit in the Status Register. See Status Register 1 (SR1) on page 49
for information on WIP.
After selecting a sector protection method, each sector can operate in each of the following states:
Dynamically Locked — A sector is protected and can be changed by a simple command.
Persistently Locked — A sector is protected and cannot be changed if its PPB Bit is 0.
Unlocked — The sector is unprotected and can be changed by a simple command.
8.4.2 Persistent Protection Bits
The Persistent Protection Bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is related to each sector.
When a PPB is 0, its related sector is protected from program and erase operations. The PPB are programmed individually but must
be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased
at the same time. The PPB have the same program and erase endurance as the main flash memory array. Preprogramming and
verification prior to erasure are handled by the device.
Programming a PPB bit requires the typical page programming time. Erasing all the PPBs requires typical sector erase time. During
PPB bit programming and PPB bit erasing, status is available by reading the Status register. Reading of a PPB bit requires the initial
access time of the device.
Notes
Each PPB is individually programmed to 0 and all are erased to 1 in parallel.
If the PPB Lock bit is 0, the PPB Program or PPB Erase command does not execute and fails without programming or erasing the
PPB.
The state of the PPB for a given sector can be verified by using the PPB Read command.
8.4.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYB only control the protection for
sectors that have their PPB set to 1. By issuing the DYB Write command, a DYB is cleared to 0 or set to 1, thus placing each sector
in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes,
yet does not prevent the easy removal of protection when changes are needed. The DYBs can be set or cleared as often as needed
as they are volatile bits.
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8.4.4 PPB Lock Bit (PPBL[0])
The PPB Lock Bit is a volatile bit for protecting all PPB bits. When cleared to 0, it locks all PPBs and when set to 1, it allows the
PPBs to be changed.
The PLBWR command is used to clear the PPB Lock bit to 0. The PPB Lock Bit must be cleared to 0 only after all the PPBs are
configured to the desired settings.
In Persistent Protection mode, the PPB Lock is set to 1 during POR or a hardware reset. When cleared to 0, no software command
sequence can set the PPB Lock bit to 1, only another hardware reset or power-up can set the PPB Lock bit.
In the Password Protection mode, the PPB Lock bit is cleared to 0 during POR or a hardware reset. The PPB Lock bit can only be
set to 1 by the Password Unlock command.
8.4.5 Sector Protection States Summary
Each sector can be in one of the following protection states:
Unlocked — The sector is unprotected and protection can be changed by a simple command. The protection state defaults
to unprotected after a power cycle, software reset, or hardware reset.
Dynamically Locked — A sector is protected and protection can be changed by a simple command. The protection state is
not saved across a power cycle or reset.
Persistently Locked — A sector is protected and protection can only be changed if the PPB Lock Bit is set to 1. The
protection state is nonvolatile and saved across a power cycle or reset. Changing the protection state requires
programming and or erase of the PPB bits
8.4.6 Persistent Protection Mode
The Persistent Protection method sets the PPB Lock bit to 1 during POR or Hardware Reset so that the PPB bits are unprotected by
a device hardware reset. Software reset does not affect the PPB Lock bit. The PLBWR command can clear the PPB Lock bit to 0 to
protect the PPB. There is no command to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or
hardware reset.
Table 37. Sector Protection States
Protection Bit Values Sector State
PPB Lock PPB DYB
1 1 1 Unprotected – PPB and DYB are changeable
1 1 0 Protected – PPB and DYB are changeable
1 0 1 Protected – PPB and DYB are changeable
1 0 0 Protected – PPB and DYB are changeable
0 1 1 Unprotected – PPB not changeable, DYB is changeable
0 1 0 Protected – PPB not changeable, DYB is changeable
0 0 1 Protected – PPB not changeable, DYB is changeable
0 0 0 Protected – PPB not changeable, DYB is changeable
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8.4.7 Password Protection Mode
Password Protection Mode allows an even higher level of security than the Persistent Sector Protection Mode, by requiring a 64-bit
password for unlocking the PPB Lock bit. In addition to this password requirement, after power up and hardware reset, the PPB Lock
bit is cleared to 0 to ensure protection at power-up. Successful execution of the Password Unlock command by entering the entire
password clears the PPB Lock bit, allowing for sector PPB modifications.
Password Protection Notes
Once the Password is programmed and verified, the Password Mode (ASPR[2]=0) must be set in order to prevent reading
the password.
The Password Program Command is only capable of programming ‘0’s. Programming a 1 after a cell is programmed as a 0
results in the cell left as a 0 with no programming error set.
The password is all 1’s when shipped from Cypress. It is located in its own memory space and is accessible through the
use of the Password Program and Password Read commands.
All 64-bit password combinations are valid as a password.
The Password Mode, once programmed, prevents reading the 64-bit password and further password programming. All
further program and read commands to the password region are disabled and these commands are ignored. There is no
means to verify what the password is after the Password Mode Lock Bit is selected. Password verification is only allowed
before selecting the Password Protection mode.
The Protection Mode Lock Bits are not erasable.
The exact password must be entered in order for the unlocking function to occur. If the password unlock command provided
password does not match the hidden internal password, the unlock operation fails in the same manner as a programming
operation on a protected sector. The P_ERR bit is set to one and the WIP Bit remains set. In this case it is a failure to
change the state of the PPB Lock bit because it is still protected by the lack of a valid password.
The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an
unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in an attempt to correctly
match a password. The Read Status Register 1 command may be used to read the WIP bit to determine when the device
has completed the password unlock command or is ready to accept a new password command. When a valid password is
provided the password unlock command does not insert the 100 µs delay before returning the WIP bit to zero.
If the password is lost after selecting the Password Mode, there is no way to set the PPB Lock bit.
ECC status may only be read from sectors that are readable. In read protection mode the addresses are forced to the boot
sector address. ECC status is shown in that sector while read protection mode is active.
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9. Commands
All communication between the host system and the S25FL512S memory device is in the form of units called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands
may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All
instruction, address, and data information is transferred serially between the host system and memory device.
All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.
Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to the host serially on
SO signal.
Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be returned to the host as a
sequence of bit pairs on I/O0 and I/O1 or four bit (nibble) groups on I/O0, I/O1, I/O2, and I/O3.
Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on I/O0 and I/O1 or, four bit (nibble)
groups on I/O0, I/O1, I/O2, and I/O3. Data is returned to the host similarly as bit pairs on I/O0 and I/O1 or, four bit (nibble) groups on
I/O0, I/O1, I/O2, and I/O3.
Commands are structured as follows:
Each command begins with an eight bit (byte) instruction.
The instruction may be stand alone or may be followed by address bits to select a location within one of several address
spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.
The Serial Peripheral Interface with Multiple I/O provides the option for each transfer of address and data information to be
done one, two, or four bits in parallel. This enables a trade off between the number of signal connections (I/O bus width)
and the speed of information transfer. If the host system can support a two or four bit wide I/O bus the memory performance
can be increased by using the instructions that provide parallel two bit (dual) or parallel four bit (quad) transfers.
The width of all transfers following the instruction are determined by the instruction sent.
All sIngle bits or parallel bit groups are transferred in most to least significant bit order.
Some instructions send instruction modifier (mode) bits following the address to indicate that the next command will be of
the same type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction
byte, only a new address and mode bits. This reduces the time needed to send each command when the same command
type is repeated in a sequence of commands.
The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period
before read data is returned to the host.
Read latency may be zero to several SCK cycles (also referred to as dummy cycles).
All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted into the device
with the most significant byte first. All data is transferred with the lowest address byte sent first. Following bytes of data are
sent in lowest to highest byte address order i.e. the byte address increments.
All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored.
The embedded operation will continue to execute without any affect. A very limited set of commands are accepted during
an embedded operation. These are discussed in the individual command descriptions. While a program, erase, or write
operation is in progress, it is recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most
commands to the device, to ensure the new command can be accepted.
Depending on the command, the time for execution varies. A command to read status information from an executing
command is available to determine when the command completes execution and whether the command was successful.
Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the
host system and the memory device generally handle the details of signal relationships and timing. For this reason, signal
relationships and timing are not covered in detail within this software interface focused section of the document. Instead,
the focus is on the logical sequence of bits transferred in each command rather than the signal timing and relationships.
Following are some general signal relationship descriptions to keep in mind. For additional information on the bit level
format and signal timing relationships of commands, see Command Protocol on page 14.
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The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide transfers.
The memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive the I/O0-I/O3
signals during Dual and Quad transfers.
–All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept
low throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for eight bit
transfer multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned high
not at an 8 bit boundary.
9.1 Command Set Summary
9.1.1 Extended Addressing
To accommodate addressing above 128 Mb, there are three options:
1. New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.
2. For backward compatibility to the 3-byte address instructions, the standard instructions can be used in conjunction with
the EXTADD Bit in the Bank Address Register (BAR[7]). By default BAR[7] is cleared to 0 (following power up and
hardware reset), to enable 3-byte (24-bit) addressing. When set to 1, the legacy commands are changed to require 4
bytes (32 bits) for the address field. The following instructions can be used in conjunction with EXTADD bit to switch from
3 bytes to 4 bytes of address field.
Instruction Name Description Code (Hex)
4FAST_READ Read Fast (4-byte Address) 0C
4READ Read (4-byte Address) 13
4DOR Read Dual Out (4-byte Address) 3C
4QOR Read Quad Out (4-byte Address) 6C
4DIOR Dual I/O Read (4-byte Address) BC
4QIOR Quad I/O Read (4-byte Address) EC
4DDRFR Read DDR Fast (4-byte Address) 0E
4DDRDIOR DDR Dual I/O Read (4-byte Address) BE
4DDRQIOR DDR Quad I/O Read (4-byte Address) EE
4PP Page Program (4-byte Address) 12
4QPP Quad Page Program (4-byte Address) 34
4SE Erase 256 kB (4-byte Address) DC
Instruction Name Description Code (Hex)
READ Read (3-byte Address) 03
FAST_READ Read Fast (3-byte Address) 0B
DOR Read Dual Out (3-byte Address) 3B
QOR Read Quad Out (3-byte Address) 6B
DIOR Dual I/O Read (3-byte Address) BB
QIOR Quad I/O Read (3-byte Address) EB
DDRFR Read DDR Fast (3-byte Address) 0D
DDRDIOR DDR Dual I/O Read (3-byte Address) BD
DDRQIOR DDR Quad I/O Read (3-byte Address) ED
PP Page Program (3-byte Address) 02
QPP Quad Page Program (3-byte Address) 32
SE Erase 256 kB (3-byte Address) D8
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3. For backward compatibility to the 3-byte addressing, the standard instructions can be used in conjunction with the Bank
Address Register:
a. The Bank Address Register is used to switch between 128-Mbit (16-Mbyte) banks of memory, The standard 3-byte
address selects an address within the bank selected by the Bank Address Register.
i. The host system writes the Bank Address Register to access beyond the first 128 Mbits of
memory.
ii. This applies to read, erase, and program commands.
b. The Bank Register provides the high order (4th) byte of address, which is used to address the available memory at
addresses greater than 16 Mbytes.
c. Bank Register bits are volatile.
i. On power up, the default is Bank0 (the lowest address 16 Mbytes).
d. For Read, the device will continuously transfer out data until the end of the array.
i. There is no bank to bank delay.
ii. The Bank Address Register is not updated.
iii. The Bank Address Register value is used only for the initial address of an access.
Table 38. Bank Address Map
Bank Address Register Bits Bank Memory Array Address Range (Hex)
Bit 1 Bit 0
0 0 0 00000000 00FFFFFF
0 1 1 01000000 01FFFFFF
1 0 2 02000000 02FFFFFF
1 1 3 03000000 03FFFFFF
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Table 39. S25FL512S Command Set (sorted by function)
Function Command
Name Command Description Instruction
Value (Hex)
Maximum
Frequency
(MHz)
Read Device
Identification
READ_ID
(REMS) Read Electronic Manufacturer Signature 90 133
RDID Read ID (JEDEC Manufacturer ID and JEDEC CFI) 9F 133
RES Read Electronic Signature AB 50
RSFDP Read Serial Flash Discoverable Parameters 5A 133
Register Access
RDSR1 Read Status Register-1 05 133
RDSR2 Read Status Register-2 07 133
RDCR Read Configuration Register-1 35 133
WRR Write Register (Status-1, Configuration-1) 01 133
WRDI Write Disable 04 133
WREN Write Enable 06 133
CLSR Clear Status Register-1 - Erase/Prog. Fail Reset 30 133
ECCRD ECC Read (4-byte address 18 133
ABRD AutoBoot Register Read 14
133
(QUAD=0)
104
(QUAD=1)
ABWR AutoBoot Register Write 15 133
BRRD Bank Register Read 16 133
BRWR Bank Register Write 17 133
BRAC Bank Register Access
(Legacy Command formerly used for Deep Power Down) B9 133
DLPRD Data Learning Pattern Read 41 133
PNVDLR Program NV Data Learning Register 43 133
WVDLR Write Volatile Data Learning Register 4A 133
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S25FL512S
Read Flash Array
READ Read (3- or 4-byte address) 03 50
4READ Read (4-byte address) 13 50
FAST_READ Fast Read (3- or 4-byte address) 0B 133
4FAST_READ Fast Read (4-byte address) 0C 133
DDRFR DDR Fast Read (3- or 4-byte address) 0D 80
4DDRFR DDR Fast Read (4-byte address) 0E 80
DOR Read Dual Out (3- or 4-byte address) 3B 104
4DOR Read Dual Out (4-byte address) 3C 104
QOR Read Quad Out (3- or 4-byte address) 6B 104
4QOR Read Quad Out (4-byte address) 6C 104
DIOR Dual I/O Read (3- or 4-byte address) BB 104
4DIOR Dual I/O Read (4-byte address) BC 104
DDRDIOR DDR Dual I/O Read (3- or 4-byte address) BD 80
4DDRDIOR DDR Dual I/O Read (4-byte address) BE 80
QIOR Quad I/O Read (3- or 4-byte address) EB 104
4QIOR Quad I/O Read (4-byte address) EC 104
DDRQIOR DDR Quad I/O Read (3- or 4-byte address) ED 80
4DDRQIOR DDR Quad I/O Read (4-byte address) EE 80
Program Flash
Array
PP Page Program (3- or 4-byte address) 02 133
4PP Page Program (4-byte address) 12 133
QPP Quad Page Program (3- or 4-byte address) 32 80
QPP Quad Page Program - Alternate instruction (3- or 4-byte address) 38 80
4QPP Quad Page Program (4-byte address) 34 80
PGSP Program Suspend 85 133
PGRS Program Resume 8A 133
Erase Flash
Array
BE Bulk Erase 60 133
BE Bulk Erase (alternate command) C7 133
SE Erase 256 kB (3- or 4-byte address) D8 133
4SE Erase 256 kB (4-byte address) DC 133
ERSP Erase Suspend 75 133
ERRS Erase Resume 7A 133
One Time
Program Array
OTPP OTP Program 42 133
OTPR OTP Read 4B 133
Table 39. S25FL512S Command Set (sorted by function) (Continued)
Function Command
Name Command Description Instruction
Value (Hex)
Maximum
Frequency
(MHz)
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S25FL512S
9.1.2 Read Device Identification
There are multiple commands to read information about the device manufacturer, device type, and device features. SPI memories
from different vendors have used different commands and formats for reading information about the memories. The S25FL512S
device supports the three most common device information commands.
9.1.3 Register Read or Write
There are multiple registers for reporting embedded operation status or controlling device configuration options. There are
commands for reading or writing these registers. Registers contain both volatile and nonvolatile bits. Nonvolatile bits in registers are
automatically erased and programmed as a single (write) operation.
9.1.3.1 Monitoring Operation Status
The host system can determine when a write, program, erase, suspend or other embedded operation is complete by monitoring the
Write in Progress (WIP) bit in the Status Register. The Read from Status Register-1 command provides the state of the WIP bit. The
program error (P_ERR) and erase error (E_ERR) bits in the status register indicate whether the most recent program or erase
command has not completed successfully. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating
the device remains busy. Under this condition, only the CLSR, WRDI, RDSR1, RDSR2, and software RESET commands are valid
commands. A Clear Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the device to
standby state. CLSR clears the WIP, P_ERR, and E_ERR bits. WRDI clears the WEL bit. Alternatively, Hardware Reset, or Software
Reset (RESET) may be used to return the device to standby state.
9.1.3.2 Configuration
There are commands to read, write, and protect registers that control interface path width, interface timing, interface address length,
and some aspects of data protection.