ADV7390-93 Datasheet

Analog Devices Inc.

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Datasheet

Low Power, Chip Scale,
10-Bit SD/HD Video Encoder
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. I Document Feedback
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Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
3 high quality, 10-bit video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Lead frame chip scale package (LFCSP) options
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Wafer level chip scale package (WLCSP) option
30-ball, 5 × 6 WLCSP with single DAC output
Advanced power management
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
74.25 MHz 8-/10-/16-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (fSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
Enhanced definition (ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only)
Copy generation management system (CGMS)
Wide screen signaling (WSS)
Closed captioning
Serial MPU interface with I2C compatibility
2.7 V or 3.3 V analog operation
1.8 V digital operation
1.8 V or 3.3 V I/O operation
Temperature range: −40°C to +85°C
W Grade automotive range: −40°C to +105°C
Qualified for automotive applications
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. I | Page 2 of 107
TABLE OF CONTENTS
Features .............................................................................................. 1
Revision History ............................................................................... 3
Applications ....................................................................................... 5
General Description ......................................................................... 5
Functional Block Diagrams ............................................................. 6
Specifications ..................................................................................... 7
Power Supply Specifications........................................................ 7
Input Clock Specifications .......................................................... 7
Analog Output Specifications ..................................................... 7
Digital Input/Output Specifications—3.3 V ............................. 8
Digital Input/Output Specifications—1.8 V ............................. 8
MPU Port Timing Specifications ............................................... 8
Digital Timing Specifications—3.3 V ........................................ 9
Digital Timing Specifications—1.8 V ...................................... 10
Video Performance Specifications ........................................... 11
Power Specifications .................................................................. 11
Timing Diagrams ........................................................................ 12
Absolute Maximum Ratings .......................................................... 18
Thermal Resistance .................................................................... 18
ESD Caution ................................................................................ 18
Pin Configurations and Function Descriptions ......................... 19
Typical Performance Characteristics ........................................... 21
MPU Port Description ................................................................... 26
I2C Operation .............................................................................. 26
Register Map Access ....................................................................... 28
Register Programming ............................................................... 28
Subaddress Register (SR7 to SR0) ............................................ 28
ADV7390/ADV7391 Input Configuration ................................. 46
Standard Definition .................................................................... 46
Enhanced Definition/High Definition .................................... 46
Enhanced Definition (at 54 MHz) ........................................... 46
ADV7392/ADV7393 Input Configuration ................................. 47
Standard Definition .................................................................... 47
Enhanced Definition/High Definition .................................... 48
Enhanced Definition (at 54 MHz) ........................................... 48
Output Configuration .................................................................... 49
Design Features ............................................................................... 50
Output Oversampling ................................................................ 50
HD Interlace External HSYNC and VSYNC Considerations .... 51
ED/HD Timing Reset ................................................................ 51
SD Subcarrier Frequency Lock ................................................. 51
SD VCR FF/RW Sync ................................................................ 52
Vertical Blanking Interval ......................................................... 52
SD Subcarrier Frequency Control ............................................ 52
SD Noninterlaced Mode ............................................................ 52
SD Square Pixel Mode ............................................................... 53
Filters ............................................................................................ 54
ED/HD Test Pattern Color Controls ....................................... 55
Color Space Conversion Matrix ............................................... 55
SD Luma and Color Scale Control ........................................... 57
SD Hue Adjust Control .............................................................. 57
SD Brightness Detect ................................................................. 57
SD Brightness Control ............................................................... 57
SD Input Standard Autodetection ............................................ 58
Double Buffering ........................................................................ 58
Programmable DAC Gain Control .......................................... 58
Gamma Correction .................................................................... 59
ED/HD Sharpness Filter and Adaptive Filter Controls ......... 60
ED/HD Sharpness Filter and Adaptive Filter Application
Examples ...................................................................................... 61
SD Digital Noise Reduction ...................................................... 62
SD Active Video Edge Control ................................................. 64
External Horizontal and Vertical Synchronization Control ....... 65
Low Power Mode ........................................................................ 66
Cable Detection .......................................................................... 66
DAC Autopower-Down ............................................................. 66
Sleep Mode .................................................................................. 66
Pixel and Control Port Readback ............................................. 67
Reset Mechanisms ...................................................................... 67
SD Teletext Insertion ................................................................. 67
Printed Circuit Board Layout and Design .................................. 69
Unused Pins ................................................................................ 69
DAC Configurations .................................................................. 69
Video Output Buffer and Optional Output Filter .................. 69
Printed Circuit Board (PCB) Layout ....................................... 70
Additional Layout Considerations for the WLCSP Package ....... 71
Typical Applications Circuits .................................................... 72
Copy Generation Management System ....................................... 74
SD CGMS .................................................................................... 74
ED CGMS .................................................................................... 74
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. I | Page 3 of 107
HD CGMS .................................................................................... 74
CGMS CRC Functionality ......................................................... 74
SD Wide Screen Signaling .............................................................. 77
SD Closed Captioning .................................................................... 78
Internal Test Pattern Generation ................................................... 79
SD Test Patterns ........................................................................... 79
ED/HD Test Patterns .................................................................. 79
SD Timing ........................................................................................ 80
HD Timing ....................................................................................... 85
Video Output Levels ....................................................................... 86
SD YPrPb Output Levels—SMPTE/EBU N10 ........................ 86
ED/HD YPrPb Output Levels ................................................... 87
SD/ED/HD RGB Output Levels ................................................ 88
SD Output Plots .......................................................................... 89
Video Standards .............................................................................. 90
Configuration Scripts ..................................................................... 92
Standard Definition .................................................................... 92
Enhanced Definition .................................................................. 99
High Definition ......................................................................... 101
ADV7390/ADV7391/ADV7392/ADV7393 Evaluation Board .... 104
Outline Dimensions ...................................................................... 105
Ordering Guide ......................................................................... 107
Automotive Products ................................................................ 107
REVISION HISTORY
2/15—Rev. H to Rev. I
Changed ADV739x to ADV7390/ADV7391/ADV7392/
ADV7393 ............................................................................. Universal
Changes to Figure 19 ...................................................................... 19
Changes to Table 15 ........................................................................ 20
Changes to Figure 144 ..................................................................104
Updated Outline Dimensions ......................................................106
Changes to Ordering Guide .........................................................107
9/14—Rev. G to Rev. H
Changed Storage Temperature Range from −60°C to +100°C to
−60°C to +150°C; Table 13 ............................................................. 18
Updated Figure 145, Outline Dimensions .................................105
Changes to Ordering Guide .........................................................107
2/13—Rev. F to Rev. G
Change to Features Section .............................................................. 1
Changes to Table 14 ........................................................................ 18
Changes to Figure 62 ...................................................................... 48
Changes to Ordering Guide .........................................................107
11/12—Rev. E to Rev. F
Updated Outline Dimensions ......................................................105
Changes to Ordering Guide .........................................................107
2/12—Rev. D to Rev. E
Changes to Table 1 ............................................................................ 5
Changes to Digital Input/Output Specifications—
1.8 V Section ...................................................................................... 8
Changes to Table 15 ........................................................................ 21
Changes to Table 20 ........................................................................ 31
Changes to Table 23 ........................................................................ 34
Changes to Table 28 ........................................................................ 39
Changes to 16-Bit 4:4:4 RGB Mode Section ................................ 47
Added External Sync Polarity Section .......................................... 51
Deleted ED/HD Nonstandard Timing Mode Section, Figure 63,
and Table 41, Renumbered Sequentially ...................................... 51
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section ..................................................................................... 52
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode Section,
Figure 64, and Figure 65 ................................................................. 52
Changes to Ordering Guide ......................................................... 121
11/11—Rev. C to Rev. D
Changes to Features Section ............................................................ 1
Updated Outline Dimensions and changes to Automotive
Products Section ............................................................................ 107
9/11—Rev. B to Rev. C
Changes to MPU Port Description Section ................................. 26
Changes to Ordering Guide ......................................................... 107
7/10—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Change to Applications Section ...................................................... 5
Changes to General Description ..................................................... 5
Added Table 2, Renumbered Subsequent Tables .......................... 5
Added Figure 2, Renumbered Subsequent Figures ...................... 6
Changes to Full-Drive Output Current Parameter, Table 5 ........ 7
Changes to Table 14 ........................................................................ 18
Added Figure 20 .............................................................................. 19
Changes to Table 15 ........................................................................ 19
Changes to ADV7390/ADV7391 Input Configuration
Section .............................................................................................. 45
Added Additional Layout Considerations for the WLCSP
Package Section ............................................................................... 71
Added Figure 97 .............................................................................. 73
Changes to Configuration Scripts Section ................................... 92
Changes to Subaddress 0x00, Table 66 ......................................... 93
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Changes to Subaddress 0x00, Table 66 ........................................ 93
Changes to Subaddress 0x00, Table 80 ........................................ 95
Changes to Subaddress 0x00, Table 83 ........................................ 95
Changes to Subaddress 0x00, Table 97 ........................................ 98
Updated Outline Dimensions, Added Figure 150 .................... 106
Changes to Ordering Guide ........................................................ 106
3/09Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Deleted Detailed Features Section, Changes to Table 1............... 4
Changes to Figure 1, Added Figure 2 ............................................. 5
Changes to Table 2, Input Clock Specifications Section, and
Analog Output Specifications Section ........................................... 6
Changes to Digital Input/Output Specifications3.3 V Section
and Table 5 ......................................................................................... 7
Added Digital Input/Output Specifications1.8 V Section and
Table 6 ................................................................................................ 7
Changes to MPU Port Timing Specifications Section,
Default Conditions ........................................................................... 7
Changes to Digital Timing Specifications3.3 V Section and
Table 8 ................................................................................................ 8
Added Digital Timing Specifications1.8 V Section and
Table 9 ................................................................................................ 9
Added Video Performance Specifications Section, Default
Conditions ....................................................................................... 10
Added Power Specifications Section, Default Conditions ........ 10
Changes to Table 11 ........................................................................ 10
Changes to Figure 16 ...................................................................... 16
Changes to Table 12 ........................................................................ 17
Changes to Table 14, Pin 19 and Pin 1 Descriptions ................. 18
Changes to MPU Port Description Section ................................ 25
Changes to I2C Operation Section ............................................... 25
Added Table 15 ............................................................................... 25
Changes to Table 17 ........................................................................ 28
Changes to Table 19, 0x30 Bit Description ................................. 30
Changes to Table 27 ....................................................................... 37
Changes to Table 29, 0x8B Bit Description ................................. 39
Changes to Table 30 ....................................................................... 40
Changes to Table 31 ....................................................................... 41
Added Table 32 ............................................................................... 42
Renamed Features Section to Design Features Section ............. 48
Changes to ED/HD Nonstandard Timing Mode Section ......... 48
Added the HD Interlace External HSYNC and VSYNC
Considerations Section .................................................................. 49
Changes to SD Subcarrier Frequency Lock, Subcarrier Reset,
and Timing Reset Section.............................................................. 49
Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 51
Changes to Programming the FSC Section ................................... 51
Changes to Subaddress 0x82, Bit 4 Section ................................. 51
Added SD Manual CSC Matrix Adjust Feature Section ............ 54
Added Table 47 ............................................................................... 55
Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 56
Changes to Subaddress 0xBA Section.......................................... 56
Added Sleep Mode Section ........................................................... 65
Changes to Pixel and Control Port Readback Section .............. 66
Changes to Reset Mechanisms Section ....................................... 66
Added SD Teletext Insertion Section ........................................... 66
Added Figure 87 ............................................................................. 67
Added Figure 88 ............................................................................. 68
Changes to DAC Configuration Section ..................................... 68
Added Unused Pins Section .......................................................... 68
Changes to Power Supply Sequencing Section ........................... 70
Changes to Internal Test Pattern Generation Section ............... 77
Changes to SD Timing, Mode 0 (CCIR-656)Slave Option
(Subaddress 0x8A = XXXXX000) Section .................................. 78
10/06Revision 0: Initial Version
Rev. I | Page 4 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
APPLICATIONS
Mobile handsets
Digital still cameras
Portable media and DVD players
Portable game consoles
Digital camcorders
Set-top box (STB)
Automotive infotainment (ADV7392 and ADV7393 only)
GENERAL DESCRIPTION
The ADV7390/ADV7391/ADV7392/ADV7393 are a family of
high speed, digital-to-analog video encoders on single monolithic
chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for
the WLCSP package) provide support for composite (CVBS),
S-Video (Y-C), or component (YPrPb/RGB) analog outputs in
either standard definition (SD) or high definition (HD) video
formats. The single DAC WLCSP package supports CVBS
(NTSC and PAL) output only in SD resolution (see Table 2).
Optimized for low power operation, occupying a minimal
footprint, and requiring few external components, these
encoders are ideally suited to portable and power-sensitive
applications requiring TV-out functionality. Cable detection
and DAC autopower-down features ensure that power
consumption is kept to a minimum.
The ADV7390/ADV7391 have an 8-bit video input port that
supports SD video formats over an SDR interface and HD video
formats over a DDR interface. The ADV7392/ADV7393 have
a 16-bit video input port that can be configured in a variety of
ways. SD RGB input is supported.
All members of the family support embedded EAV/SAV timing
codes, external video synchronization signals, and the I2and
communication protocol. Table 1 and Table 2 list the video
standards directly supported by the ADV7390/ADV7391/
ADV7392/ADV7393 family.
Table 1. Standards Directly Supported by the LFCSP Packages
Active
Resolution I/P1
Frame
Rate (Hz)
Clock Input
(MHz) Standard
720 × 240 P 59.94 27
720 × 288 P 50 27
720 × 480
I
29.97
27
ITU-R
BT.601/656
720 × 576 I 25 27 ITU-R
BT.601/656
640 × 480 I 29.97 24.54 NTSC Square
Pixel
768 × 576 I 25 29.5 PAL Square
Pixel
720 × 483 P 59.94 27 SMPTE 293M
720 × 483 P 59.94 27 BTA T-1004
720 × 483 P 59.94 27 ITU-R BT.1358
720 × 576
P
50
27
ITU-R BT.1358
720 × 483 P 59.94 27 ITU-R BT.1362
720 × 576 P 50 27 ITU-R BT.1362
1920 × 1035 I 30 74.25 SMPTE 240M
1920 × 1035 I 29.97 74.1758 SMPTE 240M
1280 × 720
P
60, 50, 30,
25, 24
74.25
SMPTE 296M
1280 × 720 P 23.97,
59.94, 29.97
74.1758 SMPTE 296M
1920 × 1080 I 30, 25 74.25 SMPTE 274M
1920 × 1080
I
29.97
74.1758
SMPTE 274M
1920 × 1080 P 30, 25, 24 74.25 SMPTE 274M
1920 × 1080 P 23.98, 29.97 74.1758 SMPTE 274M
1920 × 1080 P 24 74.25 ITU-R BT.709-5
1 I = interlaced, P = progressive.
Table 2. Standards Directly Supported by the WLCSP Package
Active
Resolution I/P1
Frame
Rate (Hz)
Clock Input
(MHz) Standard
720 × 480 I 29.97 27 ITU-R
BT.601/656
720 × 576 I 25 27 ITU-R
BT.601/656
640 × 480
I
29.97
24.54
Pixel
768 × 576 I 25 29.5 PAL Square
Pixel
1 I = interlaced, P = progressive.
Rev. I | Page 5 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. I | Page 6 of 107
FUNCTIONAL BLOCK DIAGRAMS
GND_IO
V
DD_IO
RESET HSYNC VSYNC
11-BIT
DAC 1 DAC 1
11-BIT
DAC 2 DAC 2
11-BIT
DAC 3 DAC 3
MULTIPLEXER
REFERENCE
AND CABLE
DETECT
16×/4× OVERSAMPLING PLL
VIDEO TIMING GENERATOR
POWER
MANAGEMENT
CONTROL
CLKIN PV
DD
PGND EXT_LF COMP
R
SET
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCrCb
HDTV
TEST
PATTERN
GENERATOR
YCbCr
TO
RGB MATRIX
ASYNC
BYPASS
DGND (2) V
DD
(2) SCL SDA ALSB SFL
MPU PORT SUBCARRIER FREQUENCY
LOCK (SFL)
YCrCb
TO
RGB
PROGRAMMABLE
CHROMINANCE
FILTER
ADD
BURST SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
FILTER
AGND V
AA
ADD
SYNC
VBI DATA SERVICE
INSERTION
PROGRAMMABLE
LUMINANCE
FILTER
06234-001
ADV7390/ADV7391
8-BIT SD
OR
8-BIT ED/HD
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)
GND_IO
V
DD_IO
RESET HSYNC VSYNC
11-BIT
DAC 1 DAC 1
MULTIPLEXER
REFERENCE
AND CABLE
DETECT
16× OVERSAMPLING PLL
VIDEO TIMING GENERATOR
POWER
MANAGEMENT
CONTROL
CLKIN PV
DD
PGND EXT_LF COMP
R
SET
DGND (2) V
DD
(2) SCL SDA ALSB SFL
MPU PORT SUBCARRIER FREQUENCY
LOCK (SFL)
PROGRAMMABLE
CHROMINANCE
FILTER
ADD
BURST SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
AGND V
AA
ADD
SYNC
VBI DATA SERVICE
INSERTION
PROGRAMMABLE
LUMINANCE
FILTER
06234-146
ADV7390BCBZ
8-BIT SD
SDR/DDR
SD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)
GND_IO
V
DD_IO
RESET HSYNC VSYNC
DAC 1
DAC 2
DAC 3
MULTIPLEXER
REFERENCE
AND CABLE
DETECT
VIDEO TIMING GENERATOR
POWER
MANAGEMENT
CONTROL
CLKIN PV
DD
PGND EXT_LF COMP
R
SET
PROGRAMMABLE
ED/HD FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
YCrCb
HDTV
TEST
PATTERN
GENERATOR
YCbCr
TO
RGB MATRIX
ASYNC
BYPASS
DGND (2) V
DD
(2) SCL SDA ALSB SFL
MPU PORT SUBCARRIER FREQUENCY
LOCK (SFL)
YCrCb
TO
RGB
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
FILTER
AGND V
AA
VBI DATA SERVICE
INSERTION
PROGRAMMABLE
LUMINANCE
FILTER
06234-145
ADV7392/ADV7393
ADD
SYNC
RGB
TO
YCrCb
MATRIX
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
8-/10-/16-BIT SD
OR
8-/10-/16-BIT ED/HD
ADD
BURST
16x/4x OVERSAMPLING PLL
12-BIT
DAC 1
12-BIT
DAC 2
12-BIT
DAC 3
Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit
SUPPLY VOLTAGES
VDD 1.71 1.8 1.89 V
VDD_IO 1.71 3.3 3.63 V
PVDD 1.71 1.8 1.89 V
VAA 2.6 3.3 3.465 V
POWER SUPPLY REJECTION RATIO 0.002 %/%
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter Conditions1 Min Typ Max Unit
fCLKIN SD/ED 27 MHz
ED (at 54 MHz) 54 MHz
HD 74.25 MHz
CLKIN High Time, t9 40 % of one clock cycle
CLKIN Low Time, t10 40 % of one clock cycle
CLKIN Peak-to-Peak Jitter Tolerance 2 ±ns
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter Conditions Min Typ Max Unit
Full-Drive Output Current RSET = 510 Ω, RL = 37.5 Ω 33 34.6 37 mA
All DACs enabled
RSET = 510 Ω, RL = 37.5 Ω 31.5 33.5 37 mA
DAC 1 enabled only1
Low-Drive Output Current RSET = 4.12 kΩ, RL = 300 Ω 4.3 mA
DAC-to-DAC Matching
DAC 1, DAC 2, DAC 3
2.0
%
Output Compliance, VOC 0 1.4 V
Output Capacitance, COUT 10 pF
Analog Output Delay2 6 ns
DAC Analog Output Skew DAC 1, DAC 2, DAC 3 1 ns
1 The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
2 Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
Rev. I | Page 7 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
DIGITAL INPUT/OUTPUT SPECIFICATIONS3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter Conditions Min Typ Max Unit
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input Leakage Current, IIN VIN = VDD_IO ±10 µA
Input Capacitance, CIN 4 pF
Output High Voltage, VOH ISOURCE = 400 µA 2.4 V
Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V
Three-State Leakage Current VIN = 0.4 V, 2.4 V ±1 µA
Three-State Output Capacitance 4 pF
DIGITAL INPUT/OUTPUT SPECIFICATIONS1.8 V
When VDD_IO is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, and VS, should use 1.8 V levels.
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter Conditions Min Typ Max Unit
Input High Voltage, VIH 0.7 VDD_IO V
Input Low Voltage, VIL 0.3 VDD_IO V
Input Capacitance, CIN 4 pF
Output High Voltage, VOH ISOURCE = 400 µA VDD_IO0.4 V
Output Low Voltage, VOL ISINK = 3.2 mA 0.4 V
Three-State Output Capacitance 4 pF
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 8.
Parameter
Conditions
Min
Typ
Max
Unit
MPU PORT, I2C MODE1 See Figure 17
SCL Frequency 0 400 kHz
SCL High Pulse Width, t1 0.6 µs
SCL Low Pulse Width, t2 1.3 µs
Hold Time (Start Condition), t3 0.6 µs
Setup Time (Start Condition), t4 0.6 µs
Data Setup Time, t5 100 ns
SDA, SCL Rise Time, t6 300 ns
SDA, SCL Fall Time, t7 300 ns
Setup Time (Stop Condition), t8 0.6 µs
1 Guaranteed by characterization.
Rev. I | Page 8 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 9.
Parameter Conditions1 Min Typ Max Unit
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114 SD 2.1 ns
ED/HD-SDR 2.3 ns
ED/HD-DDR 2.3 ns
ED (at 54 MHz) 1.7 ns
Data Input Hold Time, t124 SD 1.0 ns
ED/HD-SDR 1.1 ns
ED/HD-DDR 1.1 ns
ED (at 54 MHz) 1.0 ns
Control Input Setup Time, t114 SD 2.1 ns
ED/HD-SDR or ED/HD-DDR
2.3
ns
ED (at 54 MHz) 1.7 ns
Control Input Hold Time, t124 SD 1.0 ns
ED/HD-SDR or ED/HD-DDR 1.1 ns
ED (at 54 MHz) 1.0 ns
Control Output Access Time, t134 SD 12 ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 10 ns
Control Output Hold Time, t144 SD 4.0 ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 3.5 ns
PIPELINE DELAY5
SD1
CVBS/Y-C Outputs (2×) SD oversampling disabled 68 Clock cycles
CVBS/Y-C Outputs (8×) SD oversampling enabled 79 Clock cycles
CVBS/Y-C Outputs (16×) SD oversampling enabled 67 Clock cycles
Component Outputs (2×)
SD oversampling disabled
78
Clock cycles
Component Outputs (8×) SD oversampling enabled 69 Clock cycles
Component Outputs (16×) SD oversampling enabled 84 Clock cycles
ED1
Component Outputs (1×) ED oversampling disabled 41 Clock cycles
Component Outputs (4×) ED oversampling enabled 49 Clock cycles
Component Outputs (8×) ED oversampling enabled 46 Clock cycles
HD1
Component Outputs (1×) HD oversampling disabled 40 Clock cycles
Component Outputs (2×) HD oversampling enabled 42 Clock cycles
Component Outputs (4×) HD oversampling enabled 44 Clock cycles
RESET CONTROL
RESET Low Time 100 ns
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3 Video control: HSYNC and VSYNC.
4 Guaranteed by characterization.
5 Guaranteed by design.
Rev. I | Page 9 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
DIGITAL TIMING SPECIFICATIONS1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 10.
Parameter Conditions1 Min Typ Max Unit
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114 SD 1.4 ns
ED/HD-SDR 1.9 ns
ED/HD-DDR 1.9 ns
ED (at 54 MHz) 1.6 ns
Data Input Hold Time, t124 SD 1.4 ns
ED/HD-SDR 1.5 ns
ED/HD-DDR 1.5 ns
ED (at 54 MHz) 1.3 ns
Control Input Setup Time, t114 SD 1.4 ns
ED/HD-SDR or ED/HD-DDR
1.2
ns
ED (at 54 MHz) 1.0 ns
Control Input Hold Time, t124 SD 1.4 ns
ED/HD-SDR or ED/HD-DDR 1.0 ns
ED (at 54 MHz) 1.0 ns
Control Output Access Time, t134 SD 13 ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 12 ns
Control Output Hold Time, t144 SD 4.0 ns
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 5.0 ns
PIPELINE DELAY5
SD1
CVBS/Y-C Outputs (2×) SD oversampling disabled 68 Clock cycles
CVBS/Y-C Outputs (8×) SD oversampling enabled 79 Clock cycles
CVBS/Y-C Outputs (16×) SD oversampling enabled 67 Clock cycles
Component Outputs (2×)
SD oversampling disabled
78
Clock cycles
Component Outputs (8×) SD oversampling enabled 69 Clock cycles
Component Outputs (16×) SD oversampling enabled 84 Clock cycles
ED1
Component Outputs (1×) ED oversampling disabled 41 Clock cycles
Component Outputs (4×) ED oversampling enabled 49 Clock cycles
Component Outputs (8×) ED oversampling enabled 46 Clock cycles
HD1
Component Outputs (1×) HD oversampling disabled 40 Clock cycles
Component Outputs (2×) HD oversampling enabled 42 Clock cycles
Component Outputs (4×) HD oversampling enabled 44 Clock cycles
RESET CONTROL
RESET Low Time 100 ns
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3 Video control: HSYNC and VSYNC.
4 Guaranteed by characterization.
5 Guaranteed by design.
Rev. I | Page 10 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter Conditions Min Typ Max Unit
STATIC PERFORMANCE
Resolution 10 Bits
Integral Nonlinearity (INL)1 RSET = 510 Ω, RL = 37.5 Ω 0.5 LSBs
Differential Nonlinearity (DNL)1, 2 RSET = 510 Ω, RL = 37.5 Ω 0.5 LSBs
STANDARD DEFINTION (SD) MODE
Luminance Nonlinearity 0.5 ±%
Differential Gain NTSC 0.5 %
Differential Phase NTSC 0.6 Degrees
Signal-to-Noise Ratio (SNR)
3
Luma ramp
58
dB
Flat field full bandwidth 75 dB
ENHANCED DEFINITION (ED) MODE
Luma Bandwidth 12.5 MHz
Chroma Bandwidth 5.8 MHz
HIGH DEFINITION (HD) MODE
Luma Bandwidth 30.0 MHz
Chroma Bandwidth 13.75 MHz
1 Measured on DAC 1, DAC 2, and DAC 3.
2 Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
3 Measured on the ADV7392/ADV7393 operating in 10-bit input mode.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 12.
Parameter Conditions Min Typ Max Unit
NORMAL POWER MODE1, 2
IDD3 SD (16× oversampling enabled), CVBS (only one DAC turned on) 33 mA
SD (16× oversampling enabled), YPrPb (three DACs turned on) 68 mA
ED (8× oversampling enabled)4 59 mA
HD (4× oversampling enabled)4 81 101 mA
IDD_IO 1 10 mA
IAA5 One DAC enabled 50 mA
All DACs enabled 122 151 mA
IPLL 4 10 mA
SLEEP MODE
I
DD
5
µA
IAA 0.3 µA
IDD_IO 0.2 µA
IPLL 0.1 µA
1 RSET = 510 Ω (all DACs operating in full-drive mode).
2 75% color bar test pattern applied to pixel data pins.
3 IDD is the continuous current required to drive the digital core.
4 Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5 IAA is the total current required to supply all DACs.
Rev. I | Page 11 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
TIMING DIAGRAMS
The following abbreviations are used in Figure 4 to Figure 11:
t9 = clock high time
t10 = clock low time
t11 = data setup time
t12 = data hold time
t13 = control output access time
t14 = control output hold time
In addition, see Table 35 for the ADV7390/ADV7391 pixel port
input configuration and Table 36 for the ADV7392/ADV7393
pixel port input configuration.
t
9
CLKIN
t
10
CONTROL
OUTPUTS
HSYNC
VSYNC
Cr2
Cb2Cr0Cb0
IN MASTER/SLAVE MODE
IN SLAVE MODE
Y0 Y1 Y2
PIXEL PORT
CONTROL
INPUTS
t
12
t
11
t
13
t
14
06234-002
Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000
IN MASTER/SLAVE MODE
IN SLAVE MODE
CLKIN
CONTROL
OUTPUTS
t
9
t
10
Cr2
Cb2
Cr0Cb0
Y0 Y1 Y2 Y3
t
12
t
14
t
11
t
13
HSYNC
VSYNC
CONTROL
INPUTS
PIXEL PORT
PIXEL PORT
06234-003
Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000
Rev. I | Page 12 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
CONTROL
OUTPUTS
t
9
t
10
t
11
G0 G1 G2
B0 B1 B2
R0 R1 R2
t
12
t
14
t
13
PIXEL PORT
PIXEL PORT
PIXEL PORT
CLKIN
HSYNC
VSYNC
CONTROL
INPUTS
06234-004
Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000
CONTROL
OUTPUTS
PIXEL PORT
PIXEL PORT
Y0 Y1 Y2 Y3 Y4 Y5
Cr4Cb4Cr2Cb2Cr0Cb0
CLKIN
t
9
t
10
t
12
t
11
t
14
t
13
HSYNC
VSYNC
CONTROL
INPUTS
06234-005
Figure 7. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb, Input Mode 001
CLKIN*
CONTROL
OUTPUTS
Cr2Y2
Cb2
Y1Cr0
Y0Cb0
t
9
t
10
t
12
t
11
t
12
t
11
t
14
t
13
PIXEL PORT
HSYNC
VSYNC
CONTROL
INPUTS
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
06234-006
Figure 8. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 010
Rev. I | Page 13 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
CONTROL
OUTPUTS
PIXEL PORT
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
Y1Cr0Y0Cb0XY00003FF
CLKIN*
t
9
t
10
t
12
t
11
t
12
t
11
t
14
t
13
06234-007
Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010
CLKIN
CONTROL
OUTPUTS
Y1Cr0Y0Cb0 Cr2
Y2
Cb2
t
9
t
10
t
12
t
11
t
13
t
14
PIXEL PORT
HSYNC
VSYNC
CONTROL
INPUTS
06234-008
Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 111
CLKIN
CONTROL
OUTPUTS
3FF 00 00 XY Cb0 Y0 Cr0 Y1
PIXEL PORT
t
11
t
12
t
10
t
9
t
14
t
13
06234-009
Figure 11. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111
Rev. I | Page 14 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Y0 Y1 Y2 Y3
a
Cr2
Cb2Cr0Cb0
b
Y OUTPUT
HSYNC
VSYNC
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
PIXEL PORT*
06234-010
Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Cb0 Y0 Cr0 Y1
a
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
HSYNC
VSYNC
b
Y OUTPUT
PIXEL PORT
06234-011
Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. I | Page 15 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Y0 Y1 Y2 Y3
a
Cr2Cb2
Cr0
Cb0
b
Y OUTPUT
HSYNC
VSYNC
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
PIXEL PORT
06234-012
Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
PIXEL PORT Cb0 Y0 Cr0 Y1
a
HSYNC
VSYNC
b
Y OUTPUT
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
06234-013
Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. I | Page 16 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Cb YCr Y
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
PIXEL PORT
VSYNC
HSYNC
06234-014
Figure 16. SD Input Timing Diagram (Timing Mode 1)
t
3
t
3
t
4
t
7
t
8
t
5
SDA
SCL
t
1
t
2
t
6
06234-015
Figure 17. MPU Port Timing Diagram (I2C Mode)
Rev. I | Page 17 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 13.
Parameter1 Rating
VAA to AGND −0.3 V to +3.9 V
V
DD
to DGND
−0.3 V to +2.3 V
PVDD to PGND −0.3 V to +2.3 V
VDD_IO to GND_IO −0.3 V to +3.9 V
AGND to DGND −0.3 V to +0.3 V
AGND to PGND −0.3 V to +0.3 V
AGND to GND_IO −0.3 V to +0.3 V
DGND to PGND −0.3 V to +0.3 V
DGND to GND_IO −0.3 V to +0.3 V
PGND to GND_IO −0.3 V to +0.3 V
Digital Input Voltage to GND_IO −0.3 V to VDD_IO + 0.3 V
Analog Outputs to AGND −0.3 V to VAA
Max CLKIN Input Frequency 80 MHz
Storage Temperature Range (tS) −60°C to +150°C
Junction Temperature (tJ) 150°C
Lead Temperature (Soldering, 10 sec) 260°C
1 Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 14. Thermal Resistance1
Package Type θJA2 θJC-TOP3 θJC-BOTTOM4 Unit
30-Ball WLCSP 35 1 N/A °C/W
32-Lead LFCSP
27
32
1.2
°C/W
40-Lead LFCSP
26
32
1
°C/W
1 Values are based on a JEDEC 4-layer test board.
2 With the exposed metal paddle on the underside of the LFCSP soldered to
the PCB ground.
3 This is the thermal resistance of the junction to the top of the package.
4 This is the thermal resistance of the junction to the bottom of the package.
The ADV7390/ADV7391/ADV7392/ADV7393 are RoHS-
compliant, Pb-free products. The lead finish is 100% pure Sn
electroplate. The device is suitable for Pb-free applications up to
255°C (±5°C) IR reflow (JEDEC STD-20).
The ADV7390/ADV7391/ADV7392/ADV7393 are backward
compatible with conventional SnPb soldering processes. The
electroplated Sn coating can be soldered with SnPb solder pastes
at conventional reflow temperatures of 220°C to 235°C.
ESD CAUTION
Rev. I | Page 18 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. I | Page 19 of 107
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
V
DD_IO
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
2P2
3P3
4P4
5
V
DD
6DGND
7P5
8P6
24 R
SET
23 COMP
22 DAC 1
21 DAC 2
20 DAC 3
19 V
AA
18 AGND
17 PV
DD
9
P7
10
ALSB
11
SDA
12
SCL
13
CLKIN
14
RESET
15
PGND
16
EXT_LF
32 GND_IO
31 P1
30 P0
29 DGND
28 V
DD
27 HSYNC
26 VSYNC
25 SFL
TOP VIEW
(Not to Scale)
ADV7390/
ADV7391
06234-017
Figure 18. ADV7390/ADV7391 Pin Configuration
V
DD_IO
P4
P5
P6
P7
V
DD
DGND
P8
P9
P10
PV
DD
AGND
V
AA
DAC 3
DAC 2
DAC 1
COMP
R
SET
EXT_LF
PGND
P0
V
DD
DGND
P1
P2
P3
GND_I
O
SFL
HSYNC
VSYNC
P11
ALSB
SDA
P12
P14
P13
P15
CLKIN
RESET
SCL
0
6234-018
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
ADV7392/
ADV7393
TOP VIEW
(Not to Scale)
Figure 19. ADV7392/ADV7393 Pin Configuration
06234-147
1
A
B
C
D
E
F
234
V
DD
P0
V
DD_IO
R
SET
DAC1
HSYNC
VSYNC
SFL P1 P2
V
AA
COMP DGND P3 P4
AGND
GND_IO RESET
V
DD
DGND
PV
DD EXT_LF
ALSB P5 P6
PGND SDA SCL CLKIN P7
5
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
BALL A1 CORNE
R
Figure 20. ADV7390BCBZ-A Pin Configuration
Table 15. Pin Function Descriptions
Pin No.1
Mnemonic
Input/
Output Description
ADV7390/
ADV7391
ADV7392/
ADV7393
ADV7390
WLCSP
9 to 7, 4 to 2,
31, 30
N/A F5, E5, E4, C5,
C4, B5, B4, A4
P7 to P0 I 8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for
input modes (ADV7390/ADV7391).
N/A 18 to 15, 11 to
8, 5 to 2, 39 to
37, 34
N/A P15 to P0 I 16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for
input modes (ADV7392/ADV7393).
13 19 F4 CLKIN I
Pixel Clock Input for HD (74.25 MHz), ED2 (27 MHz or 54 MHz),
or SD (27 MHz).
27 33 A2 HSYNC I/O Horizontal Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD horizontal
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
26 32 B2 VSYNC I/O Vertical Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
25 31 B3 SFL I/O Subcarrier Frequency Lock (SFL) Input.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Pin No.1
Mnemonic
Input/
Output Description
ADV7390/
ADV7391
ADV7392/
ADV7393
ADV7390
WLCSP
24 30 A1 RSET I Controls the amplitudes of the DAC 1, DAC 2, and DAC 3
outputs. For full-drive operation (for example, into a 37.5 Ω
load), a 510 Ω resistor must be connected from RSET to
AGND. For low-drive operation (for example, into a 300 Ω
load), a 4.12 kΩ resistor must be connected from RSET to
AGND.
23 29 C2 COMP O Compensation Pin. Connect a 2.2 nF capacitor from COMP
to VAA.
N/A N/A B1 DAC 1 O DAC Output. Full-drive and low-drive capable DAC
22, 21, 20
28, 27, 26
N/A
DAC 1, DAC 2,
DAC 3
O
DAC Outputs. Full-drive and low-drive capable DACs.
12 14 F3 SCL I I2C Clock Input.
11 13 F2 SDA I/O I2C Data Input/Output.
10 12 E3 ALSB I ALSB sets up the LSB3 of the MPU I2C address.
14 20 D3 RESET I Resets the on-chip timing generator and sets the
ADV7390/ADV7391/ADV7392/ADV7393 into its default
mode.
19 25 C1 VAA P Analog Power Supply (2.7 V or 3.3 V).
5, 28 6, 35 A3, D4 VDD P Digital Power Supply (1.8 V). For dual-supply
configurations, VDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
1 1 A5 VDD_IO P Input/Output Digital Power Supply (1.8 V or 3.3 V).
17 23 E1 PVDD P PLL Power Supply (1.8 V). For dual-supply configurations,
PVDD can be connected to other 1.8 V supplies through a
ferrite bead or suitable filtering.
16 22 E2 EXT_LF I External Loop Filter for the Internal PLL.
15 21 F1 PGND G PLL Ground Pin.
18 24 D1 AGND G Analog Ground Pin.
6, 29 7, 36 C3, D5 DGND G Digital Ground Pin.
32 40 D2 GND_IO G Input/Output Supply Ground Pin.
EPAD G Exposed Pad. Connect to analog ground (AGND).
1 N/A means not applicable.
2 ED = enhanced definition = 525p and 625p.
3 LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the
ADV7391/ADV7393, setting the LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
Rev. I | Page 20 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. I | Page 21 of 107
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
0
GAIN (dB)
–70
–60
–50
–40
–30
–20
–10
–80 20020 40 60 80 100 120 140 160 1800
06234-019
Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response
FREQUENCY (MHz)
EDPr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
0
GAIN (dB)
–70
–60
–50
–40
–30
–20
–10
–80 20020 40 60 80 100 120 140 160 1800
06234-020
Figure 22. ED 8× Oversampling, PrPb Filter (SSAF™) Response
FREQUENCY (MHz)
Y RESPONSE IN ED 8× OVERSAMPLING MODE
0
GAIN (dB)
–70
–60
–50
–40
–30
–20
–10
–80 20020 40 60 80 100 120 140 160 1800
06234-021
Figure 23. ED 8× Oversampling, Y Filter Response
FREQUENCY (MHz)
Y RESPONSE IN ED 8× OVERSAMPLING MODE
GAIN (dB)
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
–3.0 122468100
06234-022
Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)
FREQUENCY (MHz)
HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
10
0
GAIN (dB)
–70
–60
–50
–40
–30
–20
–10
–100
–80
–90
148.018.5 37.0 55.5 74.0 92.5 111.0 129.50
06234-023
Figure 25. HD 4× Oversampling, PrPb (SSAF) Filter Response
(4:2:2 Input)
HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE
GAIN (dB)
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 20 30 40 50 60 70 80 90 100 110 120 130 140
06234-024
Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response
(4:4:4 Input)
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. I | Page 22 of 107
FREQUENCY (MHz)
Y RESPONSE IN HD 4× OVERSAMPLING MODE
10
0
GAIN (dB)
–70
–60
–50
–40
–30
–20
–10
–100
–80
–90
148.018.5 37.0 55.5 74.0 92.5 111.0 129.50
06234-025
Figure 27. HD 4× Oversampling, Y Filter Response
Y PASS BAND IN HD 4x OVERSAMPLING MODE
3.0
–12.0
27.750 46.250
FREQUENCY (MHz)
GAIN (dB)
1.5
0
–1.5
–3.0
–4.5
–6.0
–7.5
–9.0
–10.5
30.063 32.375 34.688 37.000 39.312 41.625 43.937
06234-026
Figure 28. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)
FREQUENCY (MHz)
MAGNITUDE (dB)
0
121086420
–10
–30
–50
–60
–70
–20
–40
0
6234-027
Figure 29. SD NTSC, Luma Low-Pass Filter Response
FREQUENCY (MHz)
MAGNITUDE (dB)
0
121086420
–10
–30
–50
–60
–70
–20
–40
0
6234-028
Figure 30. SD PAL, Luma Low-Pass Filter Response
FREQUENCY (MHz)
MAGNITUDE (dB)
0
121086420
–10
–30
–50
–60
–70
–20
–40
06234-029
Figure 31. SD NTSC, Luma Notch Filter Response
FREQUENCY (MHz)
MAGNITUDE (dB)
0
121086420
–10
–30
–50
–60
–70
–20
–40
06234-030
Figure 32. SD PAL, Luma Notch Filter Response
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. I | Page 23 of 107
FREQUENCY (MHz)
Y RESPONSE IN SD OVERSAMPLING MODE
GAIN (dB)
0
–50
–800 20 40 60 80 100 120 140 160 180 200
–10
–40
–60
–70
–20
–30
06234-031
Figure 33. SD 16× Oversampling, Y Filter Response
FREQUENCY (MHz)
MAGNITUDE (dB)
0
121086420
–10
–30
–50
–60
–70
–20
–40
06234-032
Figure 34. SD Luma SSAF Filter Response up to 12 MHz
FREQUENCY (MHz)
4
7
MAGNITUDE (dB)
2
–2
–6
–8
–12
0
–4
5
–10
60 1234
06234-033
Figure 35. SD Luma SSAF Filter, Programmable Responses
FREQUENCY (MHz)
7
MAGNITUDE (dB)
5
4
2
1
–1
3
5
0
6
01234
06234-034
Figure 36. SD Luma SSAF Filter, Programmable Gain
FREQUENCY (MHz)
7
MAGNITUDE (dB)
1
0
–2
–3
–5
–1
5
–4
6
01234
0
6234-035
Figure 37. SD Luma SSAF Filter, Programmable Attenuation
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
06234-036
Figure 38. SD Luma CIF Low-Pass Filter Response
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. I | Page 24 of 107
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
06234-037
Figure 39. SD Luma QCIF Low-Pass Filter Response
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
06234-038
Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
06234-039
Figure 41. SD Chroma 2.0 MHz Low-Pass Filter Response
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
06234-040
Figure 42. SD Chroma 1.3 MHz Low-Pass Filter Response
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
0
6234-041
Figure 43. SD Chroma 1.0 MHz Low-Pass Filter Response
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
06234-042
Figure 44. SD Chroma 0.65 MHz Low-Pass Filter Response
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
46
20
06234-043
Figure 45. SD Chroma CIF Low-Pass Filter Response
FREQUENCY (MHz)
0
12
MAGNITUDE (dB)
–10
–30
–50
–60
–70
–20
–40
10
8
4620
06234-044
Figure 46. SD Chroma QCIF Low-Pass Filter Response
Rev. I | Page 25 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the
ADV7390/ADV7391/ADV7392/ADV7393 through a 2-wire
serial (I2C-compatible) bus. After power-up or reset, the MPU
port is configured for I2C operation.
I2C OPERATION
The ADV7390/ADV7391/ADV7392/ADV7393 support a 2-
wire serial (I2C-compatible) microprocessor bus driving
multiple peripherals. This port operates in an open-drain
configuration. Two wires, serial data (SDA) and serial clock
(SCL), carry information between any device connected to the
bus and the ADV7390/ADV7391/ADV7392/ADV7393. The
slave address depends on the device (ADV7390, ADV7391,
ADV7392, or ADV7393), the operation (read or write), and the
state of the ALSB pin (0 or 1). See Table 16, Figure 47, and
Figure 48. The LSB sets either a read or a write operation. Logic
1 corresponds to a read operation, and Logic 0 corresponds to a
write operation. A1 is controlled by setting the ALSB pin of the
ADV7390/ADV7391/ADV7392/ADV7393 to Logic 0 or Logic 1.
Table 16. ADV7390/ADV7391/ADV7392/ADV7393 I2C
Slave Addresses
Device ALSB Operation Slave Address
ADV7390
and
ADV7392
0 Write 0xD4
0 Read 0xD5
1 Write 0xD6
1
Read
0xD7
ADV7391
and
ADV7393
0 Write 0x54
0 Read 0x55
1 Write 0x56
1 Read 0x57
1 1 0 1 0 1 A1 X
READ/WRITE
CONTROL
0 WRITE
1 READ
06234-045
ADDRESS
CONTROL
SET UP BY
ALSB
Figure 47. ADV7390/ADV7392 I2C Slave Address
0 1 0101A1 X
READ/WRITE
CONTROL
0 WRITE
1 READ
06234-046
ADDRESS
CONTROL
SET UP BY
ALSB
Figure 48. ADV7391/ADV7393 I2C Slave Address
The various devices on the bus use the following protocol. The
master initiates a data transfer by establishing a start condition,
defined by a high-to-low transition on SDA while SCL remains
high. This indicates that an address/data stream follows. All
peripherals respond to the start condition and shift the next
eight bits (7-bit address plus the R/W bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
occurs when the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data.
Logic 0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first byte
means that the master reads information from the peripheral.
The ADV7390/ADV7391/ADV7392/ADV7393 act as a
standard slave device on the bus. The data on the SDA pin is
eight bits long, supporting the 7-bit addresses plus the R/W bit.
It interprets the first byte as the device address and the second
byte as the starting subaddress. There is a subaddress auto-
increment facility. This allows data to be written to or read from
registers in ascending subaddress sequence starting at any valid
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only a start condition, a stop
condition, or a stop condition followed by a start condition. If
an invalid subaddress is issued by the user, the ADV7390/
ADV7391/ADV7392/ADV7393 do not issue an acknowledge
but returns to the idle condition. If the user uses the auto-
increment method of addressing the encoder and exceeds the
highest subaddress, the following actions are taken:
In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge condition
occurs when the SDA line is not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7390/ADV7391/ADV7392/ADV7393, and the
part returns to the idle condition.
Figure 49 shows an example of data transfer for a write sequence
and the start and stop conditions. Figure 50 shows bus write
and read sequences.
Rev. I | Page 26 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. I | Page 27 of 107
SDA
SCL
START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP
1–7 8 9
S1–7 1–7 P
8989
06234-047
Figure 49. I2C Data Transfer
WRITE
SEQUENCE
READ
SEQUENCE
S SLAVE ADDR A(S) SUBADDR A(S) DATA DATA A(S) P
S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
LSB = 0 LSB = 1
A(S)
06234-048
Figure 50. I2C Read and Write Sequence
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV7390/ADV7391/ADV7392/ADV7393 via the MPU port,
except for registers that are specified as read-only or write-only
registers.
The subaddress register determines the register accessed by the
next read or write operation. All communication through the
MPU port starts with an access to the subaddress register. A
read/write operation is then performed from/to the target
address, incrementing to the next address until the transaction
is complete.
REGISTER PROGRAMMING
Table 17 to Table 34 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines which
register performs the next operation.
Table 17. Register 0x00
SR7 to Bit Number Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0x00 Power
mode
Sleep mode. With this control enabled, the current consumption is
reduced to µA level. All DACs and the internal PLL circuit are
disabled. Registers can be read from and written to in sleep mode.
0 Sleep
mode off
0x12
1 Sleep
mode on
PLL and oversampling control. This control allows the internal PLL
circuit to be powered down and the oversampling to be switched off.
0 PLL on
1 PLL off
DAC 3: power on/off. 0 DAC 3 off
1 DAC 3 on
DAC 2: power on/off. 0 DAC 2 off
1 DAC 2 on
DAC 1: power on/off. 0 DAC 1 off
1 DAC 1 on
Reserved. 0 0 0
Table 18. Register 0x01 to Register 0x09
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x01 Mode
select
Reserved. 0 0x00
DDR clock edge alignment
(used only for ED2 and HD
DDR modes)
0 0 Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
0 1 Reserved.
1 0 Reserved.
1 1 Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
Reserved 0
Input mode
(see Subaddress 0x30, Bits[7:3]
for ED/HD standard selection)
0 0 0 SD input.
0 0 1 ED/HD-SDR input.3
0 1 0 ED/HD-DDR input.
0 1 1 Reserved.
1 0 0 Reserved.
1 0 1 Reserved.
1
1
0
Reserved.
1 1 1 ED (at 54 MHz) input.
Reserved 0
Rev. I | Page 28 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x02 Mode
Register 0
Reserved 0 Zero must be written to this bit. 0x20
HD interlace external VSYNC
and HSYNC
0
Default.
1 If using HD HSYNC/VSYNCinterlace mode,
setting this bit to 1 is recommended (see the
HD Interlace External HSYNC and VSYNC
Considerations section for more information).
Test pattern black bar4 0 Disabled.
1 Enabled.
Manual CSC matrix adjust 0 Disable manual CSC matrix adjust.
1
Enable manual CSC matrix adjust.
Sync on RGB 0 No sync.
1 Sync on all RGB outputs.
RGB/YPrPb output select 0 RGB component outputs.
1 YPrPb component outputs.
SD sync output enable 0 No sync output.
1 Output SD syncs on HSYNC and VSYNC pins.
ED/HD sync output enable 0 No sync output.
1
Output ED/HD syncs on HSYNC and
VSYNC pins.
0x03 ED/HD
CSC
Matrix 0
x x LSBs for GY. 0x03
0x04 ED/HD
CSC
Matrix 1
x x LSBs for RV. 0xF0
x x LSBs for BU.
x x LSBs for GV.
x x LSBs for GU.
0x05 ED/HD
CSC
Matrix 2
x x x x x x x x Bits[9:2] for GY. 0x4E
0x06 ED/HD
CSC
Matrix 3
x x x x x x x x Bits[9:2] for GU. 0x0E
0x07 ED/HD
CSC
Matrix 4
x x x x x x x x Bits[9:2] for GV. 0x24
0x08 ED/HD
CSC
Matrix 5
x x x x x x x x Bits[9:2] for BU. 0x92
0x09 ED/HD
CSC
Matrix 6
x x x x x x x x Bits[9:2] for RV. 0x7C
1 x = Logic 0 or Logic 1.
2 ED = enhanced definition = 525p and 625p.
3 Available on the ADV7392/ADV7393 (40-pin devices) only.
4 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
Rev. I | Page 29 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Table 19. Register 0x0B to Register 0x17
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x0B DAC 1, DAC 2,
DAC 3 output
levels
Positive gain to DAC output voltage 0 0 0 0 0 0 0 0 0%. 0x00
0 0 0 0 0 0 0 1 +0.018%.
0 0 0 0 0 0 1 0 +0.036%.
0 0 1 1 1 1 1 1 +7.382%.
0 1 0 0 0 0 0 0 +7.5%.
Negative gain to DAC output voltage 1 1 0 0 0 0 0 0 −7.5%.
1 1 0 0 0 0 0 1 −7.382%.
1 0 0 0 0 0 1 0 −7.364%.
1 1 1 1 1 1 1 1 −0.018%.
0x0D DAC power
mode
DAC 1 low power mode 0 DAC 1 low power
disabled.
0x00
1
DAC 1 low power enabled.
DAC 2 low power mode 0 DAC 2 low power
disabled.
1 DAC 2 low power enabled.
DAC 3 low power mode 0 DAC 3 low power
disabled.
1 DAC 3 low power enabled.
SD/ED oversample rate select 0 SD = 16×, ED = 8×.
1 SD = 8×, ED = 4×.
Reserved 0 0 0 0
0x10 Cable detection DAC 1 cable detect 0 Cable detected on
DAC 1.
0x00
Read only 1 DAC 1 unconnected.
DAC 2 cable detect
0
Cable detected on
DAC 2.
Read only 1 DAC 2 unconnected.
Reserved 0 0
Unconnected DAC autopower-down
0
DAC autopower-down
disable.
1 DAC autopower-down
enable.
Reserved 0 0 0
0x13 Pixel Port
Readback A2
P[7:0] readback (ADV7390/ADV7391) x x x x x x x x Read only. 0xXX
P[15:8] readback (ADV7392/ADV7393)
0x14 Pixel Port
Readback B2
P[7:0] readback (ADV7392/ADV7393) x x x x x x x x Read only. 0xXX
0x16 Control port
readback2
Reserved x x x Read only. 0xXX
VSYNC readback x
HSYNC readback x
SFL readback x
Reserved x x
0x17
Software reset
Reserved
0
0x00
Software reset 0 Writing a 1 resets the
device; this is a self-
clearing bit.
1
Reserved. 0 0 0 0 0 0
1 x = Logic 0 or Logic 1.
2 For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.
Rev. I | Page 30 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Table 20. Register 0x30
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Note Value
0x30 ED/HD Mode
Register 1
ED/HD output standard 0 0 EIA-770.2 output
EIA-770.3 output
ED
HD
0x00
0 1 EIA-770.1 output
1 0 Output levels for full
input range
1 1 Reserved
ED/HD input
synchronization format
0 External HSYNC, VSYNC
and field inputs1
1 Embedded EAV/SAV
codes
ED/HD standard2
0
0
0
0
0
SMPTE 293M, ITU-BT.1358
525p at 59.94 Hz
0 0 0 1 0 BTA-1004, ITU-BT.1362 525p at 59.94 Hz
0 0 0 1 1 ITU-BT.1358 625p at 50 Hz
0 0 1 0 0 ITU-BT.1362 625p at 50 Hz
0 0 1 0 1 SMPTE 296M-1,
SMPTE 274M-2
720p at
60 Hz/59.94 Hz
0 0 1 1 0 SMPTE 296M-3 720p at 50 Hz
0 0 1 1 1 SMPTE 296M-4,
SMPTE 274M-5
720p at
30 Hz/29.97 Hz
0 1 0 0 0 SMPTE 296M-6 720p at 25 Hz
0
1
0
0
1
SMPTE 296M-7,
SMPTE 296M-8
720p at
24 Hz/23.98 Hz
0 1 0 1 0 SMPTE 240M 1035i at
60 Hz/59.94 Hz
0 1 0 1 1 Reserved
0 1 1 0 0 Reserved
0 1 1 0 1 SMPTE 274M-4,
SMPTE 274M-5
1080i at
30 Hz/29.97 Hz
0 1 1 1 0 SMPTE 274M-6 1080i at 25 Hz
0 1 1 1 1 SMPTE 274M-7,
SMPTE 274M-8
1080p at
30 Hz/29.97 Hz
1 0 0 0 0 SMPTE 274M-9 1080p at 25 Hz
1 0 0 0 1 SMPTE 274M-10,
SMPTE 274M-11
1080p at
24 Hz/23.98 Hz
1 0 0 1 0 ITU-R BT.709-5 1080Psf at 24 Hz
10011 to 11111 Reserved
1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6.
2 See the HD Interlace External HSYNC and VSYNC Considerations section for more information.
Rev. I | Page 31 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. I | Page 32 of 107
Table 21. Register 0x31 to Register 0x33
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x31 ED/HD Mode
Register 2
ED/HD pixel data valid 0 Pixel data valid off. 0x00
1 Pixel data valid on.
HD oversample rate select 0 4×.
1 2×.
ED/HD test pattern enable 0 HD test pattern off.
1 HD test pattern on.
ED/HD test pattern hatch/field 0 Hatch.
1 Field/frame.
ED/HD vertical blanking interval (VBI)
open
0 Disabled.
1 Enabled.
ED/HD undershoot limiter 0 0 Disabled.
0 1 −11 IRE.
1 0 6 IRE.
1 1 1.5 IRE.
ED/HD sharpness filter 0 Disabled.
1 Enabled.
0x32 ED/HD Mode
Register 3
ED/HD Y delay with respect to the
falling edge of HSYNC
0 0 0 0 clock cycles. 0x00
0 0 1 One clock cycle.
0 1 0 Two clock cycles.
0 1 1 Three clock cycles.
1 0 0 Four clock cycles.
ED/HD color delay with respect to the
falling edge of HSYNC
0 0 0 0 clock cycles.
0 0 1 One clock cycle.
0 1 0 Two clock cycles.
0 1 1 Three clock cycles.
1 0 0 Four clock cycles.
ED/HD CGMS enable 0 Disabled.
1 Enabled.
ED/HD CGMS CRC enable 0 Disabled.
1 Enabled.
0x33 ED/HD Mode
Register 4
ED/HD Cr/Cb sequence 0
Cb after falling edge of HSYNC. 0x68
1
Cr after falling edge of HSYNC.
Reserved 0 0 must be written to this bit.
ED/HD input format 0 8-bit input.
1 10-bit input
1.
Sinc compensation filter on DAC 1, DAC
2, DAC 3
0 Disabled.
1 Enabled.
Reserved 0 0 must be written to this bit.
ED/HD chroma SSAF filter 0 Disabled.
1 Enabled.
Reserved 1 1 must be written to this bit.
ED/HD double buffering 0 Disabled.
1 Enabled.
1 Available on the ADV7392/ADV7393 (40-pin devices) only.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Table 22. Register 0x34 to Register 0x38
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x34 ED/HD Mode
Register 5
ED/HD timing reset 0 Internal ED/HD timing counters enabled. 0x48
1 Resets the internal ED/HD timing counters.
ED/HD HSYNC control2 0 HSYNC output control (see Table 55).
1
ED/HD VSYNC control2 0 VSYNC output control (see Table 56).
1
Reserved 1
ED Macrovision® enable3 0 ED Macrovision disabled.
1 ED Macrovision enabled.
Reserved
0
0 must be written to this bit.
ED/HD VSYNC input/field
input
0 0 = Field input.
1 1 = VSYNC input.
ED/HD horizontal/vertical
counter mode4
0 Update field/line counter.
1 Field/line counter free running.
0x35 ED/HD Mode
Register 6
Reserved 0 0x00
Reserved
0
ED/HD sync on PrPb 0 Disabled.
1 Enabled.
ED/HD color DAC swap 0 DAC 2 = Pb, DAC 3 = Pr
1 DAC 2 = Pr, DAC 3 = Pb.
ED/HD gamma correction
curve select
0 Gamma Correction Curve A.
1 Gamma Correction Curve B.
ED/HD gamma correction
enable
0 Disabled.
1 Enabled.
ED/HD adaptive filter
mode
0
Mode A.
1 Mode B.
ED/HD adaptive filter
enable
0 Disabled.
1
Enabled.
0x36 ED/HD Y level5 ED/HD Test Pattern Y level x x x x x x x x Y level value. 0xA0
0x37 ED/HD Cr level5 ED/HD Test Pattern Cr level x x x x x x x x Cr level value. 0x80
0x38 ED/HD Cb level5 ED/HD Test Pattern Cb level x x x x x x x x Cb level value. 0x80
1 x = Logic 0 or Logic 1.
2 Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
3 Applies to the ADV7390 and ADV7392 only.
4 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
5 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Rev. I | Page 33 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Table 23. Register 0x39 to Register 0x43
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x39 ED/HD Mode
Register 7
Reserved 0 0 0 0 0 0x00
ED/HD EIA/CEA-861B
synchronization compliance
0 Disabled
1 Enabled
Reserved 0 0
0X3A ED/HD Mode
Register 8
INV_PHSYNC_POL 0 Disabled 0x00
1 Enabled
INV_PVSYNC_POL 0 Disabled
1 Enabled
INV_PBLANK_POL
0
Disabled
1 Enabled
Reserved 0 0 0 0 0
0x40 ED/HD
sharpness filter
gain
ED/HD sharpness filter gain
Value A
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
0 1 1 1 Gain A = +7
1 0 0 0 Gain A = −8
1 1 1 Gain A = −1
ED/HD sharpness filter gain
Value B
0 0 0 0 Gain B = 0
0 0 0 1 Gain B = +1
0 1 1 1 Gain B = +7
1
0
0
0
Gain B = −8
1 1 1 1 Gain B = −1
0x41 ED/HD CGMS
Data 0
ED/HD CGMS data bits 0 0 0 0 C19 C18 C17 C16 CGMS C19 to C1
6
0x00
0x42 ED/HD CGMS
Data 1
ED/HD CGMS data bits C15 C14 C13 C12 C11 C10 C9 C8 CGMS C15 to C8 0x00
0x43 ED/HD CGMS
Data 2
ED/HD CGMS data bits C7 C6 C5 C4 C3 C2 C1 C0 CGMS C7 to C0 0x00
Rev. I | Page 34 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Table 24. Register 0x44 to Register 0x57
SR7 to Bit Number1 Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0x44
ED/HD Gamma A0
ED/HD Gamma Curve A (Point 24)
x
x
x
x
x
x
x
x
A0
0x00
0x45 ED/HD Gamma A1 ED/HD Gamma Curve A (Point 32) x x x x x x x x A1 0x00
0x46 ED/HD Gamma A2 ED/HD Gamma Curve A (Point 48) x x x x x x x x A2 0x00
0x47 ED/HD Gamma A3 ED/HD Gamma Curve A (Point 64) x x x x x x x x A3 0x00
0x48 ED/HD Gamma A4 ED/HD Gamma Curve A (Point 80) x x x x x x x x A4 0x00
0x49 ED/HD Gamma A5 ED/HD Gamma Curve A (Point 96) x x x x x x x x A5 0x00
0x4A ED/HD Gamma A6 ED/HD Gamma Curve A (Point 128) x x x x x x x x A6 0x00
0x4B ED/HD Gamma A7 ED/HD Gamma Curve A (Point 160) x x x x x x x x A7 0x00
0x4C
ED/HD Gamma A8
ED/HD Gamma Curve A (Point 192)
x
x
x
x
x
x
x
x
A8
0x00
0x4D ED/HD Gamma A9 ED/HD Gamma Curve A (Point 224) x x x x x x x x A9 0x00
0x4E ED/HD Gamma B0 ED/HD Gamma Curve B (Point 24) x x x x x x x x B0 0x00
0x4F ED/HD Gamma B1 ED/HD Gamma Curve B (Point 32) x x x x x x x x B1 0x00
0x50 ED/HD Gamma B2 ED/HD Gamma Curve B (Point 48) x x x x x x x x B2 0x00
0x51 ED/HD Gamma B3 ED/HD Gamma Curve B (Point 64) x x x x x x x x B3 0x00
0x52 ED/HD Gamma B4 ED/HD Gamma Curve B (Point 80) x x x x x x x x B4 0x00
0x53 ED/HD Gamma B5 ED/HD Gamma Curve B (Point 96) x x x x x x x x B5 0x00
0x54 ED/HD Gamma B6 ED/HD Gamma Curve B (Point 128) x x x x x x x x B6 0x00
0x55
ED/HD Gamma B7
ED/HD Gamma Curve B (Point 160)
x
x
x
x
x
x
x
x
B7
0x00
0x56 ED/HD Gamma B8 ED/HD Gamma Curve B (Point 192) x x x x x x x x B8 0x00
0x57 ED/HD Gamma B9 ED/HD Gamma Curve B (Point 224) x x x x x x x x B9 0x00
1 x = Logic 0 or Logic 1.
Rev. I | Page 35 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Table 25. Register 0x58 to Register 0x5D
SR7 to Bit Number1 Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0x58 ED/HD Adaptive Filter Gain 1 ED/HD Adaptive Filter Gain 1,
Value A
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
0 1 1 1 Gain A = +7
1 0 0 0 Gain A = −8
1 1 1 1 Gain A = −1
ED/HD Adaptive Filter Gain 1,
Value B
0 0 0 0 Gain B = 0
0 0 0 1 Gain B = +1
0 1 1 1 Gain B = +7
1 0 0 0 Gain B = −8
1 1 1 1 Gain B = −1
0x59 ED/HD Adaptive Filter Gain 2 ED/HD Adaptive Filter Gain 2,
Value A
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
0 1 1 1 Gain A = +7
1 0 0 0 Gain A = −8
1 1 1 1 Gain A = −1
ED/HD Adaptive Filter Gain 2,
Value B
0 0 0 0 Gain B = 0
0
0
0
1
Gain B = +1
0 1 1 1 Gain B = +7
1 0 0 0 Gain B = −8
1 1 1 1 Gain B = −1
0x5A ED/HD Adaptive Filter Gain 3 ED/HD Adaptive Filter Gain 3,
Value A
0 0 0 0 Gain A = 0 0x00
0 0 0 1 Gain A = +1
0
1
1
1
Gain A = +7
1 0 0 0 Gain A = −8
1 1 1 1 Gain A = −1
ED/HD Adaptive Filter Gain 3,
Value B
0
0
0
0
Gain B = 0
0 0 0 1 Gain B = +1
0 1 1 1 Gain B = +7
1 0 0 0 Gain B = −8
1 1 1 1 Gain B = −1
0x5B ED/HD Adaptive Filter
Threshold A
ED/HD Adaptive Filter Threshold A x x x x x x x x Threshold A 0x00
0x5C ED/HD Adaptive Filter
Threshold B
ED/HD Adaptive Filter Threshold B x x x x x x x x Threshold B 0x00
0x5D ED/HD Adaptive Filter
Threshold C
ED/HD Adaptive Filter Threshold C x x x x x x x x Threshold C 0x00
1 x = Logic 0 or Logic 1.
Rev. I | Page 36 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Table 26. Register 0x5E to Register 0x6E
SR7 to Bit Number Register Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value
0x5E ED/HD CGMS Type B
Register 0
ED/HD CGMS Type B
enable
0 Disabled 0x00
1 Enabled
ED/HD CGMS Type B
CRC enable
0 Disabled
1 Enabled
ED/HD CGMS Type B
header bits
H5
H4
H3
H2
H1
H0
H5 to H0
0x5F ED/HD CGMS Type B
Register 1
ED/HD CGMS Type B
data bits
P7 P6 P5 P4 P3 P2 P1 P0 P7 to P0 0x00
0x60 ED/HD CGMS Type B
Register 2
ED/HD CGMS Type B
data bits
P15 P14 P13 P12 P11 P10 P9 P8 P15 to P8 0x00
0x61 ED/HD CGMS Type B
Register 3
ED/HD CGMS Type B
data bits
P23 P22 P21 P20 P19 P18 P17 P16 P23 to P16 0x00
0x62 ED/HD CGMS Type B
Register 4
ED/HD CGMS Type B
data bits
P31 P30 P29 P28 P27 P26 P25 P24 P31 to P24 0x00
0x63 ED/HD CGMS Type B
Register 5
ED/HD CGMS Type B
data bits
P39 P38 P37 P36 P35 P34 P33 P32 P39 to P32 0x00
0x64 ED/HD CGMS Type B
Register 6
ED/HD CGMS Type B
data bits
P47 P46 P45 P44 P43 P42 P41 P40 P47 to P40 0x00
0x65 ED/HD CGMS Type B
Register 7
ED/HD CGMS Type B
data bits
P55 P54 P53 P52 P51 P50 P49 P48 P55 to P48 0x00
0x66 ED/HD CGMS Type B
Register 8
ED/HD CGMS Type B
data dits
P63 P62 P61 P60 P59 P58 P57 P56 P63 to P56 0x00
0x67 ED/HD CGMS Type B
Register 9
ED/HD CGMS Type B
data bits
P71 P70 P69 P68 P67 P66 P65 P64 P71 to P64 0x00
0x68 ED/HD CGMS Type B
Register 10
ED/HD CGMS Type B
data bits
P79 P78 P77 P76 P75 P74 P73 P72 P79 to P72 0x00
0x69
ED/HD CGMS Type B
Register 11
ED/HD CGMS Type B
data bits
P87
P86
P85
P84
P83
P82
P81
P80
P87 to P80
0x00
0x6A ED/HD CGMS Type B
Register 12
ED/HD CGMS Type B
data bits
P95 P94 P93 P92 P91 P90 P89 P88 P95 to P88 0x00
0x6B ED/HD CGMS Type B
Register 13
ED/HD CGMS Type B
data bits
P103 P102 P101 P100 P99 P98 P97 P96 P103 to P96 0x00
0x6C ED/HD CGMS Type B
Register 14
ED/HD CGMS Type B
data bits
P111 P110 P109 P108 P107 P106 P105 P104 P111 to P104 0x00
0x6D ED/HD CGMS Type B
Register 15
ED/HD CGMS Type B
data bits
P119 P118 P117 P116 P115 P114 P113 P112 P119 to P112 0x00
0x6E ED/HD CGMS Type B
Register 16
ED/HD CGMS Type B
data bits
P127 P126 P125 P124 P123 P122 P121 P120 P127 to P120 0x00
Rev. I | Page 37 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Table 27. Register 0x80 to Register 0x83
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x80 SD Mode
Register 1
SD standard 0 0 NTSC 0x10
0 1 PAL B, PAL D, PAL G, PAL H, PAL I
1 0 PAL M
1 1 PAL N
SD luma filter
0
0
0
LPF NTSC
0 0 1 LPF PAL
0 1 0 Notch NTSC
0 1 1 Notch PAL
1 0 0 Luma SSAF
1 0 1 Luma CIF
1 1 0 Luma QCIF
1 1 1 Reserved
SD chroma filter 0 0 0 1.3 MHz
0
0
1
0.65 MHz
0 1 0 1.0 MHz
0 1 1 2.0 MHz
1 0 0 Reserved
1 0 1 Chroma CIF
1 1 0 Chroma QCIF
1 1 1 3.0 MHz
0x82 SD Mode
Register 2
SD PrPb SSAF filter 0 Disabled 0x0B
1 Enabled
SD DAC Output 1 0 See Table 37
1
Reserved 0
SD pedestal 0 Disabled
1
Enabled
SD square pixel mode 0 Disabled
1 Enabled
SD VCR FF/RW sync 0 Disabled
1 Enabled
SD pixel data valid 0 Disabled
1 Enabled
SD active video edge
control
0 Disabled
1 Enabled
0x83
SD Mode
Register 3
SD pedestal YPrPb output
0
No pedestal on YPrPb
0x04
1 7.5 IRE pedestal on YPrPb
SD Output Levels Y 0 Y = 700 mV/300 mV
1 Y = 714 mV/286 mV
SD Output Levels PrPb 0 0 700 mV p-p (PAL), 1000 mV p-p (NTSC)
0 1 700 mV p-p
1 0 1000 mV p-p
1 1 648 mV p-p
SD vertical blanking
interval (VBI) open
0 Disabled
1
Enabled
SD closed captioning field
control
0 0 Closed captioning disabled
0 1 Closed captioning on odd field only
1 0 Closed captioning on even field only
1
1
Closed captioning on both fields
Reserved 0 Reserved
Rev. I | Page 38 of 107
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Table 28. Register 0x84 to Register 0x87
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x84
SD Mode
Register 4
Reserved
0
0x00
SD SFL/SCR/TR mode select 0 0 Disabled.
1 1 SFL mode enabled.
SD active video length 0 720 pixels.
1 710 (NTSC), 702 (PAL).
SD chroma 0 Chroma enabled.
1 Chroma disabled.
SD burst 0 Enabled.
1 Disabled.
SD color bars
0
Disabled.
1 Enabled.
SD luma/chroma swap 0 DAC 2 = luma, DAC 3 = chroma.
1
DAC 2 = chroma, DAC 3 = luma.
0x86 SD Mode
Register 5
NTSC color subcarrier adjust (delay from
the falling edge of output HSYNC pulse to
the start of color burst)
0 0 5.17 μs. 0x02
0 1 5.31 μs.
1 0 5.59 μs (must be set for
Macrovision compliance).
1
1
Reserved.
Reserved 0
SD EIA/CEA-861B synchronization
compliance
0 Disabled.
1 Enabled.
Reserved 0 0
SD horizontal/vertical counter mode1 0 Update field/line counter.
1 Field/line counter free running.
SD RGB color swap2 0 Normal.
1 Color reversal enabled.
0x87 SD Mode
Register 6
SD luma and color scale control 0 Disabled. 0x00
1 Enabled.
SD luma scale saturation 0 Disabled.
1 Enabled.
SD hue adjust
0
Disabled.
1 Enabled.
SD brightness 0 Disabled.
1 Enabled.
SD luma SSAF gain 0 Disabled.
1
Enabled.
SD input standard autodetection 0 Disabled.
1 Enabled.
Reserved 0 0 must be written to this bit.
SD RGB input enable2 0 SD YCrCb input.
1 SD RGB input.
1 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
2 Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. I | Page 39 of 107
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Table 29. Register 0x88 to Register 0x89
SR7 to Bit Number Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x88 SD Mode Register 7 Reserved 0 0x00
SD noninterlaced mode 0 Disabled.
1 Enabled.
SD double buffering 0 Disabled.
1 Enabled.
SD input format 0 0 8-bit YCbCr input.
0 1 16-bit YCbCr input.1
1 0 10-bit YCbCr/16-bit SD RGB
input.1
1 1 Reserved.
SD digital noise reduction 0 Disabled.
1 Enabled.
SD gamma correction enable 0 Disabled.
1 Enabled.
SD gamma correction curve select 0 Gamma Correction Curve A.
1 Gamma Correction Curve B.
0x89 SD Mode Register 8 SD undershoot limiter 0 0 Disabled. 0x00
0 1 −11 IRE.
1 0 −6 IRE.
1 1 −1.5 IRE.
Reserved 0 0 must be written to this bit.
Reserved 0 Reserved.
SD chroma delay 0 0 Disabled.
0 1 4 clock cycles.
1 0 8 clock cycles.
1 1 Reserved.
Reserved 0 0 0 must be written to these bits.
1 Available on the ADV7392/ADV7393 (40-pin devices) only.
Table 30. Register 0x8A to Register 0x98
SR7 to Bit Number1 Reset
SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value
0x8A SD Timing Register 0 SD slave/master mode 0 Slave mode. 0x08
1 Master mode.
SD timing mode 0 0 Mode 0.
0 1 Mode 1.
1 0 Mode 2.
1 1 Mode 3.
Reserved 1
SD luma delay 0 0 No delay.
0 1 Two clock cycles.
1 0