ADuM5401-04 Datasheet

Analog Devices Inc.

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Datasheet

Quad-Channel, 2.5 kV Isolators with
Integrated DC-to-DC Converter
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D Document Feedback
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Tel: 781.329.4700 ©2008–2019 Analog Devices, Inc. All rights reserved.
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FEATURES
isoPower integrated, isolated dc-to-dc converter
Regulated 3.3 V or 5.0 V output
Up to 500 mW output power
Quad dc-to-25 Mbps (NRZ) signal isolation channels
16-lead SOIC package with 7.6 mm creepage
High temperature operation: 105°C maximum
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
IEC 60747-5-2 (VDE 0884, Part 2)
VIORM = 560 V peak
APPLICATIONS
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Power supply start-up bias and gate drives
Isolated sensor interfaces
Industrial PLCs
GENERAL DESCRIPTION
The ADuM5401/ADuM5402/ADuM5403/ADuM54041 are
quad-channel digital isolators with isoPower®, an integrated,
isolated dc-to-dc converter. Based on the Analog Devices, Inc.,
iCoupler® technology, the dc-to-dc converter provides up to
500 mW of regulated, isolated power at either 5.0 V or 3.3 V
from a 5.0 V input supply, or at 3.3 V from a 3.3 V supply at the
power levels shown in Table 1. These devices eliminate the need
for a separate, isolated dc-to-dc converter in low power, isolated
designs. The iCoupler chip scale transformer technology is used
to isolate the logic signals and for the power and feedback paths
in the dc-to-dc converter. The result is a small form factor, total
isolation solution.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 isolators
provide four independent isolation channels in a variety of
channel configurations and data rates (see the Ordering Guide
for more information).
isoPower uses high frequency switching elements to transfer
power through its transformer. Special care must be taken
during printed circuit board (PCB) layout to meet emissions
standards. See the AN-0971 Application Note for board layout
recommendations.
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OSC RECT
4 CHANNEL iCOUPLER CORE
V
DD1
REG
GND
1
V
IA
/V
OA
V
IB
/V
OB
V
IC
/V
OC
V
OD
RC
OUT
GND
1
V
ISO
GND
ISO
V
OA
/V
IA
V
OB
/V
IB
V
OC
/V
IC
V
ID
V
SEL
GND
ISO
ADuM5401/ADuM5402/
ADuM5403/ADuM5404
06577-001
Figure 1.
3
4
5
6
14
13
12
11
ADuM5401
06577-100
V
IA
V
IB
V
OA
V
OB
V
IC
V
OC
V
OD
V
ID
Figure 2. ADuM5401
3
4
5
6
14
13
12
11
ADuM5402
06577-101
V
IA
V
IB
V
OA
V
OB
V
OC
V
IC
V
OD
V
ID
Figure 3. ADuM5402
3
4
5
6
14
13
12
11
ADuM5403
06577-102
V
IA
V
OB
V
OA
V
IB
V
OC
V
IC
V
OD
V
ID
Figure 4. ADuM5403
3
4
5
6
14
13
12
11
ADuM5404
06577-103
V
OA
V
OB
V
IA
V
IB
V
OC
V
IC
V
OD
V
ID
Figure 5. ADuM5404
Table 1. Power Levels
Input Voltage (V) Output Voltage (V) Output Power (mW)
5.0 5.0 500
5.0 3.3 330
3.3 3.3 200
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply .......................................................... 4
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 6
Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 8
Package Characteristics ............................................................. 10
Regulatory Information ............................................................. 10
Insulation and Safety-Related Specifications .......................... 10
IEC 60747-5-2 (VDE 0884, Part 2):2003-01 Insulation
Characteristics ............................................................................ 11
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings .......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Truth Table .................................................................................. 16
Typical Performance Characteristics ........................................... 17
Terminology .................................................................................... 20
Applications Information .............................................................. 21
PCB Layout ................................................................................. 21
Thermal Analysis ....................................................................... 21
Propagation Delay-Related Parameters ................................... 22
Start-Up Behavior....................................................................... 22
EMI Considerations ................................................................... 22
DC Correctness and Magnetic Field Immunity .......................... 22
Power Consumption .................................................................. 23
Power Considerations ................................................................ 24
Increasing Available Power ....................................................... 24
Insulation Lifetime ..................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 3 of 28
REVISION HISTORY
3/2019—Rev. C to Rev. D
Change to Features Section .............................................................. 1
Change to Table 15 .......................................................................... 10
6/2012—Rev. B to Rev. C
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section ................................................................. 1
Updated Outline Dimensions ........................................................ 26
9/2011—Rev. A to Rev. B
Changes to Product Title, Features Section, and General
Description Section ........................................................................... 1
Added Table 1; Renumbered Sequentially ..................................... 1
Changes to Specifications Section ................................................... 3
Changes to Table 19 and Table 20 ................................................. 11
Changes to Table 21 ........................................................................ 12
Changes to Table 22 ........................................................................ 13
Changes to Table 23 ........................................................................ 14
Changes to Table 24 and Table 25 ................................................. 15
Changes to Figure 11 to Figure 13 ................................................ 16
Changes to Figure 11, Figure 12 Caption, Figure 14 Caption,
and Figure 16 Caption .................................................................... 16
Added Figure 19 and Figure 20; Renumbered Sequentially ...... 17
Changes to Figure 21 and Figure 22 ............................................. 17
Changes to Terminology Section .................................................. 19
Changes to Applications Information Section ............................ 20
Deleted Increasing Available Power, Figure 15, and Figure 16;
Renumbered Sequentially .............................................................. 20
Changes to PCB Layout Section .................................................... 20
Added Start-Up Behavior Section ................................................. 21
Moved and Changes to EMI Considerations Section ................ 21
Changes to DC Correctness and Magnetic Field Immunity
Section .............................................................................................. 21
Changes to Power Consumption Section and Figure 29 ........... 22
Changes to Power Considerations ................................................ 23
Added Increasing Available Power Section and Table 26 .......... 23
Added Table 27 ................................................................................ 24
Changes to Insulation Lifetime Section ....................................... 24
11/2008—Rev. 0 to Rev. A
Changes to Figure 1 and General Description Section ................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 4 ............................................................................ 7
Changes to Table 6 and Table 7 ....................................................... 8
Changes to Table 8 and Table 9 ....................................................... 9
Changes to Figure 7 and Table 10 ................................................. 10
Changes to Figure 8 and Table 11 ................................................. 11
Changes to Figure 9 and Table 12 ................................................. 12
Changes to Figure 10 and Table 13 ............................................... 13
Moved Truth Table Section ............................................................ 13
Changes to Applications Information Section and PCB Layout
Section .............................................................................................. 17
Changes to DC Correctness and Magnetic Field Immunity
Section .............................................................................................. 18
Changes to Power Considerations Section .................................. 20
Added Increasing Available Power Section, Table 15,
and Table 16 ..................................................................................... 20
5/2008—Revision 0: Initial Version
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 4 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 4.7 5.0 5.4 V IISO = 0 mA
Line Regulation VISO (LINE) 1 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
Load Regulation VISO (LOAD) 1 5 % IISO = 10 mA to 90 mA
Output Ripple VISO (RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
Output Noise VISO (NOISE) 200 mV p-p CBO = 0.1 μF||10 μF, IISO = 90 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO (MAX) 100 mA VISO > 4.5 V
Efficiency at IISO (MAX) 34 % IISO = 100 mA
IDD1, No VISO Load IDD1 (Q) 19 30 mA
IDD1, Full VISO Load IDD1 (MAX) 290 mA
Table 3. DC-to-DC Converter Dynamic Specifications
Parameter Symbol
1 Mbps—A Grade, C Grade 25 Mbps—C Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
Input IDD1
ADuM5401 19 68 mA No VISO load
ADuM5402 19 71 mA No VISO load
ADuM5403 19 75 mA No VISO load
ADuM5404 19 78 mA No VISO load
Available to Load IISO (LOAD)
ADuM5401 100 87 mA
ADuM5402 100 85 mA
ADuM5403 100 83 mA
ADuM5404 100 81 mA
Table 4. Switching Specifications
Parameter Symbol
A Grade C Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 55 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 15 ns Between any two units
Channel Matching
Codirectional1 t
PSKCD 50 6 ns
Opposing Directional2 t
PSKOD 50 15 ns
1 7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 5 of 28
Table 5. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 × VDD1 V
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 ×
VDD1
V
Logic High Output Voltages VOH V
DD1 − 0.3 or VISO − 0.3 5.0 V IOx = −20 μA, VIx = VIxH
V
DD1 − 0.5 or VISO − 0.5 4.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive Going Threshold VUV+ 2.7 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −20 +0.01 +20 μA 0 V VIxVDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity1
|CM| 25 35 kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 6 of 28
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.0 3.3 3.6 V IISO = 0 mA
Line Regulation VISO (LINE) 1 mV/V IISO = 30 mA, VDD1 = 3.0 V to 3.6 V
Load Regulation VISO (LOAD) 1 5 % IISO = 6 mA to 54 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 54 mA
Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 μF||10 μF, IISO = 54 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO (MAX) 60 mA VISO > 3 V
Efficiency at IISO (MAX) 33 % IISO = 60 mA
IDD1, No VISO Load IDD1 (Q) 14 20 mA
IDD1, Full VISO Load IDD1 (MAX) 175 mA
Table 7. DC-to-DC Converter Dynamic Specifications
Parameter Symbol
1 Mbps—A or C Grade 25 Mbps—C Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
Input IDD1
ADuM5401 14 44 mA No VISO load
ADuM5402 14 46 mA No VISO load
ADuM5403 14 47 mA No VISO load
ADuM5404 14 51 mA No VISO load
Available to Load IISO (LOAD)
ADuM5401 60 52 mA
ADuM5402 60 51 mA
ADuM5403 60 49 mA
ADuM5404 60 48 mA
Table 8. Switching Specifications
Parameter Symbol
A Grade C Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 60 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 45 ns Between any two units
Channel Matching
Codirectional1 t
PSKCD 50 6 ns
Opposing Directional2 t
PSKOD 50 15 ns
1 7Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 7 of 28
Table 9. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 × VDD1 V
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 ×
VDD1
V
Logic High Output Voltages VOH V
DD1 − 0.3 or VISO − 0.3 3.3 V IOx = −20 μA, VIx = VIxH
V
DD1 − 0.5 or VISO − 0.5 3.1 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive Going Threshold VUV+ 2.7 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −10 +0.01 +10 μA 0 V VIx ≤ VDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity1
|CM| 25 35 kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 8 of 28
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10. DC-to-DC Converter Static Specifications
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTER SUPPLY
Setpoint VISO 3.0 3.3 3.6 V IISO = 0 mA
Line Regulation VISO (LINE) 1 mV/V IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
Load Regulation VISO (LOAD) 1 5 % IISO = 6 mA to 54 mA
Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 μF||10 μF, IISO = 90 mA
Switching Frequency fOSC 180 MHz
PWM Frequency fPWM 625 kHz
Output Supply Current IISO (MAX) 100 mA VISO > 3 V
Efficiency at IISO (MAX) 30 % IISO = 90 mA
IDD1, No VISO Load IDD1 (Q) 14 20 mA
IDD1, Full VISO Load IDD1 (MAX) 230 mA
Table 11. DC-to-DC Converter Dynamic Specifications
Parameter Symbol
1 Mbps—A or C Grade 25 Mbps—C Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SUPPLY CURRENT
Input IDD1
ADuM5401 9 44 mA No VISO load
ADuM5402 9 45 mA No VISO load
ADuM5403 9 46 mA No VISO load
ADuM5404 9 47 mA No VISO load
Available to Load IISO (LOAD)
ADuM5401 100 92 mA
ADuM5402 100 91 mA
ADuM5403 100 89 mA
ADuM5404 100 88 mA
Table 12. Switching Specifications
Parameter Symbol
A Grade C Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
SWITCHING SPECIFICATIONS
Data Rate 1 25 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 60 100 45 60 ns 50% input to 50% output
Pulse Width Distortion PWD 40 6 ns |tPLH − tPHL|
Change vs. Temperature 5 ps/°C
Pulse Width PW 1000 40 ns Within PWD limit
Propagation Delay Skew tPSK 50 15 ns Between any two units
Channel Matching
Codirectional1 t
PSKCD 50 6 ns
Opposing Directional2 t
PSKOD 50 15 ns
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier.
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 9 of 28
Table 13. Input and Output Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Logic High Input Threshold VIH 0.7 × VISO or 0.7 ×
VDD1
V
Logic Low Input Threshold VIL 0.3 × VISO or 0.3 ×
VDD1
V
Logic High Output Voltages VOH V
DD1 − 0.2, VISO − 0.2 VDD1 or VISO V IOx = −20 μA, VIx = VIxH
VDD1 − 0.5 or
VISO − 0.5
VDD1 − 0.2 or
VISO − 0.2
V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.0 0.4 V IOx = 4 mA, VIx = VIxL
Undervoltage Lockout UVLO VDD1, VDDL, VISO supplies
Positive Going Threshold VUV+ 2.7 V
Negative Going Threshold VUV− 2.4 V
Hysteresis VUVH 0.3 V
Input Currents per Channel II −10 +0.01 +10 μA 0 V ≤ VIxVDDx
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient
Immunity1
|CM| 25 35 kV/μs
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 1.0 Mbps
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 10 of 28
PACKAGE CHARACTERISTICS
Table 14.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RESISTANCE AND CAPACITANCE
Resistance (Input-to-Output)1 R
I-O 1012 Ω
Capacitance (Input-to-Output)1 C
I-O 2.2 pF f = 1 MHz
Input Capacitance2 C
I 4.0 pF
IC Junction-to-Ambient Thermal
Resistance
θJA 45 °C/W
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces3
1 This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
3 See the Thermal Analysis section for thermal model definitions.
REGULATORY INFORMATION
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are approved by the organizations listed in Table 15. Refer to Table 20 and the
Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation
waveforms and insulation levels.
Table 15.
UL1 CSA VDE2
Recognized Under 1577 Component
Recognition Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to IEC 60747-5-2
(VDE 0884 Part 2):2003-012
Single Protection, 2500 V rms
Isolation Voltage
Testing was conducted per CSA 60950-1-07
and IEC 60950-1 2nd Ed. at 2.5 kV rated voltage
Basic insulation, 560 V peak
Basic insulation at 600 V rms (848 V peak)
working voltage
Reinforced insulation at 250 V rms (353 V peak)
working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second
(current leakage detection limit = 10 μA).
2 In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥
1590 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01
approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 16. Critical Safety-Related Dimensions and Material Properties
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Distance L(I01) 8.0 mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.6 mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303, Part 1
Material Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 11 of 28
IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking branded on the package denotes IEC 60747-5-2 (VDE 0884, Part 2) approval.
Table 17. VDE Characteristics
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 560 V peak
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1050 V peak
Input-to-Output Test Voltage, Method a VPR
After Environmental Tests Subgroup 1 VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC 896 V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 672 V peak
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 sec VTR 4000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 6)
Case Temperature TS 150 °C
Side 1 IDD1 Current IS1 555 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
0
100
200
300
400
500
600
0 50 100 150 200
AMBIENT TEMPERATURE (°C)
SAFE OPERATING V
DD1
CURRENT (mA)
06577-002
Figure 6. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 18.
Parameter Symbol Min Max Unit
Operating Temperature1 TA −40 +105 °C
Supply Voltages2
VDD1 @ VSEL = 0 V VDD 3.0 5.5 V
VDD1 @ VSEL = VISO V
DD 4.5 5.5 V
1 Operation at 105°C requires reduction of the maximum load current as specified in Table 19.
2 Each voltage is relative to its respective ground.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 12 of 28
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 19.
Parameter Rating
Storage Temperature Range (TST) −55°C to +150°C
Ambient Operating Temperature
Range (TA)
−40°C to +105°C
Supply Voltages (VDD1, VISO)1 −0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VID, VSEL)1, 2 −0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC, VOD)1, 2 −0.5 V to VDDO + 0.5 V
Average Output Current per Pin3 −10 mA to +10 mA
Common-Mode Transients4 −100 kV/μs to +100 kV/μs
1 Each voltage is relative to its respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
3 See Figure 6 for maximum rated current values for various temperatures.
4 Common-mode transients exceeding the absolute maximum slew rate may
cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1
Parameter Max Unit Applicable Certification
AC Voltage, Bipolar Waveform 424 V peak All certifications, 50-year operation
AC Voltage, Unipolar Waveform
Basic Insulation 600 V peak Working voltage per IEC 60950-1
Reinforced Insulation 353 V peak Working voltage per IEC 60950-1
DC Voltage
Basic Insulation 600 V peak Working voltage per IEC 60950-1
Reinforced Insulation 353 V peak Working voltage per IEC 60950-1
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 13 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1 1
GND
12
V
IA 3
V
IB 4
V
ISO
16
GND
ISO
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
OD 6
V
ID
11
RC
OUT 7
V
SEL
10
GND
18
GND
ISO
9
ADuM5401
TOP VIEW
(Not to Scale)
06577-004
Figure 7. ADuM5401 Pin Configuration
Table 21. ADuM5401 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that
both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5401 to
control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins
be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VOC Logic Output C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 14 of 28
V
DD1 1
GND
12
V
IA 3
V
IB 4
V
ISO
16
GND
ISO
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
RC
OUT 7
V
SEL
10
GND
18
GND
ISO
9
ADuM5402
TOP VIEW
(Not to Scale)
06577-005
Figure 8. ADuM5402 Pin Configuration
Table 22. ADuM5402 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that
both pins be connected to a common ground.
3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5402 to
control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins
be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 15 of 28
V
DD1 1
GND
12
V
IA 3
V
OB 4
V
ISO
16
GND
ISO
15
V
OA
14
V
IB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
RC
OUT 7
V
SEL
10
GND
18
GND
ISO
9
ADuM5403
TOP VIEW
(Not to Scale)
06577-006
Figure 9. ADuM5403 Pin Configuration
Table 23. ADuM5403 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that
both pins be connected to a common ground.
3 VIA Logic Input A.
4 VOB Logic Output B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5403 to
control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins
be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VIB Logic Input B.
14 VOA Logic Output A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 16 of 28
V
DD1 1
GND
12
V
OA 3
V
OB 4
V
ISO
16
GND
ISO
15
V
IA
14
V
IB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
RC
OUT 7
V
SEL
10
GND
18
GND
ISO
9
ADuM5404
TOP VIEW
(Not to Scale)
06577-007
Figure 10. ADuM5404 Pin Configuration
Table 24. ADuM5404 Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD1 Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended
that both pins be connected to a common ground.
3 VOA Logic Output A.
4 VOB Logic Output B.
5 VOC Logic Output C.
6 VOD Logic Output D.
7 RCOUT Regulation Control Output. This pin is connected to the RCIN pin of a slave isoPower device to allow the ADuM5404
to control the regulation of the slave device.
9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both
pins be connected to a common ground.
10 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11 VID Logic Input D.
12 VIC Logic Input C.
13 VIB Logic Input B.
14 VIA Logic Input A.
16 VISO Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
TRUTH TABLE
Table 25. Truth Table (Positive Logic)
VSEL1 RCOUT2 V
DD1 (V) VISO (V) Notes
H PWM 5 5 Master mode, normal operation
L PWM 5 3.3 Master mode, normal operation
L PWM 3.3 3.3 Master mode, normal operation
H PWM 3.3 5 This supply configuration is not recommended due to extremely poor efficiency
1 H refers to a high logic, and L refers to a low logic.
2 PWM refers to the regulation control signal. This signal is derived from the secondary side regulator and can be used to control other isoPower devices.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 17 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
0
5
10
15
20
25
30
35
40
0 0.02 0.04 0.06 0.08 0.10 0.12
06577-033
OUTPUT CURRENT (A)
EFFICIEN
C
Y (%)
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
Figure 11. Typical Power Supply Efficiency at 5 V Input/5 V Output
and 3.3 V Input/3.3 V Output
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 0.020.040.060.080.100.12
I
ISO
(A)
POWER DISSIP
A
TION (W)
V
DD1
= 5V, V
ISO
= 5V
V
DD1
= 5V, V
ISO
= 3.3V
V
DD1
= 3.3V, V
ISO
= 3.3V
0
6577-026
Figure 12. Typical Total Power Dissipation vs. Isolated Output Supply Current
in All Supported Power Configurations
0
0.02
0.04
0.06
0.08
0.10
0.12
0 0.05 0.10 0.15 0.20 0.25 0.350.30
INPUT CURRENT (A)
OUTPUT CURRENT (A)
06577-027
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
Figure 13. Typical Isolated Output Supply Current vs. Input Current
in All Supported Power Configurations
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
INPUT SUPPLY VOLTAGE (V)
POWER (W)
I
DD
06577-011
INPUT CURRENT (A)
POWER
Figure 14. Typical Short-Circuit Input Current and Power
vs. VDD1 Supply Voltage
06577-012
OUTPUT VOLTAGE
(500mV/DIV)
(100µs/DIV)
DYNAMIC LOAD
10% LOAD 90% LOAD
Figure 15. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
06577-013
OUTPUT VOLTAGE
(500mV/DIV)
(100µs/DIV)
DYNAMIC LOAD
10% LOAD 90% LOAD
Figure 16. Typical VISO Transient Load Response, 3.3 V Output,
10% to 90% Load Step
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 18 of 28
06577-014
BW = 20MHz (400ns/DIV)
5V OUTPUT RIPPLE (10mV/DIV)
Figure 17. Typical VISO = 5 V Output Voltage Ripple at 90% Load
06577-015
BW = 20MHz (400ns/DIV)
3.3V OUTPUT RIPPLE (10mV/DIV)
Figure 18. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load
06577-030
TIME (ms)
VISO (V)
7
6
5
4
3
2
1
0–1 0 1 2 3
90% LOAD
10% LOAD
Figure 19. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 5 V
06577-031
TIME (ms)
VISO (V)
5
4
3
2
1
0
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
90% LOAD
10% LOAD
Figure 20. Typical Output Voltage Start-Up Transient
at 10% and 90% Load, VISO = 3.3 V
0
4
8
12
16
20
0 5 10 15
DATA RATE (Mbps)
SUPPLY CURRENT (mA)
20 25
06577-028
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
Figure 21. Typical ICH Supply Current per Forward Data Channel
(15 pF Output Load)
0
4
8
12
16
20
0 5 10 15
DATA RATE (Mbps)
SUPPLY CURRENT (mA)
20 25
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
06577-029
Figure 22. Typical ICH Supply Current per Reverse Data Channel
(15 pF Output Load)
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 19 of 28
051015
DATA RATE (Mbps)
SUPPLY CURRENT (
m
A)
20 25
5V
3.3V
06577-119
0
2
1
3
4
5
Figure 23. Typical IISO (D) Dynamic Supply Current per Input
0
1.0
0.5
1.5
2.0
2.5
3.0
0 5 10 15
DATA RATE (Mbps)
SUPPLY CURRENT (
m
A)
20 25
5V
3.3V
06577-118
Figure 24. Typical IISO (D) Dynamic Supply Current per Output
(15 pF Output Load)
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 20 of 28
TERMINOLOGY
IDD1 (Q)
IDD1 (Q) is the minimum operating current drawn at the VDD1
pin when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic supply
current. IDD1 (Q) reflects the minimum current operating condition.
IDD1 (D)
IDD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Resistive loads on the outputs should be
treated separately from the dynamic load.
IDD1 (MAX)
IDD1 (MAX) is the input current under full dynamic and VISO load
conditions.
ISO (LOAD)
ISO (LOAD) is the current available to the load.
tPHL Propagation Delay
The tPHL propagation delay is measured from the 50% level of
the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal.
tPLH Propagation Delay
tPLH propagation delay is measured from the 50% level of the
rising edge of the VIx signal to the 50% level of the rising edge
of the VOx signal.
Propagation Delay Skew, tPSK
tPSK is the magnitude of the worst-case difference in tPHL and/or
tPLH that is measured between units at the same operating temper-
ature, supply voltages, and output load within the recommended
operating conditions.
Channel-to-Channel Matching, (tPSKCD/tPSKOD)
Channel-to-channel matching is the absolute value of the
difference in propagation delays between two channels when
operated with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 21 of 28
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 works on principles that are common to
most switching power supplies. It has a secondary side controller
architecture with isolated pulse-width modulation (PWM)
feedback. VDD1 power is supplied to an oscillating circuit that
switches current into a chip scale air core transformer. Power
transferred to the secondary side is rectified and regulated to
either 3.3 V or 5 V. The secondary (VISO) side controller regulates
the output by creating a PWM control signal that is sent to the
primary (VDD1) side by a dedicated iCoupler data channel. The
PWM modulates the oscillator circuit to control the power being
sent to the secondary side. Feedback allows for significantly higher
power and efficiency.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 implement
undervoltage lockout (UVLO) with hysteresis on the VDD1 power
input. This feature ensures that the converter does not enter
oscillation due to noisy input power or slow power-on ramp rates.
PCB LAYOUT
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 digital
isolators with 0.5 W isoPower integrated dc-to-dc converter
require no external interface circuitry for the logic interfaces.
Power supply bypassing is required at the input and output
supply pins (see Figure 25). Note that low ESR bypass capacitors
are required between Pin 1 and Pin 2 and between Pin 15 and
Pin 16, as close to the chip pads as possible.
The power supply section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 uses a 180 MHz oscillator frequency
to pass power efficiently through its chip scale transformers. In
addition, the normal operation of the data section of the iCoupler
introduces switching transients on the power supply pins. Bypass
capacitors are required for several operating frequencies. Noise
suppression requires a low inductance, high frequency capacitor;
ripple suppression and proper regulation require a large value
capacitor. These are most conveniently connected between Pin 1
and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO.
To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 μF and 10 μF for VDD1 and VISO. The smaller
capacitor must have a low ESR; for example, use of a ceramic
capacitor is advised.
The total lead length between the ends of the low ESR capacitor
and the input power supply pin must not exceed 2 mm. Installing
the bypass capacitor with traces more than 2 mm in length may
result in data corruption. Consider bypassing between Pin 1 and
Pin 8 and between Pin 9 and Pin 16 unless both common ground
pins are connected together close to the package.
V
DD1
GND
1
IA
/V
OA
V
IB
/V
OB
V
ISO
GND
ISO
V
OA
/V
IA
V
OB
/V
IB
V
IC
/V
OC
V
OC
/V
IC
V
OD
RC
OUT
V
ID
V
SEL
GND
1
BYPASS < 2mm
GND
ISO
06577-120
Figure 25. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
as specified in Table 19, thereby leading to latch-up and/or
permanent damage.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are power
devices that dissipate approximately 1 W of power when fully
loaded and running at maximum speed. Because it is not possible
to apply a heat sink to an isolation device, the devices primarily
depend on heat dissipation into the PCB through the GND
pins. If the devices are used at high ambient temperatures, provide
a thermal path from the GND pins to the PCB ground plane.
The board layout in Figure 25 shows enlarged pads for Pin 8 and
Pin 9. Large diameter vias should be implemented from the pad to
the ground, and power planes should be used to reduce inductance.
Multiple vias should be implemented from the pad to the ground
plane to significantly reduce the temperature inside the chip.
The dimensions of the expanded pads are at the discretion of
the designer and depend on the available board space.
THERMAL ANALYSIS
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices
consist of four internal die attached to a split lead frame with two
die attach paddles. For the purposes of thermal analysis, the die
is treated as a thermal unit, with the highest junction temperature
reflected in the θJA from Table 14. The value of θJA is based on
measurements taken with the devices mounted on a JEDEC
standard, 4-layer board with fine width traces and still air.
Under normal operating conditions, the ADuM5401/ADuM5402/
ADuM5403/ ADuM5404 devices operate at full load across the
full temperature range without derating the output current.
However, following the recommendations in the PCB Layout
section decreases thermal resistance to the PCB, allowing
increased thermal margins in high ambient temperatures.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 22 of 28
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 26).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
INPUT (
V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
06577-018
Figure 26. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5401/ADuM5402/ADuM5403/ADuM5404 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5401/
ADuM5402/ADuM5403/ADuM5404 components operating
under the same conditions.
START-UP BEHAVIOR
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 do not
contain a soft start circuit. Therefore, the start-up current and
voltage behavior must be taken into account when designing
with this device.
When power is applied to VDD1, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and the time
required to reach regulation voltage depends on the load and
the VDD1 slew rate.
With a fast VDD1 slew rate (200 μs or less), the peak current draws
up to 100 mA/V of VDD1. The input voltage goes high faster than
the output can turn on, so the peak current is proportional to
the maximum input voltage.
With a slow VDD1 slew rate (in the millisecond range), the input
voltage is not changing quickly when VDD1 reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VDD1 is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 14.
When starting the device for VISO = 5 V operation, do not limit
the current available to the VDD1 power pin to less than 300 mA.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices
may not be able to drive the output to the regulation point if a
current-limiting device clamps the VDD1 voltage during startup.
As a result, the ADuM5401/ADuM5402/ADuM5403/ADuM5404
devices can draw large amounts of current at low voltage for
extended periods of time.
The output voltage of the ADuM5401/ADuM5402/ADuM5403/
ADuM5404 devices exhibits VISO overshoot during startup. If
this overshoot could potentially damage components attached
to VISO, a voltage-limiting device such as a Zener diode can be
used to clamp the voltage. Typical behavior is shown in Figure 19
and Figure 20.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 devices must operate at 180 MHz to
allow efficient power transfer through the small transformers.
This creates high frequency currents that can propagate in circuit
board ground and power planes, causing edge emissions and
dipole radiation between the primary and secondary ground
planes. Grounded enclosures are recommended for applications
that use these devices. If grounded enclosures are not possible,
follow good RF design practices in the layout of the PCB. See the
AN-0971 Application Note for board layout recommendations
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions at the input for more than 1 μs, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
correctness at the output. If the decoder receives no internal pulses
for more than approximately 5 μs, the input side is assumed to
be unpowered or nonfunctional, and the isolator output is forced to
a default low state by the watchdog timer circuit. This situation
should occur in the ADuM5401/ADuM5402/ADuM5403/
ADuM5404 during power-up and power-down operations.
The limitation on the magnetic field immunity of the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 is set by the
condition in which induced voltage in the receiving coil of the
transformer is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this may occur. The 3.3 V operating condition of the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 is examined
because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 23 of 28
Given the geometry of the receiving coil in the ADuM5401/
ADuM5402/ADuM5403/ADuM5404, and an imposed
requirement that the induced voltage be, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated as shown in Figure 27.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001 1M
10
0.01
1k 10k 10M
0.1
1
100M100k
06577-019
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum
allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at
the receiving coil. This voltage is approximately 50% of the sensing
threshold and does not cause a faulty output transition. Similarly, if
such an event occurs during a transmitted pulse (and is of the
worst-case polarity), it reduces the received pulse from >1.0 V to
0.75 V, still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM5401/
ADuM5402/ADuM5403/ADuM5404 transformers. Figure 28
expresses these allowable current magnitudes as a function of
frequency for selected distances. As shown in Figure 28, the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 are extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example, a 0.5 kA current placed 5 mm away from the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 is required
to affect the operation of the device.
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE CURRENT (kA)
1k
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
06577-020
Figure 28. Maximum Allowable Current for Various Current-to-
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Spacings
Note that, at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler data
channels, as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
and secondary input/output channels cannot be determined sepa-
rately. All of these quiescent power demands have been combined
into the IDD1 (Q) current, as shown in Figure 29. The total IDD1 supply
current is the sum of the quiescent operating current; the dynamic
current, IDD1 (D), demanded by the I/O channels; and any external
IISO load.
CONVERTER
PRIMARY CONVERTER
SECONDARY
PRIMARY
DATA
INPUT/OUTPUT
4-CHANNEL
I
DDP(D)
SECONDARY
DATA
INPUT/OUTPUT
4-CHANNEL
I
ISO(D)
I
ISO
I
DD1(Q)
I
DD1(D)
06577-024
Figure 29. Power Consumption Within the
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Both dynamic input and output current is consumed only
when operating at channel speeds higher than the refresh rate,
fr. Each channel has a dynamic current determined by its data
rate. Figure 21 shows the current for a channel in the forward
direction, which means that the input is on the primary side of
the device. Figure 22 shows the current for a channel in the reverse
direction, which means that the input is on the secondary side of
the device. Both figures assume a typical 15 pF load. The following
relationship allows the total IDD1 current to be calculated:
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4 (1)
where:
IDD1 is the total supply input current.
ICHn is the current drawn by a single channel determined from
Figure 21 or Figure 22, depending on channel direction.
IISO is the current drawn by the secondary side external load.
E is the power supply efficiency at 100 mA load from Figure 11
at the VISO and VDD1 condition of interest.
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 24 of 28
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4 (2)
where:
IISO (LOAD) is the current available to supply an external secondary
side load.
IISO (MAX) is the maximum external secondary side load current
available at VISO.
IISO (D)n is the dynamic load current drawn from VISO by an input
or output channel, as shown in Figure 23 and Figure 24.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of IDD1 and IISO (LOAD).
POWER CONSIDERATIONS
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 power
input, data input channels on the primary side, and data channels
on the secondary side are all protected from premature operation
by undervoltage lockout (UVLO) circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive
and all input channel drivers and refresh circuits are idle. Outputs
remain in a high impedance state to prevent transmission of
undefined states during power-up and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because no
data comes from the secondary side inputs until secondary side
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
The secondary VISO voltage is below its UVLO limit at this
point; the regulation control signal from the secondary side
is not being generated. The primary side power oscillator is
allowed to free run under these conditions, supplying the
maximum amount of power to the secondary side.
As the secondary side voltage rises to its regulation setpoint,
a large inrush current transient is present at VDD1. When the
regulation point is reached, the regulation control circuit produces
the regulation control signal that modulates the oscillator on the
primary side. The VDD1 current is then reduced and is propor-
tional to the load current. The inrush current is less than the
short-circuit current shown in Figure 14. The duration of the
inrush current depends on the VISO loading conditions and on
the current and voltage available at the VDD1 pin.
As the secondary side converter begins to accept power from the
primary, the VISO voltage starts to rise. When the secondary side
UVLO is reached, the secondary side outputs are initialized to
their default low state until data is received from the corresponding
primary side input. It can take up to 1 μs after the secondary
side is initialized for the state of the output to correlate to the
primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care that the design allows the converter
sufficient time to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is reached
and the outputs are placed in their high impedance state, or the
outputs detect a lack of activity from the primary side inputs and
the outputs are set to their default low value before the secondary
power reaches UVLO.
INCREASING AVAILABLE POWER
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are
designed with the capability of running in combination with
other compatible isoPower devices. The RCOUT pin allows the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 to provide its
PWM signal to another device acting as a master to regulate its
self and slave devices. Power outputs are combined in parallel
while sharing output power equally.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 can only
be a master/standalone, and the ADuM5200 can only be a slave/
standalone device. The ADuM5000 can operate as either a master
or slave. This means that the ADuM5000, ADuM520x, and
ADuM540x can only be used in the master/slave combinations
listed in Table 26.
Table 26. Allowed Combinations of isoPower Devices
Slave
Master ADuM5000 ADuM520x ADuM540x
ADuM5000 Yes Yes No
ADuM520x No No No
ADuM540x Yes Yes No
The allowed combinations of master and slave configured devices
listed in Table 26 is sufficient to make any combination of power
and channel count.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 25 of 28
Table 27 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single unit power.
Table 27. Configurations for Power and Data Channels
Number of Data Channels
Power Unit 0 Channels 2 Channels 4 Channels 6 Channels
1-Unit Power ADuM5000 master ADuM520x master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master
ADuM121x
2-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master
ADuM5000 slave ADuM520x slave ADuM520x slave ADuM520x slave
3-Unit Power ADuM5000 master ADuM5000 master ADuM5401 to ADuM5404 master ADuM5401 to ADuM5404 master
ADuM5000 slave ADuM5000 slave ADuM5000 slave ADuM520x slave
ADuM5000 slave ADuM520x slave ADuM5000 slave ADuM5000 slave
INSULATION LIFETIME
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices carries
out an extensive set of evaluations to determine the lifetime
of the insulation structure within the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 devices.
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual working
voltage. The values shown in Table 20 summarize the peak voltage
for 50 years of service life for a bipolar ac operating condition
and the maximum CSA/VDE approved working voltages. In
many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 devices depends on the voltage wave-
form type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30,
Figure 31, and Figure 32 illustrate these different isolation
voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 20 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases.
Any cross-insulation voltage waveform that does not conform
to Figure 31 or Figure 32 should be treated as a bipolar ac wave-
form and its peak voltage limited to the 50-year lifetime voltage
value listed in Table 20.
The voltage presented in Figure 32 is shown as sinusoidal for
illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
0V
RATED PEAK VOLTAGE
06577-021
Figure 30. Bipolar AC Waveform
0V
RATED PEAK VOLTAGE
06577-023
Figure 31. DC Waveform
NOTES:
1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION
PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE
WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE.
THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE
VOLTAGE CANNOT CROSS 0V.
0V
RATED PEAK VOLTAGE
06577-022
Figure 32. Unipolar AC Waveform
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 26 of 28
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
16 9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VISO Side
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay, 5 V (ns)
Maximum
Pulse Width
Distortion (ns)
Tem perature
Range (°C)
Package
Description
Package
Option
ADuM5401ARWZ 3 1 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5401CRWZ 3 1 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
ADuM5402ARWZ 2 2 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5402CRWZ 2 2 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
ADuM5403ARWZ 1 3 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5403CRWZ 1 3 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
ADuM5404ARWZ 0 4 1 100 40 −40 to +105 16-Lead SOIC_W RW-16
ADuM5404CRWZ 0 4 25 60 6 −40 to +105 16-Lead SOIC_W RW-16
1 Z = RoHS Compliant Part.
2 Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option.
Data Sheet ADuM5401/ADuM5402/ADuM5403/ADuM5404
Rev. D | Page 27 of 28
NOTES
ADuM5401/ADuM5402/ADuM5403/ADuM5404 Data Sheet
Rev. D | Page 28 of 28
NOTES
©2008–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06577-0-3/19(D)

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