ADM7150 Datasheet

Analog Devices Inc.

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Datasheet

800 mA Ultralow Noise,
High PSRR, RF Linear Regulator
Data Sheet
ADM7150
FEATURES
Input voltage range: 4.5 V to 16 V
Maximum output current: 800 mA
Low noise
1.0 µV rms total integrated noise from 100 Hz to 100 kHz
1.6 µV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV√Hz typical from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR) at 400 mA load
>90 dB from 1 kHz to 100 kHz, VOUT = 5 V
>60 dB at 1 MHz, VOUT = 5 V
Dropout voltage: 0.6 V at VOUT = 5 V, 800 mA load
Initial voltage accuracy: ±1%
Voltage accuracy over line, load and temperature: ±2%
Quiescent current (IGND): 4.3 mA at no load
Low shutdown current: 0.1 µA
Stable with a 10 µF ceramic output capacitor
Fixed output voltage options: 1.8 V, 2.8 V, 3.0 V, 3.3 V, 4.5 V,
4.8 V, and 5.0 V (16 outputs between 1.5 V and 5.0 V are
available)
Exposed pad 8-lead LFCSP and 8-lead SOIC packages
APPLICATIONS
Regulated power noise sensitive applications
RF mixers, phase-locked loops (PLLs), voltage-controlled
oscillators (VCOs), and PLLs with integrated VCOs
Communications and infrastructure
Cable digital-to-analog converter (DAC) drivers
Backhaul and microwave links
TYPICAL APPLICATION CIRCUIT
VOUT
REF
REF_SENSE
GND
VIN
EN
BYP
VREG
ADM7150
C
REG
10µF
C
BYP
1µF
C
REF
1µF
C
IN
10µF C
OUT
10µF
OFF
ON
V
IN
= 6.2V V
OUT
= 5.0V
11043-001
Figure 1. 5 V Output Circuit
GENERAL DESCRIPTION
The ADM7150 is a low dropout (LDO) linear regulator that
operates from 4.5 V to 16 V and provides up to 800 mA of
output current. Using an advanced proprietary architecture, it
provides high power supply rejection (>90 dB from 1 kHz to 1 MHz),
ultralow output noise (<1.7 nV√Hz), and achieves excellent line and
load transient response with a 10 µF ceramic output capacitor.
The ADM7150 is available in 1.8 V, 2.8 V, 3.0 V, 3.3 V, 4.5 V,
4.8 V, and 5.0 V fixed outputs. In addition, 16 fixed output
voltages between 1.5 V and 5.0 V are available upon request.
The ADM7150 regulator typical output noise is 1.0 µV rms
from 100 Hz to 100 kHz for fixed output voltage options, and
the noise spectral density is 1.7 nV/√Hz from 10 kHz to 1 MHz.
The ADM7150 is available in 8-lead, 3 mm × 3 mm LFCSP and
8-lead SOIC packages, making it not only a very compact solution
but also providing excellent thermal performance for applications
requiring up to 800 mA of output current in a small, low profile
footprint. See the ADM7151 adjustable LDO to generate additional
output voltages.
100k
1
10
100
1k
10k
0.1 110 100 1k 10k 100k 1M
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (Hz)
C
BYP
= 1µF
C
BYP
= 10µF
C
BYP
= 100µF
C
BYP
= 1mF
11043-002
Figure 2. Noise Spectral Density (NSD) vs. Frequency for Various CBYP
Rev. 0 Document Feedback
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ADM7150 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor Recommended Specifications ... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 15
Applications Information .............................................................. 16
Capacitor Selection .................................................................... 16
Enable (EN) and Undervoltage Lockout (UVLO) ................. 17
Start-Up Time ............................................................................. 18
REF, BYP, and, VREG pins ........................................................ 18
Current-Limit and Thermal Overload Protection ................. 19
Thermal Considerations ............................................................ 19
Printed Circuit Board Layout Considerations........................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
9/13Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet ADM7150
SPECIFICATIONS
VIN = VOUT + 1.2 V or VIN = 4.5 V, whichever is greater, VEN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 µF, CREF = CBYP = 1 µF. TA = 25°C
for typical specifications. TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN 4.5 16 V
OPERATING SUPPLY CURRENT IGND IOUT = 0 µA 4.3 7.0 mA
IOUT = 800 mA 8.6 12 mA
SHUTDOWN CURRENT IIN-SD VEN = 0 V 0.1 3 µA
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, independent of output voltage 1.6 µV rms
100 Hz to 100 kHz, independent of output voltage 1.0 µV rms
NOISE SPECTRAL DENSITY NSD 10 kHz to 1 MHz, independent of output voltage 1.7 nV/√Hz
POWER SUPPLY REJECTION RATIO PSRR 1 kHz to 100 kHz, VIN = 6.2 V, VOUT = 5 V at 800 mA 86 dB
1 MHz, V
IN
= 6.2 V, V
OUT
= 5 V at 800 mA
dB
1 kHz to 100 kHz, V
IN
= 6.2 V, V
OUT
= 5 V at 400 mA
dB
1 MHz, VIN = 6.2 V, VOUT = 5 V at 400 mA 62 dB
1 kHz to 100 kHz, VIN = 5 V, VOUT = 3.3 V at 800 mA 94 dB
1 MHz, VIN = 5 V, VOUT = 3.3 V at 800 mA 62 dB
1 kHz to 100 kHz, VIN = 5 V, VOUT = 3.3 V at 400 mA 95 dB
1 MHz, VIN = 5 V, VOUT = 3.3 V at 400 mA 68 dB
VOUT VOLTAGE ACCURACY VOUT = VREF
Voltage Accuracy VOUT IOUT = 10 mA, TJ = 25°C −1 +1 %
1 mA < IOUT < 800 mA, over line, load and
temperature
−2 +2 %
VOUT REGULATION
Line Regulation ΔVOUT/ΔVIN VIN = VOUT + 1.2 V or VOUT + 4.5 V, whichever is
greater, to 16 V
−0.01 +0.01 %/V
Load Regulation1 ΔVOUT/ΔIOUT IOUT = 1 mA to 800 mA 0.4 1.0 %/A
V
OUT
CURRENT-LIMIT THRESHOLD
2
I
LIMIT
1.0
1.6
A
DROPOUT VOLTAGE3 VDROPOUT IOUT = 400 mA, VOUT = 5 V 0.3 0.5 V
IOUT = 800 mA, VOUT = 5 V 0.6 1.0 V
PULL-DOWN RESISTANCE
VOUT Pull-Down Resistance VOUT-PULL VEN = 0 V, VOUT = 1 V 600 Ω
VREG Pull-Down Resistance VREG-PULL VEN = 0 V, VREG = 1 V 34
VREF Pull-Down Resistance VREF-PULL VEN = 0 V, VREF = 1 V 800 Ω
VBYP Pull-Down Resistance VBYP-PULL VEN = 0 V, VBYP = 1 V 500 Ω
START-UP TIME
4
V
OUT
= 5 V
VOUT Start-Up Time tSTART-UP 2.8 ms
VREG Start-Up Time tREG-START-UP 1.0 ms
VREF Start-Up Time tREF-START-UP 1.8 ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD TJ rising 155 °C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
UNDERVOLTAGE THRESHOLDs
Input Voltage Rising UVLORISE 4.49 V
Input Voltage Falling UVLOFALL 3.85 V
Hysteresis UVLOHYS 240 mV
VREG5 UNDERVOLTAGE THRESHOLDS
VREG Rise VREGUVLORISE 3.1 V
VREG Fall VREGUVLOFALL 2.55 V
Hysteresis VREGUVLOHYS 210 mV
Rev. 0 | Page 3 of 24
ADM7150 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
EN INPUT 4.5 V ≤ VIN 16 V
EN Input Logic High ENHIGH 3.2 V
EN Input Logic Low ENLOW 0.8 V
EN Input Logic Hysteresis ENHYS VIN = 5 V 225 mV
EN Input Leakage Current
I
EN-LKG
V
EN
= V
IN
or GND
1.0
µA
1 Based on an end-point calculation using 1 mA and 800 mA loads. See Figure 7, Figure 16, and Figure 22 for typical load regulation performance for loads less than 1 mA.
2 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to achieve the nominal output voltage. Dropout applies only for
output voltages above 4.5 V.
4 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
5 The output voltage is turned off until the VREG UVLO rise threshold is crossed. The VREG output is turned off until the input voltage UVLO rise threshold is crossed.
INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CAPACITANCE TA = −40°C to +125°C
Minimum Input1 CIN 7.0 µF
Minimum Regulator1 CREG 7.0 µF
Minimum Output
1
C
OUT
7.0
µF
Minimum Bypass
C
BYP
0.1
µF
Minimum Reference CREF 0.7 µF
CAPACITOR Equivalent Series Resistance (ESR) RESR TA = −40°C to +125°C
CREG, COUT, CIN, CREF 0.001 0.2 Ω
CBYP 0.001 2.0 Ω
1 The minimum input, regulator, and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions
in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are
recommended; however, Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. 0 | Page 4 of 24
Data Sheet ADM7150
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND 0.3 V to +18 V
VREG to GND 0.3 V to VIN, or +6 V
(whichever is less)
VOUT to GND 0.3 V to VREG, or +6 V
(whichever is less)
VOUT to BYP ±0.3 V
EN to GND 0.3 V to +18 V
BYP to GND 0.3 V to VREG, or +6 V
(whichever is less)
REF to GND 0.3 V to VREG, or +6 V
(whichever is less)
REF_SENSE to GND 0.3 V to +6 V
Storage Temperature Range 65°C to +150°C
Junction Temperature 150°C
Operating Ambient Temperature Range 40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADM7150 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may have to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
Junction to ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information
on the board construction.
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and the
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance JB). Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that is,
a device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC ΨJB Unit
8-Lead LFCSP 36.7 23.5 13.3 °C/W
8-Lead SOIC 36.9 27.1 18.6 °C/W
ESD CAUTION
Rev. 0 | Page 5 of 24
ADM7150 Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
3BYP
4GND
1VREG
2VOUT
6REF
5 REF_SENSE
8 VIN
7 EN
ADM7150
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.
EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
THE BOARD TO ENSURE PROPER OPERATION.
11043-003
Figure 3. 8-Lead LFCSP Pin Configuration
ADM7150
TOP VIEW
(Not to Scale)
VREG
1
VOUT
2
BYP
3
GND
4
VIN
8
EN
7
REF
6
REF_SENSE
5
11043-004
NOTES
1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.
EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.
CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON
THE BOARD TO ENSURE PROPER OPERATION.
Figure 4. 8-Lead SOIC Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VREG Regulated I
nput Supply to LDO Amplifier. Bypass VREG to GND with a 10 µF or greater capacitor. Do not connect
a load to ground.
2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 10 µF or greater capacitor.
3 BYP Low Noise Bypass Capacitor. Connect a 1 µF capacitor to GND to reduce noise. Do not connect a load to ground.
4 GND Ground Connection.
5 REF_SENSE REF_SENSE must be connected to the REF pin for proper operation. Do not connect to VOUT or GND.
6 REF Low Noise Reference Voltage Output. Bypass REF to GND with a 1 µF capacitor. Short REF_SENSE to REF for fixed
output voltages. Do not connect a load to ground.
7
EN
Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup,
connect EN to VIN.
8 VIN Regulator Input Supply. Bypass VIN to GND with a 10 µF or greater capacitor.
EPAD Exposed Pad on the Bottom of the Package. The exposed pad enhances thermal performance and is electrically
connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure
proper operation.
Rev. 0 | Page 6 of 24
Data Sheet ADM7150
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 1.2 V, or VIN = 4.5 V, whichever is greater, VEN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 µF, CREF = CBYP = 1 µF, TA = 25°C,
unless otherwise noted.
SHUTDOWN CURRENTA)
TEMPERATURE (°C)
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
–50 –25 025 50 75 100 125
VIN = 6.2V
VIN = 6.5V
VIN = 7V
VIN = 10V
VIN = 16V
11043-005
Figure 5. Shutdown Current vs. Temperature at
Various Input Voltages, VOUT = 5 V
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
1258525–5–40
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
11043-006
Figure 6. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = 5 V
V
OUT
(V)
I
LOAD
(mA)
1000100101
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
11043-007
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 5 V
V
OUT
(V)
V
IN
(V)
1612 141086
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
5.04
5.05
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
11043-008
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 5 V
GROUND CURRENT (mA)
JUNCTION TEMPERATURE (°C)
12585
25–5–40
0
2
4
6
8
10
12
14
16
18
20 LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
11043-009
Figure 9. Ground Current vs. Junction Temperature (TJ), VOUT = 5 V
GROUND CURRENT (mA)
I
LOAD
(mA)
1000100101
0
1
2
3
4
5
6
7
8
9
10
11043-010
Figure 10. Ground Current vs. Load Current (ILOAD), VOUT = 5 V
Rev. 0 | Page 7 of 24
ADM7150 Data Sheet
GROUND CURRENT (mA)
V
IN
(V)
1615
1413
12
1110
9876
5
0
1
2
3
4
5
6
7
8
9
10
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
11043-011
Figure 11. Ground Current vs. Input Voltage (VIN), VOUT = 5 V
DROPOUT VOLTAGE (mV)
I
LOAD
(mA)
1000100101
0
700
600
500
400
300
200
100
11043-012
Figure 12. Dropout Voltage vs. Load Current (ILOAD), VOUT = 5 V
V
OUT
(V)
V
IN
(V)
6.05.85.65.45.25.04.84.6
4.0
5.2
5.0
4.8
4.6
4.4
4.2
V
DROPOUT
= 5mA
V
DROPOUT
= 10mA
V
DROPOUT
= 100mA
V
DROPOUT
= 200mA
V
DROPOUT
= 400mA
V
DROPOUT
= 800mA
11043-013
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = 5 V
GROUND CURRENT (mA)
V
IN
(V)
6.0
5.85.6
5.45.25.04.84.6
0
12
10
8
6
4
2
I
GND
= 5mA
I
GND
= 10mA
I
GND
= 100mA
I
GND
= 200mA
I
GND
= 400mA
I
GND
= 800mA
11043-014
Figure 14. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 5 V
11043-015
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
1258525
–5
–40
3.26
3.27
3.28
3.29
3.30
3.31
3.32
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 15. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = 3.3 V
V
OUT
(V)
I
LOAD
(mA)
1000100101
3.26
3.32
3.31
3.30
3.29
3.28
3.27
11043-016
Figure 16. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Rev. 0 | Page 8 of 24
Data Sheet ADM7150
11043-017
V
OUT
(V)
V
IN
(V)
1612
81410
6
4
3.26
3.32
3.31
3.30
3.29
3.28
3.27
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 3.3 V
11043-018
GROUND CURRENT (mA)
JUNCTION TEMPERATURE (°C)
1258525–5–40
0
10
9
8
7
6
5
4
3
2
1
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 18. Ground Current vs. Junction Temperature (TJ), VOUT = 3.3 V
GROUND CURRENT (mA)
I
LOAD
(mA)
1000
100101
0
1
2
3
4
5
6
7
8
9
10
11043-019
Figure 19. Ground Current vs. Load Current (ILOAD), VOUT = 3.3 V
11043-020
GROUND CURRENT (mA)
V
IN
(V)
16
12814
10
64
0
10
9
8
7
6
5
4
3
2
1
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 20. Ground Current vs. Input Voltage (VIN), VOUT = 3.3 V
V
OUT
(V)
JUNCTION TEMPERATURE (°C)
1258525–5–40
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820 LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
11043-021
Figure 21. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = 1.8 V
1000100101
V
OUT
(V)
I
LOAD
(mA)
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
11043-022
Figure 22. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.8 V
Rev. 0 | Page 9 of 24
ADM7150 Data Sheet
11043-023
V
OUT
(V)
V
IN
(V)
16
10 12 14
8
64
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820 LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 23. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 1.8 V
11043-024
GROUND CURRENT (mA)
JUNCTION TEMPERATURE (°C)
125
85
25–5
–40
0
10
9
8
7
6
5
4
3
2
1
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 24. Ground Current vs. Junction Temperature (TJ), VOUT =1.8 V
GROUND CURRENT (mA)
I
LOAD
(mA)
1000100101
0
1
2
3
4
5
6
7
8
9
10
11043-025
Figure 25. Ground Current vs. Load Current (ILOAD), VOUT = 1.8 V
11043-026
GROUND CURRENT (mA)
V
IN
(V)
16
12814
1064
0
10
9
8
7
6
5
4
3
2
1
LOAD = 1mA
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 26. Ground Current vs. Input Voltage (VIN), VOUT = 1.8 V
11043-027
PSRR (dB)
FREQUENCY (Hz)
10M110 100 1k 10k 100k 1M
–120
0
–20
–40
–60
–80
–100
LOAD = 800mA
LOAD = 400mA
LOAD = 200mA
LOAD = 100mA
LOAD = 10mA
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 5 V, VIN = 6.2 V
11043-028
PSRR (dB)
FREQUENCY (Hz)
10M110 100 1k 10k 100k 1M
–120
0
–20
–40
–60
–80
–100
400mV
500mV
600mV
700mV
800mV
900mV
1.0V
1.1V
1.2V
1.3V
1.4V
1.5V
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various
Headroom Voltage, VOUT = 5 V, 400 mA Load
Rev. 0 | Page 10 of 24
Data Sheet ADM7150
11043-029
PSRR (dB)
FREQUENCY (Hz)
10M110 100 1k 10k 100k 1M
–120
0
–20
–40
–60
–80
–100
LOAD = 800mA
LOAD = 400mA
LOAD = 200mA
LOAD = 100mA
LOAD = 10mA
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 3.3 V, VIN = 5 V
11043-030
PSRR (dB)
FREQUENCY (Hz)
10M110 100 1k 10k 100k 1M
–120
0
–20
–40
–60
–80
–100
LOAD = 800mA
LOAD = 400mA
LOAD = 200mA
LOAD = 100mA
LOAD = 10mA
Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = 1.8 V, VIN = 5 V
11043-031
PSRR (dB)
HEADROOM (V)
1.21.11.00.90.80.70.6
0.50.40.30.2
–120
0
–20
–40
–60
–80
–100
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
100 mA Load, VOUT = 5 V
11043-032
PSRR (dB)
HEADROOM (V)
1.51.31.10.90.7
0.5
0.3
–120
0
–20
–40
–60
–80
–100
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
400 mA Load, VOUT = 5 V
11043-033
PSRR (dB)
HEADROOM (V)
1.61.51.4
1.31.21.11.00.90.8
0.70.6
–120
0
–20
–40
–60
–80
–100
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
800 mA Load, VOUT = 5 V
11043-034
PSRR (dB)
CAPACITANCE (µF)
1000110 100
–70
–60
–50
–40
–30
–20
–10
010Hz
100Hz
1kHz
10kHz
100kHz
1MHz
Figure 34. Power Supply Rejection Ratio (PSRR) vs. CBYP,
400 mA Load, 400 mV Headroom, VOUT = 5 V
Rev. 0 | Page 11 of 24
ADM7150 Data Sheet
11043-035
PSRR (dB)
CAPACITANCE (µF)
1000
110 100
–120
–110
–100
–90
–80
–70
–50
–60
–40 10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Capacitance (CBYP),
400 mA Load, 1.2 V Headroom, VOUT = 5 V
11043-036
NOISE (µVrms)
LOAD CURRENT (mA)
100010 100
0
0.2
0.4
0.6
0.8
1.0
1.4
1.6
1.8
1.2
2.0
10Hz TO 100kHz
Figure 36. RMS Output Noise vs. Load Current (ILOAD), 10 Hz to 100 kHz
11043-037
NOISE (µVrms)
LOAD CURRENT (mA)
100010 100
0
0.2
0.4
0.6
0.8
1.0
1.4
1.6
1.8
1.2
2.0
100Hz TO 100kHz
Figure 37. RMS Output Noise vs. Load Current (ILOAD), 100 Hz to 100 kHz
11043-038
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (Hz)
10M1k 100k 1M
10k
0.1
1
10
Figure 38. Output Noise Spectral Density,
1 kHz to 10 MHz, ILOAD = 10 mA
11043-039
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (Hz)
100k
10k0.1 110 100 1k
1
100k
10k
1k
100
10
Figure 39. Output Noise Spectral Density,
0.1 Hz to 100 kHz, ILOAD = 10 mA
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (Hz)
10M1M1k 10k 100k
0.1
1
1k
100
10
11043-040
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 40. Output Noise Spectral Density at Different Load Currents,
1 kHz to 10 MHz
Rev. 0 | Page 12 of 24
Data Sheet ADM7150
11043-041
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (Hz)
100k0.1 110 100 1k 10k
0.1
1
100k
100
1k
10k
10
LOAD = 10mA
LOAD = 100mA
LOAD = 200mA
LOAD = 400mA
LOAD = 800mA
Figure 41. Output Noise Spectral Density at Different Load Currents,
0.1 Hz to 100 kHz
11043-042
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (Hz)
1M0.1 110 100 1k 10k 100k
1
100k
100
1k
10k
10
C
BYP
= 1µF
C
BYP
= 4.7µF
C
BYP
= 10µF
C
BYP
= 22µF
C
BYP
= 47µF
C
BYP
= 100µF
C
BYP
= 470µF
C
BYP
= 1mF
Figure 42. Output Noise Spectral Density at Different CBYP,
Load Current = 10 mA
CH1 500mA Ω
BW
CH2 20mV
BW
M20µs A CH1 200mA
T 10.40%
1
2
T
11043-043
Figure 43. Load Transient Response, ILOAD = 1 mA to 800 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
CH1 500mA Ω
BW
CH2 10mV
BW
M4µs A CH1 200mA
T 11.0%
1
2
T
11043-044
Figure 44. Load Transient Response, ILOAD = 10 mA to 800 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
CH1 200mA Ω
BW
CH2 10mV
BW
M2µs A CH1 460mA
T 11.0%
1
2
T
11043-045
Figure 45. Load Transient Response, ILOAD = 100 mA to 600 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
CH1 50.0mA Ω
BW
CH2 2.0mV
BW
M4µs A CH1 50.0mA
T 10.0%
1
2
T
11043-046
Figure 46. Load Transient Response, ILOAD = 1 mA to100 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT
Rev. 0 | Page 13 of 24
ADM7150 Data Sheet
CH1 1.0V
BW
CH2 2.0mV Ω
BW
M10µs A CH1 1.14V
T 10.0%
1
2
T
11043-047
Figure 47. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,
VOUT = 1.8 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT
CH1 1.0V
BW
CH2 2.0mV Ω
BW
M10µs A CH3 1.14V
T 10.0%
1
2
T
11043-048
Figure 48. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,
VOUT = 3.3 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT
CH1 1.0V
BW
CH2 2.0mV Ω
BW
M10µs A CH3 1.14V
T 10.0%
1
2
T
11043-049
Figure 49. Line Transient Response, 2 V Input Step, ILOAD = 800 mA,
VOUT = 5 V, VIN = 6.2 V, CH1 = VIN, CH2 = VOUT
11043-050
VOLTS
TIME (ms)
10
0 1 2 3 4 5 6789
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
EN
V
REG
V
REF
V
OUT
Figure 50. VOUT, VREF, VREG Start-Up Time After VEN Rising, VOUT = 3.3 V, VIN = 5 V
Rev. 0 | Page 14 of 24
Data Sheet ADM7150
THEORY OF OPERATION
The ADM7150 is an ultralow noise, high power supply rejection
ratio (PSRR) linear regulator targeting radio frequency (RF)
applications. The input voltage range is 4.5 V to 16 V, and it can
deliver up to 800 mA of output current. Typical shutdown current
consumption is 0.1 µA at room temperature.
Optimized for use with 10 µF ceramic capacitors, the ADM7150
provides excellent transient performance.
VREG GND
VOUT
VIN
EN
REF
REF_SENSE
REFERENCE
SHUTDOWN
ACTIVE
RIPPLE
FILTER SHORT CIRCUIT,
THERMAL
PROTECT
OTA E/A
BYP
11043-051
Figure 51. Simplified Internal Block Diagram
Internally, the ADM7150 consists of a reference, an error amplifier,
and a P-channel MOSFET pass transistor. Output current is
delivered via the PMOS pass device, which is controlled by the
error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
By heavily filtering the reference voltage, the ADM7150 is able
to achieve 1.7 nV/√Hz output typical from 10 kHz to 1 MHz.
Because the error amplifier is always in unity gain, the output
noise is independent of the output voltage.
To maintain very high PSRR over a wide frequency range, the
ADM7150 architecture uses an internal active ripple filter. This
stage isolates the low output noise LDO from noise on VIN.
The result is that the PSRR of the ADM7150 is significantly
higher over a wider frequency range than any single stage LDO.
The ADM7150 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is high, VOUT
turns on, and when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.
VREG
VIN
REF_SENSE
REF
OUT
BYP
GND
EN
18V 6V
6V
6V
6V
6V 6V
6V
6V
18V
18V
11043-052
Figure 52. Simplified ESD Protection Block Diagram
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 52).
Rev. 0 | Page 15 of 24
ADM7150 Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADM7150 is designed for operation with ceramic capacitors
but functions with most commonly used capacitors as long as
care is taken with regard to the effective series resistance (ESR)
value. The ESR of the output capacitor affects the stability of the
LDO control loop. A minimum of 10 µF capacitance with an
ESR of 0.2or less is recommended to ensure the stability of the
ADM7150. Output capacitance also affects transient response to
changes in load current. Using a larger value of output capacitance
improves the transient response of the ADM7150 to large changes
in load current. Figure 53 shows the transient responses for an
output capacitance value of 10 µF.
CH1 500mA Ω
BW
CH2 10mV
BW
M4µs A CH1 200mA
T 11.0%
1
2
T
11043-053
Figure 53. Output Transient Response, VOUT = 5 V, COUT = 10 µF,
CH1 = Load Current, CH2 = VOUT
Input and VREG Capacitor
Connecting a 10 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered.
To maintain the best possible stability and PSRR performance,
connect a 10 µF capacitor from VREG to GND. When more
than 10 µF of output capacitance is required, increase the input
and VREG capacitors to match it.
REF Capacitor
The REF capacitor is necessary to stabilize the reference amplifier.
Connect at least a 1 µF capacitor between REF and GND.
BYP Capacitor
The BYP capacitor is necessary to filter the reference buffer. A
1 µF capacitor is typically connected between BYP and GND.
Capacitors as small as 0.1 µF can be used; however, the output
noise voltage of the LDO increases as a result.
In addition, the BYP capacitor value can be increased to reduce
the noise below 1 kHz at the expense of increasing the start-up
time of the LDO. Very large values of CBYP significantly reduce
the noise below 10 Hz. Tantalum capacitors are recommended for
capacitors larger than approximately 33 µF. A 1 μF ceramic
capacitor in parallel with the larger tantalum capacitor is required
to retain good noise performance at higher frequencies. Solid
tantalum capacitors are less prone to microphonic noise issues.
11043-054
NOISE SPECTRAL DENSITY (nV/Hz)
FREQUENCY (Hz)
1M0.1 110 100 1k 10k 100k
1
100k
100
1k
10k
10
C
BYP
= 1µF
C
BYP
= 4.7µF
C
BYP
= 10µF
C
BYP
= 22µF
C
BYP
= 47µF
C
BYP
= 100µF
C
BYP
= 470µF
C
BYP
= 1mF
Figure 54. Noise Spectral Density vs. Frequency, CBYP = 1 µF to 1 mF
11043-055
NOISE SPECTRAL DENSITY (nV/Hz)
C
BYP
(µF)
1000110 100
1
10k
100
1k
10
1Hz
10Hz
100Hz
400Hz
3Hz
30Hz
300Hz
1kHz
Figure 55. Noise Spectral Density vs. Capacitance (CBYP) for
Different Frequencies
Rev. 0 | Page 16 of 24
Data Sheet ADM7150
Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADM7150 as long as they meet the minimum capacitance
and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with different
behavior over temperature and applied voltage. Capacitors must
have a dielectric adequate to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V
are recommended. However, Y5V and Z5U dielectrics are
not recommended due to their poor temperature and dc bias
characteristics.
Figure 56 depicts the capacitance vs. dc bias voltage of a 1206,
10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is 15% over the 40°C to +85°C temperature range
and is not a function of package or voltage rating.
11043-056
CAPACITANCE (µF)
DC BIAS VOLTAGE (V)
1004 8
2 6
0
12
10
8
6
4
2
Figure 56. Capacitance vs. DC Bias Voltage
Use Equation 1 to determine the worst-case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and CBIAS is 9.72 µF at 5 V, as shown in Figure 56.
Substituting these values in Equation 1 yields
CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADM7150, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
ENABLE (EN) AND UNDERVOLTAGE LOCKOUT
(UVLO)
The ADM7150 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 57,
when a rising voltage on EN crosses the upper threshold, VOUT
turns on. When a falling voltage on EN crosses the lower threshold,
VOUT turns off. The hysteresis varies as a function of the input
voltage. For example, the EN hysteresis is approximately 200 mV
with an input voltage of 4.5 V.
11043-057
V
OUT
(V)
V
EN
(V)
1.6
1.51.0 1.2 1.41.1 1.3
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VOUT_EN_RISE
VOUT_EN_FALL
Figure 57. Typical VOUT Response to EN Pin Operation, VOUT = 3.3 V, VIN = 5 V
11043-058
EN RISE THRESHOLD (V)
V
IN
(V)
16
+125°C
+25°C
–40°C
14121086
1.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
Figure 58. Typical EN Rise Threshold vs. Input Voltage (VIN) for Various
Temperatures
Rev. 0 | Page 17 of 24
ADM7150 Data Sheet
11043-059
EN FALL THRESHOLD (V)
V
IN
(V)
16
+125°C
+25°C
–40°C
14121086
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Figure 59. Typical EN Fall Threshold vs. Input Voltage (VIN) for Various
Temperatures
The ADM7150 also incorporates an internal undervoltage
lockout circuit to disable the output voltage when the input
voltage is less than the minimum input voltage rating of the
regulator. The upper and lower thresholds are internally fixed
with about 300 mV of hysteresis.
11043-060
V
OUT
(V)
V
IN
(V)
4.54.44.0 4.2 4.34.1
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VOUT_VIN_RISE
VOUT_VIN_FALL
Figure 60. Typical UVLO Hysteresis, VOUT = 3.3 V
Figure 60 shows the typical hysteresis of the UVLO function.
This hysteresis prevents on/off oscillations that can occur due to
noise on the input voltage as it passes through the threshold
points.
START-UP TIME
The ADM7150 uses an internal soft start to limit the inrush
current when the output is enabled. The start-up time for a 5 V
output is approximately 3 ms from the time the EN active threshold
is crossed to when the output reaches 90% of its final value.
The rise time of the output voltage (10% to 90%) is approximately
0.0012 × CBYP seconds
where CBYP is in microfarads.
11043-061
V
OUT
(V)
TIME (Seconds)
0.0200.016
00.008 0.0120.004 0.0180.0140.006 0.010
0.002
0
6
5
4
3
2
1
ENABLE
C
BYP
= 1µF
C
BYP
= 4.7µF
C
BYP
= 10µF
Figure 61. Typical Start-Up Behavior with CBYP = 1 µF to 10 µF
11043-062
V
OUT
(V)
TIME (Seconds)
0.200.16
00.08 0.120.04 0.180.140.06 0.100.02
0
6
5
4
3
2
1ENABLE
C
BYP
= 10µF
C
BYP
= 47µF
C
BYP
= 330µF
Figure 62. Typical Start-Up Behavior with CBYP = 10 µF to 330 µF
REF, BYP, AND, VREG PINS
REF, BYP, and VREG are internally generated voltages that
require external bypass capacitors for proper operation. Do not,
under any circumstances, connect any loads to these pins because
doing so compromises the noise and PSRR performance of the
ADM7150. Using larger values of CBYP, CREF, and CREG is acceptable
but can increase the start-up time as described in the Start-Up
Time section.
Rev. 0 | Page 18 of 24
Data Sheet ADM7150
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADM7150 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADM7150 is designed to current-limit when the
output load reaches 1.2 A (typical). When the output load
exceeds 1.2 A, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the
junction temperature to a maximum of 155°C (typical). Under
extreme conditions (that is, high ambient temperature and/or
high power dissipation) when the junction temperature starts to
rise above 155°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
140°C, the output is turned on again, and output current is
restored to its operating value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADM7150 current limits, so that only 1.2 A is
conducted into the short. If self heating of the junction is great
enough to cause its temperature to rise above 155°C, thermal
shutdown activates, turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 140°C, the output turns on and conducts 1.2 A into
the short, again causing the junction temperature to rise above
155°C. This thermal oscillation between 140°C and 155°C
causes a current oscillation between 1.2 A and 0 mA that
continues as long as the short remains at the output.
Current-limit and thermal limit protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperature does not exceed 150°C.
THERMAL CONSIDERATIONS
In applications with low input to output voltage differential, the
ADM7150 does not dissipate much heat. However, in applications
with high ambient temperature and/or high input voltage, the
heat dissipated in the package may become large enough that it
causes the junction temperature of the die to exceed the maximum
junction temperature of 150°C.
When the junction temperature exceeds 155°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature decreases below 140°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADM7150 must not exceed 150°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances
between the junction and ambient air (θJA). The θJA number is
dependent on the package assembly compounds that are used
and the amount of copper used to solder the package GND pin
and exposed pad to the PCB.
Table 6 shows typical θJA values of the 8-lead SOIC and 8-lead
LFCSP packages for various PCB copper sizes.
Table 7 shows the typical ΨJB values of the 8-lead SOIC and
8-lead LFCSP.
Table 6. Typical θJA Values
θJA C/W)
Copper Size (mm2) 8-Lead LFCSP 8-Lead SOIC
251 165.1 165
100 125.8 126.4
500 68.1 69.8
1000 56.4 57.8
6400
42.1
43.6
1 Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
Package ΨJB (°C/W)
8-Lead LFCSP 15.1
8-Lead SOIC 17.9
The junction temperature of the ADM7150 is calculated from
the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN VOUT) × ILOAD] + (VIN × IGND) (3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation simplifies
to the following:
TJ = TA + {[(VIN VOUT) × ILOAD] × θJA} (4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
that the junction temperature does not rise above 150°C.
The heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins and
exposed pad of the ADM7150. Adding thermal planes under
the package also improves thermal performance. However, as
listed in Table 6, a point of diminishing returns is eventually
reached, beyond which an increase in the copper area does not
yield significant reduction in the junction to ambient thermal
resistance.
Rev. 0 | Page 19 of 24
ADM7150 Data Sheet
Figure 63 to Figure 68 show junction temperature calculations for
different ambient temperatures, power dissipation, and areas of
PCB copper.
11043-063
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
6400mm
2
500mm
2
25mm
2
T
J
MAX
25
35
45
55
65
75
85
95
105
115
125
135
145
155
00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Figure 63. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 25°C
11043-064
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
1.8 2.0 2.2 2.41.61.41.21.00.80.60.40.20
50
60
70
80
90
100
110
120
140
160
130
150
6400mm
2
500mm
2
25mm
2
T
J
MAX
Figure 64. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 50°C
11043-065
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
1.50.8 0.9 1.0 1.1 1.2 1.3 1.40.70.60.50.40.30.20.10
65
75
85
95
105
115
125
135
155
145
6400mm
2
500mm
2
25mm
2
T
J
MAX
Figure 65. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP, TA = 85°C
11043-066
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
2.82.6
2.4 3.02.2
2.01.8
1.61.4
1.2
1.00.8
0.6
0.40.2
0
25
155
145
125
102
85
65
45
135
115
95
75
55
35
6400mm
2
500mm
2
25mm
2
T
J
MAX
Figure 66. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
11043-067
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
1.8 2.0 2.2 2.41.61.41.21.00.80.60.40.20
50
60
70
80
90
100
110
120
130
160
150
140
6400mm
2
500mm
2
25mm
2
T
J
MAX
Figure 67. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
11043-068
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
2.01.6 1.81.41.21.00.80.60.40.20
65
75
85
95
105
115
125
135
155
145
6400mm
2
500mm
2
25mm
2
T
J
MAX
Figure 68. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Rev. 0 | Page 20 of 24
Data Sheet ADM7150
Thermal Characterization Parameter JB)
When board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 69 and Figure 70). Maximum
junction temperature (TJ) is calculated from the board temperature
(TB) and power dissipation (PD) using the following formula:
TJ = TB + (PD × ΨJB) (5)
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP
package and 17.9°C/W for the 8-lead SOIC package.
11043-069
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
9.0
8.58.0
7.06.0 7.56.55.55.0
4.54.03.53.0
2.52.0
1.51.0
0.5
0
0
160
140
120
100
80
60
40
20
T
B
= 25°C
T
B
= 50°C
T
B
= 65°C
T
B
= 85°C
T
J
MAX
Figure 69. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP
11043-070
JUNCTION TEMPERATURE (°C)
TOTAL POWER DISSIPATION (W)
5.5 7.57.06.56.05.04.54.03.53.02.52.01.51.00.50
0
160
140
120
100
80
60
40
20
T
B
= 25°C
T
B
= 50°C
T
B
= 65°C
T
B
= 85°C
T
J
MAX
Figure 70. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Place the input capacitor as close as possible to the VIN and GND
pins. Place the output capacitor as close as possible to the VOUT
and GND pins. Place the bypass capacitors for VREG, VREF, and
VBYP close to the respective pins and GND. Use of an 0805,
0603, or 0402 size capacitor achieves the smallest possible
footprint solution on boards where area is limited.
11043-071
Figure 71. Example 8-Lead LFCSP PCB Layout
11043-072
Figure 72. Example 8-Lead SOIC PCB Layout
Rev. 0 | Page 21 of 24
ADM7150 Data Sheet
OUTLINE DIMENSIONS
2.44
2.34
2.24
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
11-28-2012-C
0.20 MIN
Figure 73. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MS-012-AA
06-03-2011-B
1.27
0.40
1.75
1.35
2.41
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 MAX
0.05 NOM
3.81 REF
0.25
0.17
0.50
0.25
45°
COPLANARITY
0.10
1.04 REF
8
14
5
1.27 BSC
SEATING
PLANE
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
BOTTOM VIEW
TOP VIEW
0.51
0.31
1.65
1.25
3.098
Figure 74. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Output Voltage Package Description Package Option Branding
ADM7150ACPZ-1.8-R2 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-11 LP3
ADM7150ACPZ-3.3-R2 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-11 LNA
ADM7150ACPZ-4.5-R2 −40°C to +125°C 4.5 8-Lead LFCSP_WD CP-8-11 LNL
ADM7150ACPZ-4.8-R2 −40°C to +125°C 4.8 8-Lead LFCSP_WD CP-8-11 LNM
ADM7150ACPZ-5.0-R2 −40°C to +125°C 5.0 8-Lead LFCSP_WD CP-8-11 LNB
Rev. 0 | Page 22 of 24
Data Sheet ADM7150
Model1 Temperature Range Output Voltage Package Description Package Option Branding
ADM7150ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-11 LP3
ADM7150ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-11 LNA
ADM7150ACPZ-4.5-R7 −40°C to +125°C 4.5 8-Lead LFCSP_WD CP-8-11 LNL
ADM7150ACPZ-4.8-R7 −40°C to +125°C 4.8 8-Lead LFCSP_WD CP-8-11 LNM
ADM7150ACPZ-5.0-R7
−40°C to +125°C
5.0
8-Lead LFCSP_WD
CP-8-11
LNB
ADM7150ARDZ-1.8 40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2
ADM7150ARDZ-2.8 40°C to +125°C 2.8 8-Lead SOIC_N_EP RD-8-2
ADM7150ARDZ-3.0 40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-2
ADM7150ARDZ-3.3 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2
ADM7150ARDZ-5.0 40°C to +125°C 5.0 8-Lead SOIC_N_EP RD-8-2
ADM7150ARDZ-3.0-R7 40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-2
ADM7150ARDZ-3.3-R7 40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2
ADM7150ARDZ-5.0-R7 40°C to +125°C 5.0 8-Lead SOIC_N_EP RD-8-2
ADM7150CP-EVALZ 5.0 Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADM7150 Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11043-0-9/13(0)
Rev. 0 | Page 24 of 24

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