A3967 Datasheet

Allegro MicroSystems, LLC

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Datasheet

Description
The A3967 is a complete microstepping motor driver with built-
in translator. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive
capability of 30 V and ±750 mA. The A3967 includes a fixed
off-time current regulator that has the ability to operate in slow,
fast, or mixed current-decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3967. By simply inputting one pulse on the STEP input the
motor will take one step (full, half, quarter, or eighth depending
on two logic inputs). There are no phase-sequence tables, high-
frequency control lines, or complex interfaces to program. The
A3967 interface is an ideal fit for applications where a complex
μP is unavailable or over-burdened.
Internal circuit protection includes thermal shutdown with
hysteresis, under-voltage lockout (UVLO) and crossover-
current protection. Special power-up sequencing is not
required.
The A3967 is supplied in a 24-pin SOIC, which is lead (Pb)
free with 100% matte tin leadframe plating. Four pins are
fused internally for enhanced thermal dissipation. The pins
are at ground potential and need no insulation.
26184.24H
Features and Benefits
±750 mA, 30 V output rating
Satlington® sink drivers
Automatic current-decay mode detection/selection
3.0 to 5.5 V logic supply voltage range
Mixed, fast, and slow current-decay modes
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Microstepping Driver with Translator
Package: 24-pin SOIC with internally
fused pins (suffix LB)
Functional Block Diagram
Not to scale
A3967
1918
SENSE
1
V
BB1
V
BB2
OUT
1A
OUT
1B
OUT
2A
OUT
2B
SENSE
2
5
9
20
16
21
17
8
4
TRANSLATOR
LOAD
SUPPLY
Dwg. FP-050-3A
PWM TIMER
PWM TIMER
PWM LATCH
BLANKING
MIXED DECAY
CONTROL LOGIC
UVLO
AND
FAULT
DETECT
DAC
+-
+-
DAC
SENSE
PWM LATCH
BLANKING
MIXED DECAY
3
3
REF
LOGIC
SUPPLY
V
CC
STEP
DIR
MS
1
SLEEP
MS
2
ENABLE
RC
1
RESET
PFD
RC
2
REF.
SUPPLY
V
PF
÷8
14
1
23
10
11
22
12
13
3
15
24
2
76
Microstepping Driver with Translator
A3967
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Packing Package
A3967SLBTR-T 24-pin SOIC with internally fused pins 1000 per reel
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 30 V
Logic Supply Voltage VCC 7.0 V
Logic Input Voltage Range VIN
tw > 30 ns –0.3 to 7.0 V
tw < 30 ns –1 to 7.0 V
Sense Voltage VSENSE 0.68 V
Reference Voltage VREF VCC mA
Output Current IOUT
Output current rating may be limited by duty cycle, am-
bient temperature, and heat sinking. Under any set of
conditions, do not exceed the specifi ed current rating
or a junction temperature of 150°C.
Continuous ±750 mA
Peak ±850 mA
Package Power Dissipation PDSee graph ––
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction Temperature TJ(max)
Fault conditions that produce excessive junction temperature will activate
the device’s thermal shutdown circuitry. These conditions can be toler-
ated but should be avoided.
150 ºC
Storage Temperature Tstg –55 to 150 ºC
50 75 100 125 150
5
1
0
ALLOWABLE PACKAGE POWER DISSIPATION (W)
TEMPERATURE IN
o
C
4
3
2
25
R = 6.0
o
C/W
Q
JT
Q
R = 50°C/W
JA
Q
R = 35°C/W
JA
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance, Junction
to Ambient RθJA
2-layer PCB, 1.3 in.
2 2-oz. exposed copper 50 ºC/W
4-layer PCB, based on JEDEC standard 35 ºC/W
*Additional thermal information available on Allegro website.
Microstepping Driver with Translator
A3967
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 3.0 V to 5.5V (unless otherwise
noted)
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range VBB Operating 4.75 30 V
During sleep mode 0 30 V
Output Leakage Current ICEX V
OUT = VBB<1.0 20 μA
V
OUT = 0 V <-1.0 -20 μA
Output Saturation Voltage VCE(sat)
Source driver, IOUT = -750 mA
1.9 2.1 V
Source driver, IOUT = -400 mA
1.7 2.0 V
Sink driver, IOUT = 750 mA 0.65 1.3 V
Sink driver, IOUT = 400 mA 0.21 0.5 V
Clamp Diode Forward Voltage VF I
F = 750 mA 1.4 1.6 V
I
F = 400 mA 1.1 1.4 V
Motor Supply Current IBB Outputs enabled 5.0 mA
RESET high
– – 200 μA
Sleep mode 20 μA
Control Logic
Logic Supply Voltage Range VCC Operating 3.0 5.0 5.5 V
Logic Input Voltage VIN(1) 0.7VCC V
V
IN(0) 0.3VCC V
Logic Input Current IIN(1) V
IN = 0.7VCC -20 <1.0 20 μA
I
IN(0) V
IN = 0.3VCC -20 <1.0 20 μA
Maximum STEP Frequency fSTEP 500* kHz
Blank Time tBLANK R
t = 56 kΩ, Ct = 680 pF 700 950 1200 ns
Fixed Off Time toff R
t = 56 kΩ, Ct = 680 pF 30 38 46 μs
continued next page …
Table 1. Microstep Resolution Truth Table
MS1 MS2 Resolution
L L Full step (2 phase)
H L Half step
L H Quarter step
H H Eighth step
Microstepping Driver with Translator
A3967
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VBB = 30 V, VCC = 3.0 V to 5.5V (unless
otherwise noted)
Characteristic Symbol Test Conditions
Limits
Min. Typ. Max. Units
Control Logic (cont’d)
Mixed Decay Trip Point PFDH 0.6VCC –V
PFDL – 0.21VCC –V
Ref. Input Voltage Range VREF Operating 1.0 – VCC V
Reference Input Impedance ZREF 120 160 200 kΩ
Gain (Gm) Error
(note 3)
EGVREF = 2 V, Phase Current = 38.37% † ±10 %
VREF = 2 V, Phase Current = 70.71% † ±5.0 %
VREF = 2 V, Phase Current = 100.00% † ±5.0 %
Thermal Shutdown Temp. TJ 165 – °C
Thermal Shutdown Hysteresis TJ–15°C
UVLO Enable Threshold VUVLO Increasing VCC 2.45 2.7 2.95 V
UVLO Hysteresis VUVLO 0.05 0.10 V
Logic Supply Current ICC Outputs enabled 50 65 mA
Outputs off 9.0 mA
Sleep mode 20 μA
* Operation at a step frequency greater than the specifi ed minimum value is possible but not warranteed.
† 8 microstep/step operation.
NOTES: 1. Typical Data is for design information only.
2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.
3. EG = ([VREF/8] – VSENSE)/(VREF/8)
Microstepping Driver with Translator
A3967
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Device Operation. The A3967 is a complete microstep-
ping motor driver with built in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, quarter- and eighth-step
modes. The current in each of the two output full bridges
is regulated with fi xed off time pulse-width modulated
(PWM) control circuitry. The full-bridge current at each
step is set by the value of an external current sense resis-
tor (RS), a reference voltage (VREF), and the DACs output
voltage controlled by the output of the translator.
At power up, or reset, the translator sets the DACs and
phase current polarity to initial home state (see fi gures for
home-state conditions), and sets the current regulator for
both phases to mixed-decay mode. When a step command
signal occurs on the STEP input the translator automati-
cally sequences the DACs to the next level (see table 2 for
the current level sequence and current polarity). The mic-
rostep resolution is set by inputs MS1 and MS2 as shown in
table 1. If the new DAC output level is lower than the pre-
vious level the decay mode for that full bridge will be set
by the PFD input (fast, slow or mixed decay). If the new
DAC level is higher or equal to the previous level then the
decay mode for that Full bridge will be slow decay. This
automatic current-decay selection will improve microstep-
ping performance by reducing the distortion of the current
waveform due to the motor BEMF.
Reset Input (RESET). The RESET input (active low)
sets the translator to a predefi ned home state (see fi gures
for home state conditions) and turns off all of the outputs.
STEP inputs are ignored until the RESET input goes high.
Step Input (STEP). A low-to-high transition on the
STEP input sequences the translator and advances the
motor one increment. The translator controls the input to
the DACs and the direction of current fl ow in each wind-
ing. The size of the increment is determined by the state of
inputs MS1 and MS2 (see table 1).
Microstep Select (MS1 and MS2). Input terminals
MS1 and MS2 select the microstepping format per
table 1. Changes to these inputs do not take effect until the
STEP command (see fi gure).
Direction Input (DIR). The state of the DIRECTION
input will determine the direction of rotation of the motor.
Internal PWM Current Control. Each full bridge is
controlled by a fi xed off-time PWM current-control cir-
cuit that limits the load current to a desired value (ITRIP).
Initially, a diagonal pair of source and sink outputs are
enabled and current fl ows through the motor winding and
RS. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense compara-
tor resets the PWM latch, which turns off the source driver
(slow-decay mode) or the sink and source drivers (fast- or
mixed-decay modes).
The maximum value of current limiting is set by the
selection of RS and the voltage at the VREF input with a
transconductance function approximated by:
ITRIPmax = VREF/8RS
The DAC output reduces the VREF output to the cur-
rent-sense comparator in precise steps (see table 2 for %
ITRIPmax at each step).
I
TRIP = (% ITRIPmax/100) x ITRIPmax
Fixed Off-Time. The internal PWM current-control
circuitry uses a one shot to control the time the driver(s)
remain(s) off. The one shot off-time, toff, is determined by
the selection of an external resistor (RT) and capacitor (CT)
connected from the RC timing terminal to ground. The off
time, over a range of values of CT = 470 pF to 1500 pF and
RT = 12 kΩ to 100 kΩ is approximated by:
toff = RTCT
Functional Description
Microstepping Driver with Translator
A3967
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
RC Blanking. In addition to the fi xed off-time of the
PWM control circuit, the CT component sets the compara-
tor blanking time. This function blanks the output of the
current-sense comparator when the outputs are switched by
the internal current-control circuitry. The comparator out-
put is blanked to prevent false overcurrent detection due
to reverse recovery currents of the clamp diodes, and/or
switching transients related to the capacitance of the load.
The blank time tBLANK can be approximated by:
tBLANK = 1400CT
Enable Input (ENABLE). This active-low input enables
all of the outputs. When logic high the outputs are dis-
abled. Inputs to the translator (STEP, DIRECTION, MS1,
MS2) are all active independent of the ENABLE input
state.
Shutdown. In the event of a fault (excessive junction
temperature) the outputs of the device are disabled until
the fault condition is removed. At power up, and in the
event of low VCC, the under-voltage lockout (UVLO)
circuit disables the drivers and resets the translator to the
home state.
Sleep Mode (SLEEP). An active-low control input used
to minimize power consumption when not in use. This dis-
ables much of the internal circuitry including the outputs.
A logic high allows normal operation and startup of the
device in the home position.
Percent Fast Decay Input (PFD). When a STEP input
signal commands a lower output current from the previous
step, it switches the output current decay to either slow-,
fast-, or mixed-decay depending on the voltage level at the
PFD input. If the voltage at the PFD input is greater than
0.6VCC then slow-decay mode is selected. If the voltage on
the PFD input is less than 0.21VCC then fast-decay mode is
selected. Mixed decay is between these two levels.
Mixed Decay Operation. If the voltage on the PFD in-
put is between 0.6VCC and 0.21VCC, the bridge will oper-
ate in mixed-decay mode depending on the step sequence
(see fi gures). As the trip point is reached, the device will
go into fast-decay mode until the voltage on the RC termi-
nal decays to the voltage applied to the PFD terminal. The
time that the device operates in fast decay is approximated
by:
tFD = RTCTIn (0.6VCC/VPFD)
After this fast decay portion, tFD, the device will
switch to slow-decay mode for the remainder of the fi xed
off-time period.
Functional Description (cont’d)
Typical output saturation voltages show-
ing Satlington sink-driver operation.
200
Dwg. GP-064-1A
007004
300
OUTPUT CURRENT IN MILLIAMPERES
2.0
OUTPUT SATURATION VOLTAGE IN VOLTS
1.0
0
0.5
1.5
2.5
500 600
T
A
= +25°C
SOURCE DRIVER
SINK DRIVER
Microstepping Driver with Translator
A3967
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Timing Requirements
(TA = +25°C, VCC = 5 V, Logic Levels are VCC and Ground)
A. Minimum Command Active Time
Before Step Pulse (Data Set-Up Time) ..... 200 ns
B. Minimum Command Active Time
After Step Pulse (Data Hold Time) ........... 200 ns
C. Minimum STEP Pulse Width ...................... 1.0 μs
D. Minimum STEP Low Time ......................... 1.0 μs
E. Maximum Wake-Up Time ......................... 1.0 ms
AB
C D
50%
STEP
MS1/MS2/
DIR/RESET
Dwg. WP-042
SLEEP
E
Microstepping Driver with Translator
A3967
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Layout. The printed wiring board should use a heavy
ground plane.
For optimum electrical and thermal performance, the
driver should be soldered directly onto the board.
The load supply terminal, VBB, should be decoupled
with an electrolytic capacitor (>47 μF is recommended)
placed as close to the device as possible.
To avoid problems due to capacitive coupling of the
high dv/dt switching transients, route the bridge-output
traces away from the sensitive logic-input traces. Always
drive the logic inputs with a low source impedance to
increase noise immunity.
Grounding. A star ground system located close to the
driver is recommended.
The 24-lead SOIC has the analog ground and the
power ground internally bonded to the power tabs of the
package (leads 6, 7, 18, and 19).
Applications Information
Current Sensing. To minimize inaccuracies caused by
ground-trace IR drops in sensing the output current level,
the current-sense resistor (RS) should have an indepen-
dent ground return to the star ground of the device. This
path should be as short as possible. For low-value sense
resistors the IR drops in the printed wiring board sense
resistors traces can be signifi cant and should be taken into
account. The use of sockets should be avoided as they can
introduce variation in RS due to their contact resistance.
Allegro MicroSystems recommends a value of RS
given by
RS = 0.5/ITRIPmax
Thermal protection. Circuitry turns off all drivers when
the junction temperature reaches 165°C, typically. It is
intended only to protect the device from failures due to
excessive junction temperatures and should not imply that
output short circuits are permitted. Thermal shutdown has
a hysteresis of approximately 15°C.
Microstepping Driver with Translator
A3967
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Full Step Half Step ¼ Step ǩ Step
Phase 1 Current
(%Itripmax)
(%)
Phase 2 Current
(%Itripmax)
(%)
Step Angle
(º)
1 1 1 100.00 0.00 0.0
2 98.08 19.51 11.3
2 3 92.39 38.27 22.5
4 83.15 55.56 33.8
1 2 3 5 70.71 70.71 45.0
6 55.56 83.15 56.3
4 7 38.27 92.39 67.5
8 19.51 98.08 78.8
3 5 9 0.00 100.00 90.0
10 –19.51 98.08 101.3
6 11 –38.27 92.39 112.5
12 –55.56 83.15 123.8
2 4 7 13 –70.71 70.71 135.0
14 –83.15 55.56 146.3
8 15 –92.39 38.27 157.5
16 –98.08 19.51 168.8
5 9 17 –100.00 0.00 180.0
18 –98.08 –19.51 191.3
10 19 –92.39 –38.27 202.5
20 –83.15 –55.56 213.8
3 6 11 21 –70.71 –70.71 225.0
22 –55.56 –83.15 236.3
12 23 –38.27 –92.39 247.5
24 –19.51 –98.08 258.8
7 13 25 0.00 –100.00 270.0
26 19.51 –98.08 281.3
14 27 38.27 –92.39 292.5
28 55.56 –83.15 303.8
4 8 15 29 70.71 –70.71 315.0
30 83.15 –55.56 326.3
16 31 92.39 –38.27 337.5
32 98.08 –19.51 348.8
Table 2. Step Sequencing
Home State = 45º Step Angle, DIR = H
Microstepping Driver with Translator
A3967
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Dwg. WK-004-19
PHASE 1
CURRENT
PHASE 2
CURRENT
STEP
INPUT
SLOW
DECAY
70.7%
–70.7%
70.7%
–70.7%
SLOW
DECAY
Full Step Operation
MS1 = MS2 = L, DIR = H
The vector addition of the output currents at any step is
100%.
Microstepping Driver with Translator
A3967
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Dwg. WK-004-18
PHASE 1
CURRENT
PHASE 2
CURRENT
STEP
INPUT
SLOW
DECAY
MIXED
DECAY
SLOW
DECAY
MIXED
DECAY
100%
–100%
100%
–100%
SLOW
DECAY
MIXED
DECAY
SLOW
DECAY
MIXED
DECAY
SLOW
DECAY
MIXED
DECAY
SLOW
DECAY
MIXED
DECAY
SLOW
DECAY
MIXED
DECAY
SLOW
DECAY
MIXED
DECAY
70.7%
–70.7%
70.7%
70.7%
Half Step Operation
MS1 = H, MS2 = L, DIR = H
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the volt-
age at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the volt-
age on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay
is between these two levels.
Microstepping Driver with Translator
A3967
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Quarter Step Operation
MS1 = L, MS2 = H, DIR = H
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the
voltage at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the
voltage on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed
decay is between these two levels.
Dwg. WK-004-17
PHASE 1
CURRENT
PHASE 2
CURRENT
STEP
INPUT
SLOW
DECAY MIXED
DECAY
SLOW
DECAY MIXED
DECAY
100%
–100%
100%
–100%
SLOW
DECAY MIXED
DECAY SLOW
DECAY
MIXED
DECAY
38.3%
70.7%
–70.7%
70.7%
–70.7%
–38.3%
38.3%
–38.3%
Microstepping Driver with Translator
A3967
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8 Microstep/Step Operation
MS1 = MS2 = H, DIR = H
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the volt-
age at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the volt-
age on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay
is between these two levels.
Dwg. WK-004-16
PHASE 2
CURRENT
100%
–100%
SLOW
DECAY MIXED
DECAY SLOW
DECAY
MIXED
DECAY
PHASE 1
CURRENT
STEP
INPUT
SLOW
DECAY MIXED
DECAY
SLOW
DECAY MIXED
DECAY
100%
–100%
70.7%
38.3%
–70.7%
–38.3%
70.7%
38.3%
–70.7%
–38.3%
Microstepping Driver with Translator
A3967
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List
Terminal Terminal
Name Terminal Description Number
REF Gm reference input 1
RC2 Analog input for fi xed offtime – bridge 2 2
SLEEP Logic input 3
OUT2B H bridge 2 output B 4
LOAD SUPPLY2 VBB2, the load supply for bridge 2 5
GND Analog and power ground 6, 7
SENSE2 Sense resistor for bridge 2 8
OUT2A H bridge 2 output A 9
STEP Logic input 10
DIR Logic Input 11
MS1 Logic input 12
MS2 Logic input 13
LOGIC SUPPLY VCC, the logic supply voltage 14
ENABLE Logic input 15
OUT1A H bridge 1 output A 16
SENSE1 Sense resistor for bridge 1 17
GND Analog and power ground 18, 19
LOAD SUPPLY1 VBB1, the load supply for bridge 1 20
OUT1B H bridge 1 output B 21
RESET Logic input 22
RC1 Analog Input for fi xed offtime – bridge 1 23
PFD Mixed decay setting 24
LOAD
SUPPLY
1
ENABLE
OUT
1A
STEP
OUT
1B
RESET
SENSE
1
DIR
OUT
2A
PFD
RC
1
÷8
LOGIC
SUPPLY
SLEEP
GND
LOAD
SUPPLY
2
REF
RC
2
OUT
2B
MS
2
MS
1
SENSE
2
PWM
TIMER
TRANSLATOR
& CONTROL
LOGIC
V
BB2
V
BB1
V
CC
Dwg. PP-075-2
23
17
8
1
2
3
4
5
6
7
9
12
16
15
14
13
24
22
21
20
19
18
11
10
GND
GND
GND
Pin-out Diagram
Microstepping Driver with Translator
A3967
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, go to our website at:
www.allegromicro.com
Copyright ©2002-2013, Allegro MicroSystems, LLC
The products described here are manufactured under one or more U.S. patents, including U. S. Patent No. 5,684,427, or U.S. patents pending
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
1.27
0.25
BReference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
B
0.20 ±0.10
0.41 ±0.10
2.20
0.65
9.60
1.27
21
24
A
15.40±0.20
2.65 MAX
10.30±0.33
7.50±0.10
C
SEATING
PLANE
C0.10
24X
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
E t d l d fi ti t li di ti ithi li it h
ATerminal #1 mark area
GAUGE PLANE
SEATING PLANE PCB Layout Reference View
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
21
24
Package LB 24-Pin SOIC

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