Artificial Intelligence at the Edge

About the Innovate FPGA Contest

Artificial Intelligence at the Edge

The Terasic Innovate Asia, Nordic, and North America contests have inspired thousands of aspiring engineers to design, create, and innovate. This year, these regional events have been combined into a single global contest – Innovate FPGA – where teams from around the world compete to take Artificial Intelligence to the Edge with Terasic and Intel. The competition is open to everyone including students, professors, makers, and industry. Teams can showcase their creativity and innovation with actual results and real-world designs.

Timeline for the InnovateFPGA Contest
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Competition Platforms

DE10-Nano Development Kit

DE10-Nano from Terasic

The Terasic DE10-Nano Development Kit, based on an Intel® Cyclone® FPGA, provides a reconfigurable hardware design platform for makers, educators, and IoT system developers. The kit contains a board that features two general purpose input/output (GPIO) expansion headers and an Arduino* header so you can connect to a wide range of sensors.

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DE10-Nano from Terasic


FPGA Device

  • Intel Cyclone® V SE 5CSEBA6U23I7 device (110 K LEs)
  • Serial configuration device - EPCS128
  • USB-Blaster II onboard for programming; JTAG mode
  • HDMI TX, compatible with DVI 1.0 and HDCP v1.4
  • Two push-buttons
  • Four slide switches
  • Eight green user LEDs
  • Three 50 MHz clock sources from the clock generator
  • Two 40-pin expansion headers
  • One Arduino expansion header (Uno R3 compatibility), can be connected with Arduino shields
  • One 10-pin Analog input expansion header (shared with Arduino Analog input)
  • A/D converter, 4-pin SPI with FPGA

HPS (Hard Processor System)

  • 800 MHz dual-core ARM Cortex-A9 processor
  • 1 GB DDR3 SDRAM (32-bit data bus)
  • 1 Gigabit Ethernet PHY with RJ45 connector
  • USB OTG port, USB micro-AB connector
  • Micro SD card socket
  • Accelerometer (I2C interface + interrupt)
  • UART to USB, USB Mini-B connector
  • Warm reset button and cold reset button
  • One user button and one user LED
  • LTC 2x7 expansion header

OpenVINO Starter Kit

DE10-Nano from Terasic

OpenVINO Starter Kit is a PCIe based FPGA card equipped with the largest Cyclone V GX device at 301K LE and supports PCIe Gen 1 x4. The board comes with 1GB DDR3, 64MB SDRAM, UART-to-USB interface, and extension headers such as GPIO and Arduino, making the kit a re-configurable platform with competitive computing performance and low power consumption.

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OpenVINO Starter Kit


FPGA Device

  • Cyclone V
    • 301K Programmable Logic Elements
    • 13,917 Kbits embedded memory
    • Eight Fractional PLLs
    • Two Hard Memory Controllers
    • Nine 3.125G Transceivers

Configuration and Debug

  • Quad Serial Configuration device-EPCQ256
  • On-Board USB Blaster II (Mini-B USB connector)

Memory Device

  • 64MB (32M x16) SDRAM
  • 1GB (2 x256M x16) DDR3 SDRAM


  • UART to USB(Mini-B USB connector)
  • PCIe Gen1x 4

Expansion I/O

  • 2 x40 GPIO Header
    • 36 General GPIO Pins
    • Support 8 pairs LVDS TX and 8 pairs LVDS RX
    • Diode protection circuit
    • Configurable I/O standards: 1.5/1.8/2.5/3.3V
  • One Arduino Uno Revision 3 Expansion Hearder
    • Analog ADC
      • SPI Interface
      • 500Ksps Sampling Rate
      • Eight Channels
      • 12-Bit Resolution
      • Analog Input Range:0 ~ 4.096 V
      • Resolution: 12-bit
    • Digital IO
      • Diode protection circuit
  • SMA IN/OUT 3.3V single port

Switches, Buttons, LED, and 7-Segments

  • 5 User Buttons (4 normal buttons, one CPU_RESET_n)
  • 4 User Switches
  • 4 LEDs
  • 2 7-Segments


  • 12V DC input
  • PCIe 12V Input


  • 5000 Speed Fan

Why a FPGA based SoC?

The Innovate FPGA contest is an opportunity for developers to showcase one or more of the FPGA virtues, and illustrate how FPGAs make processors better. Judges will give extra weight to designs that demonstrate how FPGAs can:

  1. Boost performance
  2. Adapt to changes
  3. Expand I/O
Adapts to

How to demonstrate the FPGA Virtues:

Boost Performance

  • Use the FPGA to perform a task or function faster than it could be performed by the CPU.
  • Use the FPGA to off-load a task or function from the CPU leaving the processor free to perform other work.

Adapt to Changes

  • Use the FPGA to perform a task or function that is expected to change over time due to evolving standards, algorithmic methods, or security threats.
  • Use the FPGA to demonstrate scalability of a design over time which extends or enhances system capabilities.

Expands I/O

DE1-SoC Development Kit from Terasic
  • Use the FPGA to add one or more interface not native to the processor.
  • Use the FPGA to create a custom peripheral set tailored to the application.
LT24 LCD Touch Module   from Terasic LTC2607 Evaluation Board from Linear Technology P0001 from Terasic Color TFT Shield with microSD and Joystick from Adafruit
Click to View All Terasic Daughter Cards

Want to learn more? Explore Intel’s Developer Zone for Set Ups, Projects, Diagrams and Schematics, and More!