MC10, MC100EP195 Datasheet by onsemi

© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 19 1Publication Order Number:
MC10EP195/D
MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and
VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
supply reference to VCF and leave open VEF pin. The 1.5 V reference
voltage to VCF pin can be accomplished by placing a 2.2 kW resistor
between VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range:
VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.6 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic
Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
Inputs
VBB Output Reference Voltage
These are Pb−Free Devices
32
1
LQFP−32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
XXX = 10 or 100
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
MCXXX
EP195
AWLYYWWG
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See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
QFN32
MN SUFFIX
CASE 488AM
32
1MCXXX
EP195
AWLYYWWG
G
1
(Note: Microdot may be in either location)
MC10EP195, MC100EP195
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2
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
VEE
D0
VCC
Q
Q
NC
VCC
VCC
CASCADE
EN
SETMAX
VCC
VEE
LEN
D2
D1
CASCADE
SETMIN
VBB
IN
VEE
D8
VEF
D3
D4
D5
D6
D7
D9
D10
IN
VCF
Figure 1. 32−Lead LQFP Pinout (Top View)
MC10EP195
MC100EP195
32 31 30 29 28 27 26 25
9 10 11 121314 1516
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Figure 2. 32−Lead QFN (Top View)
VBB
IN
D8
VEF
D9
D10
IN
VCF
D2
D1
VEE
D3
D4
D5
D6
D7
VEE
D0
VCC
Q
Q
NC
VCC
VCC
CASCADE
EN
SETMAX
VCC
VEE
LEN
CASCADE
SETMIN
Exposed Pad (EP)
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Table 1. PIN DESCRIPTION
Pin Name I/O Default State Description
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
D[0:9] LVCMOS, LVTTL,
ECL Input Low Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
(Note 1)
3 D[10] LVCMOS, LVTTL,
ECL Input Low Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to VEE. (Note 1)
4 IN ECL Input Low Noninverted Differential Input. Internal 75 kW to VEE.
5 IN ECL Input High Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to
VCC.
6 VBB ECL Reference Voltage Output
7 VEF Reference Voltage for ECL Mode Connection
8 VCF LVCMOS, ECL, OR LVTTL Input Mode Select
9, 24, 28 VEE Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
13, 18, 19, 22 VCC Positive Supply Voltage. All VCC Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
10 LEN ECL Input Low Single−ended D pins LOAD / HOLD input. Internal 75 kW to VEE.
11 SETMIN ECL Input Low Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
12 SETMAX ECL Input Low Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
VEE. (Note 1)
14 CASCADE ECL Output Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50 W to VTT = VCC − 2 V.
15 CASCADE ECL Output Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50 W to VTT = VCC − 2 V.
16 EN ECL Input Low Single−ended Output Enable Pin. Internal 75 kW to VEE.
17 NC No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
21 Q ECL Output Noninverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
20 Q ECL Output Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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Table 2. CONTROL PIN
Pin State Function
EN LOW (Note 3) Input Signal is Propagated to the Output
HIGH Output Holds Logic Low State
LEN LOW (Note 3) Transparent or LOAD mode for real time delay values present on D[0:10].
HIGH LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
SETMIN LOW (Note 3) Output Delay set by D[0:10]
HIGH Set Minimum Output Delay
SETMAX LOW (Note 3) Output Delay set by D[0:10]
HIGH Set Maximum Output Delay
D10 LOW (Note 3) CASCADE Output LOW, CASCADE Output HIGH
HIGH CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
VCF VEF Pin (Note 4) ECL Mode
VCF No Connect LVCMOS Mode
VCF 1.5 V $ 100 mV LVTTL Mode (Note 5)
4. Short VCF (pin 8) and VEF (pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value
is 2.2 kW $5%), between VCF and VEE pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
POWER SUPPLY
CONTROL DATA SELECT INPUTS PINS (D [0:10])
LVCMOS LVTTL LVPECL LVNECL
PECL Mode Operating Range YES YES YES N/A
NECL Mode Operating Range N/A N/A N/A YES
Table 5. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor (R1) 75 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6) Pb−Free Pkg
LQFP−32 Level 2
QFN−32 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 1217 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
4f} \lll—V hllp :Nonsemi .com
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D0D1D2D3D4D5D6D7D8D9
IN
IN 512
GD*
0
1256
GD*
0
1128
GD*
0
164
GD*
0
132
GD*
0
116
GD*
0
18
GD*
0
14
GD*
0
12
GD*
0
11
GD*
0
1
1
GD*
0
11
GD*
0
1
Latch
CASCADE
CASCADE
Q
Q
EN
LEN
SET MIN
SET MAX
10 BIT LATCH
D10
*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE
(MINIMUM FIXED DELAY APPROX. 2.2 ns)
VBB
VCF
VEF
Figure 3. Logic Diagram
VEE
R1R1R1R1R1R1R1R1R1R1
R1
R1
R1
R1
R1
R1
R1
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Table 6. THEORETICAL DELAY VALUES
D(9:0) Value SETMIN SETMAX Programmable Delay*
XXXXXXXXXX H L 0 ps
0000000000 L L 0 ps
0000000001 L L 10 ps
0000000010 L L 20 ps
0000000011 L L 30 ps
0000000100 L L 40 ps
0000000101 L L 50 ps
0000000110 L L 60 ps
0000000111 L L 70 ps
0000001000 L L 80 ps
0000010000 L L 160 ps
0000100000 L L 320 ps
0001000000 L L 640 ps
0010000000 L L 1280 ps
0100000000 L L 2560 ps
1000000000 L L 5120 ps
1111111111 L L 10230 ps
XXXXXXXXXX L H 10240 ps
*Fixed minimum delay not included.
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0.0
1000.0
2000.0
3000.0
4000.0
5000.0
6000.0
7000.0
8000.0
9000.0
10000.0
11000.0
12000.0
13000.0
14000.0
0.0 100.0 200.0 300.0 400.0 500.0 600.0 700.0 800.0 900.0 1000.0
DELAY ( ps)
Decimal Value of Select Inputs (D[9:0])
85°C
−40°C
Figure 4. Measured Delay vs. Select Inputs
25°C
VCC = 0 V
VEE = −3.3 V
Table 7. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Mode Power Supply VEE = 0 V 6 V
VEE Negative Mode Power Supply VCC = 0 V −6 V
VIPositive Mode Input Voltage
Negative Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI VCC
VI VEE
6
−6
V
V
Iout Output Current Continuous
Surge
50
100
mA
mA
IBB VBB Sink/Source ±0.5 mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm LQFP−23
LQFP−23 80
55
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board LQFP−23 12 to 17 °C/W
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W
Tsol Wave Solder Pb−Free <2 to 3 sec @ 260°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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Table 8. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
Symbo
l
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE Negative Power Supply Current 100 145 175 100 150 180 100 150 180 mA
VOH Output HIGH Voltage (Note 8) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
VOL Output LOW Voltage (Note 8) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
VIH Input HIGH Voltage (Single−Ended)
LVPECL
LVCMOS
LVTTL
2090
2000
2000
2415
3300
3300
2155
2000
2000
2480
3300
3300
2215
2000
2000
2540
3300
3300
mV
VIL Input LOW Voltage (Single−Ended)
LVPECL
LVCMOS
LVTTL
1365
0
0
1690
800
800
1430
0
0
1755
800
800
1490
0
0
1815
800
800
mV
VBB ECL Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV
VCF LVTTL Mode Input Detect Voltage 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 V
VEF Reference Voltage for ECL Mode Connection 1920 2020 2120 1980 2080 2180 2030 2130 2230 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9) 2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current (@ VIH) 150 150 150 mA
IIL Input LOW Current (@ VIL)IN
IN
0.5
−150 0.5
−150 0.5
−150 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V.
8. All loading with 50 W to VCC − 2.0 V.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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Table 9. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.3 V to −3.0 V (Note 10)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Negative Power Supply Current 100 145 175 100 150 180 100 150 180 mA
VOH Output HIGH Voltage (Note 11) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV
VOL Output LOW Voltage (Note 11) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV
VIH Input HIGH Voltage (Single−Ended)
LVNECL −1210 −885 −1145 −820 −1085 −760 mV
VIL Input LOW Voltage (Single−Ended)
LVNECL −1935 −1610 −1870 −1545 −1810 −1485 mV
VBB ECL Output Voltage Reference −1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185 mV
VEF Reference Voltage for ECL Mode
Connection −1380 −1280 −1180 −1320 −1220 −1120 −1270 −1170 −1070 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
IIH Input HIGH Current (@ VIH) 150 150 150 mA
IIL Input LOW Current (@ VIL)IN
IN 0.5
−150 0.5
−150 0.5
−150 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V.
11. All loading with 50 W to VCC − 2.0 V.
12.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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Table 10. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 13)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Negative Power Supply Current 100 135 160 100 140 170 100 145 175 mA
VOH Output HIGH Voltage (Note 14) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
VOL Output LOW Voltage (Note 14) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mV
VIH Input HIGH Voltage (Single−Ended)
LVPECL
CMOS
TTL
2075
2000
2000
2420
3300
3300
2075
2000
2000
2420
3300
3300
2075
2000
2000
2420
3300
3300
mV
VIL Input LOW Voltage (Single−Ended)
LVPECL
CMOS
TTL
1305
0
0
1675
800
800
1305
0
0
1675
800
800
1305
0
0
1675
800
800
mV
VBB ECL Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
VCF LVTTL Mode Input Detect Voltage 1.4 1.5 1.6 1.4 1.5 1.6 1.4 1.5 1.6 V
VEF Reference Voltage for ECL Mode Connection 1920 2020 2120 1920 2020 2120 1920 2020 2120 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 15) 2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current (@ VIH) 150 150 150 mA
IIL Input LOW Current (@ VIL)IN
IN
0.5
−150 0.5
−150 0.5
−150 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V.
14.All loading with 50 W to VCC − 2.0 V.
15.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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Table 11. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.3 V (Note 16)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Negative Power Supply Current
(Note 17)
100 135 160 100 140 170 100 145 175 mA
VOH Output HIGH Voltage (Note 18) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV
VOL Output LOW Voltage (Note 18) −1995 −1820 −1695 −1995 −1820 −1695 −1995 −1820 −1695 mV
VIH Input HIGH Voltage (Single−Ended)
LVNECL −1225 −880 −1225 −880 −1225 −880 mV
VIL Input LOW Voltage (Single−Ended)
LVNECL −1995 −1625 −1995 −1625 −1995 −1625 mV
VBB ECL Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
VEF Reference Voltage for ECL Mode Con-
nection −1380 −1280 −1180 −1380 −1280 −1180 −1380 −1280 1180 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
IIH Input HIGH Current (@ VIH) 150 150 150 mA
IIL Input LOW Current (@ VIL)IN
IN
0.5
−150 0.5
−150 0.5
−150 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
16.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −0.3 V.
17.Recommended VCC − VEE operation at 3.0 V 3.6 V.
18.All loading with 50 W to VCC − 2.0 V.
19.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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Table 12. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 20)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
fmax Maximum Frequency 1.2 1.2 1.2 GHz
tPLH
tPHL
Propagation Delay IN to Q; D(0−10) = 0
IN to Q; D(0−10) = 1023
EN to Q; D(0−10) = 0
D0 to CASCADE
1650
9500
1600
300
2050
11500
2150
420
2450
13500
2600
500
1800
10000
1800
350
2200
12200
2300
450
2600
14000
2800
550
1950
10800
2000
425
2350
13300
2500
525
2750
15800
3000
625
ps
tRANGE Programmable Range
tPD (max) − tPD (min) 7850 9450 8200 10000 8850 10950 ps
DtStep Delay (Note 21) D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
13
27
44
90
130
312
590
1100
2250
4500
14
30
47
97
140
335
650
1180
2400
4800
41
100
145
360
690
1300
2650
5300
ps
mono Monotonicity (Note 27) TBD
tSKEW Duty Cycle Skew (Note 22) |tPHL−tPLH|25 25 25 ps
tsSetup Time D to LEN
D to IN (Note 23)
EN to IN (Note 24)
200
300
300
0
140
150
200
300
300
0
160
170
200
300
300
0
180
180
ps
thHold Time LEN to D
IN to EN (Note 25)
200
400 60
250 200
400 100
280 200
400 80
300
ps
tRRelease Time EN to IN (Note 26)
SET MAX to LEN
SET MIN to LEN
150
400
350
−25
200
275
150
400
350
−75
250
200
150
400
350
−50
300
225
ps
tjitter RMS Random Clock Jitter @ 1.2 GHz
IN to Q; D(0:10) = 0 or SETMIN
IN to Q; D(0:10) = 1023 or SETMAX
0.86
0.89 1.16
1.09 1.12
1.02
ps
VPP Input Voltage Swing
(Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV
tr
tf
Output Rise/Fall Time @ 50 MHz
20−80% (Q)
20−80% (CASCADE)
85
100 100
140 135
200 85
110 110
150 135
200 95
130 125
170 155
220
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
21.Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
22.Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
23.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
24.This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
±75 mV to that IN/IN transition.
25.This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than ±75 mV to that IN/IN transition.
26.This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
27.The monotonicity indicates the increasing delay value for each binary count increment on the control inputs D[9:0].
7:<:\:>
MC10EP195, MC100EP195
http://onsemi.com
13
Figure 5. AC Reference Measurement
IN
IN
Q
Q
tPHL
tPLH
VINPP = VIH(D) − VIL(D)
VOUTPP = VOH(Q) − VOL(Q)
Cascading Multiple EP195s
To increase the programmable range of the EP195,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP195s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
Figure 6 illustrates the interconnect scheme for cascading
two EP195s. As can be seen, this scheme can easily be
expanded for larger EP195 chains. The D10 input of the
EP195 is the CASCADE control pin. With the interconnect
scheme of Figure 6 when D10 is asserted, it signals the need
for a larger programmable range than is achievable with a
single device and switches output pin CASCADE HIGH and
pin CASCADE LOW. The A11 address can be added to
generate a cascade output for the next EP195. For a 2−device
configuration, A11 is not required.
VEE
D0
VCC
Q
Q
NC
VCC
VCC
CASCADE
EN
SETMAX
VCC
VEE
LEN
D2 D1
CASCADE
SETMIN
VBB
IN
VEE
D8
VEF
D3D4D5D6D7
D9
D10
IN
VCF
INPUT OUTPU
T
VEE
D0
VCC
Q
Q
NC
VCC
VCC
CASCADE
EN
SETMAX
VCC
VEE
LEN
D2 D1
CASCADE
SETMIN
VBB
IN
VEE
D8
VEF
D3D4D5D6D7
D9
D10
IN
VCF
EP195
CHIP #2
EP195
CHIP #1
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Need if Chip #3 is used
Figure 6. Cascading Interconnect Architecture
MC10EP195, MC100EP195
http://onsemi.com
14
An expansion of the latch section of the block diagram is
pictured in Figure 7. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
of chip #1 in Figure 6 is LOW this device’s
CASCADE output will also be low while the CASCADE
output will be high. In this condition the SET MIN pin of
chip #2 will be asserted HIGH and thus all of the latches of
chip #2 will be reset and the device will be set at its minimum
delay.
Chip #1, on the other hand, will have both SET MIN and
SET MAX deasserted so that its delay will be controlled
entirely by the address bus A0—A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0—A9 address bus) D10 will be
asserted to signal the need to cascade the delay to the next
EP195 device. When D10 is asserted, the SET MIN pin of
chip #2 will be deasserted and SET MAX pin asserted
resulting in the device delay to be the maximum delay.
Table 13 shows the delay time of two EP195 chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 6. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
SET
MIN
SET
MAX
TO SELECT MULTIPLEXERS
BIT 0
D0 Q0
LEN
Set Reset
BIT 1
D1 Q1
LEN
Set Reset
BIT 2
D2 Q2
LEN
Set Reset
BIT 3
D3 Q3
LEN
Set Reset
BIT 4
D4 Q4
LEN
Set Reset
BIT 5
D5 Q5
LEN
Set Reset
BIT 6
D6 Q6
LEN
Set Reset
BIT 7
D7 Q7
LEN
Set Reset
BIT 8
D8 Q8
LEN
Set Reset
BIT 9
D9 Q9
LEN
Set Reset
Figure 7. Expansion of the Latch Section of the EP195 Block Diagram
MC10EP195, MC100EP195
http://onsemi.com
15
Table 13. Delay Value of Two EP195 Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
00000000000 0 ps 4400 ps
00000000001 10 ps 4410 ps
00000000010 20 ps 4420 ps
00000000011 30 ps 4430 ps
00000000100 40 ps 4440 ps
00000000101 50 ps 4450 ps
00000000110 60 ps 4460 ps
00000000111 70 ps 4470 ps
00000001000 80 ps 4480 ps
00000010000 160 ps 4560 ps
00000100000 220 ps 4720 ps
00001000000 640 ps 5040 ps
00010000000 1280 ps 5680 ps
00100000000 2560 ps 6960 ps
01000000000 5120 ps 9520 ps
01111111111 10230 ps 14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
10000000000 10240 ps 14640 ps
10000000001 10250 ps 14650 ps
10000000010 10260 ps 14660 ps
10000000011 10270 ps 14670 ps
10000000100 10280 ps 14680 ps
10000000101 10290 ps 14690 ps
10000000110 10300 ps 14700 ps
10000000111 10310 ps 14710 ps
10000001000 10320 ps 14720 ps
10000010000 10400 ps 14800 ps
10000100000 10560 ps 14960 ps
10001000000 10880 ps 15280 ps
10010000000 11520 ps 15920 ps
10100000000 12800 ps 17200 ps
11000000000 15360 ps 19760 ps
11111111111 20470 ps 24870 ps
MC10EP195, MC100EP195
http://onsemi.com
16
Multi−Channel Deskewing
The most practical application for EP195 is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a high−speed
system. To deskew multiple signal channels, each channel can
be sent through each EP195 as shown in Figure 8. One signal
channel can be used as reference and the other EP195s can be
used to adjust the delay to eliminate the timing skews. Nearly
any high−speed system can be fine−tuned (as small as 10 ps)
to reduce the skew to extremely tight tolerances.
EP195
IN Q
IN Q
#1
EP195
IN Q
IN Q
#2
EP195
IN Q
IN Q
#N
Digital
Data
Control
Logic
Figure 8. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
EP195s provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP195s and EP31 as shown in Figure 9,
the delay can be measured. The first EP195 can be set to
SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flip−flop of
EP31. The second EP195 is triggered along with the first
EP195 and its output provides a clock signal for EP31.
The programmed delay of the second EP195 is varied to
detect the output edge from the unknown delay device.
If the programmed delay through the second EP195 is too
long, the flip−flop output will be at logic high. On the other
hand, if the programmed delay through the second EP195 is
too short, the flip−flop output will be at a logic low. If the
programmed delay is correctly fine−tuned in the second
EP195, the flip−flop will bounce between logic high and logic
low. The digital code in the second EP195 can be directly
correlated into an accurate device delay.
EP195
IN Q
IN Q
#1
EP195
IN Q
IN Q
#2
Unknown Delay
Device
Control
Logic
D
CLK
Q
Q
EP31
CLOCK
CLOCK
Figure 9. Multiple Channel Deskewing Diagram
MC10EP195, MC100EP195
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17
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
ORDERING INFORMATION
Device Package Shipping
MC10EP195FAG LQFP−32
(Pb−Free) 250 Units / Tray
MC10EP195FAR2G LQFP−32
(Pb−Free) 2000 / Tape & Reel
MC10EP195MNG QFN−32
(Pb−Free) 74 Units / Rail
MC10EP195MNR4G QFN−32
(Pb−Free) 1000 / Tape & Reel
MC100EP195FAG LQFP−32
(Pb−Free) 250 Units / Tray
MC100EP195FAR2G LQFP−32
(Pb−Free) 2000 / Tape & Reel
MC100EP195MNG QFN−32
(Pb−Free) 74 Units / Rail
MC100EP195MNR4G QFN−32
(Pb−Free) 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D ECLinPSt I/O SPiCE Modeling Kit
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
* §:|:|:D §@ § 3 BT :EEQ /§:: B1 .3 ‘D’E/TAILVE‘7 V1 i /‘yuum_gpuuu A 514% §:E:D DE +1 ye G hf QWL sgmg- ’ :, E-l we: mm: 0250 1mm) DETAIL AD nznu REF nmmREF um REF smug;
MC10EP195, MC100EP195
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18
PACKAGE DIMENSIONS
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y BASE
N
J
DF
METAL
SECTION AE−AE
G
SEATING
PLANE
R
Q_
WK
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1 V1
4X
S
4X
9
−T−
−Z−
−U−
T-U0.20 (0.008) Z
AC
T-U0.20 (0.008) ZAB
0.10 (0.004) AC
−AC−
−AB−
M_
8X
−T−, −U−, −Z−
T-U
M
0.20 (0.008) ZAC
32 LEAD LQFP
CASE 873A−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B7.000 BSC 0.276 BSC
C1.400 1.600 0.055 0.063
D0.300 0.450 0.012 0.018
E1.350 1.450 0.053 0.057
F0.300 0.400 0.012 0.016
G0.800 BSC 0.031 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.450 0.750 0.018 0.030
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.400 BSC 0.016 BSC
Q1 5 1 5
R0.150 0.250 0.006 0.010
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
___ _
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
wi$ fiUi 7"? 9 TOP VIEW sED Cu SIDEVIEW D2 K L 9 a Féuwuuuuu‘uLE" « A F azxL j ‘ C ‘ ,3 7+77Ej: gm1m Bi 7 E ‘ E4 E x a agnnm‘fi‘rflnzs Eijfiiig w: :sz O ‘ ‘ ‘ $ 0 Eum‘umnir aorromvuaw , _{ F T 'For addmcma‘ mmrmauon on our PM: detafls‘ p‘ease aowmoad the ON Sem Mounnng Techniques Refierence Man m J
MC10EP195, MC100EP195
http://onsemi.com
19
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
SEATING
NOTE 4
K
0.15 C
(A3)
A
A1
D2
b
1
9
17
32
E2
32X
8
L
32X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
DA
B
E
0.15 C
PIN ONE
LOCATION
0.10 C
0.08 C
C
25
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
3.35
0.30
3.35
32X
0.63
32X
5.30
5.30
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL B
DETAIL A
DIM
AMIN
MILLIMETERS
0.80
A1 −−−
A3 0.20 REF
b0.18
D5.00 BSC
D2 2.95
E5.00 BSC
2.95
E2
e0.50 BSC
0.30
L
K0.20
1.00
0.05
0.30
3.25
3.25
0.50
−−−
MAX
−−−
L1 0.15
e/2 NOTE 3
PITCH
DIMENSION: MILLIMETERS
RECOMMENDED
A
M
0.10 BC
M
0.05 C
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