INA149 Datasheet by Texas Instruments

iTEXAs fi INSTRUMENTS
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Frequency (Hz)
Common−Mode Rejection Ratio (dB)
INA149
Competitor A
INA149
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High Common-Mode Voltage Difference Amplifier
1FEATURES DESCRIPTION
The INA149 is a precision unity-gain difference
2 Common-Mode Voltage Range: ±275 V amplifier with a very high input common-mode
Minimum CMRR: 90 dB from –40°C to +125°C voltage range. It is a single, monolithic device that
DC Specifications: consists of a precision op amp and an integrated thin-
film resistor network. The INA149 can accurately
Maximum Offset Voltage: 1100 μVmeasure small differential voltages in the presence of
Maximum Offset Voltage Drift: 15 μV/°C common-mode signals up to ±275 V. The INA149
Maximum Gain Error: 0.02% inputs are protected from momentary common-mode
or differential overloads of up to 500 V.
Maximum Gain Error Drift: 10 ppm/°C
Maximum Gain Nonlinearity: 0.001% FSR In many applications, where galvanic isolation in not
required, the INA149 can replace isolation amplifiers.
AC Performance: This ability can eliminate costly isolated input side
Bandwidth: 500 kHz power supplies and the associated ripple, noise, and
Typical Slew Rate: 5 V/μsquiescent current. The excellent 0.0005% nonlinearity
and 500-kHz bandwidth of the INA149 are superior to
Wide Supply Range: ±2.0 V to ±18 V those of conventional isolation amplifiers.
Maximum Quiescent Current: 900 μAThe INA149 is pin-compatible with the INA117 and
Output Swing on ±15-V Supplies: ±13.5 V INA148 type high common-mode voltage amplifiers
Input Protection: and offers improved performance over both devices.
Common-Mode: ±500 V The INA149 is available in the SOIC-8 package with
operation specified over the extended industrial
Differential: ±500 V temperature range of –40°C to +125°C.
APPLICATIONS
High-Voltage Current Sensing
Battery Cell Voltage Monitoring
Power-Supply Current Monitoring
Motor Controls
Replacement for Isolation Circuits
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS
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SBOS579B –SEPTEMBER 2011REVISED JULY 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
INA149 SOIC-8 D INA149A
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
INA149 UNIT
Supply voltage (V+) – (V–) 40 V
Input voltage range Continuous 300 V
Common-mode and differential, 10 s 500 V
Maximum Voltage on REFAand REFB(V–) – 0.3 to (V+) + 0.3 V
Input current on any input pin(2) 10 mA
Output short-circuit current duration Indefinite
Operating temperature range –55 to +150 °C
Storage temperature range –65 to +150 °C
Junction temperature +150 °C
Human body model (HBM) 1500 V
ESD rating Charged device model (CDM) 1000 V
Machine model (MM) 100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) REFAand REFBare diode clamped to the power-supply rails. Signals applied to these pins that can swing more than 0.3 V beyond the
supply rails should be limited to 10 mA or less.
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ELECTRICAL CHARACTERISTICS: V+ = +15 V and V– = –15 V
At TA= +25°C, RL= 2 kΩconnected to ground, and VCM = REFA= REFB= GND, unless otherwise noted.
INA149
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAIN
Initial VOUT = ±10.0 V 1 V/V
Gain error VOUT = ±10.0 V ±0.005 ±0.02 %FSR
Gain vs temperature, TA= –40°C to +125°C ±1.5 ±10 ppm/°C
Nonlinearity ±0.0005 ±0.001 %FSR
OFFSET VOLTAGE
350 1100 µV
Initial offset vs temperature, TA= –40°C to +125°C 3 15 µV/°C
vs supply (PSRR), VS= ±2 V to ±18 V 90 120 dB
INPUT
Differential 800 kΩ
Impedance Common-mode 200 kΩ
Differential –13.5 13.5 V
Voltage range Common-mode –275 275 V
At dc, VCM = ±275 V 90 100 dB
vs temperature, TA= –40°C to +125°C, at dc 90 dB
Common-mode rejection
(CMRR) At ac, 500 Hz, VCM = 500 VPP 90 dB
At ac, 1 kHz, VCM = 500 VPP 90 dB
OUTPUT
Voltage range –13.5 13.5 V
Short-circuit current ±25 mA
Capacitive load drive No sustained oscillations 10 nF
OUTPUT NOISE VOLTAGE
0.01 Hz to 10 Hz 20 µVPP
10 kHz 550 nV/Hz
DYNAMIC RESPONSE
Small-signal bandwidth 500 kHz
Slew rate VOUT = ±10-V step 1.7 5 V/µs
Full-power bandwidth VOUT = 20 VPP 32 kHz
Settling time 0.01%, VOUT = 10-V step 7 µs
POWER SUPPLY
Voltage range ±2 ±18 V
VS= ±18 V, VOUT = 0 V 810 900 µA
Quiescent current vs temperature, TA= –40°C to +125°C 1.1 mA
TEMPERATURE RANGE
Specified –40 +125 °C
Operating –55 +150 °C
Storage –65 +150 °C
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ELECTRICAL CHARACTERISTICS: V+ = 5 V and V– = 0 V
At TA= +25°C, RL= 2 kΩconnected to 2.5 V, and VCM= REFA= REFB= 2.5 V, unless otherwise noted.
INA149
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAIN
Initial VOUT = 1.5 V to 3.5 V 1 V/V
Gain error VOUT = 1.5 V to 3.5 V ±0.005 %FSR
Gain vs temperature, TA= –40°C to +125°C ±1.5 ppm/°C
Nonlinearity ±0.0005 %FSR
OFFSET VOLTAGE
350 µV
Initial offset vs temperature, TA= –40°C to +125°C 3 µV/°C
vs supply (PSRR), VS= 4 V to 5 V 120 dB
INPUT
Differential 800 kΩ
Impedance Common-mode 200 kΩ
Differential 1.5 3.5 V
Voltage range Common-mode –20 25 V
At dc, VCM = –20 V to 25 V 100 dB
vs temperature, TA= –40°C to +125°C, at dc 100 dB
Common-mode rejection At ac, 500 Hz, VCM = 49 VPP 100 dB
At ac, 1 kHz, VCM = 49 VPP 90 dB
OUTPUT
Voltage range 1.5 3.5 V
Short-circuit current ±15 mA
Capacitive load drive No sustained oscillations 10 nF
OUTPUT NOISE VOLTAGE
0.01 Hz to 10 Hz 20 µVPP
10 kHz 550 nV/Hz
DYNAMIC RESPONSE
Small-signal bandwidth 500 kHz
Slew rate VOUT = 2 VPP step 5 V/µs
Full-power bandwidth VOUT = 2 VPP 32 kHz
Settling time 0.01%, VOUT = 2 VPP step 7 µs
POWER SUPPLY
Voltage range 5 V
VS= 5 V 810 µA
Quiescent current vs temperature, TA= –40°C to +125°C 1 mA
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l TEXAS INSTRUMENTS UUUU flmflfl
6
8
3
1
2 7
4 5
NC
V+
VOUT
REFB
−IN
+IN
+
20 kΩ 380 kΩ
380 kΩ
380 kΩ
19 kΩ
REFA
V−
INA149
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THERMAL INFORMATION
INA149
THERMAL METRIC(1) D (SOIC) UNITS
8 PINS
θJA Junction-to-ambient thermal resistance 110
θJCtop Junction-to-case (top) thermal resistance 57
θJB Junction-to-board thermal resistance 54 °C/W
ψJT Junction-to-top characterization parameter 11
ψJB Junction-to-board characterization parameter 53
θJCbot Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
PIN CONFIGURATION
D PACKAGE
SOIC-8
(TOP VIEW)
PIN DESCRIPTIONS
NAME NO. DESCRIPTION
–IN 2 Inverting input
+IN 3 Noninverting input
NC 8 No internal connection
REFA5 Reference input
REFB1 Reference input
V– 4 Negative power supply
V+ 7 Positive power supply(1)
VOUT 6 Output
(1) In this document, (V+) – (V–) is referred to as VS.
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−20 −16 −12 −8 −4 0 4 8 12 16 20
Output Voltage (V)
Output Error (2 mV/div)
VS = ±18 V
VS = ±15 V VS = ±12 V
VS = ±10 V
G004
−20 −16 −12 −8 −4 0 4 8 12 16 20
Output Voltage (V)
Output Error (2 mV/div)
VS = ±18 V
VS = ±15 V VS = ±12 V
VS = ±10 V
G005
0
50
100
150
200
250
300
350
400
0 2 4 6 8 10 12 14 16 18 20
Power−Supply Voltage (±V)
Common−Mode Operating Range (±V)
G002
−20 −16 −12 −8 −4 0 4 8 12 16 20
Output Voltage (V)
Output Error (2 mV/div)
VS = ±18 V
VS = ±15 V VS = ±12 V
VS = ±10 V
G003
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Common−Mode Rejection Ratio (dB)
−40°C
+25°C
+125°C
G001
−6
−4
−2
0
2
4
6
−400 −300 −200 −100 0 100 200 300 400
Common−Mode Input Voltage (V)
Output Voltage (mV)
VS = ±18 V
VS = ±15 V
VS = ±10 V
VS = ±5 V
G066
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TYPICAL CHARACTERISTICS
At TA= +25°C, RL= 2 kΩconnected to ground, and VS= ±15 V, unless otherwise noted.
CMRR vs FREQUENCY COMMON-MODE REJECTION
Figure 1. Figure 2.
COMMON-MODE OPERATING RANGE TYPICAL GAIN ERROR FOR RL= 10 kΩ
vs POWER-SUPPLY VOLTAGE (Curves Offset for Clarity)
Figure 3. Figure 4.
TYPICAL GAIN ERROR FOR RL= 2 kΩTYPICAL GAIN ERROR FOR RL= 1 kΩ
(Curves Offset for Clarity) (Curves Offset for Clarity)
Figure 5. Figure 6.
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Output Voltage (V)
Error (ppm)
VS = ±12 V
RL = 10 k
G062
−20
−15
−10
−5
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5
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15
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0 5 10 15 20 25 30 35
Output Current (mA)
Output Voltage (V)
−45°C
+25°C
+85°C
+130°C
G017
−10
−8
−6
−4
−2
0
2
4
6
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10
−12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12
Output Voltage (V)
Error (ppm)
VS = ±15 V
RL = 2 k
G015
−10
−8
−6
−4
−2
0
2
4
6
8
10
−12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12
Output Voltage (V)
Error (ppm)
VS = ±15 V
RL = 1 k
G016
−5 −4 −3 −2 −1 0 1 2 3 4 5
Output Voltage (V)
Output Error (2 mV/div)
VS = ±5 V
VS = ±5 V VS = ±5 V
VS = ±2.5 V
RL = 10 k
RL = 2 k
RL = 1 k
RL = 1 k
G006
−10
−8
−6
−4
−2
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10
−12 −10 −8 −6 −4 −2 0 2 4 6 8 10 12
Output Voltage (V)
Error (ppm)
VS = ±15 V
RL = 10 k
G014
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TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, RL= 2 kΩconnected to ground, and VS= ±15 V, unless otherwise noted.
TYPICAL GAIN ERROR FOR LOW SUPPLY VOLTAGES
(Curves Offset for Clarity) GAIN NONLINEARITY
Figure 7. Figure 8.
GAIN NONLINEARITY GAIN NONLINEARITY
Figure 9. Figure 10.
GAIN NONLINEARITY OUTPUT VOLTAGE vs LOAD CURRENT
Figure 11. Figure 12.
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Frequency (Hz)
Power−Supply Rejection Ratio (dB)
−40°C
+25°C
+125°C
G064
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0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
−60 −40 −20 0 20 40 60 80 100 120 140 160
Ambient Temperature (°C)
Maximum Power Dissipation (W)
G013
−50
−50 Time (10 s/div)
Noise (10 µV/div)
G070
0
10
20
30
40
50
60
70
80
90
100
110
120
10 100 1k 10k 100k
Frequency (Hz)
Power−Supply Rejection Ratio (dB)
−40°C
+25°C
+125°C
G009
−80
−60
−40
−20
0
20
100 1k 10k 100k 1M 10M
Frequency (Hz)
Gain (dB)
25 °C
−40 °C
125 °C
G010
400
500
600
700
800
900
1000
1 10 100 1k 10k 100k
Frequency (Hz)
Noise Spectral Density (nV/ Hz)
G008
INA149
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TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, RL= 2 kΩconnected to ground, and VS= ±15 V, unless otherwise noted.
GAIN vs FREQUENCY NOISE SPECTRAL DENSITY vs FREQUENCY
Figure 13. Figure 14.
0.01 Hz TO 10 Hz NOISE POSITIVE PSRR vs FREQUENCY
Figure 15. Figure 16.
NEGATIVE PSRR vs FREQUENCY MAXIMUM POWER DISSIPATION vs TEMPERATURE
Figure 17. Figure 18.
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−15
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15
18
21
24
27
30
0
2
4
6
8
10
12
14
16
18
20
CMRR (µV/V)
Percent of Population (~5 kU)
G019
−1.4
−1.2
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
−4
−2
0
2
4
6
8
10
12
Time (5 us/div)
Error Voltage (mV)
Output Voltage (V)
Error Voltage
Output Voltage
G063
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
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Time (µs)
Voltage (mV)
0 nF
1 nF
3 nF
5 nF
10 nF
G065
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0.2
0.4
0.6
0.8
1
1.2
1.4
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0
2
4
Time (5 us/div)
Error Voltage (mV)
Output Voltage (V)
Error Voltage
Output Voltage
G018
Time (4 µs/div)
Output Voltage (5 V/div)
CL = 1000 pF
RL = 2 k
G011
Time (4 µs/div)
Output Voltage (25 mV/div)
CL = 1000 pF
RL = 2 k
G012
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TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, RL= 2 kΩconnected to ground, and VS= ±15 V, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE
Figure 19. Figure 20.
SMALL-SIGNAL RESPONSE vs CAPACITIVE LOAD SETTLING TIME
Figure 21. Figure 22.
SETTLING TIME CMRR HISTOGRAM
Figure 23. Figure 24.
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−2000
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0
400
800
1200
1600
2000
−75 −50 −25 0 25 50 75 100 125 150 175
Temperature (°C)
Offset Voltage (µV)
G027
−50
−40
−30
−20
−10
0
10
20
30
40
50
−75 −50 −25 0 25 50 75 100 125 150 175
Temperature (°C)
CMRR (µV/V)
G028
−1.50
−1.35
−1.20
−1.05
−0.90
−0.75
−0.60
−0.45
−0.30
−0.15
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
−1.50
−1.35
−1.20
−1.05
−0.90
−0.75
−0.60
−0.45
−0.30
−0.15
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
1.20
1.35
1.50
0
5
10
15
20
25
30
35
PSRR (µV/V)
Percent of Population (~5 kU)
G025
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
0
5
10
15
20
25
30
35
Nonlinearity Error (m%)
Percent of Population (~5 kU)
G026
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
0
2
4
6
8
10
12
Offset Voltage (µV)
Percent of Population (~5 kU)
G022
−20
−18
−16
−14
−12
−10
−8
−6
−4
−2
0
2
4
6
8
10
12
14
16
18
20
−20
−18
−16
−14
−12
−10
−8
−6
−4
−2
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
Differential Gain Error (m%)
Percent of Population (~5 kU)
G024
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TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, RL= 2 kΩconnected to ground, and VS= ±15 V, unless otherwise noted.
OFFSET VOLTAGE HISTOGRAM DIFFERENTIAL GAIN ERROR HISTOGRAM
Figure 25. Figure 26.
PSRR HISTOGRAM GAIN NONLINEARITY HISTOGRAM
Figure 27. Figure 28.
OFFSET VOLTAGE vs TEMPERATURE CMRR vs TEMPERATURE
Figure 29. Figure 30.
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1
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0 5 10 15 20 25 30 35 40
Supply Voltage (V)
Slew Rate (V/µs)
Negative Slew Rate
Positive Slew Rate
G038
400
600
800
1000
1200
−75 −50 −25 0 25 50 75 100 125 150 175
Temperature (°C)
Current (µA)
G043
−5
−4
−3
−2
−1
0
1
2
3
4
5
−75 −50 −25 0 25 50 75 100 125 150 175
Temperature (°C)
Linearity Error (m%)
G031
2
3
4
5
6
7
8
−75 −25 25 75 125 175
Temperature (°C)
Slew Rate (V/µs)
G071
−2
−1.6
−1.2
−0.8
−0.4
0
0.4
0.8
1.2
1.6
2
−75 −50 −25 0 25 50 75 100 125 150 175
Temperature (°C)
PSRR (µV/V)
G029
−50
−40
−30
−20
−10
0
10
20
30
40
50
−75 −50 −25 0 25 50 75 100 125 150 175
Temperature (°C)
Gain Error (m%)
G030
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TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, RL= 2 kΩconnected to ground, and VS= ±15 V, unless otherwise noted.
PSRR vs TEMPERATURE GAIN ERROR vs TEMPERATURE
Figure 31. Figure 32.
GAIN NONLINEARITY vs TEMPERATURE SLEW RATE vs TEMPERATURE
Figure 33. Figure 34.
SLEW RATE vs POWER-SUPPLY VOLTAGE QUIESCENT CURRENT vs TEMPERAUTRE
Figure 35. Figure 36.
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0.70
0.71
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0.75
0.76
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0.79
0.80
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0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.70
0.71
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0.75
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0.85
0.86
0.87
0.88
0.89
0.90
0
5
10
15
20
25
30
35
40
45
50
Quiescent Current (mA)
Percent of Population (~5 kU)
G059
−16
−12
−8
−4
0
4
Time (1 µs/div)
Voltage (V)
Input
Output
G067
0
5
10
15
20
25
30
1k 10k 100k 1M
Frequency (Hz)
Maximum Output Voltage (±V)
G057
−4
0
4
8
12
16
Time (1 µs/div)
Voltage (V)
Input
Output
G058
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
100 1k 10k 100k 1M 10M
Frequency (Hz)
VOUT / VIN (dB)
0 nF
1 nF
3 nF
5 nF
10 nF
G044
0
200
400
600
800
1000
1200
0 2 4 6 8 10 12 14 16 18 20
Supply Voltage (±V)
Quiescent Current (µA)
−45°C
+25°C
+85°C
+130°C
G056
INA149
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, RL= 2 kΩconnected to ground, and VS= ±15 V, unless otherwise noted.
FREQUENCY RESPONSE vs CAPACITIVE LOAD QUIESCENT CURRENT vs SUPPLY VOLTAGE
Figure 37. Figure 38.
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY OVERLOAD RECOVERY
Figure 39. Figure 40.
OVERLOAD RECOVERY QUIESCENT CURRENT HISTOGRAM
Figure 41. Figure 42.
12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): INA149
l TEXAS INSTRUMENTS
+
20 kΩ 380 kΩ
380 kΩ
380 kΩ
19 kΩ
30 V
1 F
GND
4 7
2
3
1
6
5
−IN
+IN VOUT = (+IN) – (–IN) + VREF
VREF
100 nF
+
20 kΩ 380 kΩ
380 kΩ
380 kΩ
19 kΩ
−15 V
1 F
15 V
1 F
GND
4 7
2
3
1
6
5
−IN
+IN VOUT = (+IN) − (−IN)
100 nF100 nF
INA149
www.ti.com
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
APPLICATION INFORMATION
BASIC INFORMATION
Figure 43 shows the basic connections required for dual-supply operation. Applications with noisy or high-
impedance power-supply lines may require decoupling capacitors placed close to the device pins. The output
voltage is equal to the differential input voltage between pins 2 and 3. The common-mode input voltage is
rejected. Figure 44 shows the basic connections required for single-supply operation.
Figure 43. Basic Power and Signal Connections for Figure 44. Basic Power and Signal Connections for
Dual-Supply Operation Single-Supply Operation
TRANSFER FUNCTION
Most applications use the INA149 as a simple unity-gain difference amplifier. The transfer function is given in
Equation 1:
VOUT = (+IN) – (–IN) (1)
Some applications, however, apply voltages to the reference terminals (REFAand REFB). The complete transfer
function is given in Equation 2:
VOUT = (+IN) – (–IN) + 20 × REFA– 19 × REFB(2)
COMMON-MODE RANGE
The high common-mode range of the INA149 is achieved by dividing down the input signal with a high precision
resistor divider. This resistor divider brings both the positive input and the negative input within the input range of
the internal operational amplifier. This input range depends on the supply voltage of the INA149.
Both Figure 2 and Figure 3 can be used to determine the maximum common-mode range for a specific supply
voltage. The maximum common-mode range can also be calculated by ensuring that both the positive and the
negative input of the internal amplifier are within 1.5 V of the supply voltage.
In case the voltage at the inputs of the internal amplifier exceeds the supply voltage, the internal ESD diodes
start conducting current. This current must be limited to 10 mA to make sure not to exceed the absolute
maximum ratings for the device.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): INA149
‘5‘ TEXAS INSTRUMENTS
+
20 kΩ 380 kΩ
380 kΩ
380 kΩ
19 kΩ
15 V
15 V
4 7
2
3
1
6
5
−IN
+IN VOUT = (+IN) − (−IN)
+
15 V
−15 V
100 Ω
100 Ω
100 µA
½ REF200
100 µA
½ REF200
10 kΩ
(1)
INA149
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
www.ti.com
COMMON-MODE REJECTION
Common-mode rejection (CMR) of the INA149 depends on the input resistor network, which is laser-trimmed for
accurate ratio matching. To maintain high CMR, it is important to have low source impedance driving the two
inputs. A 75-Ωresistance in series with pins 2 or 3 decreases the common-mode rejection ratio (CMRR) from
100 dB (typical) to 74 dB.
Resistance in series with the reference pins also degrades CMR. A 4-Ωresistance in series with pins 1 or 5
decreases CMRR from 100 dB to 74 dB.
Most applications do not require trimming. Figure 45 shows an optional circuit that may be used for trimming
offset voltage and common-mode rejection.
(1) The OPA171 (a 36-V, low-power, RRO, general-purpose operational amplifier) can be used for this application.
Figure 45. Offset Voltage Trim Circuit
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Product Folder Link(s): INA149
{5" TEXAS INSTRUMENTS “H i
INA149
www.ti.com
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
MEASURING CURRENT
The INA149 can be used to measure a current by sensing the voltage drop across a series resistor, RS.
Figure 46 shows the INA149 used to measure the supply currents of a device under test.
The sense resistor imbalances the input resistor matching of the INA149, thus degrading its CMR. Also, the input
impedance of the INA149 loads RS, causing gain error in the voltage-to-current conversion. Both of these errors
can be easily corrected.
The CMR error can be corrected with the addition of a compensation resistor (RC), equal to the value of RS, as
shown in Figure 46. If RSis less than 5 Ω, degradation in the CMR is negligible and RCcan be omitted. If RSis
larger than approximately 1 kΩ, trimming RCmay be required to achive greater than 90-dB CMR. This error is
caused by the INA149 input impedance mismatch.
Figure 46. Measuring Supply Currents of a Device Under Test
If RSis more than approximately 50 Ω, the gain error is greater than the 0.02% specification of the INA149. This
gain error can be corrected by slightly increasing the value of RS. The corrected value (RS') can be calculated by
RS' = RS× 380 kΩ/(380 kΩ– RS) (3)
Example: For a 1-V/mA transfer function, the nominal, uncorrected value for RSwould be 1 kΩ. A slightly larger
value (RS' = 1002.6 Ω), compensates for the gain error as a result of loading.
The 380-kΩterm in the equation for RS' has a tolerance of 25%, thus sense resistors above approximately 400 Ω
may require trimming to achive gain accuracy better than 0.02%.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): INA149
MENTS it" a F a “fl
+
20 kΩ 380 kΩ
380 kΩ
380 kΩ
19 kΩ
V− V+
4 7
2
3
1
6
5
+VOUT = (+IN) – (–IN)
–IN
+IN
R1R2
C2
C1
(1)
INA149
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
www.ti.com
NOISE PERFORMANCE
The wideband noise performane of the INA149 is dominated by the internal resistor network. The thermal or
Johnson noise of these resistors measures approximately 550 nV/Hz. The internal op amp contributes virtually
no excess noise at frequencies above 100 Hz.
Many applications may be satisfied with less than the full 500-kHz bandwidth of the INA149. In these cases, the
noise can be reduced with a low-pass filter on the output. The two-pole filter shown in Figure 47 limits bandwidth
and reduces noise. Because the INA149 has a 1/f noise corner frequency of approximately 100 Hz, a cutoff
frequency below 100 Hz does not further reduce noise.
Component values for different filter frequencies are shown in Table 1.
(1) For most applications, the OPA171 can be used as an operational amplifier. For directly driving successive-approximation register (SAR)
data converters, the OPA140 is a good choice.
Figure 47. Output Filter for Noise Reduction
Table 1. Components Values for Different Filter Bandwidths
BUTTERWORTH OUTPUT NOISE
LOW-PASS (f–3 dB) (mVPP) R1R2C1C2
200 kHz 1.8 No filter
100 kHz 1.1 11 kΩ11.3 kΩ100 pF 200 pF
10 kHz 0.35 11 kΩ11.3 kΩ1 nF 2 nF
1 kHz 0.11 11 kΩ11.3 kΩ10 nF 20 nF
100 Hz 0.05 11 kΩ11.3 kΩ0.1 µF 0.2 µF
16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): INA149
‘5‘ TEXAS INSTRUMENTS
+
20 kΩ 380 kΩ
380 kΩ
380 kΩ
19 kΩ
V− = −15 V V+ = +15 V
4 7
2
3
1
6
5
VOUT
RS = 10 Ω
VCM = 265 V
RC = 10 Ω(1)
IMAX = 1 A
INA149
www.ti.com
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
ERROR BUDGET ANALYSIS
The following error budget analysis demonstrates the importance of a high common-mode rejection ratio when
measuring small differential signals in the presence of high common-mode voltages. Figure 48 shows a typical
current measurement application.
(1) See the Measuring Current section for details about RC.
Figure 48. Typical Current Measurement Application
The maximum current through the shunt resistor (RS) is 1 A and generates a full-scale voltage drop of 10 V. All
error sources in this calculation are shown in relation to this full-scale voltage. The common-mode voltage in this
scenario is 265 V and the temperature range is from room temperature (+25°C) to +85°C. Table 2 shows the
dominant error sources for the INA149 and a competitor device.
Table 2. Error Budget Analysis
ERROR (ppm of FS)
ERROR
SOURCE INA149 COMPETIOR A INA149 COMPETITOR A
Accuracy, TA= +25°C
Initial gain error 0.02% FS 0.05% FS 200 500
Offset voltage 1100 µV 1000 µV 110 100
Common mode 265 V/90 dB = 8380 µV 265 V/77 dB = 37432 µV 838 3743
Total acuracy error 1148 4343
Temperature drift
Gain 10 ppm/°C × 60°C 10 ppm/°C × 60°C 600 600
Offset voltage 10 µV/°C × 60°C 20 µV/°C × 60°C 60 120
Total drift error 660 720
Total error 1808 5063
If a smaller shunt resistor is used, the full-scale voltage drop is also smaller. A shunt resistor of 1 Ωcauses a 1-V
voltage drop with a current of 1 A flowing through it. The error of 1808 ppm for a full-scale voltage of 10 V
becomes 18080 ppm (1.6%) for a full-scale voltage of only 1 V.
This example demonstrates that the dominate source of error, even over temperature, comes from the CMRR
specification of the devices. The common-mode error is 46% of the total error for the INA149 and 74% of the
total error for the competitor device.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): INA149
2
3
(+275 V max)
+VS
−VS
(−275 V max)
+
INA149
2
3+
INA149
2
3+
INA149
2
3+
INA149
Repeat
for each
cell
ADS8638
12-bit, 8-Channel,
Bipolar SAR ADC
MSP430
16-Bit Ultra-Low-
Power Microcontroller
INA149
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
www.ti.com
BATTERY CELL VOLTAGE MONITOR
The INA149 can be used to measure the voltages of single cells in a stacked battery pack. Figure 49 shows an
examples for such an application.
Figure 49. Battery Cell Voltage Monitor
18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): INA149
l TEXAS INSTRUMENTS
INA149
www.ti.com
SBOS579B –SEPTEMBER 2011REVISED JULY 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2011) to Revision B Page
Changed package marking data in Package/Ordering Information table ............................................................................. 2
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): INA149
I TEXAS INSTRUMENTS Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
INA149AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA
149A
INA149AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA
149A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF INA149 :
Enhanced Product: INA149-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
INA149AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA149AIDR SOIC D 8 2500 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
INA149AID D SOIC 8 75 506.6 8 3940 4.32
Pack Materials-Page 3
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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