M0220SD-202SDAR1-1G User Guide Datasheet by Newhaven Display Intl

Newhaven Disglay Internationall Inc. www.newhavendisglay.com nhtech@newhavendisnlav.com nhsa|es@newhavendisnlav.com
M0220SD‐202SDAR1‐1G
VacuumFluorescentDisplayModule
RoHSCompliant
NewhavenDisplayInternational,Inc.
2511TechnologyDrive,Suite101
ElginIL,60124
Ph:847‐844‐8795Fax:847‐844‐8796
www.newhavendisplay.com
nhtech@newhavendisplay.com nhsales@newhavendisplay.com
protective PCB layout. Note additional 10K ohm resistors on IC input lines (R01 ~ R08).
www.newhavendisplay.com
A Important Safety Notice
Important Safety Notice
Please read this note carefully before using the product.
Warning
•The module should be disconnected from the power supply before handling.
•The power supply should be switched off before connecting or disconnecting the
power or interface cables.
•The module contains electronic components that generate high voltages which may
cause an electrical shock when touched.
•Do not touch the electronic components of the module with any metal objects.
• The VFD used on the module is made of glass and should be handled with care.
When handling the VFD, it is recommended that cotton gloves be used.
•The module is equipped with a circuit protection fuse.
•Under no circumstances should the module be modified or repaired.
Any unauthorized modifications or repairs will invalidate the product warranty.
•The module should be abolished as the factory waste.
!
M0220SD-202SDAR1-1G
CONTENTS PAGE
1. FEATURES
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2. SPECIFICATIONS
2-1. GENERAL SPECIFICATIONS
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2-2. ENVIRONMENTAL SPECIFICATIONS
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2-3. ABSOLUTE MAXIMUM SPECIFICATIONS
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2-4. DC ELECTRICAL SPECIFICATIONS
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2-5. AC ELECTRICAL SPECIFICATIONS
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2-5-1. MOTOROLA M68-TYPE PARALLEL INTERFACE TIMING
−−−
2
2-5-2. INTEL I80-TYPE PARALLEL INTERFACE TIMING
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4
2-5-3. SYNCHRONOUS SERIAL INTERFACE TIMING
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5
2-5-4. RESET TIMING
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3. MODE OF OPERATION
3-1. PARALLEL INTERFACE MODES
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3-1-1. MOTOROLA M68-TYPE MODE
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3-1-2. INTEL I80-TYPE MODE
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3-2. SYNCHRONOUS SERIAL INTERFACE MODE
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3-3. RESET MODE
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4. FUNCTIONAL DESCRIPTION
4-1. ADDRESS COUNTER (AC)
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4-2. DISPLAY DATA RAM (DDRAM)
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4-3. CHARACTER GENERATOR RAM (CGRAM)
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4-4. INSTRUCTIONS
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4-4-1. CLEAR DISPLAY
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4-4-2. CURSOR HOME
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4-4-3. ENTRY MODE SET
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4-4-4. DISPLAY ON/OFF CONTROL
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4-4-5. CURSOR/DISPLAY SHIFT
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4-4-6. FUNCTION SET
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4-4-7. CGRAM ADDRESS SET
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4-4-8. DDRAM ADDRESS SET
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4-4-9. ADDRESS COUNTER READ
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4-4-10. DDRAM OR CGRAM WRITE
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4-4-11. DDRAM OR CGRAM READ
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4-5. RESET CONDITIONS
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5. CONNECTOR INTERFACE
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6. JUMPER SETTING
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7. CIRCUIT BLOCK DIAGRAM
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FIGURE-1 MECHANICAL DRAWING
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FIGURE-2 CHARACTER FONT TABLE
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8. WARRANTY
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9. OPERATING RECOMMENDATION
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M0220SD-202SDAR1-1G
Tableii Item Value Character Height 534 mm Character Width 235 mm Character Pitch 360 mm Line Pitch 6‘1 6 mm Peak Wavelength of Illumination Minimum Typical 350 cd/nf, 10sz 500 cd/nf, 146 fL Table72 Item Symbol Min. Max. Unit Comment Operating Humidity Hopr 20 85 %RH Without condensation Storage Humidity Hstg 20 90 %RH Without condensation Total amplitude: 1.5mm Freq: 10755 Hz sine wave Sweep time: 1 min/cycle Duration12hrst/axis (X,Y,Z) Duration: lims Wave form: half sine wave 3 times/axis (X,Y,Z,*X,*YFZ)
1. FEATURE
This vacuum fluorescent display (VFD) module consists of a 20 character by 2 line 5×8 dot
matrix display, DC-DC/AC converter, and controller/driver circuitry.
The module can be configured for a Motorola M68-type parallel interface, an Intel I80-type
parallel interface, or a synchronous serial interface.
A character generator ROM with 240 5×8 characters is provided along with RAM for the user
to program an additional 8 characters. The luminance level of the VFD can be varied by
setting two bits in the function set instruction.
Two hundred and forty character fonts consisting of a alphabets, numerals and other symbols
can be displayed.
This module has a dual-port RAM that allows data and instructions to be the module
continuously. Thus, the busy flag is always 0 and the host never has to read the busy flag bit to
determine if the module is busy.
Due to this feature, the execution times for each instruction are not specified.
2 SPECIFICATIONS
2-1.GENERAL SPECIFICATIONS
Table-1
ItemValue
Number of characters20 characters × 2 lines
Character configuration 5×8 dot matrix
Character Height 5.34 mm
Character Width 2.35 mm
Character Pitch 3.60 mm
Line Pitch 6.16 mm
Dot Size 0.39 × 0.58 mm
Dot Pitch0.49 × 0.68 mm
Peak Wavelength of
Illumination Green (λp=505nm) x=0.235, y=0.405
LuminanceMinimum
350 cd/m
2
, 102 fL
Typical
500 cd/m
2
, 146 fL
2-2. ENVIRONMENTAL SPECIFICATIONS
Table-2
ItemSymbolMin.Max.UnitComment
Operating TemperatureTopr-40+85°C
Storage TemperatureTstg -50+95°C
Operating HumidityHopr 20 85 %RH Without condensation
Storage HumidityHstg 20 90 %RH Without condensation
Vibration− − 4 G
Total amplitude: 1.5mm
Freq: 10-55 Hz sine wave
Sweep time: 1 min./cycle
Duration: 2hrs./axis (X,Y,Z)
Shock − − 40 G
Duration: 11ms
Wave form: half sine wave
3 times/axis (X,Y,Z,-X,-Y,-Z)
PAGE:1/19
M0220SD-202SDAR1-1G
Table-3 Item Symbol Min. Max. Unit Supply Voltage Vec -0.3 6.5 V Input signal Voltage VN -0.3 Vac-+0.3 V Table—4 Itcm Symbol Min. Typ. Max. Unit Supply Voltage Vce 4.5 5.0 5.5 V Supply Current ce 7 140 190 mA Power Consumption 7 7 0.7 1.045 W High - Level Input Voltage(sce Note) VIII 0.7*Vcc 7 Vec V Low - Level Input Voltage VIL 0 7 0.2* Vcc V High - Level Output Voltage V ( on : —0.1mA) 0” Low — Level Output Voltage V ( or 7 0.1mm “L Input Current (see Note) ; -500 7 1.0 uA Table-5 Item Symbol Min. Max. Unit RS. R/W Setup Time lAs 20 7 ns RS, R/W Hold Time tA” 10 7 ns Input Signal rise Time tI 7 15 ns Input Signal Fall Time tt 7 15 ns Enable Pulse Width High PWm 230 7 ns Enable Pulse Width Low PWEL 230 7 ns Write Data Setup Time lug 80 7 ns Write Data Hold Time tn” 10 7 ns Enable Cycle Time lcycu: 500 7 ns Read Data Delay Time tn.) 7 160 ns Read Data Hold Time [DIIR 5 7 ns PAGL': 2’19
PAGE: 2/19
2-3. ABSOLUTE MAXIMUM SPECIFICATIONS
Table-3
Item Symbol Min. Max. Unit
Supply Voltage Vcc -0.3 6.5 V
Input signal Voltage V
IN
-0.3 Vcc+0.3 V
2-4. DC ELECTRICAL SPECIFICATIONS
Table-4
Item Symbol Min. Typ. Max. Unit
Supply Voltage Vcc 4.5 5.0 5.5 V
Supply Current Icc
−
140 190 mA
Power Consumption
−
−
0.7 1.045 W
High - Level Input Voltage(see Note) V
IH
0.7*Vcc
−
Vcc V
Low - Level Input Voltage V
IL
0
−
0.2* Vcc V
High - Level Output Voltage
(I
OH
= -0.1mA) V
OH
Vcc-0.5
−
−
V
Low - Level Output Voltage
(I
OL
= 0.1mA) V
OL
−
−
0.5 V
Input Current (see Note) I
I
-500
−
1.0
µ
A
Note: A 10K ohm pull-up resistor is provided on each input line.
2-5. AC ELECTRICAL SPECIFICATIONS
2-5-1. MOTOROLA M68-TYPE PARALLEL INTERFACE TIMING
(See Fig. 1 and 2)
Table-5
Item Symbol Min. Max. Unit
RS, R/W Setup Time t
AS
20
−
ns
RS, R/W Hold Time t
AH
10
−
ns
Input Signal rise Time t
r
−
15 ns
Input Signal Fall Time t
f
−
15 ns
Enable Pulse Width High PW
EH
230
−
ns
Enable Pulse Width Low PW
EL
230
−
ns
Write Data Setup Time t
DS
80
−
ns
Write Data Hold Time t
DH
10
−
ns
Enable Cycle Time t
CYCLE
500
−
ns
Read Data Delay Time t
DD
−
160 ns
Read Data Hold Time t
DHR
5
−
ns
Note: All timing is specified using 20% and 80% of Vcc as the reference points.
M0220SD-202SDAR1-1G
we Fig. 1. Motorola M68—Tvpe Parallel Interface Write C ele Timing - fa ll Fig. 2. Motorola M68-TVDe Parallel Interface Read Cvcle TiminE PAGL': 3’19
PAGE: 3/19
Fig. 1. Motorola M68-Type Parallel Interface Write Cycle Timing
Fig. 2. Motorola M68-Type Parallel Interface Read Cycle Timing
tDH
tAH
tAS
tf
tr
tDS
RS
R/W
E
DB0-DB7
tCYCLE
PWEH
PWEL
RS
R/W
E
DB0-DB7
tDHR
tAH
tAS
tf
tDD
tCYCLE
PWEH
PWEL
tr
M0220SD-202SDAR1-1G
Table-6 Item Symbol Min. Max. Unit RS Setup Time [RSS 10 7 ns RS Hold Time IRS“ 10 7 ns Input Signal Fall Time It 7 15 ns Input Signal Rise Time 1. 7 15 ns WR/ Pulse Width Low [mu 30 7 ns WR/ Pulse Width High [WRII 100 7 ns Write Data Setup Time 1,35. 30 7 ns Write Data Hold Time tn“. 10 7 ns WR/ Cycle Time tcycm 166 7 ns RD/Cycle Time tevckn 166 7 ns RD/ Pulse Width Low tRDL 70 7 ns RD/ Pulse Width High tRD“ 70 7 us Read Data Delay Time tDD. 7 70 us Read Data Hold Time 1mm. 5 50 ns X i9? —X m; X a f X X Fig. 3. Intel ISO-Tyne Parallel Interface Write CVele Timing PAGL': 4’19
PAGE: 4/19
2-5-2. INTEL I80-TYPE PARALLEL INTERFACE TIMING
(See Fig. 3 and 4)
Table-6
Item Symbol Min. Max. Unit
RS Setup Time t
RSS
10
−
ns
RS Hold Time t
RSH
10
−
ns
Input Signal Fall Time t
f
−
15 ns
Input Signal Rise Time t
r
−
15 ns
WR/ Pulse Width Low t
WRL
30
−
ns
WR/ Pulse Width High t
WRH
100
−
ns
Write Data Setup Time t
DSi
30
−
ns
Write Data Hold Time t
DHi
10
−
ns
WR/ Cycle Time t
CYCWR
166
−
ns
RD/Cycle Time t
CYCRD
166
−
ns
RD/ Pulse Width Low t
RDL
70
−
ns
RD/ Pulse Width High t
RDH
70
−
ns
Read Data Delay Time t
DDi
−
70 ns
Read Data Hold Time t
DHRi
5 50 ns
Note: All timing is specified using 20% and 80% of Vcc as the reference points.
Fig. 3. Intel I80-Type Parallel Interface Write Cycle Timing
DB0-DB7
tf
tOHi
tr
tRSH
tRSS
tDSi
tCYCWR
WR/
RS
tWRL
tWRH
M0220SD-202SDAR1-1G
Fig. 4. Intel ISO-Type Parallel Interface Read C ele Timing Table-7 Item Symbol Min. Max. Unit STB Setup Time tgmg 100 ns STB Hold Time tg-mn 500 ns Input Signal Fall Time It 7 15 ns Input Signal Rise Time 1. 7 15 ns STB Pulse Width High tmm 500 ns SCK Pulse Width High tSCK” 200 ns SCK Pulse Width Low two. 200 ns SI Data Setup Time tbs, 100 ns SI Data Hold Time ID”, 100 ns SCK Cycle Time tcvcsck 500 ns SCK Wait Time Between Bytes twm- 1 us SO Data Delay Time 199, 7 150 ns SO Data Hold Time 1mm 5 ns PAGL': 5’19
PAGE: 5/19
Fig. 4. Intel I80-Type Parallel Interface Read Cycle Timing
2-5-3. SYNCHRONOUS SERIAL INTERFACE TIMING
(See Fig. 5, 6, 10, and 11)
Table-7
Item Symbol Min. Max. Unit
STB Setup Time t
STBS
100
−
ns
STB Hold Time t
STBH
500
−
ns
Input Signal Fall Time t
f
−
15 ns
Input Signal Rise Time t
r
−
15 ns
STB Pulse Width High t
WSTB
500
−
ns
SCK Pulse Width High t
SCKH
200
−
ns
SCK Pulse Width Low t
SCKL
200
−
ns
SI Data Setup Time t
DSs
100
−
ns
SI Data Hold Time t
DHs
100
−
ns
SCK Cycle Time t
CYCSCK
500
−
ns
SCK Wait Time Between Bytes t
WAIT
1
−
us
SO Data Delay Time t
DDs
−
150 ns
SO Data Hold Time t
DHRs
5
−
ns
Note: All timing is specified using 20% and 80% of Vcc as the reference points.
DB0-DB7
tf
tDHRi
tr
tRSH
tRSS
tDDi
tCYCRD
RD/
RS
tRDL
tRDH
M0220SD-202SDAR1-1G
Fig. 5. Svnehmnous Serial Interface Write C ele Timing Fig. 6. Svnehronous Serial Interface Read Cvcle Timinz PAGL': 6’19
PAGE: 6/19
Fig. 5. Synchronous Serial Interface Write Cycle Timing
Fig. 6. Synchronous Serial Interface Read Cycle Timing
tDHs
tSCKL
tDSs
tr
tf
tWSTB
STB
tSTBH
tCYCSCK
tSTBS
tSCKH
SCK
SI
tDHs
tSCKL
tDDs
tr
tf
tWSTB
STB
tSTBH
tCYCSCK
tSTBS
tSCKH
SCK
SI/SO
M0220SD-202SDAR1-1G
Table-8 Item Symbol Min. Max. Unit Delay Time After Reset 155m 100 7 us Vce Off Time Inn- 1 7 ms RST/ Pulse Width Low leTL 500 7 11s Fig. 7. Power-U9 Internal Reset Timing l l l l l l l l XZZZX XZZZX XZZZX /X X XZZZX /X X XZZZX /X X k % % Fig. 8. Typical 4-Bit Interface Sequence Using: M68-Tvpc Mode X X X XZZZX XZZZX XZZZX % k X X X XZZZX % % PAGL:7/l9 X X X X/ X/ X/ %
PAGE:7/19
2-5-4. RESET TIMING
(See Fig. 7)
Table-8
Item Symbol Min. Max. Unit
Delay Time After Reset t
BSTD
100
−
us
Vcc Off Time t
OFF
1
−
ms
RST/ Pulse Width Low t
RSTL
500
−
ns
Fig. 7. Power-Up Internal Reset Timing
3. MODE OF OPERATION
The following modes of operation are selectable via jumpers (see section 6. jumper Settings).
3-1. PARALLEL INTERFACE MODES
In the parallel interface mode, 8-bit instructions and data are sent between the host and the
module using either 4-bit nibbles or 8-bit bytes. Nibbles are transmitted high nibble first on
DB4-DB7 (DB0-DB3 are ignored) whereas bytes are transmitted on DB0-DB7. The
Register Select (RS) control signal is used to identify DB0-DB7 as an instruction (low) or
data (high).
3-1-1. MOTOROLA M68-TYPE MODE
This mode uses the Read/Write (R/W) and Enable (E) control signals to transfer
information.
Instructions/data are written to the module on the falling edge of E when R/W is low
and are read from the module after the rising edge of E when R/W is high.
Fig. 8. Typical 4-Bit Interface Sequence Using M68-Type Mode
4.5V
0.2V
Vcc
tOFF tRSTD
RS, STB
BF= “0”DB7
DB6
DB5
DB4
RS
R/W
E
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
IB6
IB5
IB4
IB3
IB2
IB1
IB0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
Write Instruction Write Instruction Read Instruction Write Data
M0220SD-202SDAR1-1G
44 J #— m m A BF:“0” K/ m /X /X 136 X//X 136 X//X 136 X//X DB6 X//X /X 130 X//X 130 X//X 130 X//X 330 X//X K >1 K >1 K >1 1% 91 Fig. 9. Tvnical S-Bit Parallcl Interface Scaucncc Using ISO—Tvnc Modc PAGL': 8’19
PAGE: 8/19
3-1-2. INTEL I80-TYPE MODE
This mode uses the Read (RD/) and Write (WR/) control signals to transfer information.
Instructions/data are written to the module on the rising edge of WR/ and are read from
the module after the falling edge of RD/.
Fig. 9. Typical 8-Bit Parallel Interface Sequence Using I80-Type Mode
3-2. SYNCHRONOUS SERIAL INTERFACE MODE
In the synchronous serial interface mode, instructions and data are sent between the host
and the module using 8-bit bytes. Two bytes are required per read/write cycle and are
transmitted MSB first. The start byte contains 5 high bits, the Read/Write (R/W) control bit,
the Register Select (RS) control bit, and a low bit. The following byte contains the
instruction/data bits. The R/W bit determines whether the cycle is a read (high) or a write
(low) cycle. The RS bit is used to identify the second byte as an instruction (low) or data
(high).
This mode uses the Strobe (STB) control signal, Serial Clock (SCK) input, and Serial I/O
(SI/SO) line to transfer information. In a write cycle, bits are clocked into the module on
the rising edge of SCK. In a read cycle, bits in the start byte are clocked into the module on
the rising edge of SCK. After the minimum wait time, each bit in the instruction/data byte
can be read from the module after each falling edge of SCK. Each read/write cycle begins
on the falling edge of STB and ends on the rising edge. To be a valid read/write cycle, the
STB must go high at the end of the cycle.
DB7
DB6
DB0
BF=“0”
IB6
IB0
IB7
IB6
IB0
IB7
IB6
IB0
RS
WR/
RD/
DB7
DB6
DB0
Write Instruction Write Instruction Read Instruction Write Data
M0220SD-202SDAR1-1G
l 2 3 4 5 6 7 8 9 10 ll 12 13 14 15 16 W JVVVVWHXXXXXXXK % % Fig. 10. Tvnical SVnehronous Serial Interface Write CVcle 71234567812345678 RW Fig. 11. TVDieal Svnchmnous Serial Interface Read CVele PAGL': 9’19
PAGE: 9/19
Fig. 10. Typical Synchronous Serial Interface Write Cycle
Fig. 11. Typical Synchronous Serial Interface Read Cycle
3-3. RESET MODE
The module is reset automatically at power-up by internal R-C circuit. However, an
external reset mode can also be selected when using one of the parallel interface modes
(this option is not available when using the synchronous serial interface mode) which
allows the module to be reset by setting the Reset (RST/) input low.
RSR/W B0B1B2B3B4B5B6B7“0”“1”“1”“1”“1”
STB
SCK
SI/SO
16151413121110987654321
“1”
Start Byte Instruction / Data
8765432187654321
STB
SCK
SI/SO RS
R/W
“0”“1”“1”“1”“1”“1”B0B1B2B3B4B5B6B7
Start Byte Instruction / Data
M0220SD-202SDAR1-1G
Rclationshi before displa shifi (non-shifted): 12345678910111213 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 40 41 42 43 44 45 46 47 48 49 4A 4B 4C Rclationshi after a display shifi to the lcfi: 12345678910111213 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D Rclationshi after a display shift to the right: 12345678910111213 27 00 01 02 03 04 05 06 07 08 09 0A 0B 67 40 41 42 43 44 45 46 47 48 49 4A 4B PAGE: 10, 19
PAGE: 10/19
4. FUNCTIONAL DESCRIPTION
4-1. ADDRESS COUNTER (AC)
The AC stores the address of the data being written to and from DDRAM or CGRAM. The
AC increments by 1 (overflows from 27H to 40H and from 67H to 00H) or decrements by
1 (underflows from 40H to 27H and from 00H to 67H) after each DDRAM access. The
AC increments by 1 (overflows from 3FH to 00H) or decrements by 1 (underflows from
00H to 3FH) after each CGRAM access. When addressing DDRAM, the value in the AC
also represents the cursor position.
4-2. DISPLAY DATA RAM (DDRAM)
The DDRAM stores the character code of each character being displayed on the VFD.
Valid DDRAM addresses are 00H to 27H and 40H to 67H. DDRAM not being used for
display characters can be used as general purpose RAM. The tables below show the
relationship between the DDRAM address and the character position on the VFD before
and after a display shift (with the number of display lines set to 2).
Relationship before a display shift (non-shifted):
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
100 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
240 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
Relationship after a display shift to the left:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
101 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14
241 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54
Relationship after a display shift to the right:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
127 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
267 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
M0220SD-202SDAR1-1G
Instruction RS R/W DB7 DB6 DBS DB4 Clear display 0 0 0 0 0 0 0 0 0 1 Cursor home 0 0 0 0 0 0 0 0 1 x Entry mode set 0 0 0 0 0 0 0 1 1/0 S Display on/off control 0 0 0 0 0 0 1 D C B Cursor/display shift 0 0 0 0 0 1 S/C R/L x x Function set 0 0 0 0 1 DL N x BR1 R0 CGRAM address set 0 0 0 1 CGRAM address DDRAM address set 0 0 1 DDRAM address Address counter read 0 1 BF=0 AC contents DDRAM or CGRAM write 1 0 Write data DDRAM or CGRAM read 1 1 Read data
PAGE: 11/19
4-3-1 CHARACTER GENERATOR RAM (CGRAM)
The CGRAM stores the pixel information (1 = pixel on, 0 = pixel off) for the eight user-
definable 5x8 characters. Valid CGRAM addresses are 00H to 3FH. CGRAM not being used to
define characters can be used as general purpose RAM (lower 5 bits only). Character codes 00H
to 07H (or 08H to 0FH) are assigned to the user-definable characters (see section 5.0 Character
Font Tables). The table below shows the relationship between the character codes, CGRAM
addresses, and CGRAM data for each user-definable character.
D7 6D 5D 4D 3D D1D2 D0 A35A 4A A0A1A2
X
Character codeCGRAM address
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
110
1 1 1
X0000 0 0 1 0
1
1
1
1
0
0
0
0
1 0 00
00
1
1
1
1
0
0
0
0
1X 11 0 01
0 0
0
0
0
0
1
1
1
1
1 1
1 1
0
0
0
0
1
1
1
1
x = don't care
4-3-2 INSTRUCTIONS
Instruction RS R/WDB7DB6DB5DB4
Clear display 0 0000000 0 1
Cursor home 0 0000000 1 x
Entry mode set
0 0 0 0 0 0 0 1 I/D S
Display on/off control 0 0000 0 1 D C B
Cursor/display shift 0 0000 1 S/C R/L x x
Function set 0 0001 DL N x BR1BR0
CGRAM address set 0 001 CGRAM address
DDRAM address set 0 0 1 DDRAM address
Address counter read 0 1 BF=0 AC contents
DDRAM or CGRAM write 1 0 Write data
DDRAM or CGRAM read 1 1 Read data
x = don’t care
DB3 DB2 DB1 DB0
0000
0000
000000
000
1 1 1
1
1
1
1
M0220SD-202SDAR1-1G
CLEAR DISPLAY RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO |0\0\0|0\0\0\0|0\0\1| CURSORHOME RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO |0\0\0|0\0\0\0|0\1\XI MODESET RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO |0\o\0|0\0\0\0|1\1/D\s| PAGE: 12, 19
PAGE: 12/19
4-4-1. CLEAR DISPLAY
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000000001
This instruction clears the display (without affecting the contents of CGRAM) by
performing the following.
1) Fills all DDRAM locations with character code 20H (character code for a space).
2) Sets the AC to DDRAM address 00H (i.e. sets cursor position to 00H).
3) Returns the display to the non-shifted position.
4) Sets the I/D bit to 1.
4-4-2. CURSOR HOME
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000000001
×
×=don’t care
This instruction returns the cursor to the home position (without affecting the contents
of DDRAM or CGRAM) by performing the following.
1) Sets the AC to DDRAM address 00H (i.e. sets cursor position to 00H).
2) Returns the display to the non-shifted position.
4-4-3. ENTRY MODE SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000001I/D S
This instruction selects whether the AC (cursor position) increments or decrements after
each DDRAM or CGRAM access and determines the direction the information on the
display shifts after each DDRAM write. The instruction also enables or disables display
shifts after each DDRAM write (information on the display does not shift after a
DDRAM read or CGRAM access). DDRAM, CGRAM, and AC contents are not
affected by this instruction.
I/D = 0 :The AC decrements after each DDRAM or CGRAM access. If S=1, the
information on the display shifts to the right by one character position after
each DDRAM write.
I/D = 1 :The AC increments after each DDRAM or CGRAM access. If S=1, the
information on the display shifts to the left by one character position after each
DDRAM write.
S = 0 : The display shift function is disabled.
S = 1 : The display shift function is enabled.
M0220SD-202SDAR1-1G
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO |0\0\0|0\0\0\1|D\C\B| RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 |0\0\0|0\0\1\S/C|WL‘X‘X| Table-10 S/C R/L AC Contents (cursor position) Information on the display 0 0 Decrcmcnts by one No change 0 1 Incrcmcnts by one No change 1 0 Decrcmcnts by one Shitts on character position to the left 1 1 Incrcmcnts by one Shifts on character position to the right PAGE: 13, 19
PAGE: 13/19
4-4-4. DISPLAY ON/OFF CONTROL
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000001DC B
This instruction selects whether the display and cursor are on or off and selects whether
or not the character at the current cursor position blinks. DDRAM, CGRAM, and AC
contents are not affected by this instruction.
D = 0 : The display is off (display blank).
D = 1 : The display is on (contents of DDRAM displayed).
C = 0 : The cursor is off.
C = 1 : The cursor is on (8th row of pixels).
B = 0 : The blinking character function is disabled.
B = 1 : The blinking character function is enabled (a character with all pixels on will
alternate with the character displayed at the current cursor position at about a
1Hz rate with a 50% duty cycle).
4-4-5. CURSOR/DISPLAY SHIFT
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
000001S/C R/L
×
×
×=don’t care
This instruction increments or decrements the AC (cursor position) and shifts the
information on the display one character position to the left or right without accessing
DDRAM or CGRAM.
DDRAM and CGRAM contents are not affected by this instruction. If the AC was
addressing CGRAM prior to this instruction, the AC will be addressing DDRAM after
this instruction.
However, if the AC was addressing DDRAM prior this instruction, the AC will still be
addressing DDRAM after this instruction.
Table-10
S/C R/L AC Contents (cursor position) Information on the display
0 0 Decrements by one No change
0 1 Increments by one No change
1 0 Decrements by one Shifts on character position to the left
1 1 Increments by one Shifts on character position to the right
M0220SD-202SDAR1-1G
Rs R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO |0\o\0|0\1\DL\N|x\BR1\BRO| Rs R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 lo 1 0 1 0 | 1 \ CGRAMAddrcss | Rs R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 | 0 1 o 1 1 | DDRAM Address | RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 \ 0 | 1 |BF:0\ AC Contents \ PAGE: 14, 19
PAGE: 14/19
4-4-6. FUNCTION SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00001DL N
×
BR1 BR0
×=don’t care
This instruction sets the width of the data bus for the parallel interface modes, the
number of display lines, and the luminance level (brightness) of the VFD. DDRAM,
CGRAM, and AC contents are not affected by this instruction.
DL = 0 : Sets the data bus width for the parallel interface modes to 4-bit (DB7-DB4).
DL = 1 : Sets the data bus width for the parallel interface modes to 8-bit (DB7-DB0).
N = 0 : Sets the number of display lines to 1 (this setting is not recommended).
N = 1 : Sets the number of display lines to 2
BR1, BR0 = 0,0: Sets the luminance level to 100%.
0,1: Sets the luminance level to 75%.
1,0: Sets the luminance level to 50%.
1,1: Sets the luminance level to 25%.
4-4-7. CGRAM ADDRESS SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0001 CG RAM Address
This instruction places the 6-bit CGRAM address specified by DB5-DB0 into the AC
(cursor position). Subsequent data writes (reads) will be to (from) CGRAM. DDRAM
and CGRAM contents are not affected by this instruction.
4-4-8. DDRAM ADDRESS SET
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001 DD RAM Address
This instruction places the 7-bit DDRAM address specified by DB6-DB0 into the AC
(cursor position). Subsequent data writes (reads) will be to (from) DDRAM. DDRAM
and CGRAM contents are not affected by this instruction.
4-4-9. ADDRESS COUNTER READ
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 BF=0 AC Contents
This instruction reads the current 7-bit address from the AC on DB6-DB0 and the busy
flag (BF) bit (always 0) on DB7. DDRAM, CGRAM, and AC contents are not affected
by this instruction. Because the BF is always 0, the host never has to read the BF bit to
determine if the module is busy before sending data or instructions. Therefore, data and
instructions can be sent to the module continuously according to the E, WR/, and SCK
cycle times specified in section 2.5 AC Timing Specifications. Due to this feature, the
execution times for each instruction are not specified.
M0220SD-202SDAR1-1G
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO I 1 I 0 I Write data I RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO I 1 I 1 I Read data
PAGE: 15/19
4-4-10. DDRAM OR CGRAM WRITE
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 Write data
This instruction writes the 8-bit data byte on DB7-DB0 into the DDRAM or CGRAM
location addressed by the AC. The most recent DDRAM or CGRAM Address Set
instruction determines whether the write is to DDRAM or CGRAM. This instruction
also increments or decrements the AC and shifts the display according to the I/D and S
bits set by the Entry Mode Set instruction.
4-4-11. DDRAM OR CGRAM READ
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 Read data
This instruction reads the 8-bit data byte from the DDRAM or CGRAM location
addressed by the AC on DB7-DB0. The most recent DDRAM or CGRAM Address Set
instruction determines whether the read is from DDRAM or CGRAM. This instruction
also increments or decrements the AC and shifts the display according to the I/D and S
bits set by the Entry Mode Set instruction. Before sending this instruction, a DDRAM
or CGRAM Address Set instruction should be executed to set the AC to the desired
DDRAM or CGRAM address to be read.
4-5. RESET CONDITIONS
After a power-up reset, the module initializes to the following conditions:
1) All DDRAM locations are set to 20H (character code for a space).
2) The AC is set to DDRAM address 00H (i.e. sets cursor position to 00H).
3) The relationship between DDRAM addresses and character positions on the VFD is set
to the non-shifted position.
4) Entry Mode Set instruction bits:
I/D = 1: The AC increments after each DDRAM or CGRAM access. If S=1, the
information on the display shifts to the left by one character position after
each DDRAM write.
S = 0: The display shift function is disabled.
5) Display On/Off Control instruction bits:
D = 0: The display is off (display blank).
C = 0: The cursor is off.
B = 0: The blinking character function is disabled.
6) Function Set instruction bits:
DL = 1: Sets the data bus width for the parallel interface modes to 8-bit (DB7-DB0).
N = 1: Number of display lines set to 2.
BR1,BR0=0,0: Sets the luminance level to 100%.
M0220SD-202SDAR1-1G
Table—11 Pin Parallel Parallel Pin Parallel Parallel No. (Intel) (Motorola) No. (Intel) (Motorola) 1 GND GND GND 2 Vce Vee Vee 5 NC WR/ R/W 6 SCK RD/ E 7 NC DBO DBO 8 NC D31 D31 9 NC DB2 DB2 10 NC D33 DB3 11 NC DB4 DB4 12 NC DBS DB5 13 NC DB6 DB6 14 NC DB7 DB7 Table-12 Mode J3 J4 J5 J6 J7 Parallel (Motorola) open shorted open shorted open Parallel (Intel) open shorted open open shorted Serial shorted open shorted shorted open 4—» 4» 4» 4» PAGE: 16 19
PAGE: 16/19
5. CONNECTOR INTERFACE
Table-11
Pin
No. Serial Parallel
(Intel)
Parallel
(Motorola)
Pin
No. Serial Parallel
(Intel)
Parallel
(Motorola)
1GND GND GND 2Vcc Vcc Vcc
5NC WR/ R/W 6SCK RD/ E
7NC DB0 DB0 8NC DB1 DB1
9NC DB2 DB2 10 NC DB3 DB3
11 NC DB4 DB4 12 NC DB5 DB5
13 NC DB6 DB6 14 NC DB7 DB7
NC = No Connection
6. JUMPER SETTING
Table-12
Mode J3 J4 J5 J6 J7
Parallel (Motorola) open shorted open shorted open
Parallel (Intel) open shorted open open shorted
Serial shorted open shorted shorted open
7. CIRCUIT BLOCK DIAGRAM
VACUUM
FLUORESCENT
DISPLAY
25-2001FN
DOT MATRIX
VFD
CONTROLLER
AND DRIVER
DC-DC/AC
CONVERTER
NC_SI/SO
RS_STB
R/W_WR/
E_RD/_SCK
DB0-DB7
Vcc
GND
Storage Humidity Hstg 20 90 %RH Without condensation
Note : JP3∼JP7 must be set as shown above for either one of the parallel modes or for the serial mode.
When the module is shipped , the parallel (Motorola) mode is set.
M0220SD-202SDAR1-1G using Parallel Transfer mode. Jumper setting:J6 shorted and J2,J3,J5,J7 open.
M0220SD-202SDAR1-S using Serial Data Transfer mode. Jumper setting:J3,J5,J6 shorted and J2,J7 open
Pin NO. 1,2,3,4,5 using a linker connected.
M0220SD-202SDAR1-1G
3 SI/SO NC/RST NC/RST 4 STB RS RS
JP2 must be shorted to allow external reset
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PAGE: 17/19
MECHANICAL DRAWING
FIGURE-1
M0220SD-202SDAR1-1G
Connector: 
2x7 Gold plated header, Molex P/N: 10-89-2141 or
equivalent. Soldered onto backside of display.
PAGE:18/19
CHARACTER FONT TABLES FIGUER-2
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CG
RAM
(8)
CG
RAM
(7)
CG
RAM
(6)
CG
RAM
(5)
CG
RAM
(4)
CG
RAM
(3)
CG
RAM
(2)
CG
RAM
(1)
CG
RAM
(8)
CG
RAM
(7)
CG
RAM
(6)
CG
RAM
(5)
CG
RAM
(4)
CG
RAM
(3)
CG
RAM
(2)
CG
RAM
(1)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
UPPER
NIBBLE
LOWER
NIBBLE
M0220SD-202SDAR1-1G
PAGE: 19/19
8.WARRANTY
This display module is guaranteed for 1 year after a shipment from Newhaven Display.
9. OPERATING RECOMMENDATION
9-1. Since VFDs are made of glass material.
Avoid applying excessive shock or vibration beyond the specification for the module.
Careful handing is essential.
9-2. Applying lower voltage than the specified may cause non activation for selected pixels.
Conversely, higher voltage may cause may non-selected pixel to be activated.
If such a phenomenon is observed, check the voltage level of the power supply.
9-3. Avoid plugging or unplugging the interface connection with the power on.
9-4. If the start up time of the supply voltage is slow, the controller may not be reset.
The supply voltage must be risen up to the specified voltage level within 30msec.
9-5. Avoid using the module where excessive noise interference is expected. Noise affects the
interface signal and causes improper operation.
Keep the length of the interface cable less than 50cm (When the longer cable is required,
please contact Newhaven Display engineering).
9-6. When power supply is turned off, the capacitor does not discharge immediately.
The high voltage applied to the VFD must not contact the controller IC.
(The shorting of the mounted components within 30 seconds after power off may cause
damage.)
9-7. The fuse is mounted on the module as circuit protection.
If the fuse blown, the problem shall be solved first and change the fuse.
9-8. When fixed pattern is displayed for long time, you may see uneven luminance.
It is recommended to change the display patterns sometimes in order to keep best display
quality.
REMARKS
This specification is subject to change without prior notice in order to improve the design and quality.
Your consultation with Newhaven Display sales office is recommended for the use of this module.
M0220SD-202SDAR1-1G