TLV1117LVxx Datasheet by Texas Instruments

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TLV1117LV
SBVS160B –MAY 2011–REVISED FEBRUARY 2015
TLV1117LV 1-A, Positive Fixed-Voltage, Low-Dropout Regulator
1 Features 3 Description
The TLV1117LV series of low-dropout (LDO) linear
1• 1.5% Typical Accuracy regulators is a low input voltage version of the
• Low IQ: 100 μA (Maximum) popular TLV1117 voltage regulator.
– 500 Times Lower Than Standard 1117 The TLV1117LV is an extremely low-power device
Devices that consumes 500 times lower quiescent current
• VIN:2Vto5.5V than traditional 1117 voltage regulators, making the
device suitable for applications that mandate very low
– Absolute Maximum VIN =6V standby current. The TLV1117LV family of LDOs is
• Stable With 0-mA Output Current also stable with 0 mA of load current; there is no
• Low Dropout: 455 mV at 1 A for VOUT = 3.3 V minimum load requirement, making the device an
• High PSRR: 65 dB at 1 kHz ideal choice for applications where the regulator must
power very small loads during standby in addition to
• Minimum Ensured Current Limit: 1.1 A large currents on the order of 1 A during normal
• Stable With Cost-Effective Ceramic Capacitors: operation. The TLV1117LV offers excellent line and
– With 0-ΩESR load transient performance, resulting in very small
magnitude undershoots and overshoots of output
• Temperature Range: –40°C to 125°C voltage when the load current requirement changes
• Thermal Shutdown and Overcurrent Protection from less than 1 mA to more than 500 mA.
• Available in SOT-223 Package A precision bandgap and error amplifier provides
– See Mechanical, Packaging, and Orderable 1.5% accuracy. A very high power-supply rejection
Information at the end of this document for a ratio (PSRR) enables use of the device for post-
complete list of available voltage options. regulation after a switching regulator. Other valuable
features include low output noise and low-dropout
2 Applications voltage.
• Set Top Boxes The device is internally compensated to be stable
with 0-Ωequivalent series resistance (ESR)
• TVs and Monitors capacitors. These key advantages enable the use of
• PC Peripherals, Notebooks, Motherboards cost-effective, small-size ceramic capacitors. Cost-
• Modems and Other Communication Products effective capacitors that have higher bias voltages
• Switching Power Supply Post-Regulation and temperature derating can also be used if desired.
The TLV1117LV series is available in a SOT-223
package.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV1117LV SOT-223 (4) 6.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SBVS160B –MAY 2011–REVISED FEBRUARY 2015
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Table of Contents
8.1 Application Information .......................................... 13
1 Features.................................................................. 18.2 Typical Application .................................................. 13
2 Applications ........................................................... 18.3 Do's and Don'ts....................................................... 14
3 Description ............................................................. 19 Power Supply Recommendations...................... 14
4 Revision History..................................................... 210 Layout................................................................... 15
5 Pin Configuration and Functions......................... 310.1 Layout Guidelines ................................................. 15
6 Specifications......................................................... 410.2 Layout Example .................................................... 15
6.1 Absolute Maximum Ratings ..................................... 410.3 Thermal Protection................................................ 15
6.2 ESD Ratings ............................................................ 410.4 Power Dissipation ................................................. 15
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support ................. 16
6.4 Thermal Information.................................................. 411.1 Device Support...................................................... 16
6.5 Electrical Characteristics........................................... 511.2 Documentation Support ........................................ 16
6.6 Typical Characteristics.............................................. 611.3 Related Links ........................................................ 16
7 Detailed Description............................................ 11 11.4 Trademarks........................................................... 16
7.1 Overview ................................................................. 11 11.5 Electrostatic Discharge Caution............................ 16
7.2 Functional Block Diagram....................................... 11 11.6 Glossary................................................................ 17
7.3 Feature Description................................................. 11 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 12 Information ........................................................... 17
8 Application and Implementation ........................ 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2011) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Replaced front-page figure .................................................................................................................................................... 1
• Deleted Dissipation Ratings table........................................................................................................................................... 4
Changes from Original (May, 2011) to Revision A Page
• Changed front-page figure ..................................................................................................................................................... 1
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INPUT
GND
2
3
1
OUTPUT
OUTPUT
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SBVS160B –MAY 2011–REVISED FEBRUARY 2015
5 Pin Configuration and Functions
DCY Package
4 Pins (SOT-223)
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
Input pin. See Input and Output Capacitor Requirements in the Application and Implementation
IN 3 I section for more details.
OUT 2, Tab O Regulated output voltage pin. See Input and Output Capacitor Requirements for more details.
GND 1 — Ground pin.
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6 Specifications
6.1 Absolute Maximum Ratings
At TJ= 25°C (unless otherwise noted). All voltages are with respect to GND.(1)
MIN MAX UNIT
VIN –0.3 6 V
Voltage VOUT –0.3 6 V
Current IOUT Internally limited
Output short-circuit duration Indefinite
Continuous total power PDISS See Thermal Information
dissipation
Operating junction, TJ–55 150 °C
Temperature Storage, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, ±2000
all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification ±500
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN 2 5.5 V
VOUT 0 5.5 V
IOUT 0 1 A
6.4 Thermal Information
TLV1117LV
THERMAL METRIC(1) DCY (SOT-223) UNIT
4 PINS
RθJA Junction-to-ambient thermal resistance 62.9
θJCtop Junction-to-case (top) thermal resistance 47.2
RθJC(top) Junction-to-board thermal resistance 12 °C/W
ψJT Junction-to-top characterization parameter 6.1
ψJB Junction-to-board characterization parameter 11.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At VIN = VOUT(nom) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA= 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2 5.5 V
VOUT > 2 V –1.5% 1.5%
DC output
VOUT 1.5 V ≤VOUT < 2 V –2% 2%
accuracy 1.2 V ≤VOUT < 1.5 V –40 40 mV
ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.5 V ≤VIN ≤5.5 V, IOUT = 10 mA 1 5 mV
ΔVOUT(ΔIOUT) Load regulation 0 mA ≤IOUT ≤1 A 1 35 mV
IOUT = 200 mA 115 mV
IOUT = 500 mA 285 mV
VOUT < 3.3 V IOUT = 800 mA 455 mV
IOUT = 1 A 570 800 mV
VIN = 0.98 x
VDO Dropout voltage(1) VOUT(nom) IOUT = 200 mA 90 mV
IOUT = 500 mA 230 mV
VOUT ≥3.3 V IOUT = 800 mA 365 mV
IOUT = 1 A 455 700 mV
ICL Output current limit VOUT = 0.9 × VOUT(nom) 1.1 A
IQQuiescent current IOUT = 0 mA 50 100 µA
Power-supply VIN = 3.3 V, VOUT = 1.8 V,
PSRR 65 dB
rejection ratio IOUT = 500 mA, f = 100 Hz
Output noise BW = 10 Hz to 100 kHz, VIN = 2.8 V, VOUT = 1.8 V,
Vn60 µVRMS
voltage IOUT = 500 mA
tSTR Startup time(2) COUT = 1.0 µF, IOUT = 1 A 100 µs
Undervoltage
UVLO VIN rising 1.95 V
lockout
Shutdown, temperature increasing 165 °C
Thermal shutdown
TSD temperature Reset, temperature decreasing 145 °C
Operating junction
TJ–40 125 °C
temperature
(1) VDO is measured for devices with VOUT(nom) = 2.5 V so that VIN = 2.45 V.
(2) Startup time = time from when VIN asserts to when output is sustained at a value greater than or equal to 0.98 × VOUT(nom).
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600
500
400
300
200
100
0
Dropout Voltage (mV)
0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
+125 C
+85 C
+25 C
40 C-
°
°
°
°
-40 -25 -10 5 20 35 65 95 125
Temperature ( )C°
1.9
1.85
1.8
1.75
1.7
Output Voltage (V)
V = 1.8 V
OUT
50 80 110
10 mA
500 mA
2 2.5 3 3.5 4 4.5
1200
1000
800
600
400
200
0
Dropout Voltage (mV)
Input Voltage (V)
+85 C
+25 C
40 C-
°
°
°
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Input Voltage (V)
1.9
1.85
1.8
1.75
1.7
Output Voltage (V)
+125 C
+85 C
+25 C
40 C-
°
°
°
°
V = 1.8 V
I = 10 mA
OUT
OUT
3.3 3.5 3.7 3.9 4.1 4.3 4.7 5.1 5.5
Input Voltage (V)
1.9
1.85
1.8
1.75
1.7
Output Voltage (V)
+85 C
+25 C
40 C-
°
°
°
V = 1.8 V
I = 1 A
OUT
OUT
4.5 4.9 5.3
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6.6 Typical Characteristics
At VIN = VOUT(nom) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA= 25°C, unless otherwise noted.
Figure 1. Line Regulation Figure 2. Line Regulation
Figure 3. Load Regulation Figure 4. Dropout Voltage vs Input
Figure 5. Dropout Voltage vs Output Figure 6. Output Voltage vs Temperature
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10
1
0.1
0.01
0.001
Noise Spectral Density ( V/ )m ?Hz
10 100 1 k 10 k 100 k 1 M 10 M
Frequency (Hz)
0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
90
80
70
60
50
40
30
20
10
0
Power-Supply Rejection Ratio (dB)
V V = 1.5 V-
IN OUT
f = 120 Hz
f = 50 Hz
f = 10 kHz
f = 10 MHz
f = 1 kHz f = 100 kHz
f = 1 MHz
10 100 1 k 100 k 1 M 10 M
Frequency (Hz)
90
80
70
60
50
40
30
20
10
0
Power-Supply Rejection Ratio (dB)
10 k
V V = 3 V-
IN OUT
I = 500 mA
I = 150 mA
I = 30 mA
OUT
OUT
OUT
10 100 1 k 100 k 1 M 10 M
Frequency (Hz)
90
80
70
60
50
40
30
20
10
0
Power-Supply Rejection Ratio (dB)
10 k
V V = 1.5 V-
IN OUT
I = 500 mA
I = 150 mA
I = 30 mA
OUT
OUT
OUT
600
500
400
300
200
100
0
Quiescent Current ( A)m
0 100 200 300 400 500 600 700 800 900 1000
Output Current (mA)
+125 C
+85 C
+25 C
40 C-
°
°
°
°
3.3 3.5 3.7 3.9 4.1 4.3 4.7 5.1 5.5
Input Voltage (V)
1.8
1.78
1.76
1.74
1.72
1.7
1.68
1.66
1.64
1.62
1.6
Current Limit (mA)
4.5 4.9 5.3
+85 C
+25 C
40 C-
°
°
°
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Typical Characteristics (continued)
At VIN = VOUT(nom) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA= 25°C, unless otherwise noted.
Figure 7. Quiescent Current vs Load Figure 8. Current Limit vs Input Voltage
Figure 9. Power-Supply Rejection Ratio vs Frequency Figure 10. Power-Supply Rejection Ratio vs Frequency
Figure 11. Power-Supply Rejection Ratio vs Output Current Figure 12. Spectral Noise Density vs Frequency
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50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
200 mA
1 A
50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
200 mA
1 A
V = 2.8 V
IN
50 s/divm
50 mV/div 500 mA/div
IOUT
VOUT
1 mA
500 mA
50 s/divm
50 mV/div 500 mA/div
IOUT
VOUT
1 mA
500 mA
V = 2.8 V
IN
50 s/divm
50 mV/div 200 mA/div
IOUT
VOUT
200 mA
500 mA
V = 2.8 V
IN
50 s/divm
50 mV/div 200 mA/div
IOUT
VOUT
200 mA
500 mA
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Typical Characteristics (continued)
At VIN = VOUT(nom) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA= 25°C, unless otherwise noted.
Figure 13. Load Transient Response 200 mA to 500 mA, Figure 14. Load Transient Response 200 mA to 500 mA,
COUT = 1 μF COUT = 10 μF
Figure 15. Load Transient Response 1 mA to 500 mA, Figure 16. Load Transient Response 1 mA to 500 mA,
COUT = 1 μF COUT = 10 μF
Figure 17. Load Transient Response 200 mA to 1 A, Figure 18. Load Transient Response 200 mA to 1 A,
COUT = 1 μF COUT = 10 μF
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200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
4.3 V
200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
5.5 V
200 s/divm
5 mV/div 1 V/div
VIN
VOUT
3.3 V
4.3 V
200 s/divm
5 mV/div 1 V/div
VIN
VOUT
3.3 V
4.3 V
50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
1 mA
1 A
50 s/divm
100 mV/div 500 mA/div
IOUT
VOUT
1 mA
1 A
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Typical Characteristics (continued)
At VIN = VOUT(nom) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA= 25°C, unless otherwise noted.
Figure 19. Load Transient Response 1 mA to 1 A, Figure 20. Load Transient Response 1 mA to 1 A,
COUT = 1 μF COUT = 10 μF
Figure 21. Line Transient Response VOUT = 1.8 V, Figure 22. Line Transient Response VOUT = 1.8 V,
IOUT = 10 mA IOUT = 500 mA
Figure 23. Line Transient Response VOUT = 1.8 V, Figure 24. Line Transient Response VOUT = 1.8 V,
IOUT = 1 A IOUT = 10 mA
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200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
5.5 V
200 s/divm
10 mV/div 1 V/div
VIN
VOUT
3.3 V
5.5 V
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Typical Characteristics (continued)
At VIN = VOUT(nom) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA= 25°C, unless otherwise noted.
Figure 25. Line Transient Response VOUT = 1.8 V, Figure 26. Line Transient Response VOUT = 1.8 V,
IOUT = 500 mA IOUT = 1 A
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Current
Limit
Bandgap
Thermal
Shutdown
IN OUT
LOGIC
GND
TLV1117LV Series
UVLO
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7 Detailed Description
7.1 Overview
The TLV1117LV family of devices are a series of low quiescent current, high PSRR LDOs capable of handling up
to 1 A of load current. These devices feature an integrated current limit, thermal shutdown, bandgap reference,
and UVLO circuit blocks.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV1117LV internal current limit helps to protect the regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the
output voltage is not regulated, and can be calculated by the formula: VOUT = ILIMIT × RLOAD. The PMOS pass
transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the
device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the
device cycles between current limit and thermal shutdown. See the Thermal Information section for more details
The PMOS pass element in the TLV1117LV device has a built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This current is not limited; if extended reverse voltage operation is
anticipated, external limiting to 5% of the rated output current is recommended.
7.3.2 Dropout Voltage
The TLV1117LV uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the
PMOS device behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
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Feature Description (continued)
7.3.3 Undervoltage Lockout
The TLV1117LV uses an undervoltage lockout (UVLO) circuit keep the output shut off until internal circuitry
operating properly.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The output current is less than the current limit.
• The device die temperature is lower than the thermal shutdown temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout may result in large output voltage deviations.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE VIN IOUT
Normal mode VIN > VOUT(nom) + VDO IOUT < ICL
Dropout mode VIN < VOUT(nom) + VDO IOUT < ICL
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INPUT OUTPUT
GND
Device
CIN
1 µF COUT
1 µF
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV1117LV is a low quiescent current linear regulator designed for high current applications. Unlike typical
high current linear regulators, the TLV1117LV series consume significantly less quiescent current. These devices
deliver excellent line and load transient performance. The device is low noise, and exhibits a very good PSRR.
As a result, it is ideal for high current applications that require very sensitive power-supply rails.
This family of regulators offers both current limit and thermal protection. The operating junction temperature
range of the device is –40°C to +125°C.
8.2 Typical Application
Figure 27 shows a typical application circuit.
Figure 27. Typical Application Circuit
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 2 as the input parameters.
Table 2. Design Parameters
PARAMETER DESIGN REQUIREMENT
Input Voltage 2.5 V to 3.3 V
Output Voltage 1.8 V
Output Current 500 mA
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
For stability, 1.0-μF ceramic capacitors are required at the output. Higher-valued capacitors improve transient
performance. TI recommends the X5R- and X7R-type ceramic capacitors because these capacitors have
minimal variation in value and equivalent series resistance (ESR) over temperature. Unlike traditional linear
regulators that need a minimum ESR for stability, the TLV1117LV series are ensured to be stable with no ESR.
Therefore, cost-effective ceramic capacitors can be used with these devices. Effective output capacitance that
takes bias, temperature, and aging effects into consideration must be greater than 0.5 μF to ensure stability of
the device.
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V = 2.8 V
IN
50 s/divm
50 mV/div 200 mA/div
IOUT
VOUT
200 mA
500 mA
200 s/divm
5 mV/div 1 V/div
VIN
VOUT
3.3 V
4.3 V
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Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1.0-μF, low-ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive
input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor
may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located physically
close to the power source. If source impedance is greater than 2 Ω, a 0.1-μF, the input capacitor may also be
necessary to ensure stability.
8.2.2.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude.
8.2.3 Application Curves
Figure 28. Load Transient Response 200 mA to 500 mA, Figure 29. Line Transient Response VOUT = 1.8 V, IOUT =
COUT = 1 μF 500 mA
8.3 Do's and Don'ts
Place input and output capacitors as close to the device as possible.
Use a ceramic output capacitor.
Do not use an electrolytic output capacitor.
Do not exceed the device absolute maximum ratings.
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the INPUT pin of the TLV1117LV. Inductive
impedances between the input supply and the INPUT pin can create significant voltage excursions at the INPUT
pin during startup or load transient events.
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TEXAS INSTRUMENTS PD VIN VOUT IOUT
P =(V V )I-
D IN OUT OUT
Tab
1 2
COUT
3
OUTPUT
GND INPUT
GND
CIN
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10 Layout
10.1 Layout Guidelines
Input and output capacitors should be placed as close to the device pins as possible. To improve characteristic
AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with
separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In
addition, the ground connection for the output capacitor should be connected directly to the GND pin of the
device. Higher value ESR capacitors may degrade PSRR performance.
10.2 Layout Example
Figure 30. Layout Example
10.3 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions.
The internal protection circuitry of the TLV1117LV has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TLV1117LV into thermal shutdown
degrades device reliability.
10.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in the
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in Equation 1:
(1)
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TLV1117LV
l TEXAS INSTRUMENTS
TLV1117LV
SBVS160B –MAY 2011–REVISED FEBRUARY 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TLV1117LV. The TLV1117LV33EVM-714 evaluation module (and related user's guide) can be requested at the
TI website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TLV1117LV is available through the product folders under
Tools & Software.
11.1.2 Device Nomenclature
Table 3. Available Options(1)
PRODUCT VOUT
xx is nominal output voltage (for example 33 = 3.3 V)
TLV1117LVxxyyyz yyy is Package Designator
zis Package Quantity
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
•TLV1117LV33EVM-714 Evaluation Module User's Guide,SLVU449.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TLV1117LV12 Click here Click here Click here Click here Click here
TLV1117LV15 Click here Click here Click here Click here Click here
TLV1117LV18 Click here Click here Click here Click here Click here
TLV1117LV25 Click here Click here Click here Click here Click here
TLV1117LV28 Click here Click here Click here Click here Click here
TLV1117LV30 Click here Click here Click here Click here Click here
TLV1117LV33 Click here Click here Click here Click here Click here
11.4 Trademarks
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TLV1117LV
l TEXAS INSTRUMENTS
TLV1117LV
www.ti.com
SBVS160B –MAY 2011–REVISED FEBRUARY 2015
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TLV1117LV
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV1117LV12DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SI
TLV1117LV12DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SI
TLV1117LV15DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VR
TLV1117LV15DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VR
TLV1117LV18DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SH
TLV1117LV18DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 SH
TLV1117LV25DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VS
TLV1117LV25DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VS
TLV1117LV28DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VT
TLV1117LV28DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VT
TLV1117LV30DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VU
TLV1117LV30DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 VU
TLV1117LV33DCYR ACTIVE SOT-223 DCY 4 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 TJ
TLV1117LV33DCYT ACTIVE SOT-223 DCY 4 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 TJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV1117LV12DCYR SOT-223 DCY 4 2500 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV12DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV12DCYT SOT-223 DCY 4 250 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV12DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV15DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV15DCYR SOT-223 DCY 4 2500 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV15DCYT SOT-223 DCY 4 250 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV15DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV18DCYR SOT-223 DCY 4 2500 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV18DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV18DCYT SOT-223 DCY 4 250 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV18DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV25DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV25DCYR SOT-223 DCY 4 2500 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV25DCYT SOT-223 DCY 4 250 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV25DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
Pack Materials-Page 1
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jun-2022
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV1117LV28DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV28DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV30DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV30DCYR SOT-223 DCY 4 2500 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV30DCYT SOT-223 DCY 4 250 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV30DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV33DCYR SOT-223 DCY 4 2500 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV33DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
TLV1117LV33DCYT SOT-223 DCY 4 250 330.0 12.4 7.0 7.42 2.0 8.0 12.0 Q3
TLV1117LV33DCYT SOT-223 DCY 4 250 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV1117LV12DCYR SOT-223 DCY 4 2500 350.0 334.0 47.0
TLV1117LV12DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV12DCYT SOT-223 DCY 4 250 350.0 334.0 47.0
TLV1117LV12DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
TLV1117LV15DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV15DCYR SOT-223 DCY 4 2500 350.0 334.0 47.0
TLV1117LV15DCYT SOT-223 DCY 4 250 350.0 334.0 47.0
TLV1117LV15DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
TLV1117LV18DCYR SOT-223 DCY 4 2500 350.0 334.0 47.0
TLV1117LV18DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV18DCYT SOT-223 DCY 4 250 350.0 334.0 47.0
TLV1117LV18DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
TLV1117LV25DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV25DCYR SOT-223 DCY 4 2500 350.0 334.0 47.0
TLV1117LV25DCYT SOT-223 DCY 4 250 350.0 334.0 47.0
TLV1117LV25DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
TLV1117LV28DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV28DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
Pack Materials-Page 3
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Jun-2022
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV1117LV30DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV30DCYR SOT-223 DCY 4 2500 350.0 334.0 47.0
TLV1117LV30DCYT SOT-223 DCY 4 250 350.0 334.0 47.0
TLV1117LV30DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
TLV1117LV33DCYR SOT-223 DCY 4 2500 350.0 334.0 47.0
TLV1117LV33DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0
TLV1117LV33DCYT SOT-223 DCY 4 250 350.0 334.0 47.0
TLV1117LV33DCYT SOT-223 DCY 4 250 340.0 340.0 38.0
Pack Materials-Page 4
MEC MPDSOS‘IAi APFUL 20 PLASTIC DCY (R-PDSO-GA) 5.70(0.254) ' 5.30(0.24a) ' 7 3.10(0.122) y‘ 4 ' 2.e0(0 14) I a} 0.10(0.004)® 7.30 (0.207) 1 3.70 (0.145) 5.70 (0.254) 3.30 0.130) 1 1 Gauge Plane—L: 7 1 1 2% L T M °“-‘°“ 2.30(0.091) 1 ‘ a,55(0.026) L416!) (0.131) 0.10 (0.004) ® 1.70 (0.057) 1.30 (0.071) MAX 1.50 (0.050) Sealing Plane T 0.10 (0.0040) Q 0.00 (0.003) 0.02 (0.0000) 4202506/B 06/2002 *5 TEXAS INSTRUMENTS posw omca aox 555303 - DALLAS 15x45 75205
MECHANICAL DATA
MPDS094A – APRIL 2001 – REVISED JUNE 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE
4202506/B 06/2002
6,30 (0.248)
6,70 (0.264)
2,90 (0.114)
3,10 (0.122)
6,70 (0.264)
7,30 (0.287) 3,70 (0.146)
3,30 (0.130)
0,02 (0.0008)
0,10 (0.0040)
1,50 (0.059)
1,70 (0.067)
0,23 (0.009)
0,35 (0.014)
1 2 3
4
0,66 (0.026)
0,84 (0.033)
1,80 (0.071) MAX
Seating Plane
0°–10°
Gauge Plane
0,75 (0.030) MIN
0,25 (0.010)
0,08 (0.003)
0,10 (0.004) M
2,30 (0.091)
4,60 (0.181) M
0,10 (0.004)
NOTES: A. All linear dimensions are in millimeters (inches).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC TO-261 Variation AA.
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