EPC2010 Datasheet by EPC

eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 1
EPC2010
EPC2010 – Enhancement Mode Power Transistor
VDSS , 200 V
RDS(ON) , 25 mW
ID , 12 A
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag-
ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-
tron mobility and low temperature coefficient allows very low R
DS(ON)
, while its lateral device structure
and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are beneficial as well as
those where on-state losses dominate.
EPC2010 eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• HighSpeedDC-DCconversion
• ClassDAudio
• HardSwitchedandHighFrequencyCircuits
Benefits
• UltraHighEfficiency
• UltraLowRDS(on)
• UltralowQG
• Ultrasmallfootprint
EFFICIENT POWER CONVERSION
Maximum Ratings
V
DS
Drain-to-Source Voltage 200 V
I
D
Continuous (T
A
=25˚C, θ
JA
= 17)12A
Pulsed (25˚C, Tpulse = 300 µs) 60
V
GS
Gate-to-Source Voltage6
V
Gate-to-Source Voltage-5
T
J
Operating Temperature -40 to 125 ˚C
T
STG
Storage Temperature -40 to 150
NEW PRODUCT
HAL
Thermal Characteristics
R
θ
JC
Thermal Resistance, Junction to Case 2.4 ˚C/W
R
θ
JB
Thermal Resistance, Junction to Board 16 ˚C/W
R
θ
JA
Thermal Resistance, Junction to Ambient (Note 1) 56 ˚C/W
TYP
Note 1: R
θ
JA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (T
J
= 25˚C unless otherwise stated)
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 200 µA 200 V
I
DSS
Drain Source Leakage V
DS
= 160 V, V
GS
= 0 V 50 150 µA
I
GSS
Gate-Source Forward Leakage V
GS
= 5 V 1 3 mA
Gate-Source Reverse Leakage V
GS
= -5 V 0.2 1
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 3 mA 0.7 1.4 2.5 V
R
DS(ON)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 6 A 18 25 mΩ
Dynamic Characteristics (T
J
= 25˚C unless otherwise stated)
C
ISS
Input Capacitance
V
DS
= 100 V, V
GS
= 0 V
V
DS
= 100 V, V
GS
= 0 V
480
pFC
OSS
Output Capacitance 270
C
RSS
Reverse Transfer Capacitance 9.2
540
350
12
Q
G
Total Gate Charge (V
GS
= 5 V)
V
DS
= 100 V, I
D
= 12 A
5
nC
Q
GD
Gate to Drain Charge 1.7
Q
GS
Gate to Source Charge 1.3
Q
OSS
Output Charge 40
7.5
2.6
2
50
Q
RR
Source-Drain Recovery Charge 0
Source-Drain Characteristics (T
J
= 25˚C unless otherwise stated)
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V, T = 25˚C 1.8
1.8 V
I
S
= 0.5 A, V
GS
= 0 V, T = 125˚C
All measurements were done with substrate shorted to source.
All measurements were done with substrate shorted to source.
o 0.5 1.5 2 25 3 as 1 15 z 25 3 35 4 4. our as —G ta (eV 92 2 25 3 3s 4 45 s 5 z 25 3 3s 4 45 s s v eéu 2V (in
eGaN® FET DATASHEET
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EPC2010
ID – Drain Current (A)
VDS – Drain to Source Voltage (V)
50
60
40
30
20
10
00 0.5 1 1.5 2 2.5 3
ID – Drain Current (A)
VGS – Gate to Source Voltage (V)
40
50
60
30
20
10
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
25˚C
125˚C
VDS = 3 V
RDS(ON) – Drain to Source Resistance (mΩ)
VGS – Gate to Source Voltage (V)
50
60
40
30
20
10
02.5 23 3.5 4 4.5 5 5.5
ID = 10 A
ID = 20 A
ID = 40 A
ID = 60 A
RDS(ON) – Drain to Source Resistance (mΩ)
VGS – Gate to Source Voltage (V)
Figure 1: Typical Output Characteristics Figure 2: Transfer Characteristics
Figure 3: RDS(ON) vs VG for Various Current Figure 4: RDS(ON) vs VG for Various Temperature
VGS = 5
VGS = 4
VGS = 3
VGS = 2
50
60
40
30
20
10
02.5 23 3.5 4 4.5 5 5.5
25˚C
125˚C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (T
J
= 25˚C unless otherwise stated)
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 200 µA 200 V
I
DSS
Drain Source Leakage V
DS
= 160 V, V
GS
= 0 V 50 150 µA
I
GSS
Gate-Source Forward Leakage V
GS
= 5 V 1 3 mA
Gate-Source Reverse Leakage V
GS
= -5 V 0.2 1
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 3 mA 0.7 1.4 2.5 V
R
DS(ON)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 6 A 18 25 mΩ
Dynamic Characteristics (T
J
= 25˚C unless otherwise stated)
C
ISS
Input Capacitance
V
DS
= 100 V, V
GS
= 0 V
V
DS
= 100 V, V
GS
= 0 V
480
pFC
OSS
Output Capacitance 270
C
RSS
Reverse Transfer Capacitance 9.2
540
350
12
Q
G
Total Gate Charge (V
GS
= 5 V)
V
DS
= 100 V, I
D
= 12 A
5
nC
Q
GD
Gate to Drain Charge 1.7
Q
GS
Gate to Source Charge 1.3
Q
OSS
Output Charge 40
7.5
2.6
2
50
Q
RR
Source-Drain Recovery Charge 0
Source-Drain Characteristics (T
J
= 25˚C unless otherwise stated)
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V, T = 25˚C 1.8
1.8 V
I
S
= 0.5 A, V
GS
= 0 V, T = 125˚C
All measurements were done with substrate shorted to source.
All measurements were done with substrate shorted to source.
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eGaN® FET DATASHEET
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EPC2010
ISD – Source to Drain Current (A)
VSD – Source to Drain Voltage (V)
10
20
30
40
50
60
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
25˚C
125˚C
Normalized On-State Resistance – RDS(ON)
TJ – Junction Temperature ( ˚C )
0
0.5
1
1.5
2
2.5
3
-20 0 20 40 60 80 100 120 140
ID = 12 A
VGS = 5 V
Normalized Threshold Voltage (V)
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
-20 0 20 40 60 80 100 120 140
ID = 3 mA
IG – Gate Current (A)
VGS – Gate-to-Source Voltage (V)
.03
.025
.02
.015
.01
.005
00 1 2 3 4 5 6
25˚C
125˚C
Figure 7: Reverse Drain-Source Characteristics Figure 8: Normalized On Resistance vs Temperature
Figure 10: Gate CurrentFigure 9: Normalized Threshold Voltage vs Temperature
TJ – Junction Temperature ( ˚C )
C – Capacitance (nF)
VDS – Drain to Source Voltage (V)
0
0.2
0.4
0.6
0.8
1
0 50 100 150 200
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
QG – Gate Charge (nC)
5
4
3
2
1
00 1 2 3 4 5 6
ID = 12 A
VD = 100 V
Figure 5: Capacitance Figure 6: Gate Charge
VG – Gate Voltage (V)
All measurements were done with substrate shortened to source.
Du Factors: fir T "T— Single Pulse
eGaN® FET DATASHEET
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EPC2010
Figure 11: Transient Thermal Response Curves
Figure 12: Safe Operating Area
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001
0.0001
10-5 10-4 10-3 10-2 10-1 1 10 100
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
ZθJC, Normalized Thermal Impedance
10-5
10-6 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.1
1
10
100
0.1 1 10 100 1000
ID- Drain Current (A)
VDS - Drain-Source Voltage (V)
limited by RDS(ON)
TJ = Max Rated, TC = +25°C, Single Pulse
10 µs
100 µs
1 ms
10 ms
100 ms/DC
1 144 WP I!—
eGaN® FET DATASHEET
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EPC2010
DIE OUTLINE
Solder Bar View
Side View
DIM MIN Nominal MAX
A3524 3554 3584
B1602 1632 1662
c1379 1382 1385
d577 580 583
e262 277 292
f245 250 255
g600 600 600
MICROMETERS
B
A
d
X2
c
e g
g
X4
f f
X5
815 Max
100 +/- 20
SEATING PLANE
(685)
2 3 4567
1
DIE MARKINGS
a
d e f g
c
b
EPC2010 (note 1)
Dimension (mm) target min max
a 12.0 11.9 12.3
b 1.75 1.65 1.85
c (note 2) 5.50 5.45 5.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
TAPE AND REEL CONFIGURATION
4mm pitch, 12mm wide tape on 7” reel
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
7” reel
Loaded Tape Feed Direction
Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
2010
YYYY
ZZZZ
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2010 2010 YYYY ZZZZ
Die orientation dot
Gate Pad solder bar
is under this corner
NME —> Nam $2 —><7>
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 6
EPC2010
Information subject to
change without notice.
Revised February, 2013
RECOMMENDED
LAND PATTERN
(units in µm) Pad no. 1 is Gate;
Pads no. 3, 5, 7 are Drain;
Padsno.4,6areSource;
Pad no. 2 is Substrate
802
134
2
567
600 600
X4
X5
1632
3554
230
1362
560
230
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patent 8,350,294
The land pattern is solder mask defined.