EPC2001 Datasheet by EPC

JIM
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 1
EPC2001
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag-
ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-
tron mobility and low temperature coefficient allows very low R
DS(ON)
, while its lateral device structure
and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are beneficial as well as
those where on-state losses dominate.
EPC2001 eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• HighSpeedDC-DCconversion
• ClassDAudio
• HardSwitchedandHighFrequencyCircuits
Benefits
• UltraHighEfficiency
• UltraLowRDS(on)
• UltralowQG
• Ultrasmallfootprint
EFFICIENT POWER CONVERSION
HAL
EPC2001 – Enhancement Mode Power Transistor
VDSS , 100 V
RDS(ON) , 7 mW
ID , 25 A
NEW PRODUCT
Maximum Ratings
V
DS
Drain-to-Source Voltage (up to 10,000 5ms pulses at 125° C) 120 V
Drain-to-Source Voltage (Continuous) 100 V
I
D
Continuous (T
A
= 25˚C, θ
JA
= 13) 25 A
Pulsed (25˚C, Tpulse = 300 µs) 100
V
GS
Gate-to-Source Voltage 6 V
Gate-to-Source Voltage -5
T
J
Operating Temperature -40 to 125 ˚C
T
STG
Storage Temperature -40 to 150
Thermal Characteristics
R
θ
JC
Thermal Resistance, Junction to Case 2.1 ˚C/W
R
θ
JB
Thermal Resistance, Junction to Board 15 ˚C/W
R
θ
JA
Thermal Resistance, Junction to Ambient (Note 1) 54 ˚C/W
TYP
Note 1: R
θ
JA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
PARAMETER TEST CONDITIONS MINTYP MAX UNIT
Static Characteristics (T
J
= 25˚C unless otherwise stated)
BV
DSS
Drain-to-Source VoltageV
GS
= 0 V, I
D
= 300 µA 100 V
I
DSS
Drain Source LeakageV
DS
= 80 V, V
GS
= 0 V 100 250 µA
I
GSS
Gate-Source Forward LeakageV
GS
= 5
V1
5mA
Gate-Source Reverse LeakageV
GS
= -5 V 0.2 1
V
GS(th)
Gate Threshold VoltageV
DS
= V
GS
, I
D
= 5 mA 0.7 1.4 2.5 V
R
DS(ON)
Drain-Source On ResistanceV
GS
= 5 V, I
D
= 25 A 5.6
7m
Ω
Source-Drain Characteristics (T
J
= 25˚C unless otherwise stated)
V
SD
Source-Drain Forward Voltage I
S
= 0.5 A, V
GS
= 0 V, T = 25˚C
1.8 V
I
S
= 0.5 A, V
GS
= 0 V, T = 125˚C
1.75
All measurements were done with substrate shorted to source.
—Vm:5 _vm:4 0.2 M 0.5 as 1 n 1.4 1.5 18 z 05 15 z 2.5 3 2.5 v Drai Sn eVo ge( 4n Ime ag 2.5 3 15 4 45 5 5. v no :v (V)
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 2
EPC2001
ID – Drain Current (A)
VDS Drain to Source Voltage (V)
100
90
80
70
60
50
40
30
20
10
00 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VGS
GS
GS
GS
= 5
V = 4
V = 3
V = 2
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
100
80
60
40
20
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
25˚C
125˚C
RDS(ON) – Drain to Source Resistance (mΩ)
RDS(ON) – Drain to Source Resistance (mΩ)
VGS – Gate to Source Voltage (V)
16
18
20
14
12
10
8
6
4
2
0
2.5 2 3 3.5 4 4.5 5 5.5
ID = 10 A
ID = 20 A
ID = 40 A
ID = 80 A
VGS Gate-to-Source Voltage (V)
20
15
10
5
0
2.5 2 3 3.5 4 4.5 5 5.5
ID = 25 A
VDS = 3V
25˚C
125˚C
C – Capacitance (nF)
VDS Drain to Source Voltage (V)
1.4
1.2
1
0.8
0.6
0.4
0.2
00 10 20 30 40 50 60 70 80 90 100
VGS Gate to Source Voltage (V)
QG – Gate Charge (nC)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0 2 4 6 8 10
ID = 25 A
VDS = 50 V
Figure 1: Typical Output Characteristics Figure 2: Transfer Characteristics
Figure 3: RDS(on) vs VGS for Various Current Figure 4: RDS(on) vs VGS for Various Temperature
Figure 5: Capacitance Figure 6: Gate Charge
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Characteristics (T
J
= 25˚C unless otherwise stated)
C
ISS
Input Capacitance
V
DS
= 50 V, V
GS
= 0 V
850
pFC
OSS
Output Capacitance 450
C
RSS
Reverse Transfer Capacitance 20
Q
G
Total Gate Charge (V
GS
= 5 V)
V
DS
= 50 V, I
D
= 25 A
V
DS
= 50 V, V = 0 V
GS
8
nC
Q
GD
Gate to Drain Charge 2.2
Q
GS
Gate to Source Charge 2.3
Q
OSS
Output Charge 35
Q
RR
Source-Drain Recovery Charge 0
950
525
30
10
2.7
2.8
40
0
All measurements were done with substrate shorted to source.
:ZSA :sv 0 ms
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 3
EPC2001
ID – Drain Current (A)
VDS – Drain to Source Voltage (V)
100
90
80
70
60
50
40
30
20
10
00 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VGS
GS
GS
GS
= 5
V = 4
V = 3
V = 2
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
100
80
60
40
20
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
25˚C
125˚C
RDS(ON) – Drain to Source Resistance (mΩ)
RDS(ON) – Drain to Source Resistance (mΩ)
VGS – Gate to Source Voltage (V)
16
18
20
14
12
10
8
6
4
2
0
2.5 2 3 3.5 4 4.5 5 5.5
ID = 10 A
ID = 20 A
ID = 40 A
ID = 80 A
VGS Gate-to-Source Voltage (V)
20
15
10
5
0
2.5 2 3 3.5 4 4.5 5 5.5
ID = 25 A
VDS = 3V
25˚C
125˚C
C – Capacitance (nF)
VDS – Drain to Source Voltage (V)
1.4
1.2
1
0.8
0.6
0.4
0.2
00 10 20 30 40 50 60 70 80 90 100
VGS Gate to Source Voltage (V)
QG – Gate Charge (nC)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0 2 4 6 8 10
ID = 25 A
VDS = 50 V
Figure 1: Typical Output Characteristics Figure 2: Transfer Characteristics
Figure 3: RDS(on) vs VGS for Various Current Figure 4: RDS(on) vs VGS for Various Temperature
Figure 5: Capacitance Figure 6: Gate Charge
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
ISD – Source to Drain Current (A)
VSD – Source to Drain Voltage (V)
10
20
30
40
50
60
70
80
90
100
25˚C
125˚C
Normalized On-State Resistance – RDS(ON)
TJ – Junction Temperature ( ˚C )
1.6
1.7
1.8
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
-20 0 20 40 60 80 100 120 140
ID = 25 A
VGS = 5 V
IG – Gate Current (A)
VGS – Gate-to-Source Voltage (V)
0.025
0.02
0.015
0.01
0.005
00 1 2 3 4 5 6
25˚C
125˚C
Normalized Threshold Voltage
0.95
1
1.05
1.1
1.15
1.2
0.9
-20 0 20 40 60 80 100 120 140
ID = 5 mA
Figure 7: Reverse Drain-Source Characteristics Figure 8: Normalized On Resistance Vs Temperature
Figure 9: Normalized Threshold Voltage vs. Temperature Figure 10: Gate Current
TJ – Junction Temperature ( ˚C )
All measurements were done with substrate shortened to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 4
EPC2001
Figure 11: Transient Thermal Response Curves
Figure 12: Safe Operating Area
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001
0.0001
10-5 10-4 10-3 10-2 10-1 1 10 100
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Duty Factors:
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001
ZθJC, Normalized Thermal Impedance
10-5
10-6 10-4 10-3 10-2 10-1 1
0.1
1
10
100
0.1 1 10 100 1000
ID- Drain Current (A)
VDS - Drain-Source Voltage (V)
limited by RDS(ON)
TJ = Max Rated, TC = +25°C, Single Pulse
10 µs
100 µs
1 ms
10 ms
100 ms/DC
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eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 5
EPC2001
815 Max
100 +/- 20
SEATING PLANE
(685)
B
A
d
X2
c
e g
3 4 5 7 6 9
8 10 11
g
X8
f f
X9
2
1
DIE OUTLINE
Solder Bar View
Side View
DIM MICROMETERS
MIN Nominal MAX
A 4075 4105 4135
B 1602 1632 1662
c 1379 1382 1385
d 577 580 583
e 235 250 265
f 195 200 205
g 400 400 400
TAPE AND REEL CONFIGURATION
4mm pitch, 12mm wide tape on 7” reel
a
d e f g
c
b
EPC2001 (note 1)
Dimension (mm) target min max
a 12.0 11 .7 12.3
b 1.75 1.65 1.85
c (note 2) 5.50 5.45 5.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
7” reel
Loaded Tape Feed Direction
2001
YYYY
ZZZZ
Die orientation dot
Gate Pad solder bar
is under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2001 2001 YYYY ZZZZ
DIE MARKINGS
m we 4w xx 4m w): :2
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2013 | | PAGE 6
EPC2001
1362
560
180 180
X9
X2
RECOMMENDED
LAND PATTERN
(units in µm)
Pad no. 1 is Gate;
Padsno.3,5,7,9,11areDrain;
Padsno.4,6,8,10areSource;
Pad no. 2 is Substrate.
Information subject to
change without notice.
Revised January, 2013
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
The land pattern is solder mask defined.