MC68HC908JB8,08JB8,08JT8, Datasheet by Freescale Semiconductor - NXP

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M68HC08
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MC68HC908JB8
MC68HC08JB8
MC68HC08JT8
Technical Data
MC68HC908JB8/D
Rev. 2.3
9/2005
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor 3
MC68HC908JB8
MC68HC08JB8
MC68HC08JT8
Technical Data
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The following revision history table summarizes changes contained in
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have been linked to the appropriate location.
Freescale and the Freescale logo are registered trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Revision History
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
4Freescale Semiconductor
Revision History
Date Revision
Level Description Page
Number(s)
September
2005 2.3 Added Pb-free parts. 267, 284
August
2005 2.2 Updated to meet Freescale identity guidelines. Throughout
December
2003 2.1
4.9 ROM-Resident Routines — Removed block erase
references for ROM-resident routines. 61
9.8.8 USB Control Register 3 — Clarified bit descriptions for
OSTALL0 and ISTALL0. 149, 150
9.8.11 USB Status Register 1 — Clarified bit descriptions for
TXACK, TXNAK, and TXSTL. 153
Section 19. Mechanical Specifications — Replaced incorrect
44-pin QFP drawing, case 824E to case 824A. 263
February
2002 2
Corrected PTD6 and PTD7: not direct LED drive pins. 28, 210, 217
Removed incorrect RX1E text from USB control register 1. 146
Corrected Figure 9-30 for USB module. 159
Corrected timer discrepancies throughout Section 11. Timer
Interface Module (TIM).177
Added Table 12-1 . Port Control Register Bits Summary.201
Changed pullup resistor limits for D– and I/O ports in
18.6 DC Electrical Characteristics.256
Added mechanical drawing for 20-pin SOIC package. 266
Added Appendix A. MC68HC08JB8 — ROM part. 269
Added Appendix B. MC68HC08JT8 — low-voltage ROM part. 277
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor List of Sections 5
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 27
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 3. Random-Access Memory (RAM) . . . . . . . . . . 51
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . .53
Section 5. Configuration Register (CONFIG) . . . . . . . . .65
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 69
Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . .89
Section 8. System Integration Module (SIM) . . . . . . . . .93
Section 9. Universal Serial Bus Module (USB). . . . . . . 117
Section 10. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 163
Section 11. Timer Interface Module (TIM) . . . . . . . . . . .177
Section 12. Input/Output Ports (I/O) . . . . . . . . . . . . . . . 199
Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . . 219
Section 14. Keyboard Interrupt Module (KBI). . . . . . . . 227
Section 15. Computer Operating Properly (COP) . . . .237
Section 16. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . .243
Section 17. Break Module (BREAK) . . . . . . . . . . . . . . .245
Section 18. Electrical Specifications. . . . . . . . . . . . . . . 253
Section 19. Mechanical Specifications . . . . . . . . . . . . .263
Section 20. Ordering Information . . . . . . . . . . . . . . . . . 267
Appendix A. MC68HC08JB8. . . . . . . . . . . . . . . . . . . . . . 269
Appendix B. MC68HC08JT8 . . . . . . . . . . . . . . . . . . . . . .277
List of Sections
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Table of Contents 7
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.5.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . .34
1.5.2 Voltage Regulator Out (VREG) . . . . . . . . . . . . . . . . . . . . . . .34
1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35
1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . .35
1.5.5 External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . .35
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0). .36
1.5.7 Port B (I/O) Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . .36
1.5.8 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . .36
1.5.9 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . .36
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . . .36
Section 2. Memory Map
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
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8 Table of Contents Freescale Semiconductor
Section 3. Random-Access Memory (RAM)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 4. FLASH Memory
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .56
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .57
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .60
4.9 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.9.1 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.9.2 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.9.3 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.9.4 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 5. Configuration Register (CONFIG)
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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Section 6. Central Processor Unit (CPU)
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Section 7. Oscillator (OSC)
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.3 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . .91
7.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . .91
7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . .91
7.4.4 External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . .91
7.4.5 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.6 Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . .92
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10 Table of Contents Freescale Semiconductor
Section 8. System Integration Module (SIM)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .96
8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . .97
8.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .97
8.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .97
8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .99
8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . .101
8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . .102
8.4.2.6 Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . .102
8.4.2.7 Registers Values After Different Resets. . . . . . . . . . . . .102
8.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . .103
8.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . .104
8.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . .104
8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
8.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . .108
8.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . .109
8.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .110
8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
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8.8.1 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8.8.2 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
8.8.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .116
Section 9. Universal Serial Bus Module (USB)
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9.5.1 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.5.1.1 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9.5.1.2 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.5.1.3 Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.5.1.4 Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . .128
9.5.1.5 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . .128
9.5.1.6 End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . .128
9.5.2 Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.5.3 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
9.5.4 Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.4.1 Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.4.2 USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.4.3 Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
9.5.5 Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.6 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.7 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.7.1 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.7.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
9.7.2.1 Output Driver Characteristics. . . . . . . . . . . . . . . . . . . . .134
9.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . .134
9.7.2.3 Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.7.2.4 Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
9.7.2.5 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .136
9.7.3 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
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9.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .139
9.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .141
9.8.4 USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .144
9.8.5 USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.8.6 USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .146
9.8.7 USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9.8.8 USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.8.9 USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
9.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
9.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . .154
9.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . .155
9.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . .156
9.9 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
9.9.1 USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . .157
9.9.1.1 Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . .158
9.9.1.2 Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . .160
9.9.1.3 Transmit Endpoint 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .161
9.9.1.4 Transmit Endpoint 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .162
9.9.1.5 Receive Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
9.9.2 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
9.9.3 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .162
Section 10. Monitor ROM (MON)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
10.4.2 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
10.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10.4.4 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10.4.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
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10.4.6 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Section 11. Timer Interface Module (TIM)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
11.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
11.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .182
11.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .183
11.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .183
11.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .184
11.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .185
11.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
11.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
11.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .188
11.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
11.9.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .189
11.9.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) . . . . . . .189
11.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
11.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .190
11.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
11.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .193
11.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .194
11.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .198
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Section 12. Input/Output Ports (I/O)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . .203
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . .205
12.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
12.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
12.5.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . .208
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
12.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . .211
12.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
12.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
12.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . .215
12.8 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
12.8.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . .217
Section 13. External Interrupt (IRQ)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
13.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
13.6 PTE4/D– Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
13.7 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .223
13.8 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .224
13.9 IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . .225
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Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
14.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
14.6 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
14.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .233
14.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
14.9.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . .233
14.9.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . .235
Section 15. Computer Operating Properly (COP)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
15.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .240
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
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15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .242
Section 16. Low Voltage Inhibit (LVI)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.4 LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .244
16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Section 17. Break Module (BREAK)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . .248
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .248
17.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .248
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .248
17.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .249
17.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .250
17.6.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
17.6.4 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . .252
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Section 18. Electrical Specifications
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .254
18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .255
18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
18.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .256
18.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
18.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
18.9 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .258
18.10 USB Low-Speed Source Electrical Characteristics . . . . . . . .259
18.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
18.12 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . .260
18.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Section 19. Mechanical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
19.3 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .264
19.4 28-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . .265
19.5 20-Pin Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . .265
19.6 20-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . .266
Section 20. Ordering Information
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
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Appendix A. MC68HC08JB8
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A.5 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
A.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
A.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
A.7.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .274
A.7.2 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .275
A.8 MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .275
Appendix B. MC68HC08JT8
B.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
B.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B.5 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
B.6 Reserved Register Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
B.7 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
B.8 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
B.9 Universal Serial Bus Module. . . . . . . . . . . . . . . . . . . . . . . . . .282
B.10 Low-Voltage Inhibit Module . . . . . . . . . . . . . . . . . . . . . . . . . .282
B.11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
B.11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .282
B.11.2 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . .283
B.11.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .283
B.11.4 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
B.11.5 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .284
B.12 MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .284
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
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Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Figures
Figure Title Page
1-1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1-2 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .32
1-3 28-pin SOIC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .33
1-4 20-pin PDIP and SOIC Pin Assignments . . . . . . . . . . . . . . . . .33
1-5 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
1-6 Regulator Supply Capacitor Configuration . . . . . . . . . . . . . . . .35
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2-2 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .42
4-1 FLASH Memory Register Summary . . . . . . . . . . . . . . . . . . . . .54
4-2 FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .55
4-3 FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .59
4-4 FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .60
4-5 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .60
5-1 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . .66
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6-3 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .74
7-1 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90
8-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8-3 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
List of Figures
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
20 List of Figures Freescale Semiconductor
Figure Title Page
8-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8-8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
8-9 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
8-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
8-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .107
8-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .109
8-13 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8-14 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . .111
8-15 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .111
8-16 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8-17 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . .113
8-18 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . .113
8-19 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . .115
8-20 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .116
9-1 USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .120
9-2 USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
9-3 Supported Transaction Types Per Endpoint. . . . . . . . . . . . . .125
9-4 Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . .126
9-5 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9-6 SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . .127
9-7 EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . .129
9-8 EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9-9 External Low-Speed Device Configuration . . . . . . . . . . . . . . .132
9-10 Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . . . .133
9-11 Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9-12 Differential Input Sensitivity Range. . . . . . . . . . . . . . . . . . . . .135
9-13 Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
9-14 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . .136
9-15 USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . . . .138
9-16 USB Interrupt Register 0 (UIR0) . . . . . . . . . . . . . . . . . . . . . . .139
9-17 USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . .141
9-18 USB Interrupt Register 2 (UIR2) . . . . . . . . . . . . . . . . . . . . . . .144
List of Figures
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor List of Figures 21
Figure Title Page
9-19 USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . .145
9-20 USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . .146
9-21 USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . .147
9-22 USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . .149
9-23 USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . .151
9-24 USB Status Register 0 (USR0). . . . . . . . . . . . . . . . . . . . . . . .152
9-25 USB Status Register 1 (USR1). . . . . . . . . . . . . . . . . . . . . . . .153
9-26 USB Endpoint 0 Data Registers (UE0D0–UE0D7). . . . . . . . .154
9-27 USB Endpoint 1 Data Registers (UE1D0–UE1D7). . . . . . . . .155
9-28 USB Endpoint 2 Data Registers (UE2D0–UE2D7). . . . . . . . .156
9-29 OUT Token Data Flow for Receive Endpoint 0. . . . . . . . . . . .158
9-30 SETUP Token Data Flow for Receive Endpoint 0 . . . . . . . . .159
9-31 IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . . . .160
9-32 IN Token Data Flow for Transmit Endpoint 1 . . . . . . . . . . . . .161
10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
10-2 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .168
10-3 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-4 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-5 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
10-6 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
10-7 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .175
11-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
11-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .180
11-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .184
11-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .190
11-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .192
11-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .193
11-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . .194
11-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
11-9 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . .198
12-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .200
12-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .202
12-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .203
List of Figures
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
22 List of Figures Freescale Semiconductor
12-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
12-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .204
12-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .205
12-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
12-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .207
12-9 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .208
12-10 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .210
12-12 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .211
12-13 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
12-14 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .213
12-15 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .215
12-16 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
12-17 Port Option Control Register (POCR). . . . . . . . . . . . . . . . . . .217
13-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .221
13-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .221
13-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .224
13-4 IRQ Option Control Register (IOCR) . . . . . . . . . . . . . . . . . . .225
14-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .229
14-2 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .234
14-3 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .235
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
15-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .240
15-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .241
16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .244
17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .247
17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .247
17-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .249
17-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .250
17-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .250
17-6 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . .251
17-7 Break Flag Control Register High (BFCR) . . . . . . . . . . . . . . .252
List of Figures
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor List of Figures 23
Figure Title Page
19-1 44-Pin QFP (Case #824E) . . . . . . . . . . . . . . . . . . . . . . . . . . .264
19-2 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .265
19-3 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
19-4 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . .266
A-1 MC68HC08JB8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .271
A-2 MC68HC08JB8 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . .272
B-1 MC68HC08JT8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .279
B-2 MC68HC08JT8 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . .280
B-3 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
List of Figures
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
24 List of Figures Freescale Semiconductor
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor List of Tables 25
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
List of Tables
Table Title Page
1-1 Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4-1 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4-2 ROM-Resident Routine Variables. . . . . . . . . . . . . . . . . . . . . . .62
4-3 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4-4 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4-5 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
8-1 SIM Module Signal Name Conventions . . . . . . . . . . . . . . . . . .95
8-2 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8-3 Registers not Affected by Normal Reset. . . . . . . . . . . . . . . . .103
8-4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9-1 USB Module Pin Name Conventions . . . . . . . . . . . . . . . . . . .120
9-2 Supported Packet Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . .127
10-1 Mode Entry Requirements and Options . . . . . . . . . . . . . . . . .166
10-2 Monitor Mode Vector Differences . . . . . . . . . . . . . . . . . . . . . .169
10-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .169
10-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .172
10-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .172
10-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .173
10-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .173
10-8 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .174
10-9 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . .174
List of Tables
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
26 List of Tables Freescale Semiconductor
11-1 TIM Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .178
11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
11-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .196
12-1 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .201
12-2 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
12-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
12-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
12-6 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
14-1 KBI Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .228
14-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
A-1 Summary of MC68HC08JB8 and MC68HC908JB8
Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
A-2 MC68HC08JB8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .275
B-1 Summary of MC68HC08JT8 and MC68HC908JB8
Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
B-2 MC68HC08JT8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . .284
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor General Description 27
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.5.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . .34
1.5.2 Voltage Regulator Out (VREG) . . . . . . . . . . . . . . . . . . . . . . .34
1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .35
1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . .35
1.5.5 External Interrupt Pins (IRQ, PTE4/D–) . . . . . . . . . . . . . . . .35
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0). .36
1.5.7 Port B (I/O) Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . .36
1.5.8 Port C I/O Pins (PTC7–PTC0) . . . . . . . . . . . . . . . . . . . . . . .36
1.5.9 Port D I/O Pins (PTD7–PTD0) . . . . . . . . . . . . . . . . . . . . . . .36
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1,
PTE1/TCH0, PTE0/TCLK). . . . . . . . . . . . . . . . . . . . . . . .36
1.2 Introduction
The MC68HC908JB8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.
General Description
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
28 General Description Freescale Semiconductor
1.3 Features
Features of the MC68HC908JB8 include:
High-performance M68HC08 architecture
Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families
3-MHz internal bus frequency
8,192 bytes of on-chip FLASH memory
256 bytes of on-chip random-access memory (RAM)
FLASH program memory security1
On-chip programming firmware for use with host PC computer
Up to 37 general-purpose 3.3V input/output (I/O) pins, including:
13 or 10 shared-function I/O pins, depending on package
24, 8, or 2 dedicated I/O pins, depending on package
8 keyboard interrupts on port A, on all packages
10mA sink capability for normal LED on 4 pins
25mA sink capability for infrared LED on 2 pins
10mA sink capability for PS/2 connection on 2 pins
(with USB module disabled)
16-bit, 2-channel timer interface module (TIM) with selectable
input capture, output compare, PWM capability on each channel,
and external clock input option (TCLK)
Full Universal Serial Bus Specification 1.1 low-speed functions:
1.5 Mbps data rate
On-chip 3.3V regulator
Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer
Endpoint 1 with 8-byte transmit buffer
Endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
General Description
Features
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor General Description 29
System protection features:
Optional computer operating properly (COP) reset
Optional low-voltage detection with reset
Illegal opcode detection with reset
Illegal address detection with reset
Low-power design (fully static with stop and wait modes)
Master reset pin with internal pullup and power-on reset
External interrupt pin with programmable internal pullup (IRQ)
44-pin quad flat pack (QFP), 28-pin small outline integrated circuit
package (SOIC), 20-pin small outline integrated circuit package
(SOIC), and 20-pin plastic dual in-line package (DIP)
Specific features of MC68HC908JB8 in 44-pin are:
Port B is 8 bits: PTB0–PTB7
Port C is 8 bits: PTC0–PTC7
Port D is 8 bits: PTD0–PTD7
Port E is 5 bits: PTE0–PTE4;
2-channel TIM module with TCLK input option
Specific features of MC68HC908JB8 in 28-pin are:
Port B is not available
Port C is only one bit: PTC0
Port D is only 7 bits: PTD0–PTD6
Port E is 5 bits: PTE0–PTE4;
2-channel TIM module with TCLK input option
Specific features of MC68HC908JB8 in 20-pin are:
Port B is not available
Port C is only one bit: PTC0
Port D is only one bit: PTD0/1; internal PTD0 and PTD1 pads
are bonded together to a single pin, PTD0/1
Port E is only 3 bits: PTE1, PTE3, and PTE4;
1-channel TIM module without TCLK input option
General Description
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
30 General Description Freescale Semiconductor
Features of the CPU08 include the following:
Enhanced HC05 programming model
Extensive loop control functions
16 addressing modes (eight more than the HC05)
16-bit index register and stack pointer
Memory-to-memory data transfers
Fast 8 × 8 multiply instruction
Fast 16/8 divide instruction
Binary-coded decimal (BCD) instructions
Optimization for controller applications
Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908JB8.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor General Description 31
General Description
MCU Block Diagram
Figure 1-1. MCU Block Diagram
SYSTEM INTEGRATION
MODULE
TIMER INTERFACE
MODULE
LOW VOLTAGE INHIBIT
MODULE
COMPUTER OPERATING PROPERLY
MODULE
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS — 64 BYTES
USER FLASH MEMORY — 8,192 BYTES
USER RAM — 256 BYTES
MONITOR ROM — 976 BYTES
USER FLASH VECTORS — 16 BYTES
IRQ
MODULE
POWER
PTA
DDRA
DDRE
PTE
INTERNAL BUS
OSC1
OSC2
(1), (2) RST
(1), (3) IRQ
VDD
VSS
PTA7/KBA7 (3)
PTE4/D– (3) (4) (5)
PTE3/D+ (3) (4) (5)
PTE2/TCH1 (3)
PTE1/TCH0 (3)
PTE0/TCLK (3)
PTB
DDRB
PTB7–PTB0 (3)
PTD
DDRD
PTD5–PTD2 (4) (5)
USB
MODULE
USB ENDPOINT 0, 1, 2
INTERNAL VOLTAGE REGULATOR
VREG
(3.3 V)
(1) Pins have 5V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pullup device.
(4) Pins are open-drain when configured as output.
(5) Pins have 10mA sink capability.
(6) Pins have 25mA sink capability.
LS USB
TRANSCEIVER
BREAK
MODULE
OSCILLATOR
PTC
DDRC
PTC7–PTC0 (3)
KEYBOARD INTERRUPT
MODULE
POWER-ON RESET
MODULE
PTD7–PTD6 (4)
PTD1–PTD0 (4) (6)
PTA0/KBA0 (3)
:
jjjjjjjjjjj TH—H—H—HTTH—H—H—HTH O UUUUUUUUUUU EEEEEEEEEEE
General Description
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
32 General Description Freescale Semiconductor
1.5 Pin Assignments
Figure 1-2. 44-Pin QFP Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
PTA2/KBA2
OSC2
OSC1
VSS
PTB3
PTB4
PTB5
PTB6
PTB7
RST
PTA0/KBA0
PTA1/KBA1PTA7/KBA7
PTA3/KBA3
PTC7
PTC6
PTC5
PTC4
PTE0/TCLK
PTE2/TCH1
PTA4/KBA4
PTA5/KBA5
PTA6/KBA6
PTE3/D+
PTE4/D–
PTC0
PTC1
PTC2
PTC3
IRQ
PTD5
VREG
VDD
PTB2
PTB1
PTD1
PTD2
PTD3
PTB0
PTD0
PTD4
PTE1/TCH0
PTD7
PTD6
i i i 3333333333333: 3333333333 EEEEEEEEEEEEEE EEEEEEEEEE
General Description
Pin Assignments
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor General Description 33
Figure 1-3. 28-Pin SOIC Pin Assignments
Figure 1-4. 20-Pin PDIP and SOIC Pin Assignments
NOTE: In 20-pin package, the PTD0 and PTD1 internal pads are bonded
together to PTD0/1 pin.
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
12
13
14
17
16
15
8
9
10
11
OSC1
IRQ
PTA0/KBA0
RST
PTA1/KBA1
PTA2/KBA2
PTA3/KBA3
PTE0/TCLK
PTE2/TCH1
PTA4/KBA4
PTA5/KBA5
PTA6/KBA6
PTA7/KBA7
PTD5
PTD6
OSC2
VREG
VDD
PTD0
PTD1
PTD2
PTD3
PTD4
PTE1/TCH0
PTE3/D+
PTE4/D–
PTC0
VSS
Pins not available on 28-pin package:
PTB0
PTB1 PTC1
PTB2 PTC2
PTB3 PTC3
PTB4 PTC4
PTB5 PTC5
PTB6 PTC6
PTB7 PTC7 PTD7
Internal pads are unconnected.
1
2
3
4
5
6
7
20
19
18
17
16
15
14
13
12
11
8
9
10
OSC1 PTA0/KBA0
RST
PTA1/KBA1
PTA2/KBA2
PTA3/KBA3
PTA4/KBA4
PTA5/KBA5
PTA6/KBA6
PTA7/KBA7
IRQ
OSC2
VREG
VDD
PTD0/1
PTE1/TCH0
PTE3/D+
PTE4/D–
PTC0
VSS
PTD0/1 pin: PTD0 and PTD1 internal pads are
bonded together to PTD0/1 pin.
Pins not available on 20-pin package:
PTB0 PTE0/TCLK
PTB1 PTC1
PTB2 PTC2 PTD2 PTE2/TCH1
PTB3 PTC3 PTD3
PTB4 PTC4 PTD4
PTB5 PTC5 PTD5
PTB6 PTC6 PTD6
PTB7 PTC7 PTD7
Internal pads are unconnected.
g4
General Description
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
34 General Description Freescale Semiconductor
1.5.1 Power Supply Pins (VDD, VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as Figure 1-5
shows. Place the bypass capacitors as close to the MCU power pins as
possible. Use high-frequency-response ceramic capacitors for CBYPASS.
CBULK are optional bulk current bypass capacitors for use in applications
that require the port pins to source high current levels.
Figure 1-5. Power Supply Bypassing
1.5.2 Voltage Regulator Out (VREG)
VREG is the 3.3 V output of the on-chip voltage regulator. VREG is used
internally for the MCU operation and the USB data driver. It is also used
to supply the voltage for the external pullup resistor required on the
USB’s D– line. The VREG pin requires an external bulk capacitor 4.7µF
or larger and a 0.1 µF ceramic bypass capacitor as Figure 1-6 shows.
Place the bypass capacitors as close to the VREG pin as possible.
MCU
CBULK
CBYPASS
0.1 µF
+
NOTE: Values shown are typical values.
VDD
VDD VSS
General Description
Pin Assignments
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor General Description 35
Figure 1-6. Regulator Supply Capacitor Configuration
1.5.3 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit.
1.5.4 External Reset Pin (RST)
A logic zero on the RST pin forces the MCU to a known start-up state.
RST is bidirectional, allowing a reset of the entire system. It is driven low
when any internal reset source is asserted. The RST pin contains an
internal pullup device to VDD. (See Section 8. System Integration
Module (SIM).)
1.5.5 External Interrupt Pins (IRQ, PTE4/D–)
IRQ is an asynchronous external interrupt pin. IRQ is also the pin to
enter monitor mode. The IRQ pin contains a software configurable pullup
device to VDD. PTE4/D– can be programmed to trigger the IRQ interrupt.
(See Section 13. External Interrupt (IRQ).)
MCU
VREG
CREGBULK
CREGBYPASS
0.1 µF
VSS
+
VREG
> 4.7 µF
General Description
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
36 General Description Freescale Semiconductor
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0)
PTA7/KBA7–PTA0/KBA0 are general-purpose bidirectional I/O port
pins. (See Section 12. Input/Output Ports (I/O).) Each pin contains a
software configurable pullup device to VREG when the pin is configured
as an input. (See 12.8 Port Options.) Each pin can also be programmed
as an external keyboard interrupt pin. (See Section 14. Keyboard
Interrupt Module (KBI).)
1.5.7 Port B (I/O) Pins (PTB7–PTB0)
PTB7–PTB0 are general-purpose bidirectional I/O port pins. Each pin
contains a software configurable pullup device to VREG when the pin is
configured as an input. (See 12.8 Port Options.)
1.5.8 Port C I/O Pins (PTC7–PTC0)
PTC7–PTC0 are general-purpose bidirectional I/O port pins. (See
Section 12. Input/Output Ports (I/O).) Each pin contains a software
configurable pullup device to VREG when the pin is configured as an
input. (See 12.8 Port Options.)
1.5.9 Port D I/O Pins (PTD7–PTD0)
PTD7–PTD0 are general-purpose bidirectional I/O port pins; open-drain
when configured as output. (See Section 12. Input/Output Ports (I/O).)
PTD5–PTD2 are software configurable to be 10mA sink pins for direct
LED connections. PTD1–PTD0 are software configurable to be 25mA
sink pins for direct infrared LED connections. (See 12.8 Port Options.)
1.5.10 Port E I/O Pins (PTE4/D–, PTE3/D+, PTE2/TCH1, PTE1/TCH0, PTE0/TCLK)
Port E is a 5-bit special function port that shares two of its pins with the
USB module and three of its pins with the timer interface module.
Each PTE2–PTE0 pin contains a software configurable pullup device to
VREG when the pin is configured as an input or output.
General Description
Pin Assignments
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor General Description 37
When the USB module is disabled, the PTE4 and PTE3 pins are
general-purpose bidirectional I/O port pins with 10mA sink capability.
Each pin is open-drain when configured as an output; and each pin
contains a software configurable 5kpullup to VDD when configured as
an input. The PTE4 pin can also be enabled to trigger the IRQ interrupt.
When the USB module is enabled, the PTE4/D– and PTE3/D+ pins
become the USB module D– and D+ pins. The D– pin contains a
software configurable 1.5kpullup to VREG. (See Section 11. Timer
Interface Module (TIM), Section 9. Universal Serial Bus Module
(USB) and Section 12. Input/Output Ports (I/O).)
Summary of the pin functions are provided in Table 1-1.
Table 1-1. Summary of Pin Functions
PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL
VDD Power supply. IN 4.0 to 5.5V
VSS Power supply ground. OUT 0V
VREG Regulated 3.3V output from MCU. OUT VREG (3.3V)
RST Reset input; active low.
With internal pullup to VDD and schmitt trigger input. IN/OUT VDD
IRQ
External IRQ pin; with programmable internal pullup to VDD
and schmitt trigger input. IN VDD
Used for mode entry selection. IN VREG to VDD+VHI
OSC1 Crystal oscillator input. IN VREG
OSC2 Crystal oscillator output; inverting of OSC1 signal. OUT VREG
PTA0/KBA0
:
PTA7/KBA7
8-bit general-purpose I/O port. IN/OUT VREG
Pins as keyboard interrupts, KBA0–KBA7.IN
VREG
Each pin has programmable internal pullup to VREG when
configured as input. IN VREG
PTB0–PTB7
8-bit general-purpose I/O port. IN/OUT VREG
Each pin has programmable internal pullup to VREG when
configured as input. IN VREG
General Description
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
38 General Description Freescale Semiconductor
PTC0–PTC7
8-bit general-purpose I/O port. IN/OUT VREG
Each pin has programmable internal pullup to VREG when
configured as input. IN VREG
PTD0–PTD7
8-bit general-purpose I/O port;
open-drain when configured as output.
IN
OUT
VREG
VREG or VDD
PTD0–PTD1 have configurable 25mA sink for infrared LED. OUT VREG or VDD
PTD2–PTD5 have configurable 10mA sink for LED. OUT VREG or VDD
PTE0/TCLK
PTE1/TCH0
PTE2/TCH1
PTE0–PTE2 are general-purpose I/O pins. IN/OUT VREG
PTE0–PTE2 have programmable internal pullup to VREG
when configured as input or output. IN/OUT VREG
PTE0 as TCLK of timer interface module. IN VREG
PTE1 as TCH0 of timer interface module. IN/OUT VREG
PTE2 as TCH1 of timer interface module. IN/OUT VREG
PTE3/D+
PTE4/D–
PTE3–PTE4 are general-purpose I/O pins;
open-drain when configured as output.
IN
OUT
VDD
VREG or VDD
PTE3–PTE4 have programmable internal pullup to VDD
when configured as input. IN VDD
PTE3 as D+ of USB module. IN/OUT VREG
PTE4 as D– of USB module. IN/OUT VREG
PTE4 as additional IRQ interrupt. IN VDD
Table 1-1. Summary of Pin Functions
PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Memory Map 39
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 2. Memory Map
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.2 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
8,192 bytes of user FLASH memory
256 bytes of RAM
16 bytes of user-defined vectors
976 bytes of monitor ROM
Memory Map
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
40 Memory Map Freescale Semiconductor
$0000
$003F
I/O Registers
64 Bytes
$0040
$013F
RAM
256 Bytes
$0140
$DBFF
Unimplemented
56,000 Bytes
$DC00
$FBFF
FLASH
8,192 Bytes
$FC00
$FDFF
Monitor ROM 1
512 Bytes
$FE00 Break Status Register (BSR)
$FE01 Reset Status Register (RSR)
$FE02 Reserved
$FE03 Break Flag Control Register (BFCR)
$FE04 Interrupt Status Register 1 (INT1)
$FE05 Reserved
$FE06 Reserved
$FE07 Reserved
$FE08 FLASH Control Register (FLCR)
$FE09 FLASH Block Protect Register (FLBPR)
$FE0A Reserved
$FE0B Reserved
$FE0C Break Address High Register (BRKH)
$FE0D Break Address Low Register (BRKL)
$FE0E Break Status and Control Register (BRKSCR)
$FE0F Reserved
$FE10
$FFDF
Monitor ROM 2
464 Bytes
$FFE0
$FFEF
Reserved
16 Bytes
$FFF0
$FFFF
FLASH Vectors
16 Bytes
Figure 2-1. Memory Map
Memory Map
I/O Section
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Memory Map 41
2.3 I/O Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
$FE00; break status register, BSR
$FE01; reset status register, RSR
$FE02; reserved
$FE03; break flag control register, BFCR
$FE04; interrupt status register 1, INT1
$FE05; reserved
$FE06; reserved
$FE07; reserved
$FE08; FLASH control register, FLCR
$FE09; FLASH block protect register, FLBPR
$FE0A; reserved
$FE0B; reserved
$FE0C; break Address Register High, BRKH
$FE0D; break Address Register Low, BRKL
$FE0E; break status and control register, BRKSCR
$FFFF; COP control register, COPCTL
2.4 Monitor ROM
The 512 bytes at addresses $FC00–$FDFF and 464 bytes at addresses
$FE10–$FFDF are reserved ROM addresses that contain the
instructions for the monitor functions. (See Section 10. Monitor ROM
(MON).)
Memory Map
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
42 Memory Map Freescale Semiconductor
Addr.Register Name Bit 7654321Bit 0
$0000 Port A Data Register
(PTA)
Read:
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001 Port B Data Register
(PTB)
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002 Port C Data Register
(PTC)
Read:
PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Write:
Reset: Unaffected by reset
$0003 Port D Data Register
(PTD)
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
$0004 Data Direction Register A
(DDRA)
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:0*0000000
* DDRA7 bit is reset by POR or LVI reset only.
$0005 Data Direction Register B
(DDRB)
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
$0006 Data Direction Register C
(DDRC)
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:00000000
$0007 Data Direction Register D
(DDRD)
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
Write:
Reset:00000000
$0008 Port E Data Register
(PTE)
Read: 0 0 0
PTE4 PTE3 PTE2 PTE1 PTE0
Write:
Reset: Unaffected by reset
$0009 Data Direction Register E
(DDRE)
Read: 0 0 0
DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Memory Map
Monitor ROM
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Memory Map 43
$000A
TIM Status and Control
Register
(TSC)
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$000B Unimplemented
Read:
Write:
$000C
TIM Counter Register
High
(TCNTH)
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$000D
TIM Counter Register
Low
(TCNTL)
Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:00000000
$000E
TIM Counter Modulo
Register High
(TMODH)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:11111111
$000F
TIM Counter Modulo
Register Low
(TMODL)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:11111111
$0010
TIM Channel 0 Status and
Control Register
(TSC0)
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0011
TIM Channel 0
Register High
(TCH0H)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
$0012
TIM Channel 0
Register Low
(TCH0L)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
$0013
TIM Channel 1 Status and
Control Register
(TSC1)
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
Memory Map
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
44 Memory Map Freescale Semiconductor
$0014
TIM Channel 1
Register High
(TCH1H)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
$0015
TIM Channel 1
Register Low
(TCH1L)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
$0016
Keyboard Status and
Control Register
(KBSCR)
Read: 0000KEYF 0
IMASKK MODEK
Write: ACKK
Reset:00000000
$0017
Keyboard Interrupt
Enable Register
(KBIER)
Read:
KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0
Write:
Reset:00000000
$0018 USB Interrupt Register 2
(UIR2)
Read: 00000000
Write: EOPFR RSTFR TXD2FR RXD2FR TDX1FR RESUMFR TXD0FR RXD0FR
Reset:00000000
$0019 USB Control Register 2
(UCR2)
Read:
T2SEQ STALL2 TX2E RX2E TP2SIZ3 TP2SIZ2 TP2SIZ1 TP2SIZ0
Write:
Reset:00000000
$001A USB Control Register 3
(UCR3)
Read: TX1ST 0
OSTALL0 ISTALL0
0
PULLEN ENABLE2 ENABLE1
Write: TX1STR
Reset:000000*00
* PULLEN bit is reset by POR or LVI reset only.
$001B USB Control Register 4
(UCR4)
Read: 00000
FUSBO FDP FDM
Write:
Reset:00000000
$001C
IRQ Option Control
Register
(IOCR)
Read: 00000PTE4IF
PTE4IE IRQPD
Write:
Reset:00000000
$001D
Port Option Control
Register
(POCR)
Read:
PTE20P PTDLDD PTDILDD PTE4P PTE3P PCP PBP PAP
Write:
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
Memory Map
Monitor ROM
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Memory Map 45
$001E
IRQ Status and Control
Register
(ISCR)
Read: 0000IRQF0
IMASK MODE
Write: ACK
Reset:00000000
$001F Configuration Register
(CONFIG)
Read: 0 0
URSTD LVID SSREC COPRS STOP COPD
Write:
Reset:00000000
† One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
$0020
USB Endpoint 0 Data
Register 0
(UE0D0)
Read: UE0R07 UE0R06 UE0R05 UE0R04 UE0R03 UE0R02 UE0R01 UE0R00
Write: UE0T07 UE0T06 UE0T05 UE0T04 UE0T03 UE0T02 UE0T01 UE0T00
Reset: Unaffected by reset
$0021
USB Endpoint 0 Data
Register 1
(UE0D1)
Read: UE0R17 UE0R16 UE0R15 UE0R14 UE0R13 UE0R12 UE0R11 UE0R10
Write: UE0T17 UE0T16 UE0T15 UE0T14 UE0T13 UE0T12 UE0T11 UE0T10
Reset: Unaffected by reset
$0022
USB Endpoint 0 Data
Register 2
(UE0D2)
Read: UE0R27 UE0R26 UE0R25 UE0R24 UE0R23 UE0R22 UE0R21 UE0R20
Write: UE0T27 UE0T26 UE0T25 UE0T24 UE0T23 UE0T22 UE0T21 UE0T20
Reset: Unaffected by reset
$0023
USB Endpoint 0 Data
Register 3
(UE0D3)
Read: UE0R37 UE0R36 UE0R35 UE0R34 UE0R33 UE0R32 UE0R31 UE0R30
Write: UE0T37 UE0T36 UE0T35 UE0T34 UE0T33 UE0T32 UE0T31 UE0T30
Reset: Unaffected by reset
$0024
USB Endpoint 0 Data
Register 4
(UE0D4)
Read: UE0R47 UE0R46 UE0R45 UE0R44 UE0R43 UE0R42 UE0R41 UE0R40
Write: UE0T47 UE0T46 UE0T45 UE0T44 UE0T43 UE0T42 UE0T41 UE0T40
Reset: Unaffected by reset
$0025
USB Endpoint 0 Data
Register 5
(UE0D5)
Read: UE0R57 UE0R56 UE0R55 UE0R54 UE0R53 UE0R52 UE0R51 UE0R50
Write: UE0T57 UE0T56 UE0T55 UE0T54 UE0T53 UE0T52 UE0T51 UE0T50
Reset: Unaffected by reset
$0026
USB Endpoint 0 Data
Register 6
(UE0D6)
Read: UE0R67 UE0R66 UE0R65 UE0R64 UE0R63 UE0R62 UE0R61 UE0R60
Write: UE0T67 UE0T66 UE0T65 UE0T64 UE0T63 UE0T62 UE0T61 UE0T60
Reset: Unaffected by reset
$0027
USB Endpoint 0 Data
Register 7
(UE0D7)
Read: UE0R77 UE0R76 UE0R75 UE0R74 UE0R73 UE0R72 UE0R71 UE0R70
Write: UE0T77 UE0T76 UE0T75 UE0T74 UE0T73 UE0T72 UE0T71 UE0T70
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
Memory Map
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46 Memory Map Freescale Semiconductor
$0028
USB Endpoint 1 Data
Register 0
(UE1D0)
Read:
Write: UE1T07 UE1T06 UE1T05 UE1T04 UE1T03 UE1T02 UE1T01 UE1T00
Reset: Unaffected by reset
$0029
USB Endpoint 1 Data
Register 1
(UE1D1)
Read:
Write: UE1T17 UE1T16 UE1T15 UE1T14 UE1T13 UE1T12 UE1T11 UE1T10
Reset: Unaffected by reset
$002A
USB Endpoint 1 Data
Register 2
(UE1D2)
Read:
Write: UE1T27 UE1T26 UE1T25 UE1T24 UE1T23 UE1T22 UE1T21 UE1T20
Reset: Unaffected by reset
$002B USB Endpoint 1 Data
Register 3
(UE1D3)
Read:
Write: UE1T37 UE1T36 UE1T35 UE1T34 UE1T33 UE1T32 UE1T31 UE1T30
Reset: Unaffected by reset
$002C USB Endpoint 1 Data
Register 4
(UE1D4)
Read:
Write: UE1T47 UE1T46 UE1T45 UE1T44 UE1T43 UE1T42 UE1T41 UE1T40
Reset: Unaffected by reset
$002D USB Endpoint 1 Data
Register 5
(UE1D5)
Read:
Write: UE1T57 UE1T56 UE1T55 UE1T54 UE1T53 UE1T52 UE1T51 UE1T50
Reset: Unaffected by reset
$002E USB Endpoint 1 Data
Register 6
(UE1D6)
Read:
Write: UE1T67 UE1T66 UE1T65 UE1T64 UE1T63 UE1T62 UE1T61 UE1T60
Reset: Unaffected by reset
$002F USB Endpoint 1 Data
Register 7
(UE1D7)
Read:
Write: UE1T77 UE1T76 UE1T75 UE1T74 UE1T73 UE1T72 UE1T71 UE1T70
Reset: Unaffected by reset
$0030
USB Endpoint 2 Data
Register 0
(UE2D0)
Read: UE2R07 UE2R06 UE2R05 UE2R04 UE2R03 UE2R02 UE2R01 UE2R00
Write: UE2T07 UE2T06 UE2T05 UE2T04 UE2T03 UE2T02 UE2T01 UE2T00
Reset: Unaffected by reset
$0031
USB Endpoint 2 Data
Register 1
(UE2D1)
Read: UE2R17 UE2R16 UE2R15 UE2R14 UE2R13 UE2R12 UE2R11 UE2R10
Write: UE2T17 UE2T16 UE2T15 UE2T14 UE2T13 UE2T12 UE2T11 UE2T10
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
Memory Map
Monitor ROM
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Memory Map 47
$0032
USB Endpoint 2 Data
Register 2
(UE2D2)
Read: UE2R27 UE2R26 UE2R25 UE2R24 UE2R23 UE2R22 UE2R21 UE2R20
Write: UE2T27 UE2T26 UE2T25 UE2T24 UE2T23 UE2T22 UE2T21 UE2T20
Reset: Unaffected by reset
$0033
USB Endpoint 2 Data
Register 3
(UE2D3)
Read: UE2R37 UE2R36 UE2R35 UE2R34 UE2R33 UE2R32 UE2R31 UE2R30
Write: UE2T37 UE2T36 UE2T35 UE2T34 UE2T33 UE2T32 UE2T31 UE2T30
Reset: Unaffected by reset
$0034
USB Endpoint 2 Data
Register 4
(UE2D4)
Read: UE2R47 UE2R46 UE2R45 UE2R44 UE2R43 UE2R42 UE2R41 UE2R40
Write: UE2T47 UE2T46 UE2T45 UE2T44 UE2T43 UE2T42 UE2T41 UE2T40
Reset: Unaffected by reset
$0035
USB Endpoint 2 Data
Register 5
(UE2D5)
Read: UE2R57 UE2R56 UE2R55 UE2R54 UE2R53 UE2R52 UE2R51 UE2R50
Write: UE2T57 UE2T56 UE2T55 UE2T54 UE2T53 UE2T52 UE2T51 UE2T50
Reset: Unaffected by reset
$0036
USB Endpoint 2 Data
Register 6
(UE2D6)
Read: UE2R67 UE2R66 UE2R65 UE2R64 UE2R63 UE2R62 UE2R61 UE2R60
Write: UE2T67 UE2T66 UE2T65 UE2T64 UE2T63 UE2T62 UE2T61 UE2T60
Reset: Unaffected by reset
$0037
USB Endpoint 2 Data
Register 7
(UE2D7)
Read: UE2R77 UE2R76 UE2R75 UE2R74 UE2R73 UE2R72 UE2R71 UE2R70
Write: UE2T77 UE2T76 UE2T75 UE2T74 UE2T73 UE2T72 UE2T71 UE2T70
Reset: Unaffected by reset
$0038 USB Address Register
(UADDR)
Read:
USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
Write:
Reset:0*0000000
* USBEN bit is reset by POR or LVI reset only.
$0039 USB Interrupt Register 0
(UIR0)
Read:
EOPIE SUSPND TXD2IE RXD2IE TXD1IE
0
TXD0IE RXD0IE
Write:
Reset:00000000
$003A USB Interrupt Register 1
(UIR1)
Read: EOPF RSTF TXD2F RXD2F TXD1F RESUMF TXD0F RXD0F
Write:
Reset:00000000
$003B USB Control Register 0
(UCR0)
Read:
T0SEQ
0
TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
Write:
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
Memory Map
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48 Memory Map Freescale Semiconductor
$003C USB Control Register 1
(UCR1)
Read:
T1SEQ STALL1 TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
Write:
Reset:00000000
$003D USB Status Register 0
(USR0)
Read: R0SEQ SETUP 0 0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0
Write:
Reset: Unaffected by reset
$003E USB Status Register 1
(USR1)
Read: R2SEQ TXACK TXNAK TXSTL RP2SIZ3 RP2SIZ2 RP2SIZ1 RP2SIZ0
Write:
Reset:U0 0 0UUUU
$003F Unimplemented
Read:
Write:
$FE00 Break Status Register
(BSR)
Read:
RRRRRR
SBSW
R
Write: See note
Reset: 0
Note: Writing a logic 0 clears SBSW.
$FE01 Reset Status Register
(RSR)
Read: POR PIN COP ILOP ILAD USB LVI 0
Write:
POR:10000000
$FE02 Reserved
Read:
RRRRRRRR
Write:
$FE03
Break Flag Control
Register
(BFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04 Interrupt Status Register 1
(INT1)
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05 Reserved
Read:
RRRRRRRR
Write:
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
Memory Map
Monitor ROM
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Memory Map 49
$FE06 Reserved
Read:
RRRRRRRR
Write:
$FE07 Reserved
Read:
RRRRRRRR
Write:
$FE08 FLASH Control Register
(FLCR)
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
$FE09
FLASH Block Protect
Register
(FLBPR)
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset:00000000
$FE0A Reserved
Read:
RRRRRRRR
Write:
$FE0B Reserved
Read:
RRRRRRRR
Write:
$FE0C
Break Address High
Register
(BRKH)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$FE0D
Break Address low
Register
(BRKL)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:00000000
$FE0E
Break Status and Control
Register
(BRKSCR)
Read:
BRKE BRKA
000000
Write:
Reset:00000000
$FFFF COP Control Register
(COPCTL)
Read: Low byte of reset vector
Write: Writing clears COP counter (any value)
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)
Memory Map
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Table 2-1 is a list of vector locations.
Table 2-1. Vector Addresses
Vector Priority INT Flag Address Vector
Lowest
IF6
$FFF0 Keyboard Vector (High)
$FFF1 Keyboard Vector (Low)
IF5
$FFF2 TIM Overflow Vector (High)
$FFF3 TIM Overflow Vector (Low)
IF4
$FFF4 TIM Channel 1 Vector (High)
$FFF5 TIM Channel 1 Vector (Low)
IF3
$FFF6 TIM Channel 0 Vector (High)
$FFF7 TIM Channel 0 Vector (Low)
IF1
$FFF8 IRQ Vector (High)
$FFF9 IRQ Vector (Low)
IF2
$FFFA USB Vector (High)
$FFFB USB Vector (Low)
$FFFC SWI Vector (High)
$FFFD SWI Vector (Low)
$FFFE Reset Vector (High)
Highest $FFFF Reset Vector (Low)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Random-Access Memory (RAM) 51
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2 Introduction
This section describes the 256 bytes of RAM.
3.3 Functional Description
Addresses $0040–$013F are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 192 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can
access efficiently all page zero RAM locations. Page zero RAM,
therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE: For M6805 Family compatibility, the H register is not stacked.
Random-Access Memory (RAM)
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During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor FLASH Memory 53
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 4. FLASH Memory
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .56
4.6 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .57
4.7 FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.8 FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.8.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . .60
4.9 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.9.1 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.9.2 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.9.3 PROGRAM Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.9.4 VERIFY Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
FLASH Memory
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4.3 Functional Description
The FLASH memory consists of an array of 8,192 bytes for user memory
plus a small block of 16 bytes for user interrupt vectors. An erased bit
reads as logic 1 and a programmed bit reads as a logic 0. The FLASH
memory is block erasable. The minimum erase block size is 512 bytes.
Program and erase operation operations are facilitated through control
bits in FLASH control register (FLCR).The address ranges for the
FLASH memory are shown as follows:
$DC00–$FBFF (user memory; 8,192 bytes)
$FFF0–$FFFF (user interrupt vectors; 16 bytes)
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.1
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
$FE08 FLASH Control Register
(FLCR)
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
$FE09
FLASH Block Protect
Register
(FLBPR)
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset:00000000
Figure 4-1. FLASH Memory Register Summary
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
FLASH Memory
FLASH Control Register
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor FLASH Memory 55
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the
memory for either program or erase operation. It can only be set if
either PGM or ERASE is high and the sequence for erase or
program/verify is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or
block erase operation when the ERASE bit is set.
1 = Mass Erase operation selected
0 = Block Erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. This bit
and the PGM bit should not be set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. This
bit and the ERASE bit should not be set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
Address: $FE08
Bit 7654321Bit 0
Read: 0000
HVEN MASS ERASE PGM
Write:
Reset:00000000
Figure 4-2. FLASH Control Register (FLCR)
FLASH Memory
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4.5 FLASH Block Erase Operation
Use the following procedure to erase a block of FLASH memory. A block
consists of 512 consecutive bytes starting from addresses $X000,
$X200, $X400, $X600, $X800, $XA00, $XC00 or $XE00. Any block
within the 8,192 bytes user memory area ($DC00–$FBFF) can be
erased alone.
NOTE: The 16-byte user vectors, $FFF0–$FFFF, cannot be erased by the block
erase operation because of security reasons. Mass erase is required to
erase this block.
1. Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2. Write any data to any FLASH address within the address range of
the block to be erased.
3. Wait for a time, tnvs (5 µs).
4. Set the HVEN bit.
5. Wait for a time terase (2 ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh (5 µs).
8. Clear the HVEN bit.
9. After time, trcv (1 µs), the memory can be accessed in read mode
again.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
FLASH Memory
FLASH Mass Erase Operation
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Freescale Semiconductor FLASH Memory 57
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH control
register.
2. Write any data to any FLASH address within the address range
$FFE0–$FFFF.
3. Wait for a time, tnvs (5 µs).
4. Set the HVEN bit.
5. Wait for a time tme (2 ms).
6. Clear the ERASE bit.
7. Wait for a time, tnvh1 (100 µs).
8. Clear the HVEN bit.
9. After time, trcv (1 µs), the memory can be accessed in read mode
again.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
FLASH Memory
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4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $XX80 or $XXC0. The procedure for programming a row of the
FLASH memory is outlined below:
1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Write any data to any FLASH address within the address range of
the row to be programmed.
3. Wait for a time, tnvs (5 µs).
4. Set the HVEN bit.
5. Wait for a time, tpgs (10 µs).
6. Write data to the byte being programmed.
7. Wait for time, tPROG (20 µs).
8. Repeat step 6 and 7 until all the bytes within the row are
programmed.
9. Clear the PGM bit.
10. Wait for time, tnvh (5 µs).
11. Clear the HVEN bit.
12. After time, trcv (1 µs), the memory can be accessed in read mode
again.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum (see 18.13
Memory Characteristics).
Figure 4-3 shows a flowchart representation for programming the
FLASH memory.
FLASH Memory
FLASH Program Operation
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor FLASH Memory 59
Figure 4-3. FLASH Programming Flowchart
Set HVEN bit
Write any data to any FLASH address
within the row address range desired
Wait for a time, tnvs
Set PGM bit
Wait for a time, tpgs
Write data to the FLASH address
to be programmed
Wait for a time, tPROG
Clear PGM bit
Wait for a time, tnvh
Clear HVEN bit
Wait for a time, trcv
Completed
programming
this row?
Y
N
End of Programming
The time between each FLASH address change (step 6 to step 6), or
must not exceed the maximum programming
time, tPROG max.
the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
NOTE:
1
2
3
4
5
6
7
9
10
11
12
Algorithm for programming
a row (64 bytes) of FLASH memory
This row program algorithm assumes the row/s
to be programmed are initially erased.
FLASH Memory
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4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE: When the FLBPR is cleared (all 0’s), the entire FLASH memory is
protected from being programmed and erased. When all the bits are set,
the entire FLASH memory is accessible for program and erase.
4.8.1 FLASH Block Protect Register
The FLASH block protect register is implemented as an 8-bit I/O register.
The content of this register determine the starting location of the
protected range within the FLASH memory.
BPR[7:0] — FLASH Block Protect Register Bit 7 to Bit 0
BPR[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0]
are logic 0’s.
Figure 4-5. FLASH Block Protect Start Address
Address: $FE09
Bit 7654321Bit 0
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Reset:00000000
Figure 4-4. FLASH Block Protect Register (FLBPR)
16-bit memory address
Start address of FLASH block protect 000000000
BPR[7:1]
FLASH Memory
ROM-Resident Routines
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Freescale Semiconductor FLASH Memory 61
BPR0 is used only for BPR[7:0] = $FF, for no block protection.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be X000, X200, X400,
X600, X800, XA00, XC00, or XE00 within the FLASH memory.
Examples of protect start address:
4.9 ROM-Resident Routines
ROM-resident routines can be called by a program running in user mode
or in monitor mode (see Section 10. Monitor ROM (MON)) for FLASH
programming, erasing, and verifying. The range of the FLASH memory
must be unprotected (see 4.8 FLASH Protection) before calling the
erase or programming routine.
BPR[7:0] Start of Address of Protect Range
$00 to $DC The entire FLASH memory is protected.
$DE (1101 1110) $DE00 (1101 1110 0000 0000)
$E0 (1110 0000)$E000 (1110 0000 0000 0000)
$E2 (1110 0010)$E200 (1110 0010 0000 0000)
$E4 (1110 0100)$E400 (1110 0100 0000 0000)
and so on...
$FE $FFE0–$FFFF (User vectors)
$FF The entire FLASH memory is not protected.
Note:
The end address of the protected range is always $FFFF.
Table 4-1. ROM-Resident Routines
Routine
Name Call Address Routine Function
VERIFY $FC03 FLASH verify routine
ERASE $FC06 FLASH mass erase routine
PROGRAM $FC09 FLASH program routine
FLASH Memory
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4.9.1 Variables
The ROM-resident routines use three variables: CTRLBYT, CPUSPD
and LADDR; and one data buffer. The minimum size of the data buffer
is one byte and the maximum size is 64 bytes.
CPUSPD must be set before calling the ERASE or PROGRAM routine,
and should be set to four times the value of the CPU internal bus speed
in MHz. For example: for CPU speed of 3MHz, CPUSPD should be set
to 12.
4.9.2 ERASE Routine
The ERASE routine erases the entire FLASH memory. The routine does
not check for a blank range before or after erase.
Table 4-2. ROM-Resident Routine Variables
Variable Address Description
CTRLBYT $0048 Control byte for setting mass erase.
CPUSPD $0049 Timing adjustment for different CPU
speeds.
LADDR $004A–$004B Last FLASH address to be programmed.
DATABUF $004C–$008B Data buffer for programming and verifying.
Table 4-3. ERASE Routine
Routine ERASE
Calling Address $FC06
Stack Use 5 Bytes
Input
CPUSPD — CPU speed
HX — Contains any address in the range to be
erased
CTRLBYT — Mass erase
Mass erase if bit 6 = 1
FLASH Memory
ROM-Resident Routines
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Freescale Semiconductor FLASH Memory 63
4.9.3 PROGRAM Routine
The PROGRAM routine programs a range of addresses in FLASH
memory, which does not have to be on page boundaries, either at the
begin or end address.
4.9.4 VERIFY Routine
The VERIFY routine reads and verifies a range of FLASH memory.
Table 4-4. PROGRAM Routine
Routine PROGRAM
Calling Address $FC09
Stack Use 7 Bytes
Input
CPUSPD — CPU speed
HX — FLASH start address to be programmed
LADDR — FLASH end address to be programmed
DATABUF — Contains the data to be programmed
Table 4-5. VERIFY Routine
Routine VERIFY
Calling Address $FC03
Stack Use 6 Bytes
Input
HX — FLASH start address to be verified
LADDR — FLASH end address to be verified
DATABUF — Contains the data to be verified
Output
C Bit — C bit is set if verify passes
DATABUF — Contains the data in the range of the
FLASH memory
FLASH Memory
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Configuration Register (CONFIG) 65
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.2 Introduction
This section describes the configuration register (CONFIG). This write-
once-after-reset register controls the following options:
USB reset
Low voltage inhibit
Stop mode recovery time (2048 or 4096 OSCXCLK cycles)
COP timeout period (218 – 24 or 213 – 24 OSCXCLK cycles)
STOP instruction
Computer operating properly module (COP)
Configuration Register (CONFIG)
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66 Configuration Register (CONFIG) Freescale Semiconductor
5.3 Functional Description
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. Bit-5 and
bit-4 are cleared by a POR or LVI reset only. Bit-3 to bit-0 are cleared
during any reset. Since the various options affect the operation of the
MCU, it is recommended that this register be written immediately after
reset. The configuration register is located at $001F. The configuration
register may be read at any time.
URSTD — USB Reset Disable Bit
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU.
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
LVID — Low Voltage Inhibit Disable Bit
LVID disables the LVI circuit
1 = Disable LVI circuit
0 = Enable LVI circuit
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
2048×OSCXCLK cycles instead of a 4096×OSCXCLK cycle delay.
1 = Stop mode recovery after 2048×OSCXCLK cycles
0 = Stop mode recovery after 4096×OSCXCLK cycles
Address: $001F
Bit 7654321Bit 0
Read: 0 0
URSTD LVID SSREC COPRS STOP COPD
Write:
Reset:000*0*0000
= Unimplemented
* URSTD and LVID bits are reset by POR or LVI reset only.
Figure 5-1. Configuration Register (CONFIG)
Configuration Register (CONFIG)
Functional Description
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Freescale Semiconductor Configuration Register (CONFIG) 67
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPD selects the COP timeout period. Reset clears COPRS. (See
Section 15. Computer Operating Properly (COP).)
1 = COP timeout period = (213 – 24)×OSCXCLK cycles
0 = COP timeout period = (218 – 24)×OSCXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 15. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Configuration Register (CONFIG)
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MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 69
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.7 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.8 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.9 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Central Processor Unit (CPU)
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6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
6.3 Features
Object code fully upward-compatible with M68HC05 Family
16-bit stack pointer with stack manipulation instructions
16-bit index register with x-register manipulation instructions
3-MHz CPU internal bus frequency
64-Kbyte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64-Kbytes
Low-power stop and wait modes
géééa
Central Processor Unit (CPU)
CPU Registers
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Freescale Semiconductor Central Processor Unit (CPU) 71
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
Figure 6-1. CPU Registers
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
ACCUMULATOR (A)
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
V11HINZC
H X
0
0
0
0
7
15
15
15
70
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 6-2. Accumulator (A)
Central Processor Unit (CPU)
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72 Central Processor Unit (CPU) Freescale Semiconductor
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
6.4.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15 1413121110987654321
Bit
0
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 6-3. Index Register (H:X)
Bit
15 1413121110987654321
Bit
0
Read:
Write:
Reset:0000000011111111
Figure 6-4. Stack Pointer (SP)
Central Processor Unit (CPU)
CPU Registers
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Freescale Semiconductor Central Processor Unit (CPU) 73
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
6.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15 1413121110987654321
Bit
0
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Central Processor Unit (CPU)
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6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Bit 7654321Bit 0
Read:
V11HI NZC
Write:
Reset:X11X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
Central Processor Unit (CPU)
CPU Registers
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Freescale Semiconductor Central Processor Unit (CPU) 75
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
Central Processor Unit (CPU)
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76 Central Processor Unit (CPU) Freescale Semiconductor
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Freescale document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
6.6.1 Wait Mode
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
Central Processor Unit (CPU)
CPU During Break Interrupts
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Freescale Semiconductor Central Processor Unit (CPU) 77
6.6.2 Stop Mode
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
Central Processor Unit (CPU)
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6.8 Instruction Set Summary
Table 6-1. Instruction Set Summary (Sheet 1 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
Add with Carry A (A) + (M) + (C) RRRRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry A (A) + (M) RRRRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
AIS #opr Add Immediate Value (Signed) to SP SP (SP) + (16 « M) ––––––IMM A7 ii 2
AIX #opr Add Immediate Value (Signed) to H:X H:X (H:X) + (16 « M) ––––––IMM AF ii 2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Logical AND A (A) & (M) 0 RR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
Arithmetic Shift Left
(Same as LSL) R––RRR
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right R––RRR
DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
ff
4
1
1
4
3
5
C
b0
b7
0
b0
b7
C
Central Processor Unit (CPU)
Instruction Set Summary
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 79
BCC rel Branch if Carry Bit Clear PC (PC) + 2 + rel ? (C) = 0 REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn 0 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCS rel Branch if Carry Bit Set (Same as BLO) PC (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BEQ rel Branch if Equal PC (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
BGE opr Branch if Greater Than or Equal To
(Signed Operands) PC (PC) + 2 + rel ? (N V) = 0 ––––––REL 90 rr 3
BGT opr Branch if Greater Than (Signed
Operands) PC (PC) + 2 + rel ? (Z) | (N V) = 0 ––––––REL 92 rr 3
BHCC rel Branch if Half Carry Bit Clear PC (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3
BHCS rel Branch if Half Carry Bit Set PC (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3
BHI rel Branch if Higher PC (PC) + 2 + rel ? (C) | (Z) = 0 REL 22 rr 3
BHS rel Branch if Higher or Same
(Same as BCC) PC (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
BIH rel Branch if IRQ Pin High PC (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test (A) & (M) 0 RR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
BLE opr Branch if Less Than or Equal To
(Signed Operands) PC (PC) + 2 + rel ? (Z) | (N V) = 1 ––––––REL 93 rr 3
BLO rel Branch if Lower (Same as BCS) PC (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3
BLS rel Branch if Lower or Same PC (PC) + 2 + rel ? (C) | (Z) = 1 REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) PC (PC) + 2 + rel ? (N V) =1 ––––––REL 91 rr 3
BMC rel Branch if Interrupt Mask Clear PC (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3
Table 6-1. Instruction Set Summary (Sheet 2 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
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BNE rel Branch if Not Equal PC (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus PC (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC (PC) + 2 + rel ––––––REL 20 rr 3
BRCLR n,opr,rel Branch if Bit n in M Clear PC (PC) + 3 + rel ? (Mn) = 0 –––––R
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never PC (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC (PC) + 3 + rel ? (Mn) = 1 –––––R
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n,opr Set Bit n in M Mn 1 ––––––
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSR rel Branch to Subroutine
PC (PC) + 2; push (PCL)
SP (SP) – 1; push (PCH)
SP (SP) – 1
PC (PC) + rel
––––––REL AD rr 4
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
Compare and Branch if Equal
PC (PC) + 3 + rel ? (A) – (M) = $00
PC (PC) + 3 + rel ? (A) – (M) = $00
PC (PC) + 3 + rel ? (X) – (M) = $00
PC (PC) + 3 + rel ? (A) – (M) = $00
PC (PC) + 2 + rel ? (A) – (M) = $00
PC (PC) + 4 + rel ? (A) – (M) = $00
––––––
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
CLC Clear Carry Bit C 0 –––––0INH 98 1
CLI Clear Interrupt Mask I 0 ––0–––INH 9A 2
Table 6-1. Instruction Set Summary (Sheet 3 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
Instruction Set Summary
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 81
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
Clear
M $00
A $00
X $00
H $00
M $00
M $00
M $00
0––01–
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
3
1
1
1
3
2
4
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M (A) – (M) R––RRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (One’s Complement)
M (M) = $FF – (M)
A (A) = $FF – (M)
X (X) = $FF – (M)
M (M) = $FF – (M)
M (M) = $FF – (M)
M (M) = $FF – (M)
0––RR1
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E63
dd
ff
ff
4
1
1
4
3
5
CPHX #opr
CPHX opr Compare H:X with M (H:X) – (M:M + 1) R––RRR
IMM
DIR
65
75
ii ii+1
dd
3
4
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M (X) – (M) R––RRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
DAA Decimal Adjust A (A)10 U–RRRINH 72 2
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
Decrement and Branch if Not Zero
A (A) – 1 or M (M) – 1 or X (X) – 1
PC (PC) + 3 + rel ? (result) 0
PC (PC) + 2 + rel ? (result) 0
PC (PC) + 2 + rel ? (result) 0
PC (PC) + 3 + rel ? (result) 0
PC (PC) + 2 + rel ? (result) 0
PC (PC) + 4 + rel ? (result) 0
––––––
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
5
3
3
5
4
6
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
M (M) – 1
A (A) – 1
X (X) – 1
M (M) – 1
M (M) – 1
M (M) – 1
R––RR
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
dd
ff
ff
4
1
1
4
3
5
DIV Divide A (H:A)/(X)
H Remainder ––––RRINH 52 7
Table 6-1. Instruction Set Summary (Sheet 4 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
82 Central Processor Unit (CPU) Freescale Semiconductor
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
Exclusive OR M with A A (A M) 0––RR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
Increment
M (M) + 1
A (A) + 1
X (X) + 1
M (M) + 1
M (M) + 1
M (M) + 1
R––RR
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
ff
ff
4
1
1
4
3
5
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Jump PC Jump Address ––––––
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3)
Push (PCL); SP (SP) – 1
Push (PCH); SP (SP) – 1
PC Unconditional Address
––––––
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M A (M) 0––RR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
LDHX #opr
LDHX opr Load H:X from M H:X ← (M:M + 1)0––RRIMM
DIR
45
55
ii jj
dd
3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
Load X from M X (M) 0––RR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
Logical Shift Left
(Same as ASL) R––RRR
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E68
dd
ff
ff
4
1
1
4
3
5
Table 6-1. Instruction Set Summary (Sheet 5 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
C
b0
b7
0
Central Processor Unit (CPU)
Instruction Set Summary
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 83
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
Logical Shift Right R––0RR
DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E64
dd
ff
ff
4
1
1
4
3
5
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
(M)Destination (M)Source
H:X (H:X) + 1 (IX+D, DIX+)
0––RR
DD
DIX+
IMD
IX+D
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
4
4
4
MUL Unsigned multiply X:A (X) × (A) –0–––0INH 42 5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Two’s Complement)
M –(M) = $00 – (M)
A –(A) = $00 – (A)
X –(X) = $00 – (X)
M –(M) = $00 – (M)
M –(M) = $00 – (M)
R––RRR
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E60
dd
ff
ff
4
1
1
4
3
5
NOP No Operation None INH 9D 1
NSA Nibble Swap A A (A[3:0]:A[7:4]) INH 62 3
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M A (A) | (M) 0 RR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
PSHA Push A onto Stack Push (A); SP (SP) 1 ––––––INH 87 2
PSHH Push H onto Stack Push (H); SP (SP) 1 ––––––INH 8B 2
PSHX Push X onto Stack Push (X); SP (SP) 1 ––––––INH 89 2
PULA Pull A from Stack SP (SP + 1); Pull (A)––––––INH 86 2
PULH Pull H from Stack SP (SP + 1); Pull (H)––––––INH 8A 2
PULX Pull X from Stack SP (SP + 1); Pull (X)––––––INH 88 2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry R––RRR
DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E69
dd
ff
ff
4
1
1
4
3
5
Table 6-1. Instruction Set Summary (Sheet 6 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
b0
b7
C0
C
b0
b7
Em;
Central Processor Unit (CPU)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
84 Central Processor Unit (CPU) Freescale Semiconductor
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry R––RRR
DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ff
ff
4
1
1
4
3
5
RSP Reset Stack Pointer SP $FF ––––––INH 9C 1
RTI Return from Interrupt
SP (SP) + 1; Pull (CCR)
SP (SP) + 1; Pull (A)
SP (SP) + 1; Pull (X)
SP (SP) + 1; Pull (PCH)
SP (SP) + 1; Pull (PCL)
RRRRRRINH 80 7
RTS Return from Subroutine SP SP + 1; Pull (PCH)
SP SP + 1; Pull (PCL) ––––––INH 81 4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry A (A) – (M) – (C) R––RRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SEC Set Carry Bit C 1 –––––1INH 99 1
SEI Set Interrupt Mask I 1 ––1–––INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M M (A) 0––RR
DIR
EXT
IX2
IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
STHX opr Store H:X in M (M:M + 1) (H:X) 0 RR– DIR 35 dd 4
STOP Enable IRQ Pin; Stop Oscillator I 0; Stop Oscillator 0 INH 8E 1
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M M (X) 0––RR
DIR
EXT
IX2
IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
ff
ee ff
3
4
4
3
2
4
5
Table 6-1. Instruction Set Summary (Sheet 7 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
b0
b7
C
Central Processor Unit (CPU)
Instruction Set Summary
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 85
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Subtract A (A) – (M) R––RRR
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
SWI Software Interrupt
PC (PC) + 1; Push (PCL)
SP (SP) – 1; Push (PCH)
SP (SP) – 1; Push (X)
SP (SP) – 1; Push (A)
SP (SP) – 1; Push (CCR)
SP (SP) – 1; I 1
PCH Interrupt Vector High Byte
PCL Interrupt Vector Low Byte
––1–––INH 83 9
TAP Transfer A to CCR CCR (A) RRRRRRINH 84 2
TAX Transfer A to X X (A) ––––––INH 97 1
TPA Transfer CCR to A A (CCR) INH 85 1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 RR
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
TSX Transfer SP to H:X H:X (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP) (H:X) 1 ––––––INH 94 2
Table 6-1. Instruction Set Summary (Sheet 8 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
Central Processor Unit (CPU)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
86 Central Processor Unit (CPU) Freescale Semiconductor
6.9 Opcode Map
See Table 6-2.
A Accumulator nAny bit
C Carry/borrow bit opr Operand (one or two bytes)
CCR Condition code register PC Program counter
dd Direct address of operand PCH Program counter high byte
dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte
DD Direct to direct addressing mode REL Relative addressing mode
DIR Direct addressing mode rel Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode
EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer
H Half-carry bit U Undefined
H Index register high byte V Overflow bit
hh ll High and low bytes of operand address in extended addressing X Index register low byte
I Interrupt mask Z Zero bit
ii Immediate operand byte & Logical AND
IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode Logical EXCLUSIVE OR
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset addressing mode –( ) Negation (two’s complement)
IX+ Indexed, no offset, post increment addressing mode # Immediate value
IX+D Indexed with post increment to direct addressing mode «Sign extend
IX1 Indexed, 8-bit offset addressing mode Loaded with
IX1+ Indexed, 8-bit offset, post increment addressing mode ? If
IX2 Indexed, 16-bit offset addressing mode : Concatenated with
M Memory location RSet or cleared
N Negative bit Not affected
Table 6-1. Instruction Set Summary (Sheet 9 of 9)
Source
Form Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I NZC
MSE LSE MSE LEE
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Central Processor Unit (CPU) 87
Central Processor Unit (CPU)
Opcode Map
Table 6-2. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
01234569E6789ABCD9EDE9EEF
0
5
BRSET0
3DIR
4
BSET0
2DIR
3
BRA
2REL
4
NEG
2DIR
1
NEGA
1INH
1
NEGX
1INH
4
NEG
2IX1
5
NEG
3SP1
3
NEG
1IX
7
RTI
1INH
3
BGE
2REL
2
SUB
2IMM
3
SUB
2DIR
4
SUB
3EXT
4
SUB
3IX2
5
SUB
4SP2
3
SUB
2IX1
4
SUB
3SP1
2
SUB
1IX
1
5
BRCLR0
3DIR
4
BCLR0
2DIR
3
BRN
2REL
5
CBEQ
3DIR
4
CBEQA
3IMM
4
CBEQX
3IMM
5
CBEQ
3IX1+
6
CBEQ
4SP1
4
CBEQ
2IX+
4
RTS
1INH
3
BLT
2REL
2
CMP
2IMM
3
CMP
2DIR
4
CMP
3EXT
4
CMP
3IX2
5
CMP
4SP2
3
CMP
2IX1
4
CMP
3SP1
2
CMP
1IX
2
5
BRSET1
3DIR
4
BSET1
2DIR
3
BHI
2REL
5
MUL
1INH
7
DIV
1INH
3
NSA
1INH
2
DAA
1INH
3
BGT
2REL
2
SBC
2IMM
3
SBC
2DIR
4
SBC
3EXT
4
SBC
3IX2
5
SBC
4SP2
3
SBC
2IX1
4
SBC
3SP1
2
SBC
1IX
3
5
BRCLR1
3DIR
4
BCLR1
2DIR
3
BLS
2REL
4
COM
2DIR
1
COMA
1INH
1
COMX
1INH
4
COM
2IX1
5
COM
3SP1
3
COM
1IX
9
SWI
1INH
3
BLE
2REL
2
CPX
2IMM
3
CPX
2DIR
4
CPX
3EXT
4
CPX
3IX2
5
CPX
4SP2
3
CPX
2IX1
4
CPX
3SP1
2
CPX
1IX
4
5
BRSET2
3DIR
4
BSET2
2DIR
3
BCC
2REL
4
LSR
2DIR
1
LSRA
1INH
1
LSRX
1INH
4
LSR
2IX1
5
LSR
3SP1
3
LSR
1IX
2
TA P
1INH
2
TXS
1INH
2
AND
2IMM
3
AND
2DIR
4
AND
3EXT
4
AND
3IX2
5
AND
4SP2
3
AND
2IX1
4
AND
3SP1
2
AND
1IX
5
5
BRCLR2
3DIR
4
BCLR2
2DIR
3
BCS
2REL
4
STHX
2DIR
3
LDHX
3IMM
4
LDHX
2DIR
3
CPHX
3IMM
4
CPHX
2DIR
1
TPA
1INH
2
TSX
1INH
2
BIT
2IMM
3
BIT
2DIR
4
BIT
3EXT
4
BIT
3IX2
5
BIT
4SP2
3
BIT
2IX1
4
BIT
3SP1
2
BIT
1IX
6
5
BRSET3
3DIR
4
BSET3
2DIR
3
BNE
2REL
4
ROR
2DIR
1
RORA
1INH
1
RORX
1INH
4
ROR
2IX1
5
ROR
3SP1
3
ROR
1IX
2
PULA
1INH
2
LDA
2IMM
3
LDA
2DIR
4
LDA
3EXT
4
LDA
3IX2
5
LDA
4SP2
3
LDA
2IX1
4
LDA
3SP1
2
LDA
1IX
7
5
BRCLR3
3DIR
4
BCLR3
2DIR
3
BEQ
2REL
4
ASR
2DIR
1
ASRA
1INH
1
ASRX
1INH
4
ASR
2IX1
5
ASR
3SP1
3
ASR
1IX
2
PSHA
1INH
1
TA X
1INH
2
AIS
2IMM
3
STA
2DIR
4
STA
3EXT
4
STA
3IX2
5
STA
4SP2
3
STA
2IX1
4
STA
3SP1
2
STA
1IX
8
5
BRSET4
3DIR
4
BSET4
2DIR
3
BHCC
2REL
4
LSL
2DIR
1
LSLA
1INH
1
LSLX
1INH
4
LSL
2IX1
5
LSL
3SP1
3
LSL
1IX
2
PULX
1INH
1
CLC
1INH
2
EOR
2IMM
3
EOR
2DIR
4
EOR
3EXT
4
EOR
3IX2
5
EOR
4SP2
3
EOR
2IX1
4
EOR
3SP1
2
EOR
1IX
9
5
BRCLR4
3DIR
4
BCLR4
2DIR
3
BHCS
2REL
4
ROL
2DIR
1
ROLA
1INH
1
ROLX
1INH
4
ROL
2IX1
5
ROL
3SP1
3
ROL
1IX
2
PSHX
1INH
1
SEC
1INH
2
ADC
2IMM
3
ADC
2DIR
4
ADC
3EXT
4
ADC
3IX2
5
ADC
4SP2
3
ADC
2IX1
4
ADC
3SP1
2
ADC
1IX
A
5
BRSET5
3DIR
4
BSET5
2DIR
3
BPL
2REL
4
DEC
2DIR
1
DECA
1INH
1
DECX
1INH
4
DEC
2IX1
5
DEC
3SP1
3
DEC
1IX
2
PULH
1INH
2
CLI
1INH
2
ORA
2IMM
3
ORA
2DIR
4
ORA
3EXT
4
ORA
3IX2
5
ORA
4SP2
3
ORA
2IX1
4
ORA
3SP1
2
ORA
1IX
B
5
BRCLR5
3DIR
4
BCLR5
2DIR
3
BMI
2REL
5
DBNZ
3DIR
3