INA220 Datasheet by Texas Instruments

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V'.‘ 1!. B X E I TEXAS INSTRUMENTS

×Power Register

Current Register

I C-/SMBUS-

Compatible

Interface

Voltage Register

V (Supply Voltage)

ADC

INA220

GND

VIN+

VIN-

SDA DATA

SCL CLK

CBYPASS

0.1µF

+3.3V to

+5V

Bus Voltage Input

High-

Side

Shunt

Low-

Side

Shunt R1F

R2F

Load

Supply (0 to 26V)

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

INA220

SBOS459E –JUNE 2009–REVISED JANUARY 2016

INA220 High- or Low-Side, Bidirectional Current and Power Monitor

With Two-Wire Interface

1 Features

1• High- or Low-Side Sensing

• Senses Bus Voltages from 0 V to 26 V

• Reports Current, Voltage, and Power

• 16 Programmable Addresses

• High Accuracy: 0.5% (Maximum) Over

Temperature (INA220B)

• User-Programmable Calibration

• Fast (2.56-MHz) I2C- or SMBUS-Compatible

Interface

• VSSOP-10 Package

2 Applications

• Servers

• Telecom Equipment

• Notebook Computers

• Power Management

• Battery Chargers

• Automotive

• Power Supplies

• Test Equipment

3 Description

The INA220 is a current shunt and power monitor

with an I2C- or SMBUS-compatible interface. The

INA220 monitors both shunt drop and supply voltage.

A programmable calibration value, combined with an

internal multiplier, enables direct readouts in

amperes. An additional multiplying register calculates

power in watts. The I2C- or SMBUS-compatible

interface features 16 programmable addresses. The

separate shunt input on the INA220 allows it to be

used in systems with low-side sensing.

The INA220 is available in two grades: A and B. The

B grade version has higher accuracy and higher

precision specifications.

The INA220 senses across shunts on buses that can

vary from 0 to 26 V, useful for low-side sensing or

CPU power supplies. The device uses a single 3- to

5.5-V supply, drawing a maximum of 1 mA of supply

current. The INA220 operates from –40°C to 125°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

INA220 VSSOP (10) 3.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

General Load, Low- or High-Side Sensing

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Related Products ................................................... 4

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Bus Timing Diagram Definitions................................ 7

7.7 Typical Characteristics.............................................. 8

8 Detailed Description............................................ 10

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram....................................... 10

8.3 Feature Description................................................. 10

8.4 Device Functional Modes........................................ 11

8.5 Programming .......................................................... 12

8.6 Register Maps......................................................... 18

9 Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Application .................................................. 25

10 Power Supply Recommendations ..................... 29

11 Layout................................................................... 29

11.1 Layout Guidelines ................................................. 29

11.2 Layout Example .................................................... 29

12 Device and Documentation Support ................. 30

12.1 Related Documentation......................................... 30

12.2 Community Resources.......................................... 30

12.3 Trademarks........................................................... 30

12.4 Electrostatic Discharge Caution............................ 30

12.5 Glossary................................................................ 30

13 Mechanical, Packaging, and Orderable

Information ........................................................... 30

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (September 2010) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1

• Changed front page diagram. ................................................................................................................................................ 1

• Changed pin names in the pin description............................................................................................................................. 4

• Changed the temperature values in the Absolute Maximum Ratings table ........................................................................... 5

• Changed Ambient temperature from –25 to –40 in the MIN column. .................................................................................... 5

• Deleted Temperature Range parameters from Electrical Characteristics.............................................................................. 7

• Changed I2C timing spec change based on characterization data. ...................................................................................... 7

Changes from Revision C (September, 2009) to Revision D Page

• Changed High Accuracy bullet in Features from 1% to 0.5% for B-grade device.................................................................. 1

• Added new paragraph to Description regarding A- and B-grade versions of the device....................................................... 1

• Added new row to Packaging Information table to show new B-grade device ...................................................................... 4

• Added B-grade columns in Electrical Characteristics for MIN, TYP and MAX values ........................................................... 6

• Changed Current Sense Gain Error over temperature specification from 10 ppm/°C to 1m%/°C......................................... 6

• Added Configure/Measure/Calculate Example..................................................................................................................... 25

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Changes from Revision B (June, 2009) to Revision C Page

• Changed specified temperature range from –25°C to –40°C................................................................................................. 6

• Changed Offset Voltage (RTI) vs Temperature minimum specification from 0.1 μV/°C to 0.16 μV/°C.................................. 6

• Changed Typical Characteristics:Figure 3,Figure 4,Figure 5,Figure 6 .............................................................................. 8

• Changed Typical Characteristics:Figure 9,Figure 10 ........................................................................................................... 8

l TEXAS INSTRUMENTS ﬂﬂﬂﬂﬂ UUUUU

IN+

IN-

GND

VBUS

SCL

SDA

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5 Related Products

DEVICE DESCRIPTION

INA209 Current/power monitor with watchdog, peak-hold, and fast comparator functions

INA210,INA211,INA212,INA213,INA214 Zero-drift, low-cost, analog current shunt monitor series in small package

INA219 Zero-drift, bidirectional current power monitor with two-wire interface

6 Pin Configuration and Functions

DGS Package

10-PIN VSSOP

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

A1 1 Digital Input Address pin. Connect to GND, SCL, SDA, or VS.Table 1 shows pin settings and corresponding addresses.

A0 2 Digital Input Address pin. Connect to GND, SCL, SDA, or VS.Table 1 shows pin settings and corresponding addresses.

NC 3 — No internal connection

SDA 4 Digital I/O Serial bus data line

SCL 5 Digital Input Serial bus clock line

VS6 Analog Power supply, 3 V to 5.5 V

GND 7 Analog Ground

VBUS 8 Analog Input Bus voltage input

IN– 9 Analog Input Negative differential shunt voltage. Connect to negative side of shunt resistor. Bus voltage is measured

from this pin to ground.

IN+ 10 Analog Input Positive differential shunt voltage. Connect to positive side of shunt resistor.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) IN+ and IN– may have a differential voltage of –26 to 26 V; however, the voltage at these pins must not exceed the range of –0.3 to 26

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted).(1)

MIN MAX UNIT

VSSupply voltage 6 V

Analog inputs

IN+, IN–

Differential (VIN+) – (VIN–)(2) –26 26 V

Common-mode (VIN+ + VIN-) / 2 –0.3 26 V

VVBUS Voltage at VBUS pin –0.3 26 V

VSDA Voltage at SDA pin GND – 0.3 6 V

VSCL Voltage at SCL pin GND – 0.3 VS+ 0.3 V

Input current into any pin 5 mA

Open-drain digital output current 10 mA

Operating temperature –40 125 °C

TJJunction temperature 150 °C

Tstg Storage temperature –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000

VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000

Machine model (MM) ±150

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VCM (VIN+ + VIN-) / 2 12 V

VSSupply voltage 3.3 V

TAAmbient temperature –40 85 ºC

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1)

INA220

UNITDGS (VSSOP)

10 PINS

RθJA Junction-to-ambient thermal resistance 165.4 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 53.2 °C/W

RθJB Junction-to-board thermal resistance 86.6 °C/W

ψJT Junction-to-top characterization parameter 6.4 °C/W

ψJB Junction-to-board characterization parameter 85.0 °C/W

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(1) BRNG is bit 13 of the Configuration Register 00h (see Figure 19).

(2) This parameter only expresses the full-scale range of the ADC scaling. In no event should more than 26 V be applied to this device.

(3) Referred-to-input (RTI)

(4) Indicates improved specifications of the INA220B.

(5) The input impedance of this pin may vary approximately ±15%.

(6) Input leakage is positive (current flowing into the pin) for the conditions shown at the top of the table. Negative leakage currents can

occur under different input conditions.

(7) SMBus timeout in the INA220 resets the interface any time SCL or SDA is low for more than 28 ms.

7.5 Electrical Characteristics

at TA= 25°C, VS= 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+ – VIN–) = 32 mV, VVBUS = 12 V, PGA = /1, and BRNG(1) = 1, unless

otherwise noted.

TEST CONDITIONS INA220A INA220B UNIT

MIN TYP MAX MIN TYP MAX

INPUT

Full-scale current sense (input) voltage

range VSHUNT

PGA = /1 0 ±40 0 ±40 mV

PGA = /2 0 ±80 0 ±80 mV

PGA = /4 0 ±160 0 ±160 mV

PGA = /8 0 ±320 0 ±320 mV

Bus voltage (input voltage)(2) BRNG = 1 0 32 0 32 V

BRNG = 0 0 16 0 16 V

Common-mode rejection VIN+ = 0 to 26 V 100 120 100 120 dB

Offset Voltage,

RTI(3)

VOS

PGA = /1 ±10 ±100 ±10 ±50(4) μV

PGA = /2 ±20 ±125 ±20 ±75(4) μV

PGA = /4 ±30 ±150 ±30 ±75(4) μV

PGA = /8 ±40 ±200 ±40 ±100(4) μV

TA= –40°C to 85°C 0.16 0.16 μV/°C

versus power

supply PSRR VS= 3 to 5.5 V 10 10 μV/V

Current sense gain error ±40 ±40 m%

TA= –40°C to 85°C 1 1 m%/°C

IN+ pin input impedance Active mode 20 20 μA

IN– pin input impedance Active mode 20 20 μA

VBUS pin input impedance(5) Active mode 320 320 kΩ

IN+ pin input leakage(6) Power-down mode 0.1 ±0.5 0.1 ±0.5 μA

IN– pin input leakage(6) Power-down mode 0.1 ±0.5 0.1 ±0.5 μA

DC ACCURACY

ADC basic resolution 12 12 bits

Shunt voltage 1-LSB step size 10 10 μV

Bus voltage 1-LSB step size 4 4 mV

Current measurement error

±0.2% ±0.5% ±0.2% ±0.3%(4)

over Temperature

TA= –40°C to 85°C ±1% ±0.5%(4)

Bus voltage measurement error

VBUS = 12 V ±0.2% ±0.5% ±0.2% ±0.5%

over Temperature

TA= –40°C to 85°C ±1% ±1%

Differential nonlinearity ±0.1 ±0.1 LSB

ADC TIMING

ADC conversion time

12-bit 532 586 532 586 μs

11-bit 276 304 276 304 μs

10-bit 148 163 148 163 μs

9-bit 84 93 84 93 μs

Minimum convert input low time 4 4 μs

SMBus

SMBus timeout(7) 28 35 28 35 ms

SCL

SDA

t(LOW) tRtFt(HDSTA)

t(HDSTA)

t(HDDAT)

t(BUF)

t(SUDAT)

t(HIGH) t(SUSTA) t(SUSTO)

P S S P

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Electrical Characteristics (continued)

at TA= 25°C, VS= 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+ – VIN–) = 32 mV, VVBUS = 12 V, PGA = /1, and BRNG(1) = 1, unless

otherwise noted.

TEST CONDITIONS INA220A INA220B UNIT

MIN TYP MAX MIN TYP MAX

DIGITAL INPUTS (SDA as Input, SCL, A0, A1)

Input capacitance 3 3 pF

Leakage input current 0 ≤VIN ≤VS0.1 1 0.1 1 μA

VIH input logic level 0.7 (VS) 6 0.7 (VS) 6 V

VIL input logic level –0.3 0.3 (VS) –0.3 0.3 (VS) V

Hysteresis 500 500 mV

OPEN-DRAIN DIGITAL OUTPUTS (SDA)

Logic 0 output level ISINK = 3 mA 0.15 0.4 0.15 0.4 V

High-level output leakage current VOUT = VS0.1 1 0.1 1 μA

POWER SUPPLY

Operating supply range 3 5.5 3 5.5 V

Quiescent current 0.7 1 0.7 1 mA

Quiescent current, power-down mode 6 15 6 15 μA

Power-on reset threshold 2 2 V

(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not ensured and not

production tested. Condition: A0=A1=0.

7.6 Bus Timing Diagram Definitions(1)

FAST MODE HIGH-SPEED MODE UNIT

MIN TYP MAX MIN TYP MAX

ƒ(SCL) SCL operating frequency 0.001 0.4 0.001 2.56 MHz

t(BUF) Bus free time between STOP and START

condition 1300 160 ns

t(HDSTA)

Hold time after repeated START condition

After this period, the first clock is

generated. 600 160 ns

t(SUSTA) Repeated START condition setup time 600 160 ns

t(SUSTO) STOP condition setup time 600 160 ns

t(HDDAT) Data hold time 0 900 0 90 ns

t(SUDAT) Data setup time 100 10 ns

t(LOW) SCL clock LOW period 1300 250 ns

t(HIGH) SCL clock HIGH period 600 60 ns

tFDA Data fall time 300 150 ns

tFCL Clock fall time 300 40 ns

tRCL Clock rise time 300 40 ns

tRCL Clock rise time for SCLK ≤100 kHz 1000 ns

Figure 1. Bus Timing Diagram

l TEXAS INSTRUMENTS

-5

-10

-15

-20

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3

INL( V)m

InputVoltage(V)

0.4

GainError(m%)

32V

16V

-50 -25 0 25 50 75 100

Temperature( C)°

125

100

-25-50 0 25 50 75 100 125

GainError(m%)

320mVRange 160mVRange

40mVRange

80mVRange

Temperature( C)°

100

Offset(mV)

32VRange 16VRange

-50 -25 0 25 50 75 100

Temperature( C)°

125

-50 -25 0 25 50 75 100

Offset( V)m

Temperature( C)°

125

100

160mVRange

320mVRange

80mVRange 40mVRange

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

10 100 1k 10k 100k 1M

Gain(dB)

InputFrequency(Hz)

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7.7 Typical Characteristics

at TA= 25°C, VS= 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+ – VIN–) = 32 mV, PGA = /1, and BRNG = 1, unless otherwise noted.

Figure 2. Frequency Response Figure 3. ADC Shunt Offset vs Temperature

Figure 4. ADC Shunt Gain Error vs Temperature Figure 5. ADC Bus Voltage Offset vs Temperature

Figure 6. ADC Bus Gain Error vs Temperature Figure 7. Integral Nonlinearity vs Input Voltage

l TEXAS INSTRUMENTS Vaus

%BusVoltageError

0 1 2 3 4 5 24 25 26

V (V)

BUS

5V Error-

3.3V Error-

5V+Error

3.3V+Error

300

250

200

150

100

1k 10k 100k 1M 10M

I ( A)

SCLFrequency(Hz)

V =5V

V =3V

I ( A)m

-50 -25 0 25 50 75 100

Temperature( C)°

125

V =5V

V =3V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1k 10k 100k 1M 10M

IQ(mA)

SCLFrequency(Hz)

V =5V

V =

S3V

2.0

1.5

1.0

0.5

-0.5

-1.0

-1.5

0510 15 20 25

InputCurrents(mA)

V Voltage(V)

IN-

VS+ =5V

V 5V

S+ =

VS+ =3V

V 3V

S+ =

I (mA)

V =3V

V =5V

-50 -25 0 25 50 75 100

Temperature( C)°

125

1.2

1.0

0.8

0.6

0.4

0.2

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Typical Characteristics (continued)

at TA= 25°C, VS= 3.3 V, VIN+ = 12 V, VSHUNT = (VIN+ – VIN–) = 32 mV, PGA = /1, and BRNG = 1, unless otherwise noted.

Figure 8. Input Currents With Large Differential Voltages

(VIN+ at 12 V, Sweep Of VIN–)

Figure 9. Active IQvs Temperature

Figure 10. Shutdown IQvs Temperature Figure 11. Active IQvs Two-Wire Clock Frequency

Figure 12. Total Percent Bus Voltage Error

vs Supply Voltage Figure 13. Shutdown IQvs Two-Wire Clock Frequency

ADC

ShuntVoltage

Channel

BusVoltage

Channel

PGA

(InConfigurationRegister)

ShuntVoltage(1)

DataRegisters

Full-ScaleCalibration(2)

Current(1)

BusVoltage(1)

Power(1)

NOTES:

(1)Read-only

(2)Read/write

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8 Detailed Description

8.1 Overview

The INA220 is a digital current sense amplifier with an I2C- and SMBus-compatible interface. It provides digital

current, voltage, and power readings necessary for accurate decision-making in precisely-controlled systems.

Programmable registers allow flexible configuration for measurement resolution as well as continuous-versus-

triggered operation. Detailed register information appears at the end of this data sheet, beginning with Table 2.

See Functional Block Diagram for a block diagram of the INA220 device.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Basic ADC Functions

The two analog inputs to the INA220, IN+ and IN–, connect to a shunt resistor in the bus of interest. Bus voltage

is measured at VBUS pin. The INA220 is typically powered by a separate supply from 3 to 5.5 V. The bus being

sensed can vary from 0 to 26 V. It requires no special considerations for power-supply sequencing (for example,

a bus voltage can be present with the supply voltage off, and vice-versa). The INA220 senses the small drop

across the shunt for shunt voltage, and senses the voltage with respect to ground from VBUS pin for the bus

voltage.

When the INA220 is in the normal operating mode (that is, MODE bits of the Configuration register are set to

111), it continuously converts the shunt voltage up to the number set in the shunt voltage averaging function

(Configuration register, SADC bits). The device then converts the bus voltage up to the number set in the bus

voltage averaging (Configuration register, BADC bits). The Mode control in the Configuration register also

permits selecting modes to convert only voltage or current, either continuously or in response to an event

(triggered).

All current and power calculations are performed in the background and do not contribute to conversion time;

conversion times shown in Electrical Characteristics can be used to determine the actual conversion time.

Power-down mode reduces the quiescent current and turns off current into the INA220 inputs, avoiding any

supply drain. Full recovery from power-down requires 40 μs. ADC off mode (set by the Configuration register,

MODE bits) stops all conversions.

In triggered mode, writing any of the triggered convert modes into the Configuration register (even if the desired

mode is already programmed into the register) triggers a single-shot conversion.

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Feature Description (continued)

Although the INA220 can be read at any time, and the data from the last conversion remain available, the

Conversion Ready bit (Status register, CNVR bit) is provided to help coordinate one-shot or triggered

conversions. The Conversion Ready bit is set after all conversions, averaging, and multiplication operations are

complete.

The Conversion Ready bit clears under any of these conditions:

• Writing to the Configuration register, except when configuring the MODE bits for power down or ADC off

(disable) modes

• Reading the Status register

• Triggering a single-shot conversion with the convert pin

8.3.1.1 Power Measurement

Current and bus voltage are converted at different points in time, depending on the resolution and averaging

mode settings. For instance, when configured for 12-bit and 128-sample averaging, up to 68 ms in time between

sampling these two values is possible. Again, these calculations are performed in the background and do not add

to the overall conversion time.

8.3.1.2 PGA Function

If larger full-scale shunt voltages are desired, the INA220 provides a PGA function that increases the full-scale

range up to 2, 4, or 8 times (320 mV). Additionally, the bus voltage measurement has two full-scale ranges: 16 or

32 V.

8.3.1.3 Compatibility With TI Hot Swap Controllers

The INA220 is designed for compatibility with hot swap controllers such the TI TPS2490. The TPS2490 uses a

high-side shunt with a limit at 50 mV; the INA220 full-scale range of 40 mV enables the use of the same shunt for

current sensing below this limit. When sensing is required at (or through) the 50-mV sense point of the TPS2490,

the PGA of the INA220 can be set to /2 to provide an 80-mV full-scale range.

8.4 Device Functional Modes

8.4.1 Filtering and Input Considerations

Measuring current is often noisy, and such noise can be difficult to define. The INA220 offers several options for

filtering by choosing resolution and averaging in the Configuration register. These filtering options can be set

independently for either voltage or current measurement.

The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. This

architecture has good inherent noise rejection; however, transients that occur at or very close to the sampling

rate harmonics can cause problems. Because these signals are at 1 MHz and higher, they can be dealt with by

incorporating filtering at the input of the INA220. The high frequency enables the use of low-value series resistors

on the filter for negligible effects on measurement accuracy. In general, filtering the INA220 input is only

necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate (>1 MHz). Filter using

the lowest possible series resistance and ceramic capacitor. TI recommends values of 0.1 to 1 μF. Figure 14

shows the INA220 with an additional filter added at the input.

Overload conditions are another consideration for the INA220 inputs. The INA220 inputs are specified to tolerate

26 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This

type of event can result in full power-supply voltage across the shunt (as long the power supply or energy

storage capacitors support it). It must be remembered that removing a short to ground can result in inductive

kickbacks that could exceed the 26-V differential and common-mode rating of the INA220. Inductive kickback

voltages are best dealt with by Zener-type transient-absorbing devices combined with sufficient energy storage

capacitance.

l TEXAS INSTRUMENTS Maximum Expected Current 21 B

Power_LSB = 20 Current_LSB

Maximum Expected Current

Current _ LSB 2

Cal = trunc 0.04096

Current_LSB R´SHUNT

Supply Load

R 10Ω

FILTER

R 10Ω

FILTER

0.1µF to 1µF

Ceramic Capacitor

RSHUNT

Data (SDA)

3.3V Supply

Clock (SCL)

×Power Register

Current Register I C-/SMBUS

Compatible

Interface

Voltage Register

VIN+

ADC

INA220

GND

Supply Voltage

VIN- VS

VBUS

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Device Functional Modes (continued)

In applications that do not have large energy storage electrolytics on one or both sides of the shunt, an input

overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physical short

is the most likely cause of this event, particularly in applications with no large electrolytics present. This problem

occurs because an excessive dV/dt can activate the ESD protection in the INA220 in systems where large

currents are available. Testing has demonstrated that the addition of 10-Ωresistors in series with each input of

the INA220 sufficiently protects the inputs against dV/dt failure up to the 26-V rating of the INA220. These

resistors have no significant effect on accuracy.

Figure 14. INA220 With Input Filtering

8.5 Programming

8.5.1 Programming the INA220 Calibration Register

programmed to anything other than default values, they must be reprogrammed at every device power-up. The

Calibration Register is calculated based on Equation 1. This equation includes the term Current_LSB, which is

the programmed value for the LSB for the Current Register (04h). The Current_LSB value is used to convert the

value in the Current Register (04h) to the actual current in amperes. The highest resolution for the Current

current as shown in Equation 2. While this value yields the highest resolution, it is common to select a value for

the Current_LSB to the nearest round number above this value to simplify the conversion of the Current Register

(04h) and Power Register (03h) to amperes and watts respectively. The RSHUNT term is the value of the external

shunt used to develop the differential voltage across the input pins. The Power Register (03h) is internally set to

be 20 times the programmed Current_LSB (see Equation 3).

where

• 0.04096 is an internal fixed value used to ensure scaling is maintained properly

• Current_LSB is the programmed value for the LSB for the Current Register (04h) (1)

(2)

(3)

TEXAS INSTRUMENTS C 4096 p 5000 Ca‘ >< measshumcurrent="">

Corrected_Full_Scale_Cal = trunc Cal MeasShuntCurrent´

INA220_Current

Current Re gister Bus Voltage Register

Power Register 5000

Shunt Voltage Register Calibration Register

Current Register 4096

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Programming (continued)

Shunt voltage is calculated by multiplying the Shunt Voltage Register contents with the Shunt Voltage LSB of 10

μV. The Bus Voltage register bits are not right-aligned. To compute the value of the Bus Voltage, Bus Voltage

contents can be multiplied by the Bus Voltage LSB of 4-mV to compute the bus voltage measured by the device.

After programming the Calibration Register, the value expected in the Current Register (04h) can be calculated

by multiplying the Shunt Voltage register contents by the Calibration Register and then dividing by 4096 as

shown in Equation 4. To obtain a value in amperes, the Current register value is multiplied by the programmed

Current_LSB.

(4)

The value expected in the Power register (03h) can be calculated by multiplying the Current register value by the

Bus Voltage register value and then dividing by 5000 as shown in Equation 5. Power Register content is

multiplied by Power LSB which is 20 times the Current_LSB for a power value in watts.

(5)

8.5.2 Programming the INA220 Power Measurement Engine

8.5.2.1 Calibration Register and Scaling

The Calibration register makes it possible to set the scaling of the Current and Power registers to whatever

values are most useful for a given application. One strategy may be to set the Calibration register such that the

largest possible number is generated in the Current register or Power register at the expected full-scale point;

this approach yields the highest resolution. The Calibration register can also be selected to provide values in the

Current and Power registers that either provide direct decimal equivalents of the values being measured, or yield

a round LSB number. After these choices have been made, the Calibration register also offers possibilities for

end-user system-level calibration, where the value is adjusted slightly to cancel total system error. After

determining the exact current by using an external ammeter, the value of the Calibration Register can then be

adjusted based on the measured current result of the INA220 to cancel the total system error as shown in

Equation 6.

(6)

8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)

The INA220 can be used without any programming if it is only necessary to read a shunt voltage drop and bus

voltage with the default 12-bit resolution, 320-mV shunt full-scale range (PGA = /8), 32-V bus full-scale range,

and continuous conversion of shunt and bus voltage.

Without programming, current is measured by reading the shunt voltage. The Current register and Power register

are only available if the Calibration register contains a programmed value.

8.5.4 Bus Overview

The INA220 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are

essentially compatible with one another.

The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only

when a difference between the two systems is being addressed. Two lines, SCL and SDA, connect the INA220

to the bus. Both SCL and SDA are open-drain connections.

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates START and STOP conditions.

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Programming (continued)

To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a

high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge

of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a

START or STOP condition.

After all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from low

to high while SCL is high. The INA220 includes a 28-ms timeout on its interface to prevent locking up an SMBus.

8.5.4.1 Serial Bus Address

To communicate with the INA220, the master must first address slave devices through a slave address byte. The

slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or

write operation.

The INA220 has two address pins, A0 and A1. Table 1 describes the pin logic levels for each of the 16 possible

addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set before any

activity on the interface occurs. The address pins are read at the start of each communication event.

Table 1. INA220 Address Pins and Slave Addresses

A1 A0 SLAVE ADDRESS

GND GND 1000000

GND VS1000001

GND SDA 1000010

GND SCL 1000011

VSGND 1000100

VSVS1000101

VSSDA 1000110

VSSCL 1000111

SDA GND 1001000

SDA VS1001001

SDA SDA 1001010

SDA SCL 1001011

SCL GND 1001100

SCL VS1001101

SCL SDA 1001110

SCL SCL 1001111

8.5.4.2 Serial Interface

The INA220 operates only as a slave device on the I2C bus and SMBus. Connections to the bus are made by the

open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and

Schmitt triggers to minimize the effects of input spikes and bus noise. The INA220 supports the transmission

protocol for fast (1-kHz to 400-kHz) and high-speed (1-kHz to 2.56-MHz) modes. All data bytes are transmitted

most significant byte first.

8.5.5 Writing to and Reading from the INA220

Accessing a particular register on the INA220 is accomplished by writing the appropriate value to the register

pointer. Refer to Table 2 for a complete list of registers and corresponding addresses. The value for the register

pointer, as shown in Figure 18, is the first byte transferred after the slave address byte with the R/W bit LOW.

Every write operation to the INA220 requires a value for the register pointer.

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Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the

R/W bit LOW. The INA220 then acknowledges receipt of a valid address. The next byte transmitted by the

master is the address of the register to which data will be written. This register address value updates the

pointer. The INA220 acknowledges receipt of each data byte. The master may terminate data transfer by

generating a START or STOP condition.

When reading from the INA220, the last value stored in the register pointer by a write operation determines

which register is read during a read operation. To change the register pointer for a read operation, a new value

must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/W

bit LOW, followed by the register pointer byte. No additional data are required. The master then generates a

START condition and sends the slave address byte with the R/W bit HIGH to initiate the read command. The

next byte is transmitted by the slave and is the most significant byte of the register indicated by the register

pointer. This byte is followed by an Acknowledge from the master; then the slave transmits the least significant

byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a

Not Acknowledge after receiving any data byte, or generating a START or STOP condition. If repeated reads

from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA220

retains the register pointer value until it is changed by the next write operation.

Figure 15 and Figure 16 show write and read operation timing diagrams, respectively. Note that register bytes

are sent most-significant byte first, followed by the least significant byte. Figure 17 shows the timing diagram for

the SMBus Alert response operation. Figure 18 shows a typical register pointer configuration.

l TEXAS INSTRUMENTS Address Byte \s delermmed by (he seumgs D'lhe Au and AI pms Refer m mm 1 1 s \ A” “MR; ”4000090.i m ‘ / Stop H 4+7\+—4% ACK by Master can also be sen|

Frame 1 Two-Wire Slave Address Byte(1) Frame 2 Data MSByte(2)

Start By

Master

ACK By

INA220

ACK By

Master

From

INA220

19 1 9

SDA

SCL

0 0 A3 R/WD15 D14 D13 D12 D11 D10 D9 D8

A2 A1 A0

Frame 3 Data LSByte(2)

StopNo ACK By(3)

Master

From

INA220

D7 D6 D5 D4 D3 D2 D1 D0

NOTES: (1) The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins.

Refer to Table 1.

(2) Read data is from the last register pointer location. If a new register is desired, the register

pointer must be updated. See Figure 19.

(3) ACK by Master can also be sent.

Frame 1 Two-Wire Slave Address Byte(1) Frame 2 Register Pointer Byte

Start By

Master

ACK By

INA220

ACK By

INA220

19 1

ACK By

INA220

D15 D14 D13 D12 D11 D10 D9 D8

SDA

SCL

1 0 0 A3 A2 A1 A0 R/WP7 P6 P5 P4 P3 P2 P1 P0

NOTE (1): The value of the Slave Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 1.

Frame 4 Data LSByte

Frame 3 Data MSByte

ACK By

INA220

Stop By

Master

D7 D6 D5 D4 D3 D2 D1 D0

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Figure 15. Timing Diagram for Write Word Format

Figure 16. Timing Diagram for Read Word Format

l TEXAS INSTRUMENTS

Frame1Two-WireSlaveAddressByte(1) Frame2RegisterPointerByte

StartBy

Master

ACKBy

INA220

ACKBy

INA220

1 9 1 9

SDA

SCL

0 0 A3 A2 A1 A0 R/WP7 P6 P5 P4 P3 P2 P1 P0 Stop

NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0andA1pins.RefertoTable1.

Frame1SMBusALERTResponseAddressByte Frame2SlaveAddressByte(1)

StartBy

Master

ACKBy

INA220

From

INA220

NACKBy

Master

StopBy

Master

1 9 1 9

SDA

SCL

ALERT

0 0 0 1 1 0 0 R/W1 0 0 A3 A2 A1 A0 0

NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0andA1pins.RefertoTable1.

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Figure 17. Timing Diagram for SMBus Alert

Figure 18. Typical Register Pointer Set

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(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not ensured and not

production tested. Condition: A0=A1=0.

(1) Type: R= Read only, R/W = Read/Write.

(2) The Power register and Current register default to 0 because the Calibration register defaults to 0, yielding a zero current value until the

Calibration register is programmed.

8.5.5.1 High-Speed Two-Wire Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup devices. The master generates a

start condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This

transmission is made in fast (400 kbps) or standard (100 kbps) (F/S) mode at no more than 400 kbps. The

INA220 does not acknowledge the HS master code, but does recognize it and switches its internal filters to

support 2.56-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission

speeds up to 2.56 Mbps are allowed. Instead of using a stop condition, repeated start conditions should be used

to secure the bus in HS-mode. A STOP condition ends the HS-mode and switches all the internal filters of the

INA220 to support the F/S mode. See Bus Timing Diagram Definitions(1) and Figure 1 for timing.

8.5.5.2 Power-Up Conditions

Power-up conditions apply to a software reset through the RST bit (bit 15) in the Configuration register, or the I2C

bus General Call Reset.

8.6 Register Maps

8.6.1 Register Information

The INA220 uses a bank of registers for holding configuration settings, measurement results, and status

information. Table 2 summarizes the INA220 registers; Functional Block Diagram illustrates the registers.

between completion of a write to a given register and a subsequent read of that register (without changing the

pointer) when using SCL frequencies in excess of 1 MHz.

Table 2. Summary of Register Set

POINTER

ADDRESS REGISTER NAME FUNCTION POWER-ON RESET TYPE(1)

HEX BINARY HEX

00 Configuration All-register reset, settings for bus

voltage range, PGA gain, ADC

resolution/averaging. 00111001 10011111 399F R/W

01 Shunt voltage Shunt voltage measurement data. Shunt voltage — R

02 Bus voltage Bus voltage measurement data. Bus voltage — R

03 Power(2) Power measurement data. 00000000 00000000 0000 R

04 Current(2) Contains the value of the current flowing

through the shunt resistor. 00000000 00000000 0000 R

05 Calibration Sets full-scale range and LSB of current

and power measurements. Overall

system calibration. 00000000 00000000 0000 R/W

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8.6.2 Register Details

All INA220 registers 16-bit registers are actually two 8-bit bytes through the I2C- or SMBUS-compatible interface.

8.6.2.1 Configuration Register (address = 00h) [reset = 399Fh]

Figure 19. Configuration Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RST — BRNG PG1 PG0 BADC

4BADC

3BADC

2BADC

1SADC

4SADC

3SADC

2SADC

1MODE

3MODE

2MODE

R/W-

0R/W-

0R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

RST: Reset Bit

Bit 15 Setting this bit to 1 generates a system reset that is the same as power-on reset. Resets all registers to default

values; this bit self-clears.

BRNG: Bus Voltage Range

Bit 13 0 = 16-V FSR

1 = 32-V FSR (default value)

PG: PGA (Shunt Voltage Only)

Bits 11, 12 Sets PGA gain and range. Note that the PGA defaults to ÷8 (320-mV range). Table 3 shows the gain and range for

the various product gain settings.

(1) Shaded values are default.

Table 3. PG Bit Settings [12:11] (1)

PG1 PG0 GAIN RANGE

0 0 1 ±40 mV

0 1 /2 ±80 mV

1 0 /4 ±160 mV

1 1 /8 ±320 mV

BADC: BADC Bus ADC Resolution/Averaging

Bits 7–10 These bits adjust the Bus ADC resolution (9-, 10-, 11-, or 12-bit) or set the number of samples used when

averaging results for the Bus Voltage Register (02h).

SADC: SADC Shunt ADC Resolution/Averaging

Bits 3–6 These bits adjust the Shunt ADC resolution (9-, 10-, 11-, or 12-bit) or set the number of samples used when

averaging results for the Shunt Voltage Register (01h).

BADC (Bus) and SADC (Shunt) ADC resolution/averaging and conversion time settings are shown in Table 4.

(1) Shaded values are default.

(2) X = Don't care

Table 4. ADC Settings (SADC [6:3], BADC [10:7])(1)

ADC4 ADC3 ADC2 ADC1 Mode/Samples Conversion Time

0 X(2) 0 0 9-bit 84 μs

0 X(2) 0 1 10-bit 148 μs

0 X(2) 1 0 11-bit 276 μs

0 X(2) 1 1 12-bit 532 μs

1 0 0 0 12-bit 532 μs

1 0 0 1 2 1.06 ms

1 0 1 0 4 2.13 ms

1 0 1 1 8 4.26 ms

1 1 0 0 16 8.51 ms

1 1 0 1 32 17.02 ms

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Table 4. ADC Settings (SADC [6:3], BADC [10:7])() (continued)

ADC4 ADC3 ADC2 ADC1 Mode/Samples Conversion Time

1 1 1 0 64 34.05 ms

1 1 1 1 128 68.10 ms

MODE: Operating Mode

Bits 0–2 Selects continuous, triggered, or power-down mode of operation. These bits default to continuous shunt and bus

measurement mode. The mode settings are shown in Table 5.

(1) Shaded values are default.

Table 5. Mode Settings [2:0](1)

MODE3 MODE2 MODE1 MODE

0 0 0 Power-down

0 0 1 Shunt voltage, triggered

0 1 0 Bus voltage, triggered

0 1 1 Shunt and bus, triggered

1 0 0 ADC off (disabled)

1 0 1 Shunt voltage, continuous

1 1 0 Bus voltage, continuous

1 1 1 Shunt and bus, continuous

8.6.3 Data Output Registers

8.6.3.1 Shunt Voltage Register (address = 01h)

The Shunt Voltage register stores the current shunt voltage reading, VSHUNT. Shunt Voltage register bits are

shifted according to the PGA setting selected in the Configuration register (00h). When multiple sign bits are

present, they are all the same value. Negative numbers are represented in 2's complement format. Generate the

2's complement of a negative number by complementing the absolute value binary number and adding 1. Extend

the sign, denoting a negative number by setting the MSB = 1. Extend the sign to any additional sign bits to form

the 16-bit word.

Example: For a value of VSHUNT = –320 mV:

1. Take the absolute value (include accuracy to 0.01 mV) →320.00

2. Translate this number to a whole decimal number →32000

3. Convert it to binary →111 1101 0000 0000

4. Complement the binary result : 000 0010 1111 1111

5. Add 1 to the complement to create the 2's-complement formatted result →000 0011 0000 0000

6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h (Remember to extend the sign to

all sign-bits, as necessary based on the PGA setting.)

At PGA = /8, full-scale range = ±320 mV (decimal = 32000). For VSHUNT = +320 mV, Value = 7D00h; For VSHUNT

= –320 mV, Value =8300h; and LSB = 10 μV.

Figure 20. Shunt Voltage Register at PGA = /8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SIGN SD14_

8SD13_

8SD12_

8SD11_

8SD10_

8SD9_8 SD8_8 SD7_8 SD6_8 SD5_8 SD4_8 SD3_8 SD2_8 SD1_8 SD0_8

At PGA = /4, full-scale range = ±160 mV (decimal = 16000). For VSHUNT = +160 mV, Value = 3E80h; For VSHUNT

= –160 mV, Value = C180h; and LSB = 10 μV.

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Figure 21. Shunt Voltage Register at PGA = /4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SIGN SIGN SD13_

4SD12_

4SD11_

4SD10_

4SD9_4 SD8_4 SD7_4 SD6_4 SD5_4 SD4_4 SD3_4 SD2_4 SD1_4 SD0_4

At PGA = /2, full-scale range = ±80 mV (decimal = 8000). For VSHUNT = +80 mV, Value = 1F40h; For VSHUNT =

–80 mV, Value = E0C0h; and LSB = 10 μV.

Figure 22. Shunt Voltage Register at PGA = /2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SIGN SIGN SIGN SD12_

2SD11_

2SD10_

2SD9_2 SD8_2 SD7_2 SD6_2 SD5_2 SD4_2 SD3_2 SD2_2 SD1_2 SD0_2

At PGA = /1, full-scale range = ±40 mV (decimal = 4000). For VSHUNT = +40 mV, Value = 0FA0h; For VSHUNT =

–40 mV, Value = F060h; and LSB = 10 μV.

Figure 23. Shunt Voltage Register at PGA = /1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SIGN SIGN SIGN SIGN SD11_

1SD10_

1SD9_1 SD8_1 SD7_1 SD6_1 SD5_1 SD4_1 SD3_1 SD2_1 SD1_1 SD0_1

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(1) Out-of-range values are shown in gray shading.

Table 6. Shunt Voltage Register Format(1)

VSHUNT Reading (mV) Decimal Value PGA = /8

(D15:D0) PGA = /4

(D15:D0) PGA = /2

(D15:D0) PGA = /1

(D15:D0)

320.02 32002 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

320.01 32001 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

320.00 32000 0111 1101 0000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

319.99 31999 0111 1100 1111 1111 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

319.98 31998 0111 1100 1111 1110 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

160.02 16002 0011 1110 1000 0010 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

160.01 16001 0011 1110 1000 0001 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

160.00 16000 0011 1110 1000 0000 0011 1110 1000 0000 0001 1111 0100 0000 0000 1111 1010 0000

159.99 15999 0011 1110 0111 1111 0011 1110 0111 1111 0001 1111 0100 0000 0000 1111 1010 0000

159.98 15998 0011 1110 0111 1110 0011 1110 0111 1110 0001 1111 0100 0000 0000 1111 1010 0000

80.02 8002 0001 1111 0100 0010 0001 1111 0100 0010 0001 1111 0100 0000 0000 1111 1010 0000

80.01 8001 0001 1111 0100 0001 0001 1111 0100 0001 0001 1111 0100 0000 0000 1111 1010 0000

80.00 8000 0001 1111 0100 0000 0001 1111 0100 0000 0001 1111 0100 0000 0000 1111 1010 0000

79.99 7999 0001 1111 0011 1111 0001 1111 0011 1111 0001 1111 0011 1111 0000 1111 1010 0000

79.98 7998 0001 1111 0011 1110 0001 1111 0011 1110 0001 1111 0011 1110 0000 1111 1010 0000

40.02 4002 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0010 0000 1111 1010 0000

40.01 4001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0001 0000 1111 1010 0000

40.00 4000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000 0000 1111 1010 0000

39.99 3999 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111 0000 1111 1001 1111

39.98 3998 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110 0000 1111 1001 1110

0.02 2 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0010

0.01 1 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001

0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

–0.01 –1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111

–0.02 –2 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110 1111 1111 1111 1110

–39.98 –3998 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010 1111 0000 0110 0010

–39.99 –3999 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001 1111 0000 0110 0001

–40.00 –4000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000 1111 0000 0110 0000

–40.01 –4001 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0101 1111 1111 0000 0110 0000

–40.02 –4002 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0101 1110 1111 0000 0110 0000

–79.98 –7998 1110 0000 1100 0010 1110 0000 1100 0010 1110 0000 1100 0010 1111 0000 0110 0000

–79.99 –7999 1110 0000 1100 0001 1110 0000 1100 0001 1110 0000 1100 0001 1111 0000 0110 0000

–80.00 –8000 1110 0000 1100 0000 1110 0000 1100 0000 1110 0000 1100 0000 1111 0000 0110 0000

–80.01 –8001 1110 0000 1011 1111 1110 0000 1011 1111 1110 0000 1100 0000 1111 0000 0110 0000

–80.02 –8002 1110 0000 1011 1110 1110 0000 1011 1110 1110 0000 1100 0000 1111 0000 0110 0000

–159.98 –15998 1100 0001 1000 0010 1100 0001 1000 0010 1110 0000 1100 0000 1111 0000 0110 0000

–159.99 –15999 1100 0001 1000 0001 1100 0001 1000 0001 1110 0000 1100 0000 1111 0000 0110 0000

–160.00 –16000 1100 0001 1000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

–160.01 –16001 1100 0001 0111 1111 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

–160.02 –16002 1100 0001 0111 1110 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

–319.98 –31998 1000 0011 0000 0010 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

–319.99 –31999 1000 0011 0000 0001 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

–320.00 –32000 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

–320.01 –32001 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

–320.02 –32002 1000 0011 0000 0000 1100 0001 1000 0000 1110 0000 1100 0000 1111 0000 0110 0000

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8.6.3.2 Bus Voltage Register (address = 02h)

The Bus Voltage register stores the most recent bus voltage reading, VBUS.

At full-scale range = 32 V (decimal = 8000, hex = 1F40), and LSB = 4 mV.

Figure 24. Bus Voltage Register (BRNG = 1)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF

At full-scale range = 16 V (decimal = 4000, hex = 0FA0), and LSB = 4 mV.

Figure 25. Bus Voltage Register (BRNG = 0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 — CNVR OVF

CNVR: Conversion Ready

Bit 1 Although the data from the last conversion can be read at any time, the INA220 Conversion Ready bit (CNVR)

indicates when data from a conversion is available in the data output registers. The CNVR bit is set after all

conversions, averaging, and multiplications are complete. CNVR will clear under the following conditions:

1.) Writing a new mode into the Operating Mode bits in the Configuration Register (except for Power-Down or

Disable)

2.) Reading the Power Register

OVF: Math Overflow Flag

Bit 0 The Math Overflow Flag (OVF) is set when the Power or Current calculations are out of range. It indicates that

current and power data may be meaningless.

8.6.3.3 Power Register (address = 03h) [reset = 00h]

Full-scale range and LSB are set by the Calibration register. See Programming the INA220 Calibration Register.

Figure 26. Power Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

The Power register records power in watts by multiplying the values of the current with the value of the bus

voltage according to the Equation 5:

8.6.3.4 Current Register (address = 04h) [reset =00h]

Full-scale range and LSB depend on the value entered in the Calibration register. See Programming the INA220

Calibration Register. Negative values are stored in 2's complement format.

Figure 27. Current Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CSIGN CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

I TEXAS INSTRUMENTS

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The value of the Current register is calculated by multiplying the value in the Shunt Voltage register with the

value in the Calibration register according to the Equation 4.

8.6.4 Calibration Register

8.6.4.1 Calibration Register (address = 05h) [reset = 00h]

Current and power calibration are set by bits FS15 to FS1 of the Calibration register. Note that bit FS0 is not

used in the calculation. This register sets the current that corresponds to a full-scale drop across the shunt. Full-

scale range and the LSB of the current and power measurement depend on the value entered in this register.

See the Programming the INA220 Calibration Register. This register is suitable for use in overall system

calibration. Note that the 0 POR values are all default.

(1) FS0 is a void bit and will always be 0. It is not possible to write a 1 to FS0. CALIBRATION is the value stored in FS15:FS1.

Figure 28. Calibration Register(1)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

l TEXAS INSTRUMENTS

×Power Register

Current Register

I C-/SMBUS-

Compatible

Interface

Voltage Register

V (Supply Voltage)

ADC

INA220

GND

VIN+

VIN-

SDA DATA

SCL CLK

CBYPASS

0.1µF

+3.3V to

+5V

Bus Voltage Input

High-

Side

Shunt

Low-

Side

Shunt R1F

R2F

Load

Supply (0 to 26V)

INA220

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The INA220 is a digital current-shunt monitor with an I2C- and SMBus-compatible interface. It provides digital

current, voltage, and power readings necessary for accurate decision-making in precisely-controlled systems.

Programmable registers allow flexible configuration for measurement resolution, and continuous-versus-triggered

operation. See Table 2 for detailed register information. See Figure 29 for a block diagram of the INA220.

9.2 Typical Application

Figure 29 shows a typical application circuit for the INA220. Use a 0.1-μF ceramic capacitor for power-supply

bypassing, placed as closely as possible to the supply and ground pins.

The input filter circuit consisting of RF1, RF2, and CFis not necessary in most applications. If the need for filtering

is unknown, reserve board space for the components and install 0-Ωresistors unless a filter is needed. See

Filtering and Input Considerations.

Figure 29. General Load, Low- or High-Side Sensing

9.2.1 Design Requirements

The INA220 measures the voltage across a current-sensing resistor (RSHUNT) when current passes through the

resistor. The device also measures the bus supply voltage, and calculates power when calibrated. This section

goes through the steps to program the device for power measurements, and shows the register results in

Table 7. The Conditions for the example circuit is: Maximum expected load current = 15 A, Nominal load current

= 10 A, VCM = 12 V, RSHUNT =2mΩ, VSHUNT FSR = 40 mV (PGA = /1), and BRNG = 0 (VBUS range = 16 V).

9.2.2 Detailed Design Procedure

In this example, the 10-A load creates a differential voltage of 20 mV across a 2-mΩshunt resistor. The voltage

present at the IN– pin is equal to the common-mode voltage minus the differential drop across the resistor. The

bus voltage for the INA220 is measured at the external VBUS input pin, which in this example is connected to

the IN– pin to measure the voltage level delivered to the load. For this example, the voltage at the IN– pin is

11.98 V. For this particular range (40-mV full-scale), this small difference is not a significant deviation from the

12-V common-mode voltage. However, at larger full-scale ranges, this deviation can be much larger.

l TEXAS INSTRUMENTS

RSHUNT

2mΩ 10A

Load

+12V

VCM

GND

VIN+

VIN-

Power Register

I C-/

SMBUS

Compatible

Interface

Current Register

Voltage Register

SDA

SCK

0.1µF10µF

+3.3V to +5V

V (Supply Voltage)

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Typical Application (continued)

Note that the Bus Voltage register bits are not right-aligned. To compute the value of the Bus Voltage register

contents using the LSB of 4 mV, the register must be shifted right by three bits. This shift puts the BD0 bit in the

LSB position so that the contents can be multiplied by the 4-mV LSB value to compute the bus voltage measured

by the device. The shifted value of the bus voltage register contents is now equal to BB3h, a decimal equivalent

of 2995. This value of 2995 multiplied by the 4-mV LSB results in a value of 11.98 V.

The Calibration register (05h) is set to provide the device information about the current shunt resistor that was

used to create the measured shunt voltage. By knowing the value of the shunt resistor, the device can then

calculate the amount of current that created the measured shunt voltage drop. The first step when calculating the

calibration value is setting the current LSB. The Calibration register value is based on a calculation that has its

precision capability limited by the size of the register and the Current register LSB. The device can measure

bidirectional current; thus, the MSB of the Current register is a sign bit that allows for the rest of the 15 bits to be

used for the Current register value. For this example, the minimum current LSB would be 457.78 µA/bit assuming

a maximum expected current of 15 A using Equation 2. For this example, a value of 1 mA/bit was chosen for the

current LSB. Setting the current LSB to this value allows for sufficient precision while serving to simplify the math

as well. Using Equation 1 results in a Calibration register value of 20480 or 5000h.

The Current register (04h) is internally calculated by multiplying the shunt voltage contents by the Calibration

the Calibration register of 20480 and then divided by 4096 to yield a Current register value of 10000 (2710h).

The Power register (03h) is internally calculated by multiplying the Current register value of 10000 by the Bus

Voltage register value of 2995 and then dividing by 5000 using Equation 5. For this example, the Power register

contents are 5990 (1766h). Multiplying this result by the power LSB that is 20 times the 1 × 10–3 current LSB, or

20 × 10–3, results in a power calculation of 5990 × 20 mW/bit, which equals 119.8 W. This result matches what is

expected for this register. A manual calculation for the power being delivered to the load would use 11.98 V

(12 VCM – 20 mV shunt drop) multiplied by the load current of 10 A to give a 119.8-W result.

Figure 30. Example Circuit Configuration

l TEXAS INSTRUMENTS s

Data

Clock

Current Register I C-/SMBUS

Compatible

Interface

Voltage Register

VIN+

ADC

INA220

GND

V (

SSupply Voltage)

V (Bus Voltage Input)

BUS

Shunt

(40mV max

for 12-bit)

4.3kW

+3.3V to +5V

1/4W Zener

or shunt reg

HCPL2300

4.3kW

SDA

SCL

+5V

35.7kW

13.7kW

24V

Tranzorb Power Register

-48V

Supply

-48V

to Load

VIN-

0.1 Fm

10 Fm

0.1 Fm

-48V

Supply 0.1mF

INA220

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Product Folder Links: INA220

Typical Application (continued)

(1) Conditions: load = 10 A, VCM = 12 V, RSHUNT = 2 mΩ, VSHUNT FSR = 40 mV, and VBUS = 16 V.

9.2.2.1 Register Results for the Example Circuit

Table 7 shows the register readings for the Calibration example.

Table 7. Register Results(1)

Configuration 00h 019Fh

Shunt 01h 07D0h 2000 10 µV 20 mV

Bus 02h 5D98h 0BB3 2995 4 mV 11.98 V

Calibration 05h 5000h 20480

Current 04h 2710h 10000 1 mA 10.0 A

Power 03h 1766h 5990 20 mW 119.8 W

9.2.3 Typical Application: –48-V Telecom Current/Voltage/Power Sense With Isolation

Figure 31,Figure 32, and Figure 33 show the INA220 in additional circuit configurations for current, voltage, and

power monitoring applications.

Figure 31. –48-V Telecom Current/Voltage/Power Sense With Isolation

l TEXAS INSTRUMENTS

×Power Register

Current Register I C-/SMBUS

Compatible

Interface

Voltage Register

V (Supply Voltage)

ADC

INA220

GND

VIN+

VIN-

SDA DATA

SCL CLK

CBYPASS

0.1µF

+3.3V to

+5V

Bus Voltage Input

R1F

R2F

Load

Address

Select

Shunt

(40mV

max

for

12-bit)

Battery

From

Supply Load

10kΩ

Data

(SDA)

Clock

(SCL)

×Power Register

Current Register I C-/SMBUS

Compatible

Interface

Voltage Register

VIN+

ADC

INA220

GND

VIN-

V (

SSupply Voltage)

V (Bus Voltage Input)

BUS

10µF

0.1µF

+3.3V to

+5V

OPA333

100Ω

35.7kΩ

13.7kΩ

Shunt

RSHUNT

5.1V

Zener

24V

Tranzorb

100Ω

MOSFET rated to

standoff supply voltage

such as BSS84 for

up to 50V

INA220

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Product Folder Links: INA220

9.2.4 Typical Application: 48-V Telecom Current/Voltage/Power Sense

Figure 32. 48-V Telecom Current/Voltage/Power Sense

9.2.5 Typical Application: General Source Low-Side Sensing

Figure 33. General Source Low-Side Sensing

l TEXAS INSTRUMENTS

Supply bypass

capacitor

SDA

IN+

IN±

GND

VBUS

SCL VS

(1)

I2C/SMBUS

interface

Via to Ground Plane

Via to Power Plane

Sense/Shunt

Resistor

INA220

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10 Power Supply Recommendations

The input circuitry of the device can accurately measure signals on common-mode voltages beyond its power

supply voltage, VS. For example, the voltage applied to the VSpower supply terminal can be 5 V, whereas the

load power-supply voltage being monitored (the common-mode voltage) can be as high as 26 V. Note also that

the device can withstand the full 0-V to 26-V range at the input terminals, regardless of whether the device has

power applied or not. Place the required power-supply bypass capacitors as close as possible to the supply and

ground terminals of the device to ensure stability. A typical value for this supply bypass capacitor is 0.1 μF.

Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject

power-supply noise.

11 Layout

11.1 Layout Guidelines

Connect the input pins (IN+ and IN–) to the sensing resistor using a Kelvin connection or a 4-wire connection.

These connection techniques ensure that only the current-sensing resistor impedance is detected between the

input pins. Poor routing of the current-sensing resistor commonly results in additional resistance present between

the input pins. Given the very low ohmic value of the current-sensing resistor, any additional high-current carrying

impedance causes significant measurement errors. Place the power-supply bypass capacitor as close as

possible to the supply and ground pins.

11.2 Layout Example

(1) Connect the VBUS pin to the power supply rail

Figure 34. Layout Recommendation

l TEXAS INSTRUMENTS Am

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12 Device and Documentation Support

12.1 Related Documentation

For related documentation see the TPS2490/1 Positive High-Voltage Power-Limiting Hotswap Controller data

sheet (SLVS503).

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com

PACKAGE OUTLINE

TYP

5.05

4.75

1.1 MAX

8X 0.5

10X 0.27

0.17

0.15

0.05

TYP

0.23

0.13

0 - 8

0.25

GAGE PLANE

0.7

0.4

NOTE 3

3.1

2.9

NOTE 4

3.1

2.9

4221984/A 05/2015

VSSOP - 1.1 mm max height

DGS0010A

SMALL OUTLINE PACKAGE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

110

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

TYPICAL

DETAIL A

SCALE 3.200

INA220

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Product Folder Links: INA220

‘5‘ TEXAS INSTRUMENTS www.“ com

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EXAMPLE BOARD LAYOUT

(4.4)

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

10X (1.45)

10X (0.3)

8X (0.5)

(R )

TYP

0.05

4221984/A 05/2015

SYMM

VSSOP - 1.1 mm max height

DGS0010A

SMALL OUTLINE PACKAGE

SYMM

LAND PATTERN EXAMPLE

SCALE:10X

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

NOT TO SCALE

SOLDER MASK DETAILS

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

INA220

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Product Folder Links: INA220

‘5‘ TEXAS INSTRUMENTS www.“ com

www.ti.com

EXAMPLE STENCIL DESIGN

(4.4)

8X (0.5)

10X (0.3)

10X (1.45)

(R ) TYP0.05

4221984/A 05/2015

VSSOP - 1.1 mm max height

DGS0010A

SMALL OUTLINE PACKAGE

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

BASED ON 0.125 mm THICK STENCIL

SOLDER PASTE EXAMPLE

SCALE:10X

INA220

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I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

INA220AIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OOUI

INA220AIDGST ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OOUI

INA220BIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ZAEI

INA220BIDGST ACTIVE VSSOP DGS 10 250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ZAEI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF INA220 :

•Automotive: INA220-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+Ko '«Pt» Reel DlameIer A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component Iength K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier Iape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE DOODOOOD ,,,,,,,,,,, ‘ User Direcllon 0' Feed SprockeI Hoies Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

INA220AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

INA220AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

INA220AIDGST VSSOP DGS 10 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

INA220AIDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

INA220BIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

INA220BIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

INA220BIDGST VSSOP DGS 10 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

INA220BIDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2021

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

INA220AIDGSR VSSOP DGS 10 2500 367.0 367.0 38.0

INA220AIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0

INA220AIDGST VSSOP DGS 10 250 366.0 364.0 50.0

INA220AIDGST VSSOP DGS 10 250 213.0 191.0 35.0

INA220BIDGSR VSSOP DGS 10 2500 367.0 367.0 38.0

INA220BIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0

INA220BIDGST VSSOP DGS 10 250 366.0 364.0 50.0

INA220BIDGST VSSOP DGS 10 250 213.0 191.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2021

Pack Materials-Page 2

DGSOO10A I

www.ti.com

PACKAGE OUTLINE

TYP

5.05

4.75

1.1 MAX

8X 0.5

10X 0.27

0.17

0.15

0.05

TYP

0.23

0.13

0 - 8

0.25

GAGE PLANE

0.7

0.4

NOTE 3

3.1

2.9

NOTE 4

3.1

2.9

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

110

0.1 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 3.200

DGSOO10A

www.ti.com

EXAMPLE BOARD LAYOUT

(4.4)

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

10X (1.45)

10X (0.3)

8X (0.5)

(R )

TYP

0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

SYMM

LAND PATTERN EXAMPLE

SCALE:10X

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

DGSOO10A

www.ti.com

EXAMPLE STENCIL DESIGN

(4.4)

8X (0.5)

10X (0.3)

10X (1.45)

(R ) TYP0.05

4221984/A 05/2015

VSSOP - 1.1 mm max heightDGS0010A

SMALL OUTLINE PACKAGE

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

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