ATMEGA64A Summary Datasheet by Microchip Technology

AtmeE
8-bit AVR Micrcontroller
ATmega64A
DATASHEET SUMMARY
Introduction
The Atmel® ATmega64A is a low-power CMOS 8-bit microcontroller based
on the AVR® enhanced RISC architecture. By executing powerful instructions
in a single clock cycle, the ATmega64A achieves throughputs close to
1MIPS per MHz. This empowers system designer to optimize the device for
power consumption versus processing speed.
Features
•High-performance, Low-power Atmel AVR 8-bit Microcontroller
•Advanced RISC Architecture
–130 Powerful Instructions - Most Single-clock Cycle Execution
–32 × 8 General Purpose Working Registers + Peripheral Control
Registers
–Fully Static Operation
–Up to 16MIPS Throughput at 16MHz
–On-chip 2-cycle Multiplier
•High Endurance Non-volatile Memory segments
–64Kbytes of In-System Self-programmable Flash program
memory
–2Kbytes EEPROM
–4Kbytes Internal SRAM
–Write/Erase cycles: 10,000 Flash/100,000 EEPROM
–Data retention: 20 years at 85°C/100 years at 25°C(1)
–Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
–Up to 64 Kbytes Optional External Memory Space
–Programming Lock for Software Security
–SPI Interface for In-System Programming
•JTAG (IEEE std. 1149.1 Compliant) Interface
–Boundary-scan Capabilities According to the JTAG Standard
–Extensive On-chip Debug Support
Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015
This is a summary document. A
complete document is available
on our Web site at
www.atmel.com
Atmel
–Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
•Atmel QTouch® library support
–Capacitive touch buttons, sliders and wheels
–Atmel QTouch and QMatrix acquisition
–Up to 64 sense channels
•Peripheral Features
–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
–Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture
Mode
–Real Time Counter with Separate Oscillator
–Two 8-bit PWM Channels
–6 PWM Channels with Programmable Resolution from 1 to 16 Bits
–Output Compare Modulator
–8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
–Byte-oriented Two-wire Serial Interface
–Dual Programmable Serial USARTs
–Master/Slave SPI Serial Interface
–Programmable Watchdog Timer with On-chip Oscillator
–On-chip Analog Comparator
•Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection
–Internal Calibrated RC Oscillator
–External and Internal Interrupt Sources
–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
–Software Selectable Clock Frequency
–ATmega103 Compatibility Mode Selected by a Fuse
–Global Pull-up Disable
•I/O and Packages
–53 Programmable I/O Lines
–64-lead TQFP and 64-pad QFN/MLF
•Operating Voltages
–2.7 - 5.5V
•Speed Grades
–0 - 16MHz
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Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description.................................................................................................................4
2. Configuration Summary............................................................................................. 5
3. Ordering Information..................................................................................................6
4. Block Diagram........................................................................................................... 7
5. ATmega103 and ATmega64A Compatibility.............................................................. 8
5.1. ATmega103 Compatibility Mode...................................................................................................8
6. Pin Configurations..................................................................................................... 9
6.1. Pin Descriptions............................................................................................................................9
7. Resources................................................................................................................12
8. Data Retention.........................................................................................................13
9. About Code Examples.............................................................................................14
10. Capacitive Touch Sensing....................................................................................... 15
11. Packaging Information.............................................................................................16
11.1. 64A............................................................................................................................................. 16
11.2. 64M1...........................................................................................................................................17
12. Errata.......................................................................................................................18
12.1. ATmega64A Rev. D.................................................................................................................... 18
Atmel
1. Description
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with Read-
While- Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes
and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional
differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip
Debug system and programming, and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with
low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer
continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot Program can use any interface to download the Application Program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega64A is a powerful microcontroller that
provides a highly-flexible and cost-effective solution to many embedded control applications.
The ATmega64A AVR is supported with a full suite of program and system development tools including: C
compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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Atmel
2. Configuration Summary
Features ATmega64A
Pin count 64
Flash (KB) 64
SRAM (KB) 4
EEPROM (KB) 2
General Purpose I/O pins 53
SPI 1
TWI (I2C) 1
USART 2
ADC 10-bit, up to 76.9ksps (15ksps at max resolution)
ADC channels 6 (8 in TQFP and QFN/MLF packages)
AC propagation delay Typ 400ns
8-bit Timer/Counters 2
16-bit Timer/Counters 1
PWM channels 8
RC Oscillator +/-3%
VREF Bandgap
Operating voltage 2.7 - 5.5V
Max operating frequency 16MHz
Temperature range -55°C to +125°C
JTAG Yes
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Atmel
3. Ordering Information
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
16 2.7 - 5.5V
ATmega64A-AU
ATmega64A-AUR(3)
ATmega64A-MU
ATmega64A-MUR(3)
64A
64A
64M1
64M1
Industrial (-40oC to 85oC)
ATmega64A-AN
ATmega64A-ANR(3)
ATmega64A-MN
ATmega64A-MNR(3)
64A
64A
64M1
64M1
Extended (-40oC to 105oC)(4)
Note: 
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape and Reel
4. See characterization specifications at 105°C
Package Type
64A 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package
(QFN/MLF)
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4. Block Diagram
Figure 4-1 Block Diagram
CPU
ADC ADC[7:0]
AREF
I/O
PORTS
D
A
T
A
B
U
S
SRAM
OCD FLASH
NVM
programming
JTAG
TC 0
(8-bit async)
SPI
AC
AIN0
AIN1
ACO
ADCMUX
EEPROM
EEPROMIF
TC 3
(16-bit)
OC3A/B
T3
ICP3
TWI
SDA
SCL
USART 1
RxD1
TxD1
XCK1
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Power
Supervision
POR/BOD &
RESET
TOSC2
XTAL2
RESET
XTAL1
TOSC1
TCK
TMS
TDI
TDO
INT[7:0]
OC0
MISO
MOSI
SCK
SS
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF[7:0]
PG[4:0]
USART 0
RxD0
TxD0
XCK0
TC 1
(16-bit)
OC1A/B/C
T1
ICP1
TC 2
(8-bit)
T2
OC2
AD[7:0]
A[15:8]
RD/WR/ALE
ExtMem
ExtInt
SERPROG
PARPROG
PEN
PDI
PDO
SCK
Clock generation
1MHz int
osc
32.768kHz
XOSC
External
clock
8MHz
Crystal Osc
12MHz
External
RC Osc
8MHz
Calib RC
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Atmel
5. ATmega103 and ATmega64A Compatibility
The ATmega64A is a highly complex microcontroller where the number of I/O locations supersedes the
64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the
ATmega103, all I/O locations present in ATmega103 have the same location in ATmega64A. Most
additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (that is, in the
ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and
ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM
space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might
be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility
mode can be selected by programming the fuse M103C. In this mode, none of the functions in the
Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended
Interrupt vectors are removed.
The Atmel AVR ATmega64A is 100% pin compatible with ATmega103, and can replace the ATmega103
on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega64A” describes
what the user should be aware of replacing the ATmega103 by an ATmega64A.
5.1. ATmega103 Compatibility Mode
By programming the M103C fuse, the ATmega64A will be compatible with the ATmega103 regards to
RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega64A are
not available in this compatibility mode, these features are listed below:
•One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the
Baud Rate Register is available.
•One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters with
three compare registers.
•Two-wire serial interface is not supported.
•Port C is output only.
•Port G serves alternate functions only (not a general I/O port).
•Port F serves as digital input only in addition to analog input to the ADC.
•Boot Loader capabilities is not supported.
•It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
•The External Memory Interface can not release any Address pins for general I/O, neither configure
different wait-states to different External Memory Address sections.
•In addition, there are some other minor differences to make it more compatible to ATmega103:
•Only EXTRF and PORF exists in MCUCSR.
•Timed sequence not required for Watchdog Time-out change.
•External Interrupt pins 3 - 0 serve as level interrupt only.
•USART has no FIFO buffer, so data overrun comes earlier.
Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega64A.
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Ell-III Atmel (g) PEN GND AREF GND VCC PAO (ADO) PAl (ADI) PAZ (ADZ) RESET VCC GN D :1 PAS (ADS) j PA4(AD4) 3 ms (ADS) j mums) j PA7(AD7) :1 P02 (ALE) j PC7 (A15) :1 PC6(A14) 3 PCS (A13) 3 PC4 (A12) :1 Pcs (A11) 3 PCZ (A10) :1 PC1(A9) :1 PCO(A8) 3 m1 (E) 3 mo (W)
6. Pin Configurations
Figure 6-1 Pinout ATmega64A
1
2
3
4
44
43
42
41
40
39
38
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
45
46
47
48
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RESET
VCC
GND
GND
VCC
AREF
AVCC
GND
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1 (RD)
PG0 (WR)
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PF7 (ADC7/TDI)
PF6 (ADC6/TDO)
PF5 (ADC5/TMS)
PF4 (ADC4/TCK)
PF3 (ADC3)
PF2 (ADC2)
PF1 (ADC1)
PF0 (ADC0)
XTAL2
XTAL1
(TOSC1) PG4
(TOSC2) PG3
(OC2/OC1C) PB7
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T2) PD7
PEN
(RXD0/PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(ICP3/INT7) PE7
(SS) PB0
(SCK) PB1
(MOSI) PB2
(MISO) PB3
(OC0) PB4
(OC1A) PB5
(OC1B) PB6
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
External Memory
Note:  The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF
package should be soldered to ground.
6.1. Pin Descriptions
6.1.1. VCC
Digital supply voltage.
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Atmel
6.1.2. GND
Ground.
6.1.3. Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
A pins are tristated when a reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port A.
6.1.4. Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port B.
6.1.5. Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tristated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the ATmega64A as listed in Alternate Functions of
Port C. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated
when a reset condition becomes active.
Note:  The Atmel AVR ATmega64A is by default shipped in ATmega103 compatibility mode. Thus, if the
parts are not programmed before they are put on the PCB, PORTC will be output during first power up,
and until the ATmega103 compatibility mode is disabled.
6.1.6. Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tristated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port D.
6.1.7. Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
E pins are tristated when a reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port E.
6.1.8. Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
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Atmel
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can
provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset
condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up
resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input Port only.
6.1.9. Port G (PG4:PG0)
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
G pins are tristated when a reset condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features.
The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.
In Atmel AVR ATmega103 compatibility mode, these pins only serves as strobes signals to the external
memory as well as input to the 32kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and
PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3
and PG4 are oscillator pins.
6.1.10. RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. The minimum pulse length is given in System and Reset Characteristics. Shorter
pulses are not guaranteed to generate a reset.
6.1.11. XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
6.1.12. XTAL2
Output from the inverting Oscillator amplifier.
6.1.13. AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC,
even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
6.1.14. AREF
AREF is the analog reference pin for the A/D Converter.
6.1.15. PEN
PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high. By
holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode.
PEN has no function during normal operation.
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Atmel
7. Resources
A comprehensive set of development tools, application notes and datasheets are available for download
on http://www.atmel.com/avr.
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Atmel
8. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
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Atmel
9. About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware
that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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Atmel
10. Capacitive Touch Sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most
Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix®
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.
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Atmel DRAWING ND, Atmel
11. Packaging Information
11.1. 64A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO. REV.
64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,
0.8mm Lead Pitch, Thin Prof le Plastic Quad Flat Package (TQFP) C
64A
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
e
E1 E
B
COMMON DIMENSIONS
(Unit of measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
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123 U’UUJU \ :ij UUUUUUUU 2232:3232: ccccctcccccccccc D 2 4mm nnnnnnnnnnnnnnnn _|_ E. * f! DRAWINGN O. Atmet
11.2. 64M1
2325 Orchard Pa rkway
San Jos e, CA 9513 1
TITLE DR AWING N O. RE V.
64M1 , 64-pad, 9 x 9 x 1.0 mm Bod y, Lead Pitch 0.50 mm , H
64M1
2010-10-19
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 – 0.02 0.05
b 0.18 0.25 0.30
D
D2 5.20 5.40 5.60
8.90 9.00 9.10
8.90 9.00 9.10
E
E2 5.20 5.40 5.60
e 0.50 BSC
L 0.35 0.40 0.45
Notes:
1 . JEDEC Standard MO-220, (S AW Singulation) Fig . 1, VMM D.
2 . Dimension and tole rance con form to ASMEY14.5M-1994 .
TOP VIE W
SIDE VIEW
BOTTOM VIE W
D
E
Ma rked Pin# 1 I D
SE ATING PLAN E
A1
C
A
C
0.08
1
2
3
K 1.25 1.40 1.55
E2
D2
be
Pin #1 Co rne r
L
Pin #1
Triangle
Pin #1
Cham fer
(C 0.30)
Option A
Option B
Pin #1
Notch
(0.20 R)
Option C
K
K
5.40 mm Exposed Pad, Micro Lead Frame Pa ckage (MLF)
Atmel ATmega64A [DATASHEET]
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Atmel
12. Errata
The revision letter in this section refers to the revision of the ATmega64A device.
12.1. ATmega64A Rev. D
•First Analog Comparator conversion may be delayed
•Interrupts may be lost when writing the timer registers in the asynchronous timer
•Stabilizing time needed when changing XDIV Register
•Stabilizing time needed when changing OSCCAL Register
•IDCODE masks data from TDI input
•Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take
longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable the Analog Comparator before
the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous Timer/Counter register (TCNTx) is 0x00.
Problem Fix/Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00
before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter
Register (TCNTx), or asynchronous Output Compare Register (OCRx).
3. Stabilizing time needed when changing XDIV Register
After increasing the source clock frequency more than 2% with settings in the XDIV register, the
device may execute some of the subsequent instructions incorrectly.
Problem Fix/Workaround
The NOP instruction will always be executed correctly also right after a frequency change. Thus,
the next 8 instructions after the change should be NOP instructions. To ensure this, follow this
procedure:
3.1. Clear the I bit in the SREG Register.
3.2. Set the new pre-scaling factor in XDIV register.
3.3. Execute 8 NOP instructions
3.4. Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI ; clear global interrupt enable
OUT XDIV, temp ; set new prescale value
NOP ; no operation
NOP ; no operation
NOP ; no operation
Atmel ATmega64A [DATASHEET]
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Atmel
NOP ; no operation
NOP ; no operation
NOP ; no operation
NOP ; no operation
NOP ; no operation
SEI ; set global interrupt enable
4. Stabilizing time needed when changing OSCCAL Register
After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the
device may execute some of the subsequent instructions incorrectly.
Problem Fix/Workaround
The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata.
5. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by
all-ones during Update-DR.
Problem Fix/Workaround
–If ATmega64A is the only device in the scan chain, the problem is not visible.
–Select the Device ID Register of the ATmega64A by issuing the IDCODE instruction or by
entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device
ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS
instruction to the ATmega64A while reading the Device ID Registers of preceding devices of
the boundary scan chain.
–If the Device IDs of all devices in the boundary scan chain must be captured simultaneously,
the ATmega64A must be the first device in the chain.
6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register
triggers an unexpected EEPROM interrupt request.
Problem Fix/Workaround
Always use OUT or SBI to set EERE in EECR.
Atmel ATmega64A [DATASHEET]
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Atmet ‘Enabllng Unlimited Possnbllltles‘ “um-ID
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