Datasheet

P|C18CXX2 Z::::::::: jjjjjjjjjjjjjjjjjjjj EEEEEEEEEEEEEEEEEEEE :I:::::::: MICROCHIP
1999-2013 Microchip Technology Inc. DS39026D-page 1
PIC18CXX2
High Performance RISC CPU:
• C compiler optimized architecture/instruction set
- Source code compatible with the PIC16CXX
instruction set
• Linear program memory addressing to 2 Mbytes
•Linear data memory addressing to 4 Kbytes
• Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time-base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules.
CCP pins that can be configured as:
- Capture input: capture is 16-bit,
max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit.
Max. PWM freq. @: 8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Master Synchronous Serial Port (MSSP) module.
Two modes of operation:
- 3-wire SPI (supports all 4 SPI modes)
-I
2C™ master and slave mode
• Addressable USART module:
- Supports interrupt on Address bit
• Parallel Slave Port (PSP) module
Pin Diagrams
Analog Features:
• Compatible 10-bit Analog-to-Digital Converter
module (A/D) with:
- Fast sampling rate
- Conversion available during SLEEP
- DNL = ±1 LSb, INL = ±1 LSb
• Programmable Low Voltage Detection (LVD)
module
- Supports interrupt-on-low voltage detection
• Programmable Brown-out Reset (BOR)
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming (ICSP™) via two pins
CMOS Technology:
• Low power, high speed EPROM technology
• Fully static design
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
Device
On-Chip Program Memory On-Chip
RAM
(bytes)
EPROM
(bytes) # Single Word
Instructions
PIC18C242 16K 8192 512
PIC18C252 32K 16384 1536
PIC18C442 16K 8192 512
PIC18C452 32K 16384 1536
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18C4X2
* RB3 is the alternate pin for the CCP2 pin multiplexing.
DIP, Windowed CERDIP
Note: Pin compatible with 40-pin PIC16C7X devices.
High Performance Microcontrollers with 10-bit A/D
E:::: :3: : w, 1 M75 w a 1 a
PIC18CXX2
DS39026D-page 2 1999-2013 Microchip Technology Inc.
Pin Diagrams
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
PIC18C4X2
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
OSC2/CLKO/RA6
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
OSC1/CLKI
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18C4X2
37
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2*
PLCC
TQFP
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 44-pin PIC16C7X devices.
VSS
RC0/T1OSO/T1CKI
1999-2013 Microchip Technology Inc. DS39026D-page 3
PIC18CXX2
Pin Diagrams (Cont.’d)
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18C4X2
PIC18C2X2
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
* RB3 is the alternate pin for the CCP2 pin multiplexing.
DIP, JW
DIP, SOIC, JW
Note: Pin compatible with 40-pin PIC16C7X devices.
Note: Pin compatible with 28-pin PIC16C7X devices.
PIC18CXX2
DS39026D-page 4 1999-2013 Microchip Technology Inc.
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 7
2.0 Oscillator Configurations........................................................................................................................................................... 17
3.0 Reset......................................................................................................................................................................................... 25
4.0 Memory Organization................................................................................................................................................................ 35
5.0 Table Reads/Table Writes ........................................................................................................................................................ 55
6.0 8 X 8 Hardware Multiplier.......................................................................................................................................................... 61
7.0 Interrupts................................................................................................................................................................................... 63
8.0 I/O Ports.................................................................................................................................................................................... 77
9.0 Timer0 Module.......................................................................................................................................................................... 93
10.0 Timer1 Module.......................................................................................................................................................................... 97
11.0 Timer2 Module........................................................................................................................................................................ 101
12.0 Timer3 Module........................................................................................................................................................................ 103
13.0 Capture/Compare/PWM (CCP) Modules................................................................................................................................ 107
14.0 Master Synchronous Serial Port (MSSP) Module................................................................................................................... 115
15.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................ 149
16.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module ................................................................................................. 165
17.0 Low Voltage Detect................................................................................................................................................................. 173
18.0 Special Features of the CPU .................................................................................................................................................. 179
19.0 Instruction Set Summary......................................................................................................................................................... 187
20.0 Development Support ............................................................................................................................................................. 229
21.0 Electrical Characteristics......................................................................................................................................................... 235
22.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 263
23.0 Packaging Information ............................................................................................................................................................ 277
Appendix A: Revision History......................................................................................................................................................... 287
Appendix B: Device Differences..................................................................................................................................................... 287
Appendix C: Conversion Considerations........................................................................................................................................ 288
Appendix D: Migration from Baseline to Enhanced Devices .......................................................................................................... 288
Appendix E: Migration from Mid-Range to Enhanced Devices ...................................................................................................... 289
Appendix F: Migration from High-End to Enhanced Devices......................................................................................................... 289
Index ................................................................................................................................................................................................. 291
On-Line Support................................................................................................................................................................................ 299
Reader Response ............................................................................................................................................................................. 300
PIC18CXX2 Product Identification System ....................................................................................................................................... 301
1999-2013 Microchip Technology Inc. DS39026D-page 5
PIC18CXX2
TO OUR VALUED CUSTOMERS
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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We welcome your feedback.
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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PIC18CXX2
DS39026D-page 6 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 7
PIC18CXX2
1.0 DEVICE OVERVIEW
This document contains device specific information for
the following four devices:
1. PIC18C242
2. PIC18C252
3. PIC18C442
4. PIC18C452
These devices come in 28-pin and 40-pin packages.
The 28-pin devices do not have a Parallel Slave Port
(PSP) implemented and the number of Analog-to-
Digital (A/D) converter input channels is reduced to 5.
An overview of features is shown in Table 1-1.
The following two figures are device block diagrams
sorted by pin count: 28-pin for Figure 1-1 and 40-pin for
Figure 1-2. The 28-pin and 40-pin pinouts are listed in
Table 1-2 and Table 1-3, respectively.
TABLE 1-1: DEVICE FEATURES
Features PIC18C242 PIC18C252 PIC18C442 PIC18C452
Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz
Program Memory (Bytes) 16K 32K 16K 32K
Program Memory (Instructions) 8192 16384 8192 16384
Data Memory (Bytes) 512 1536 512 1536
Interrupt Sources 16 16 17 17
I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E
Timers 44 44
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
Parallel Communications — — PSP PSP
10-bit Analog-to-Digital Module 5 input channels 5 input channels 8 input channels 8 input channels
RESETS (and Delays) POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Programmable Low Voltage
Detect Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions
Packages 28-pin DIP
28-pin SOIC
28-pin JW
28-pin DIP
28-pin SOIC
28-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
1 L
PIC18CXX2
DS39026D-page 8 1999-2013 Microchip Technology Inc.
FIGURE 1-1: PIC18C2X2 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RB0/INT0
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
Addressable
CCP1 Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
4X PLL
A/D Converter
Precision
Reference
RB1/INT1
Data Latch
Data RAM
Address Latch
Address<12>
12(2)
BSR FSR0
FSR1
FSR2
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP 8
8
ALU<8>
8
Address Latch
Program Memory
(up to 2M Bytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21
8
Data Bus<8>
8
Instruction
12
3
ROM Latch
Timer3
CCP2
RB2/INT2
RB3/CCP2(1)
T1OSI
T1OSO
Bank0, F
PCLATU
PCU
RA6
Voltage
USART
Master
8
Register
Table Latch
Table Pointer <2>
inc/dec
logic
Decode
1999-2013 Microchip Technology Inc. DS39026D-page 9
PIC18CXX2
FIGURE 1-2: PIC18C4X2 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RB0/INT0
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
Addressable
CCP1
Master
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Parallel Slave Port
Timing
Generation
4X PLL
A/D Converter
RB1/INT1
Data Latch
Data RAM
(up to 4K
address reach)
Address Latch
Address<12>
12(2)
Bank0, F
BSR FSR0
FSR1
FSR2
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP 8
8
ALU<8>
8
Address Latch
Program Memory
(up to 2M Bytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21
8
Data Bus<8>
8
Instruction
12
3
ROM Latch
Timer3
PORTD
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
CCP2
RB2/INT2
RB3/CCP2(1)
T1OSI
T1OSO
PCLATU
PCU
RA6
Precision
Reference
Voltage
Synchronous USART
Register
8
Table Pointer <2>
inc/dec
logic
Decode
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Table Latch
PIC18CXX2
DS39026D-page 10 1999-2013 Microchip Technology Inc.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP SOIC
MCLR/VPP
MCLR
VPP
11I
P
ST Master clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
NC — — — — These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
99I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 10 O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
22
I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
33
I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
44
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
55
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
T0CKI
66
I/O
IST/OD
ST Digital I/O. Open drain when configured as output.
Timer0 external clock input.
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
77
I/O
I
I
I
TTL
Analog
ST
Analog
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 11
PIC18CXX2
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
21 21 I/O
ITTL
ST Digital I/O.
External Interrupt 0.
RB1/INT1
RB1
INT1
22 22 I/O
ITTL
ST External Interrupt 1.
RB2/INT2
RB2
INT2
23 23 I/O
ITTL
ST Digital I/O.
External Interrupt 2.
RB3/CCP2
RB3
CCP2
24 24 I/O
I/O TTL
ST Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
RB4 25 25 I/O TTL Digital I/O.
Interrupt-on-change pin.
RB5 26 26 I/O TTL Digital I/O.
Interrupt-on-change pin.
RB6 27 27 I/O
I
TTL
ST
Digital I/O.
Interrupt-on-change pin.
ICSP programming clock.
RB7 28 28 I/O
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
ICSP programming data.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026D-page 12 1999-2013 Microchip Technology Inc.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 11 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12 12 I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
13 13 I/O
I/O ST
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 14 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 15 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
SDO
16 16 I/O
OST
—Digital I/O.
SPI Data Out.
RC6/TX/CK
RC6
TX
CK
17 17 I/O
O
I/O
ST
—
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
18 18 I/O
I
I/O
ST
ST
ST
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 13
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
MCLR/VPP
MCLR
VPP
1218
I
P
ST Master clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active
low RESET to the device.
Programming voltage input.
NC — — — These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
13 14 30 I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 15 31 O
O
I/O
—
—
TTL
Oscillator crystal output.
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT, which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
2319
I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3420
I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
4521
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
5622
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
T0CKI
6723
I/O
IST/OD
ST Digital I/O. Open drain when configured as output.
Timer0 external clock input.
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
7824
I/O
I
I
I
TTL
Analog
ST
Analog
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026D-page 14 1999-2013 Microchip Technology Inc.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0
RB0
INT0
33 36 8 I/O
ITTL
ST Digital I/O.
External Interrupt 0.
RB1/INT1
RB1
INT1
34 37 9 I/O
ITTL
ST External Interrupt 1.
RB2/INT2
RB2
INT2
35 38 10 I/O
ITTL
ST Digital I/O.
External Interrupt 2.
RB3/CCP2
RB3
CCP2
36 39 11 I/O
I/O TTL
ST Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
RB4 37 41 14 I/O TTL Digital I/O. Interrupt-on-change pin.
RB5 38 42 15 I/O TTL Digital I/O. Interrupt-on-change pin.
RB6 39 43 16 I/O
ITTL
ST Digital I/O. Interrupt-on-change pin.
ICSP programming clock.
RB7 40 44 17 I/O
I/O TTL
ST Digital I/O. Interrupt-on-change pin.
ICSP programming data.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 15
PIC18CXX2
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 16 32 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16 18 35 I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
17 19 36 I/O
I/O ST
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 20 37 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 25 42 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
SDO
24 26 43 I/O
OST
—Digital I/O.
SPI Data Out.
RC6/TX/CK
RC6
TX
CK
25 27 44 I/O
O
I/O
ST
—
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
26 29 1 I/O
I
I/O
ST
ST
ST
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026D-page 16 1999-2013 Microchip Technology Inc.
PORTD is a bi-directional I/O port, or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.
RD0/PSP0 19 21 38 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD1/PSP1 20 22 39 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD2/PSP2 21 23 40 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD3/PSP3 22 24 41 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD4/PSP4 27 30 2 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD5/PSP5 28 31 3 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD6/PSP6 29 32 4 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD7/PSP7 30 33 5 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8925I/O
ST
TTL
Analog
Digital I/O.
Read control for parallel slave port (see also WR
and CS pins).
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
91026I/OST
TTL
Analog
Digital I/O.
Write control for parallel slave port (see CS
and RD pins).
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 11 27 I/O ST
TTL
Analog
Digital I/O.
Chip Select control for parallel slave port (see related
RD and WR).
Analog input 7.
VSS 12, 31 13, 34 6, 29 P — Ground reference for logic and I/O pins.
VDD 11, 32 12, 35 7, 28 P — Positive supply for logic and I/O pins.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 17
PIC18CXX2
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
The PIC18CXX2 can be operated in eight different
oscillator modes. The user can program three configu-
ration bits (FOSC2, FOSC1, and FOSC0) to select one
of these eight modes:
1. LP Low Power Crystal
2. XT Crystal/Resonator
3. HS High Speed Crystal/Resonator
4. HS + PLL High Speed Crystal/Resonator
with x 4 PLL enabled
5. RC External Resistor/Capacitor
6. RCIO External Resistor/Capacitor with
RA6 I/O pin enabled
7. EC External Clock
8. ECIO External Clock with RA6 I/O pin
enabled
2.2 Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HS-PLL oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The PIC18CXX2 oscillator design requires the use of a
parallel cut crystal.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
TABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
Ranges Tested:
Mode Freq C1 C2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only.
See notes following this table.
Resonators Used:
455 kHz Panasonic EFO-A455K04B 0.3%
2.0 MHz Murata Erie CSA2.00MG 0.5%
4.0 MHz Murata Erie CSA4.00MG 0.5%
8.0 MHz Murata Erie CSA8.00MT 0.5%
16.0 MHz Murata Erie CSA16.00MX 0.5%
All resonators used did not have built-in capacitors.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: When operating below 3V VDD, it may be
necessary to use high gain HS mode on
lower frequency ceramic resonators.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents or verify oscillator performance.
@th
PIC18CXX2
DS39026D-page 18 1999-2013 Microchip Technology Inc.
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATORS
An external clock source may also be connected to the
OSC1 pin in these modes, as shown in Figure 2-2.
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP CONFIGURATION)
2.3 RC Oscillator
For timing insensitive applications, the “RC” and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 2-3 shows how the
R/C combination is connected.
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
FIGURE 2-3: RC OSCILLATOR MODE
The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
Ranges Tested:
Mode Freq C1 C2
LP 32.0 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1.0 MHz 15 pF 15 pF
4.0 MHz 15 pF 15 pF
HS 4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF
20.0
MHz 15-33 pF 15-33 pF
25.0
MHz 15-33 pF 15-33 pF
These values are for design guidance only.
See notes following this table.
Crystals Used
32.0 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000kHz ± 20 PPM
1.0 MHz ECS ECS-10-13-1 ± 50 PPM
4.0 MHz ECS ECS-40-20-1 ± 50 PPM
8.0 MHz Epson CA-301 8.000M-C ± 30 PPM
20.0 MHz Epson CA-301 20.000M-C ± 30 PPM
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents or verify oscillator performance.
1999-2013 Microchip Technology Inc. DS39026D-page 19
PIC18CXX2
2.4 External Clock Input
The EC and ECIO oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
oscillator mode.
FIGURE 2-4: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
The ECIO oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
FIGURE 2-5: EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
2.5 HS/PLL
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
FIGURE 2-6: PLL BLOCK DIAGRAM
MUX
VCO
Loop
Filter
Divide by 4
Crystal
Osc
OSC1
PLL Enable
FIN
FOUT SYSCLK
Phase
Comparator
(from Configuration HS Osc
bit Register)
OSC2
EMXEMX When OSCSEN configuvalion bxl : '0' and T1 OSCEN bit is set. When OSCSEN and TWOSCEN are m olher slales.
PIC18CXX2
DS39026D-page 20 1999-2013 Microchip Technology Inc.
2.6 Oscillator Switching Feature
The PIC18CXX2 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18CXX2 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crys-
tal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low power
execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration Register1H to a
’0’. Clock switching is disabled in an erased device.
See Section 9.0 for further details of the Timer1 oscilla-
tor. See Section 18.0 for Configuration Register details.
FIGURE 2-7: DEVICE CLOCK SOURCES
2.6.1 SYSTEM CLOCK SWITCH BIT
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON<0>) controls the clock switching. When the
SCS bit is’0’, the system clock source comes from the
main oscillator that is selected by the FOSC configura-
tion bits in Configuration Register1H. When the SCS bit
is set, the system clock source will come from the
Timer1 oscillator. The SCS bit is cleared on all forms of
RESET.
REGISTER 2-1: OSCCON REGISTER
PIC18CXXX
TOSC
4 x PLL
TT1P
TSCLK
Clock
Source
MUX
TOSC/4
Timer1 Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source option
for other modules
OSC1
OSC2
SLEEP
Main Oscillator
Note: The Timer1 oscillator must be enabled and
operating to switch the system clock
source. The Timer1 oscillator is enabled by
setting the T1OSCEN bit in the Timer1
control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS bit will be ignored (SCS bit forced
cleared) and the main oscillator will con-
tinue to be the system clock source.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
— — — — — — —SCS
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 SCS: System Clock Switch bit
When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other states:
bit is forced clear
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
X ‘ ‘ ‘ )k ‘PCM
1999-2013 Microchip Technology Inc. DS39026D-page 21
PIC18CXX2
2.6.2 OSCILLATOR TRANSITIONS
The PIC18CXX2 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that it’s
pulse width will not be less than the shortest pulse
width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in
Figure 2-8. The Timer1 oscillator is assumed to be run-
ning all the time. After the SCS bit is set, the processor
is frozen at the next occurring Q1 cycle. After eight syn-
chronization cycles are counted from the Timer1 oscil-
lator, operation resumes. No additional delays are
required after the synchronization cycles.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crys-
tal (HS, XT, LP), then the transition will take place after
an oscillator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3Q2Q1Q4Q3Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program PC + 2PC
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
Q1
T1OSI
Q4 Q1
PC + 4
Q1
Tscs
Clock
Counter
System
Q2 Q3 Q4 Q1
TDLY
TT1P
TOSC
21 34 5678
Q3
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
OSC2
TOST
Q1
PC + 6
TT1P
TOSC
TSCS
12345678
PIC18CXX2
DS39026D-page 22 1999-2013 Microchip Technology Inc.
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
TOST
Q3
PC + 4
TPLL
TOSC
TT1P
TSCS
Q4
OSC2
PLL Clock
Input 1 234 5678
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: RC oscillator mode assumed.
PC + 4
T1OSI
Clock
OSC2
Q4
TT1P
TOSC
TSCS
123
45678
1999-2013 Microchip Technology Inc. DS39026D-page 23
PIC18CXX2
2.7 Effects of SLEEP Mode on the
On-chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
2.8 Power-up Delays
Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see the “RESET” section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer, OST, intended to keep the
chip in RESET until the crystal oscillator is stable.
With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other oscillator modes. The time-out sequence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies. The PWRT timer is used to provide
an additional fixed 2ms (nominal) time-out to allow the
PLL ample time to lock to the incoming clock frequency.
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should
pull high At logic low
RCIO Floating, external resistor should
pull high Configured as PORTA, bit 6
ECIO Floating Configured as PORTA, bit 6
EC Floating At logic low
LP, XT, and HS Feedback inverter disabled, at
quiescent voltage level Feedback inverter disabled, at
quiescent voltage level
Note: See Table 3-1, in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
PIC18CXX2
DS39026D-page 24 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 25
PIC18CXX2
3.0 RESET
The PIC18CXX2 differentiates between various kinds
of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during SLEEP, and by the
RESET instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
MCLR pin is not driven low by any internal RESETS,
including WDT.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External Reset
MCLR
VDD
OSC1
WDT
Module
VDD Rise
Detect
OST/PWRT
On-chip
RC OSC
(1)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST(2)
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
Brown-out
Reset BOREN
RESET
Instruction
Stack
Pointer Stack Full/Underflow Reset
PIC18CXX2
DS39026D-page 26 1999-2013 Microchip Technology Inc.
3.1 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR cir-
cuitry, just tie the MCLR pin directly (or through a resis-
tor) to VDD. This will eliminate external RC components
usually needed to create a Power-on Reset delay. A
minimum rise rate for VDD is specified (parameter
D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in reset until the operating condi-
tions are met.
FIGURE 3-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3.2 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.3 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4 PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator start-
up time-out (OST).
3.5 Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A RESET may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will then be invoked and
will keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once VDD rises above BVDD, the Power-up Timer
will execute the additional time delay.
3.6 Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXXX device oper-
ating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all the registers.
1999-2013 Microchip Technology Inc. DS39026D-page 27
PIC18CXX2
TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS
REGISTER 3-1: RCON REGISTER BITS AND POSITIONS
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Oscillator
Configuration
Power-up(2)
Brown-out(2) Wake-up from
SLEEP or
Oscillator Switch
PWRTE = 0 PWRTE = 1
HS with PLL enabled(1) 72 ms + 1024TOSC
+ 2ms 1024TOSC
+ 2 ms 72 ms + 1024TOSC
+ 2ms 1024TOSC + 2 ms
HS, XT, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
EC 72 ms — 72 ms —
External RC 72 ms — 72 ms —
Note 1: 2 ms is the nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal Power-up Timer delay.
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
Note: See Register 4-3 on page 53 for bit definitions.
Condition Program
Counter RCON
Register RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 00-1 1100 1 1 1 0 0 u u
MCLR Reset during normal
operation
0000h 00-u uuuu u u u u u u u
Software Reset during normal
operation
0000h 0u-0 uuuu 0 u u u u u u
Stack Full Reset during normal
operation
0000h 0u-u uu11 u u u u u u 1
Stack Underflow Reset during
normal operation
0000h 0u-u uu11 u u u u u 1 u
MCLR Reset during SLEEP 0000h 00-u 10uu u 1 0 u u u u
WDT Reset 0000h 0u-u 01uu 1 0 1 u u u u
WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u
Brown-out Reset 0000h 0u-1 11u0 1 1 1 1 0 u u
Interrupt wake-up from SLEEP PC + 2(1) uu-u 00uu u 1 0 u u u u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
PIC18CXX2
DS39026D-page 28 1999-2013 Microchip Technology Inc.
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 242 442 252 452 00-0 0000 00-0 0000 uu-u uuuu(3)
PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu
PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PCL 242 442 252 452 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PRODH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 242 442 252 452 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 242 442 252 452 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 242 442 252 452 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 242 442 252 452 N/A N/A N/A
POSTINC0 242 442 252 452 N/A N/A N/A
POSTDEC0 242 442 252 452 N/A N/A N/A
PREINC0 242 442 252 452 N/A N/A N/A
PLUSW0 242 442 252 452 N/A N/A N/A
FSR0H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 242 442 252 452 N/A N/A N/A
POSTINC1 242 442 252 452 N/A N/A N/A
POSTDEC1 242 442 252 452 N/A N/A N/A
PREINC1 242 442 252 452 N/A N/A N/A
PLUSW1 242 442 252 452 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc. DS39026D-page 29
PIC18CXX2
FSR1H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
INDF2 242 442 252 452 N/A N/A N/A
POSTINC2 242 442 252 452 N/A N/A N/A
POSTDEC2 242 442 252 452 N/A N/A N/A
PREINC2 242 442 252 452 N/A N/A N/A
PLUSW2 242 442 252 452 N/A N/A N/A
FSR2H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu
TMR0H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
OSCCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
LVDCON 242 442 252 452 --00 0101 --00 0101 --uu uuuu
WDTCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
RCON(4, 6) 242 442 252 452 00-1 11q0 00-1 qquu uu-u qquu
TMR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu
TMR2 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PR2 242 442 252 452 1111 1111 1111 1111 1111 1111
T2CON 242 442 252 452 -000 0000 -000 0000 -uuu uuuu
SSPBUF 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
PIC18CXX2
DS39026D-page 30 1999-2013 Microchip Technology Inc.
ADRESH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
ADCON1 242 442 252 452 --0- 0000 --0- 0000 --u- uuuu
CCPR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
CCPR2H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TMR3H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu
SPBRG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
RCREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA 242 442 252 452 0000 -01x 0000 -01u uuuu -uuu
RCSTA 242 442 252 452 0000 000x 0000 000u uuuu uuuu
IPR2 242 442 252 452 ---- 1111 ---- 1111 ---- uuuu
PIR2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu(1)
PIE2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
IPR1 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
242 442 252 452 -111 1111 -111 1111 -uuu uuuu
PIR1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(1)
242 442 252 452 -000 0000 -000 0000 -uuu uuuu(1)
PIE1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
242 442 252 452 -000 0000 -000 0000 -uuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc. DS39026D-page 31
PIC18CXX2
TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu
TRISD 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISA(5, 7) 242 442 252 452 -111 1111(5) -111 1111(5) -uuu uuuu(5)
LATE 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu
LATD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5, 7) 242 442 252 452 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)
PORTE 242 442 252 452 ---- -000 ---- -000 ---- -uuu
PORTD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5, 7) 242 442 252 452 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
PIC18CXX2
DS39026D-page 32 1999-2013 Microchip Technology Inc.
FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
1999-2013 Microchip Technology Inc. DS39026D-page 33
PIC18CXX2
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD)
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V 1V
5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
PIC18CXX2
DS39026D-page 34 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 35
PIC18CXX2
4.0 MEMORY ORGANIZATION
There are two memory blocks in Enhanced MCU
devices. These memory blocks are:
• Program Memory
• Data Memory
Program and data memory use separate buses so that
concurrent access can occur.
4.1 Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ’0’s (a NOP
instruction).
PIC18C252 and PIC18C452 have 32 Kbytes of
EPROM, while PIC18C242 and PIC18C442 have
16 Kbytes of EPROM. This means that PIC18CX52
devices can store up to 16K of single word instructions,
and PIC18CX42 devices can store up to 8K of single
word instructions.
The RESET vector address is at 0000h and the inter-
rupt vector addresses are at 0008h and 0018h.
Figure 4-1 shows the Program Memory Map for
PIC18C242/442 devices and Figure 4-2 shows the
Program Memory Map for PIC18C252/452 devices.
21 21
PIC18CXX2
DS39026D-page 36 1999-2013 Microchip Technology Inc.
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC18C442/242
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC18C452/252
1999-2013 Microchip Technology Inc. DS39026D-page 37
PIC18CXX2
4.2 Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction.
PCLATU and PCLATH are not affected by any of the call
or return instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all RESETS. There is no RAM associated
with stack pointer 00000b. This is only a RESET value.
During a CALL type instruction causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR is trans-
ferred to the PC and then the stack pointer is
decremented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the address on the top of the stack is readable and writ-
able through SFR registers. Data can also be pushed
to, or popped from, the stack, using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.
4.2.1 TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack opera-
tions..
4.2.2 RETURN STACK POINTER
(STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full, depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 18.0 for a description of the device configura-
tion bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stack, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to 0.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note: Returning a value of zero to the PC on an
underflow, has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
PIC18CXX2
DS39026D-page 38 1999-2013 Microchip Technology Inc.
REGISTER 4-1: STKPTR REGISTER
FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
4.2.3 PUSH AND POP INSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
4.2.4 STACK FULL/UNDERFLOW RESETS
These resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflow will set the appropriate STKFUL or STKUNF
bit and then cause a device RESET. The STKFUL or
STKUNF bits are only cleared by the user software or
a POR Reset.
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
bit 7(1) STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6(1) STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as '0'
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
00011
0x001A34
11111
11110
11101
00010
00001
00000
00010
Return Address Stack
Top-of-Stack 0x000D58
TOSLTOSHTOSU 0x340x1A0x00
STKPTR<4:0>
1999-2013 Microchip Technology Inc. DS39026D-page 39
PIC18CXX2
4.3 Fast Register Stack
A "fast interrupt return" option is available for interrupts.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers and are only one in depth.
The stack is not readable or writable and is loaded with
the current value of the corresponding register when
the processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters, if the FAST RETURN instruction is used to return
from the interrupt.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority inter-
rupt will be overwritten.
If high priority interrupts are not disabled during low pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1: FAST REGISTER STACK
CODE EXAMPLE
4.4 PCL, PCLATH and PCLATU
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ’0’.
The PC increments by 2 to address sequential instruc-
tions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
4.5 Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 4-4.
FIGURE 4-4: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+2 PC+4
Execute INST (PC-2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+2)
Fetch INST (PC+4)
Internal
Phase
Clock
PIC18CXX2
DS39026D-page 40 1999-2013 Microchip Technology Inc.
4.6 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW
4.7 Instructions in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB =’0’). Figure 4-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (see Section 4.4).
The CALL and GOTO instructions have an absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-5 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single word instructions that the
PC will be offset by. Section 19.0 provides further
details of the instruction set.
FIGURE 4-5: INSTRUCTIONS IN PROGRAM MEMORY
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
Word Address
LSB = 1 LSB = 0
Program Memory
Byte Locations 000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
1999-2013 Microchip Technology Inc. DS39026D-page 41
PIC18CXX2
4.7.1 TWO-WORD INSTRUCTIONS
The PIC18CXX2 devices have four two-word instruc-
tions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to 1’s
and is a special kind of NOP instruction. The lower 12-
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A pro-
gram example that demonstrates this concept is shown
in Example 4-3. Refer to Section 19.0 for further details
of the instruction set.
EXAMPLE 4-3: TWO-WORD INSTRUCTIONS
4.8 Lookup Tables
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
4.8.2 TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored 2 bytes per program
word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 5.0.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction
1111 0100 0101 0110 ; 2nd operand holds address of REG2
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes
1111 0100 0101 0110 ; 2nd operand becomes NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
PIC18CXX2
DS39026D-page 42 1999-2013 Microchip Technology Inc.
4.9 Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
and Figure 4-7 show the data memory organization for
the PIC18CXX2 devices.
The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(0xFFF) and extend downwards. Any remaining space
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ’0’s.
The entire data memory may be accessed directly, or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and corresponding Indirect
File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10 pro-
vides a detailed description of the Access RAM.
4.9.1 GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or indi-
rectly. Indirect addressing operates using the File
Select Registers (FSRn) and corresponding Indirect
File Operand (INDFn). The operation of indirect
addressing is shown in Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. The top half of bank 15 (0xF80 to 0xFFF)
contains SFRs. All other banks of data memory contain
GPR registers, starting with bank 0.
4.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-1 and Table 4-2.
The SFRs can be classified into two sets; those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the peripher-
als whose functions they control.
The unused SFR locations will be unimplemented and
read as '0's. See Table 4-1 for addresses for the SFRs.
1999-2013 Microchip Technology Inc. DS39026D-page 43
PIC18CXX2
FIGURE 4-6: DATA MEMORY MAP FOR PIC18C242/442
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000b
= 0001b
= 1111b
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
F7Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Unused
Access RAM high
Access RAM low
Bank 2
to
200h
Unused
Read ’00h’
= 1110b
= 0010b
(SFR’s)
H )J (( ))
PIC18CXX2
DS39026D-page 44 1999-2013 Microchip Technology Inc.
FIGURE 4-7: DATA MEMORY MAP FOR PIC18C252/452
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000b
= 0001b
= 1110b
= 1111b
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
Bank 4
Bank 3
Bank 2
F7Fh
F00h
EFFh
3FFh
300h
2FFh
200h
1FFh
100h
0FFh
000h
= 0110b
= 0101b
= 0011b
= 0010b
Access RAM
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
GPR
GPR
SFR
Unused
Access RAM high
Access RAM low
Bank 5
GPR
GPR
Bank 6
to
4FFh
400h
5FFh
500h
600h
Unused
Read ’00h’
= 0100b
(SFR’s)
1999-2013 Microchip Technology Inc. DS39026D-page 45
PIC18CXX2
TABLE 4-1: SPECIAL FUNCTION REGISTER MAP
FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1
FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1
FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1
FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch —
FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —
FF9h PCL FD9h FSR2L FB9h —F99h—
FF8h TBLPTRU FD8h STATUS FB8h —F98h—
FF7h TBLPTRH FD7h TMR0H FB7h —F97h—
FF6h TBLPTRL FD6h TMR0L FB6h —F96hTRISE
(2)
FF5h TABLAT FD5h T0CON FB5h —F95hTRISD
(2)
FF4h PRODH FD4h —FB4h—F94hTRISC
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —
FF0h INTCON3 FD0h RCON FB0h —F90h—
FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh —
FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh —
FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE(2)
FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD(2)
FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC
FEAh FSR0H FCAh T2CON FAAh —F8AhLATB
FE9h FSR0L FC9h SSPBUF FA9h —F89hLATA
FE8h WREG FC8h SSPADD FA8h —F88h—
FE7h INDF1(3) FC7h SSPSTAT FA7h —F87h—
FE6h POSTINC1(3) FC6h SSPCON1 FA6h —F86h—
FE5h POSTDEC1(3) FC5h SSPCON2 FA5h —F85h—
FE4h PREINC1(3) FC4h ADRESH FA4h —F84hPORTE
(2)
FE3h PLUSW1(3) FC3h ADRESL FA3h —F83hPORTD
(2)
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h —FA0hPIE2F80hPORTA
Note 1: Unimplemented registers are read as ’0’.
2: This register is not available on PIC18C2X2 devices.
3: This is not a physical register.
PIC18CXX2
DS39026D-page 46 1999-2013 Microchip Technology Inc.
TABLE 4-2: REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Details
on page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 37
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 37
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 37
STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 38
PCLATU — — — Holding Register for PC<20:16> ---0 0000 39
PCLATH Holding Register for PC<15:8> 0000 0000 39
PCL PC Low Byte (PC<7:0>) 0000 0000 39
TBLPTRU ——bit21
(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 57
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 57
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 57
TABLAT Program Memory Table Latch 0000 0000 57
PRODH Product Register High Byte xxxx xxxx 61
PRODL Product Register Low Byte xxxx xxxx 61
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 65
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 66
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 67
INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) N/A 50
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) N/A 50
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) N/A 50
PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) N/A 50
PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) -
value of FSR0 offset by value in WREG N/A 50
FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 50
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 50
WREG Working Register xxxx xxxx
INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) N/A 50
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) N/A 50
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) N/A 50
PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) N/A 50
PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) -
value of FSR1 offset by value in WREG N/A 50
FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 50
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 50
BSR — — — — Bank Select Register ---- 0000 49
INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) N/A 50
POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) N/A 50
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) N/A 50
PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) N/A 50
PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) -
value of FSR2 offset by value in WREG N/A 50
FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 50
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50
STATUS — — —NOVZDCC---x xxxx 52
TMR0H Timer0 Register High Byte 0000 0000 95
TMR0L Timer0 Register Low Byte xxxx xxxx 95
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 93
OSCCON — — — — — — —SCS---- ---0 20
LVDCON —— IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 175
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
1999-2013 Microchip Technology Inc. DS39026D-page 47
PIC18CXX2
WDTCON — — — — — — —SWDTE---- ---0 183
RCON IPEN LWRT —RITO PD POR BOR 0q-1 11qq 53, 56,
74
TMR1H Timer1 Register High Byte xxxx xxxx 97
TMR1L Timer1 Register Low Byte xxxx xxxx 97
T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 97
TMR2 Timer2 Register 0000 0000 101
PR2 Timer2 Period Register 1111 1111 102
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 101
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 121
SSPADD SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 128
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 116
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 118
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 120
ADRESH A/D Result Register High Byte xxxx xxxx 171,172
ADRESL A/D Result Register Low Byte xxxx xxxx 171,172
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 165
ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 166
CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 111, 113
CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 111, 113
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 107
CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx 111, 113
CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx 111, 113
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 107
TMR3H Timer3 Register High Byte xxxx xxxx 103
TMR3L Timer3 Register Low Byte xxxx xxxx 103
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 103
SPBRG USART1 Baud Rate Generator 0000 0000 151
RCREG USART1 Receive Register 0000 0000 158, 161,
163
TXREG USART1 Transmit Register 0000 0000 156, 159,
162
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 149
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 150
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
PIC18CXX2
DS39026D-page 48 1999-2013 Microchip Technology Inc.
IPR2 — — — — BCLIP LVDIP TMR3IP CCP2IP ---- 1111 73
PIR2 — — — — BCLIF LVDIF TMR3IF CCP2IF ---- 0000 69
PIE2 — — — — BCLIE LVDIE TMR3IE CCP2IE ---- 0000 71
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 72
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 68
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 70
TRISE IBF OBF IBOV PSPMODE — Data Direction bits for PORTE 0000 -111 88
TRISD Data Direction Control Register for PORTD 1111 1111 85
TRISC Data Direction Control Register for PORTC 1111 1111 83
TRISB Data Direction Control Register for PORTB 1111 1111 80
TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 77
LATE — — — — — Read PORTE Data Latch,
Write PORTE Data Latch ---- -xxx 87
LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 85
LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 83
LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 80
LATA —LATA6
(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 77
PORTE Read PORTE pins, Write PORTE Data Latch ---- -000 87
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 85
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 83
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 80
PORTA —RA6
(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 77
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
D111 mm
1999-2013 Microchip Technology Inc. DS39026D-page 49
PIC18CXX2
4.10 Access Bank
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit).
When forced in the Access Bank (a = ’0’), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers, so that these registers
can be accessed without any software overhead. This
is useful for testing status flags and modifying control
bits.
4.11 Bank Select Register (BSR)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
A MOVLB instruction has been provided in the instruc-
tion set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
FIGURE 4-8: DIRECT ADDRESSING
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the reg-
isters of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data
Memory(1)
Direct Addressing
Bank Select(2) Location Select(3)
BSR<3:0> 7 0
From Opcode(3)
00h 01h 0Eh 0Fh
Bank 0 Bank 1 Bank 14 Bank 15
1FFh
100h
0FFh
000h
EFFh
E00h
FFFh
F00h
PIC18CXX2
DS39026D-page 50 1999-2013 Microchip Technology Inc.
4.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = '0'), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-4: HOW TO CLEAR RAM
(BANK1) USING INDIRECT
ADDRESSING
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an instruction writes a value to INDF0, the value will
be written to the address pointed to by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all '0's are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
STATUS bits are not affected.
4.12.1 INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
LFSR FSR0, 0x100 ;
NEXT CLRF POSTINC0 ; Clear INDF register
; & inc pointer
BTFSS FSR0H, 1 ; All done w/ Bank1?
GOTO NEXT ; NO, clear next
CONTINUE ; YES, continue
1999-2013 Microchip Technology Inc. DS39026D-page 51
PIC18CXX2
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or post-
increment/decrement functions.
FIGURE 4-9: INDIRECT ADDRESSING OPERATION
FIGURE 4-10: INDIRECT ADDRESSING
Opcode Address
File Address = access of an indirect addressing register
FSR
Instruction
Executed
Instruction
Fetched
RAM
Opcode File
12
12
12
BSR<3:0>
8
4
0h
FFFh
Note 1: For register file map detail, see Table 4-1.
Data
Memory(1)
Indirect Addressing
FSR Register11 0
0FFFh
0000h
Location Select
PIC18CXX2
DS39026D-page 52 1999-2013 Microchip Technology Inc.
4.13 STATUS Register
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic. There-
fore, the result of an instruction with the STATUS regis-
ter as destination may be different than intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register, because these instructions
do not affect the Z, C, DC, OV or N bits from the
STATUS register. For other instructions not affecting
any status bits, see Table 19-2.
REGISTER 4-2: STATUS REGISTER
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — —NOVZDCC
bit 7 bit 0
bit 7-5 Unimplemented: Read as '0'
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative, (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
bit 0 C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 53
PIC18CXX2
4.13.1 RCON REGISTER
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
.
REGISTER 4-3: RCON REGISTER
Note 1: If the BOREN configuration bit is set
(Brown-out Reset enabled), the BOR bit is
’1’ on a Power-on Reset. After a Brown-
out Reset has occurred, the BOR bit will
be clear and must be set by firmware to
indicate the occurrence of the next Brown-
out Reset.
If the BOREN configuration bit is clear
(Brown-out Reset disabled), BOR is
unknown after Power-on Reset and
Brown-out Reset conditions.
2: It is recommended that the POR bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
Once this bit is set, it can only be cleared by a POR or MCLR Reset.
0 = Disable TBLWT to internal program memory; TBLWT only to external program memory
bit 5 Unimplemented: Read as '0'
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed
0 = The RESET instruction was executed causing a device RESET
(must be set in software after a Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred
0 = A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 54 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 55
PIC18CXX2
5.0 TABLE READS/TABLE WRITES
Enhanced devices have two memory spaces: the pro-
gram memory space and the data memory space. The
program memory space is 16-bits wide, while the data
memory space is 8 bits wide. Table Reads and Table
Writes have been provided to move data between
these two memory spaces through an 8-bit register
(TABLAT).
The operations that allow the processor to move data
between the data and program memory spaces are:
• Table Read (TBLRD)
• Table Write (TBLWT)
Table Read operations retrieve data from program
memory and place it into the data memory space.
Figure 5-1 shows the operation of a Table Read with
program and data memory.
Table Write operations store data from the data mem-
ory space into program memory. Figure 5-2 shows the
operation of a Table Write with program and data
memory.
Table operations work with byte entities. A table block
containing data is not required to be word aligned, so a
table block can start and end at any byte address. If a
Table Write is being used to write an executable pro-
gram to program memory, program instructions will
need to be word aligned.
FIGURE 5-1: TABLE READ OPERATION
FIGURE 5-2: TABLE WRITE OPERATION
Table Pointer(1)
Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer points to a byte in program memory.
Program Memory
(TBLPTR)
Table Pointer(1) Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer points to a byte in program memory.
PIC18CXX2
DS39026D-page 56 1999-2013 Microchip Technology Inc.
5.1 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• TBLPTR registers
• TABLAT register
• RCON register
5.1.1 RCON REGISTER
The LWRT bit specifies the operation of Table Writes to
internal memory when the VPP voltage is applied to the
MCLR pin. When the LWRT bit is set, the controller
continues to execute user code, but long Table Writes
are allowed (for programming internal program mem-
ory) from user mode. The LWRT bit can be cleared only
by performing either a POR or MCLR Reset.
REGISTER 5-1: RCON REGISTER (ADDRESS: FD0h)
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
0 = Disable TBLWT to internal program memory.
Note: Only cleared on a POR or MCLR Reset.
This bit has no effect on TBLWTs to external program memory.
bit 5 Unimplemented: Read as '0'
bit 4 RI: RESET Instruction Flag bit
1 = No RESET instruction occurred
0 = A RESET instruction occurred
bit 3 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset or POR Reset occurred
0 = A Brown-out Reset or POR Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 57
PIC18CXX2
5.1.2 TABLAT - TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memory.
5.1.3 TBLPTR - TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper Byte, High
Byte and Low Byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The lower 21-bits allow the device to
address up to 2 Mbytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways, based on the table operation.
These operations are shown in Table 5-1. These opera-
tions on the TBLPTR only affect the lower 21-bits.
TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
5.2 Internal Program Memory Read/
Writes
5.2.1 TABLE READ OVERVIEW (TBLRD)
The TBLRD instructions are used to read data from
program memory to data memory.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into TAB-
LAT. In addition, TBLPTR can be modified automati-
cally for the next Table Read operation.
Table Reads from program memory are performed one
byte at a time. The instruction will load TABLAT with the
one byte from program memory pointed to by TBLPTR.
5.2.2 INTERNAL PROGRAM MEMORY
WRITE BLOCK SIZE
The internal program memory of PIC18CXXX devices
is written in blocks. For PIC18CXX2 devices, the write
block size is 2 bytes. Consequently, Table Write opera-
tions to internal program memory are performed in
pairs, one byte at a time.
When a Table Write occurs to an even program mem-
ory address (TBLPTR<0> = 0), the contents of TABLAT
are transferred to an internal holding register. This is
performed as a short write and the program memory
block is not actually programmed at this time. The hold-
ing register is not accessible by the user.
When a Table Write occurs to an odd program memory
address (TBLPTR<0>=1), a long write is started. Dur-
ing the long write, the contents of TABLAT are written
to the high byte of the program memory block and the
contents of the holding register are transferred to the
low byte of the program memory block.
Figure 5-3 shows the holding register and the program
memory write blocks.
If a single byte is to be programmed, the low (even)
byte of the destination program word should be read
using TBLRD*, modified or changed, if required, and
written back to the same address using TBLWT*+. The
high (odd) byte should be read using TBLRD*, modified
or changed if required, and written back to the same
address using TBLWT. A write to the odd address will
cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
Example Operation on Table Pointer
TBLRD*
TBLWT* TBLPTR is not modified
TBLRD*+
TBLWT*+ TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*- TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+* TBLPTR is incremented before the read/write
PIC18CXX2
DS39026D-page 58 1999-2013 Microchip Technology Inc.
FIGURE 5-3: HOLDING REGISTER AND THE WRITE BLOCK
5.2.2.1 Operation
The long write is what actually programs words of data
into the internal memory. When a TBLWT to the MSB of
the write block occurs, instruction execution is halted.
During this time, programming voltage and the data
stored in internal latches is applied to program memory.
For a long write to occur:
1. MCLR/VPP pin must be at the programming
voltage
2. LWRT bit must be set
3. TBLWT to the address of the MSB of the write
block
If the LWRT bit is clear, a short write will occur and pro-
gram memory will not be changed. If the TBLWT is not
to the MSB of the write block, then the programming
phase is not initiated.
Setting the LWRT bit enables long writes when the
MCLR pin is taken to VPP voltage. Once the LWRT bit
is set, it can be cleared only by performing a POR or
MCLR Reset.
To ensure that the memory location has been well pro-
grammed, a minimum programming time is required.
The long write can be terminated after the program-
ming time has expired by a RESET or an interrupt.
Having only one interrupt source enabled to terminate
the long write ensures that no unintended interrupts will
prematurely terminate the long write.
5.2.2.2 Sequence of Events
The sequence of events for programming an internal
program memory location should be:
1. Enable the interrupt that terminates the long
write. Disable all other interrupts.
2. Clear the source interrupt flag.
3. If Interrupt Service Routine execution is desired
when the device wakes, enable global
interrupts.
4. Set LWRT bit in the RCON register.
5. Raise MCLR/VPP pin to the programming
voltage, VPP.
6. Clear the WDT (if enabled).
7. Set the interrupt source to interrupt at the
required time.
8. Execute the Table Write for the lower (even)
byte. This will be a short write.
9. Execute the Table Write for the upper (odd) byte.
This will be a long write. The microcontroller will
then halt internal operations. (This is not the
same as SLEEP mode, as the clocks and
peripherals will continue to run.) The interrupt
will cause the microcontroller to resume
operation.
10. If GIE was set, service the interrupt request.
11. Lower MCLR/VPP pin to VDD.
12. Verify the memory location (Table Read).
Block n
Block n + 1
Block n + 2
MSB
The write to the MSB of the Write Block
causes the entire block to be written to pro-
gram memory. The program memory block
that is written depends on the address that is
written to in the MSB of the Write Block.
Holding Register
Program Memory (x 2-bits)
Write Block
1999-2013 Microchip Technology Inc. DS39026D-page 59
PIC18CXX2
5.2.3 INTERRUPTS
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur, regardless of the
settings of interrupt priority bits, the GIE/GIEH bit, or
the PIE/GIEL bit.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
TABLE 5-2: LONG WRITE EXECUTION, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
5.2.4 UNEXPECTED TERMINATION OF
WRITE OPERATIONS
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
GIE/
GIEH PIE/
GIEL Priority Interrupt
Enable Interrupt
Flag Action
XX X 0
(default) XLong write continues
even if interrupt flag becomes set.
XX X 1 0
Long write continues, will resume operations
when the interrupt flag is set.
0
(default) 0
(default) X11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default) 11
high priority
(default) 11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
10
(default) 0
low 11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default) 10
low 11
Terminates long write,
branches to low priority interrupt vector.
Interrupt flag can be cleared by ISR.
10
(default)
1
high priority
(default) 11
Terminates long write,
branches to high priority interrupt vector.
Interrupt flag can be cleared by ISR.
PIC18CXX2
DS39026D-page 60 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 61
PIC18CXX2
6.0 8 X 8 HARDWARE MULTIPLIER
6.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18CXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 6-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 6-1: PERFORMANCE COMPARISON
6.2 Operation
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 6-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 6-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 6-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)
Routine Multiply Method Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardware multiply 13 69 6.9 s27.6 s69 s
Hardware multiply 1 1 100 ns 400 ns 1 s
8 x 8 signed Without hardware multiply 33 91 9.1 s36.4 s91 s
Hardware multiply 6 6 600 ns 2.4 s6 s
16 x 16 unsigned Without hardware multiply 21 242 24.2 s96.8 s242 s
Hardware multiply 24 24 2.4 s9.6 s24 s
16 x 16 signed Without hardware multiply 52 254 25.4 s 102.6 s254 s
Hardware multiply 36 36 3.6 s14.4 s36 s
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
PIC18CXX2
DS39026D-page 62 1999-2013 Microchip Technology Inc.
EXAMPLE 6-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 6-4 shows the sequence to do a 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 6-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
= ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 216)+
(-1 ARG1H<7> ARG2H:ARG2L 216)
EXAMPLE 6-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
1999-2013 Microchip Technology Inc. DS39026D-page 63
PIC18CXX2
7.0 INTERRUPTS
The PIC18CXX2 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level, or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will over-
ride any low priority interrupts that may be in progress.
There are ten registers which are used to control inter-
rupt operation. These registers are:
• RCON
•INTCON