LMV321, NCV321, LMV358, LMV324 Datasheet by onsemi

GD 0N Semiconducior® m «@ gag Q 6;? @ Q
© Semiconductor Components Industries, LLC, 2015
January, 2021 Rev. 16
1Publication Order Number:
LMV321/D
Single, Dual, Quad
Low-Voltage, Rail-to-Rail
Operational Amplifiers
LMV321, NCV321, LMV358,
LMV324
The LMV321, LMV321I, NCV321, LMV358/LMV358I and
LMV324 are CMOS single, dual, and quad low voltage operational
amplifiers with railtorail output swing. These amplifiers are a
costeffective solution for applications where low power consumption
and space saving packages are critical. Specification tables are
provided for operation from power supply voltages at 2.7 V and 5 V.
RailtoRail operation provides improved signaltonoise
preformance. Ultra low quiescent current makes this series of
amplifiers ideal for portable, battery operated equipment. The
common mode input range includes ground making the device useful
for lowside currentshunt measurements. The ultra small packages
allow for placement on the PCB in close proximity to the signal source
thereby reducing noise pickup.
Features
Operation from 2.7 V to 5.0 V SingleSided Power Supply
LMV321 Single Available in Ultra Small 5 Pin SC70 Package
No Output Crossover Distortion
RailtoRail Output
Low Quiescent Current: LMV358 Dual 220 mA, Max per Channel
No Output PhaseReversal from Overdriven Input
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
Notebook Computers and PDAs
Portable BatteryOperated Instruments
Active Filters
SC70
CASE 419A
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING AND MARKING INFORMATION
Micro8
CASE 846A
UDFN8
CASE 517AJ
SOIC14
CASE 751A
TSSOP14
CASE 948G
11
1
SOIC8
CASE 751
1
8
1
1
8
1
5
TSOP5
CASE 483
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LMV321, NCV321, LMV358, LMV324
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2
MARKING DIAGRAMS
AAC MG
G
AAC = Specific Device Code
M = Date Code
G= PbFree Package
PIN CONNECTIONS
(Top View)
SC705/TSOP5
+IN
V
IN
V+
OUTPUT
+
2
1
3
5
4
LMV
324
ALYW
1
14
LMV324 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
V358 = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= PbFree Package
(Note: Microdot may be in either location)
V358
AYWG
G
1
8
LMV324
AWLYWWG
1
14
LMV324 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = PbFree Package
AC = Specific Device Code
M = Date Code
G= PbFree Package
OUT A 1
2
3
4
+
+
8
7
6
5
IN A
IN A+
V
V+
OUT B
IN B
IN B+
A
B
UDFN8/Micro8/SOIC81
2
3
4
5
6
7
14
13
12
11
10
9
8
+
A+
D
++
B C
OUT A
IN A
IN A+
V+
IN B+
IN B
OUT B
OUT D
IN D
IN D+
V
IN C+
IN C
OUT C
SOIC14 1
2
3
4
5
6
7
14
13
12
11
10
9
8
+
A+
D
++
B C
OUT A
IN A
IN A+
V+
IN B+
IN B
OUT B
OUT D
IN D
IN D+
V
IN C+
IN C
OUT C
TSSOP14
(Top View) (Top View) (Top View)
V358
ALYW
G
1
8
V358 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
SC70
UDFN8
SOIC14 TSSOP14
Micro8
SOIC8
AC M
G
1
5
3ACAYWG
G
3AC = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= PbFree Package
TSOP5
(Note: Microdot may be in either location)
(Note: Microdot may be in either location)
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LMV321, NCV321, LMV358, LMV324
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3
MAXIMUM RATINGS
Symbol Rating Value Unit
VSSupply Voltage (Operating Range VS = 2.7 V to 5.5 V) 5.5 V
VIDR Input Differential Voltage $Supply Voltage V
VICR Input Common Mode Voltage Range 0.5 to (V+) + 0.5 V
Maximum Input Current 10 mA
tSo Output Short Circuit (Note 1) Continuous
TJMaximum Junction Temperature 150 °C
TAOperating Ambient Temperature Range
LMV321, LMV358, LMV324
LMV321I, LMV358I
NCV321 (Note 2)
40 to 85
40 to 125
40 to 125
°C
°C
°C
qJA Thermal Resistance: °C/W
SC70 280
Micro8 238
TSOP5 333
UDFN8 (1.2 mm x 1.8 mm x 0.5 mm) 350
SOIC8 212
SOIC14 156
TSSOP14 190
Tstg Storage Temperature 65 to 150 °C
Mounting Temperature (Infrared or Convection 20 sec) 260 °C
VESD ESD Tolerance (Note 3)
LMV321, LMV321I, NCV321
Machine Model
Human Body Model
LMV358/358I/324
Machine Model
Human Body Mode
100
1000
100
2000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functional-
ity should not be assumed, damage may occur and reliability may be affected.
1. Continuous shortcircuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction
temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability. Shorting output to either V+
or V will adversely affect reliability.
2. NCV prefix is qualified for automotive usage.
3. Human Body Model, applicable std. MILSTD883, Method 3015.7
Machine Model, applicable std. JESD22A115A (ESD MM std. of JEDEC)
FieldInduced ChargeDevice Model, applicable std. JESD22C101C (ESD FICDM std. of JEDEC).
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LMV321, NCV321, LMV358, LMV324
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4
2.7 V DC ELECTRICAL CHARACTERISTICS (Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 2.7 V,
RL = 1 MW, V = 0 V, VO = V+/2)
Parameter Symbol Condition Min Typ Max Unit
Input Offset Voltage VIO TA = TLow to THigh (Note 4) 1.7 9 mV
Input Offset Voltage Average Drift ICVOS TA = TLow to THigh (Note 4) 5mV/°C
Input Bias Current IBTA = TLow to THigh (Note 4) <1 nA
Input Offset Current IIO TA = TLow to THigh (Note 4) <1 nA
Common Mode Rejection Ratio CMRR 0 V v VCM v 1.7 V 50 63 dB
Power Supply Rejection Ratio PSRR 2.7 V v V+ v 5 V,
VO = 1 V
50 60 dB
Input CommonMode Voltage Range VCM For CMRR w 50 dB 0 to 1.7 0.2 to 1.9 V
Output Swing VOH RL = 10 kW to 1.35 V VCC 100 VCC 10 mV
VOL RL = 10 kW to 1.35 V (Note 5) 60 180 mV
Supply Current LMV321, NCV321
LMV358/LMV358I (Both Amplifiers)
LMV324 (4 Amplifiers)
ICC 80
140
260
185
340
680
mA
2.7 V AC ELECTRICAL CHARACTERISTICS (Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 2.7 V,
RL = 1 MW, V = 0 V, VO = V+/2)
Parameter Symbol Condition Min Typ Max Unit
Gain Bandwidth Product GBWP CL = 200 pF 1 MHz
Phase Margin Qm60 °
Gain Margin Gm10 dB
InputReferred Voltage Noise enf = 50 kHz 50 nV/Hz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. For LMV321, LMV358, LMV324: TA = 40°C to +85°C
For LMV321I, LMV358I, NCV321: TA = 40°C to +125°C.
5. Guaranteed by design and/or characterization.
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LMV321, NCV321, LMV358, LMV324
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5
5.0 V DC ELECTRICAL CHARACTERISTICS (Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5.0 V,
RL = 1 MW, V = 0 V, VO = V+/2)
Parameter Symbol Condition Min Typ Max Unit
Input Offset Voltage VIO TA = TLow to THigh (Note 6) 1.7 9 mV
Input Offset Voltage Average Drift TCVIO TA = TLow to THigh (Note 6) 5mV/°C
Input Bias Current (Note 7) IBTA = TLow to THigh (Note 6) < 1 nA
Input Offset Current (Note 7) IIO TA = TLow to THigh (Note 6) < 1 nA
Common Mode Rejection Ratio CMRR 0 V v VCM v 4 V 50 65 dB
Power Supply Rejection Ratio PSRR 2.7 V v V+ v 5 V,
VO = 1 V, VCM = 1 V
50 60 dB
Input CommonMode Voltage Range VCM For CMRR w 50 dB 0 to 4 0.2 to 4.2 V
Large Signal Voltage Gain (Note 7) AVRL = 2 kW15 100 V/mV
TA = TLow to THigh (Note 6) 10
Output Swing VOH RL = 2 kW to 2.5 V
TA = TLow to THigh (Note 6)
VCC 300
VCC 400
VCC 40 mV
VOL RL = 2 kW to 2.5 V (Note 7)
TA = TLow to THigh (Note 6)
120 300
400
mV
VOH RL = 10 kW to 2.5 V (Note 7)
TA = TLow to THigh (Note 6)
VCC 100
VCC 200
mV
VOL RL = 10 kW to 2.5 V
TA = TLow to THigh (Note 6)
65 180
280
mV
Output Short Circuit Current IOSourcing = VO = 0 V (Note 7)
Sinking = VO = 5 V (Note 7)
10
10
60
160
mA
Supply Current ICC LMV321
TA = TLow to THigh (Note 6)
130 250
350
mA
NCV321
TA = TLow to THigh (Note 6)
130 250
350
LMV358/358I Both Amplifiers
TA = TLow to THigh (Note 6)
210 440
615
LMV324 All Four Amplifiers
TA = TLow to THigh (Note 6)
410 830
1160
5.0 V AC ELECTRICAL CHARACTERISTICS (Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 5.0 V,
RL = 1 MW, V = 0 V, VO = V+/2)
Parameter Symbol Condition Min Typ Max Unit
Slew Rate SR1V/ms
Gain Bandwidth Product GBWP CL = 200 pF 1 MHz
Phase Margin Qm60 °
Gain Margin Gm10 dB
InputReferred Voltage Noise enf = 50 kHz 50 nV/Hz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. For LMV321, LMV358, LMV324: TA = 40°C to +85°C
For LMV321I, LMV358I, NCV321: TA = 40°C to +125°C.
7. Guaranteed by design and/or characterization.
Same Gain :13 as 1Typ) ~ mmm mm mm
LMV321, NCV321, LMV358, LMV324
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6
TYPICAL CHARACTERISTICS
(TA = 25°C and VS = 5 V unless otherwise specified)
Figure 1. Open Loop Frequency Response
(RL = 2 kW, TA = 255C, VS = 5 V)
Figure 2. Open Loop Phase Margin
(RL = 2 kW, TA = 255C, VS = 5 V)
FREQUENCY (Hz)
PHASE MARGIN (°)
100
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k
Figure 3. CMRR vs. Frequency
(RL = 5 kW, VS = 5 V)
FREQUENCY (Hz)
CMRR (dB)
30
35
40
45
50
55
60
65
70
75
80
0.5 0 0.5 1 1.5 2 2.5 3
Figure 4. CMRR vs. Input Common Mode
Voltage
INPUT COMMON MODE VOLTAGE (V)
CMRR (dB)
30
40
50
60
70
80
1012345
Figure 5. CMRR vs. Input Common Mode
Voltage
INPUT COMMON MODE VOLTAGE (V)
CMRR (dB)
100
90
80
70
60
50
40
30
20
10
0
1k 10k 100k 1M 10M
Figure 6. PSRR vs. Frequency
(RL = 5 kW, VS = 2.7 V, +PSRR)
FREQUENCY (Hz)
PSRR (dB)
FREQUENCY (Hz)
GAIN (dB)
VS = 5 V
f = 10 kHz
VS = 2.7 V
f = 10 kHz
10
30
50
70
90
110
130
150
170
20
0
20
40
60
80
100
120
Same Gain $1.8 dB (Typ)
1k 10k 100k 1M 10M10010 1k 10k 100k 1M 10M10010
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LMV321, NCV321, LMV358, LMV324
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7
TYPICAL CHARACTERISTICS
(TA = 25°C and VS = 5 V unless otherwise specified)
90
80
70
60
50
40
30
20
10
0
1k 10k 100k 1M 10M
Figure 7. PSRR vs. Frequency
(RL = 5 kW, VS = 2.7 V, PSRR)
FREQUENCY (Hz)
PSRR (dB)
100
90
80
70
60
50
40
30
20
10
0
1k 10k 100k 1M 10M
Figure 8. PSRR vs. Frequency
(RL = 5 kW, VS = 5 V, +PSRR)
FREQUENCY (Hz)
PSRR (dB)
100
90
80
70
60
50
40
30
20
10
01k 10k 100k 1M 10M
Figure 9. PSRR vs. Frequency
(RL = 5 kW, VS = 5 V, PSRR)
FREQUENCY (Hz)
PSRR (dB)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.5 1 1.5 2 2.5 3
Figure 10. VOS vs CMR
VCM (V)
VOS (mV)
VS = 2.7 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 11. VOS vs CMR
VCM (V)
VOS (mV)
VS = 5.0 V
0
20
40
60
80
100
120
140
160
180
200
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 12. Supply Current vs. Supply Voltage
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
-20 —40 -60 -80 -100 -120 440
LMV321, NCV321, LMV358, LMV324
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8
TYPICAL CHARACTERISTICS
(TA = 25°C and VS = 5 V unless otherwise specified)
Figure 13. THD+N vs Frequency
(Hz)
(%)
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
2.5 3 3.5 4 4.5
5
Figure 14. Output Voltage Swing vs Supply
Voltage (RL = 10k)
SUPPLY VOLTAGE (V)
VOUT REFERENCED TO V+ (V)
Positive Swing
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
2.5 3 3.5 4 4.5 5
Figure 15. Output Voltage Swing vs Supply
Voltage (RL = 10k)
SUPPLY VOLTAGE (V)
VOUT REFERENCED TO V (V)
Negative Swing
160
140
120
100
80
60
40
20
0
0 0.5 1 1.5 2 2.5
Figure 16. Sink Current vs. Output Voltage
VS = 2.7 V
VOUT REFERENCED TO V (V)
SINK CURRENT (mA)
120
100
80
60
40
20
0
012345
Figure 17. Sink Current vs. Output Voltage
VS = 5.0 V
VOUT REFERENCED TO V (V)
SINK CURRENT (mA)
0
20
40
60
80
100
120
0 0.5 1.0 1.5 2.0 2.5
Figure 18. Source Current vs. Output Voltage
VS = 2.7 V
VOUT REFERENCED TO V+ (V)
SOURCE CURRENT (mA)
0.001
0.01
0.1
1
10 100 1k 10k 100k
RL = 10 kW
Vout = 1 VPP
Av = +1
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LMV321, NCV321, LMV358, LMV324
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9
TYPICAL CHARACTERISTICS
(TA = 25°C and VS = 5 V unless otherwise specified)
0
10
20
30
40
50
60
70
80
90
100
110
012345
Figure 19. Source Current vs. Output Voltage
VS = 5.0 V
VOUT REFERENCED TO V+ (V)
SOURCE CURRENT (mA)
Figure 20. Settling Time vs. Capacitive Load
Figure 21. Settling Time vs. Capacitive Load Figure 22. Step Response Small Signal
NonInverting (G = +1)
Figure 23. Step Response Small Signal
Inverting (G = 1)
Figure 24. Step Response Large Signal
NonInverting (G = +1)
RL = 2 kW
AV = 1
50 mV/div
2 ms/div
RL = 1 MW
AV = 1
50 mV/div
2 ms/div
50 mV/div
2 ms/div
Output
Input
50 mV/div
2 ms/div
Output
Input
1 V/div
2 ms/div
Output
Input
/
LMV321, NCV321, LMV358, LMV324
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10
TYPICAL CHARACTERISTICS
(TA = 25°C and VS = 5 V unless otherwise specified)
Figure 25. Step Response Large Signal
Inverting (G = 1)
1 V/div
2 ms/div
Output
Input
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LMV321, NCV321, LMV358, LMV324
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11
APPLICATIONS
+
R1
R2
VO
Vref
Vin
VOH
VO
VOL
Hysteresis
VinL VinH
Vref
REF
LMV321
+
R1
VCC
VCC
VO
2.5 V
R2
50 k
10 k
Vref
5.0 k
RC
RC
+
VO
For: fo = 1.0 kHz
R = 16 kW
C = 0.01 mF
VCC
LMV321
LMV321
Figure 26. Voltage Reference Figure 27. Wien Bridge Oscillator
Figure 28. Comparator with Hysteresis
VO+2.5 V(1 )R1
R2)
Vref +1
2VCC
fO+1
2pRC
VinL+R1
R1 )R2 (VOL *Vref) )Vref
VinH+R1
R1 )R2 (VOH *Vref) )Vref
H+R1
R1 )R2 (VOH *VOL)
For less than 10% error from operational amplifier,
((QO fO)/BW) < 0.1 where fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
Given: fo= center frequency
A(fo) = gain at center frequency
Choose value fo, C
Vin
Figure 29. Multiple Feedback Bandpass Filter
+
VCC
R3
R1
R2
Vref
CC
VO
CO = 10 C
CO
LMV321
Then : R3 +Q
pfOC
R1 +R3
2A(f
O)
R2 +
R1 R3
4Q2R1 *R3
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LMV321, NCV321, LMV358, LMV324
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12
ORDERING INFORMATION
Order Number
Number
of
Channels Specific Device Marking Package Type Shipping
LMV321SQ3T2G Single AAC SC70
(PbFree)
3000 / Tape & Reel
LMV321SN3T1G Single 3AC TSOP5
(PbFree)
3000 / Tape & Reel
LMV321ISN3T1G Single 3AC TSOP5
(PbFree)
3000 / Tape & Reel
NCV321SN3T1G* Single 3AC TSOP5
(PbFree)
3000 / Tape & Reel
LMV358DMR2G Dual V358 Micro8
(PbFree)
4000 / Tape & Reel
LMV358MUTAG Dual AC UDFN8
(PbFree)
3000 / Tape & Reel
LMV358DR2G Dual V358 SOIC8
(PbFree)
2500 / Tape & Reel
LMV358IDR2G Dual V358 SOIC8
(PbFree)
2500 / Tape & Reel
LMV324DR2G Quad LMV324 SOIC14
(PbFree)
2500 / Tape & Reel
LMV324DTBR2G Quad LMV
324
TSSOP14
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP
Capable.
0N Semiwndudw" NOTES I DIMENsIoNING AND TOLERANCING , PER ANSWNEMJSEZ 2 CONTROLLING DIMENSION INCH :1] [IL 3 MSA m OBSOLETE NEW STANDARD MSA U2 4 DIMENSIONS AAND B DO NOT INCLUDE I f MOLD FLASH PROTRUSIONS 0R GATE I I swam I I: oI H IIIcIIzs MILLIMEYERS MIN MAX IIIIII MAX II III I am I ED 2 an I Ius nus: I I5 I 35 II III II on a fin I In I IIIII II m2 a II I an amass nssasc II HM , II In I IIIII I am a II II 25 II IIIII II m2 a II I an I “BE REF IuII REF am 0057 2IIII 2m J L as». 69—- EUEDJJ ME NH MIW I—jr (nanaa amaa an. MODE 2 Ewan 3 ma ON SanIaanaaaIan and J ana hademavks aI SemIcanduclur canaananIa lnduslnes. Lu: mm ON SemIcanduclar an Ils suhsIdIarIes In Ina Umled Slates andJm mhev caInInas ON SanIaanaIaIan naaayas me “gm Ia make anangas WIInaaI mnhel naIIaa Ia any mama nanan oN SanIaanaaaIan makes na walvamy. napaaaanIanan an gIananIaa naganang Ina aaIIaInIIIy aI II; mama In any panIaaIan aunaaaa nan dues ON Semumnduclm aaaama any IIaInIIIy anang aaIaI Ina aaaIaaIIan m Isa aI any pmdudnv cIrcuI| and saaaIIaaIIy aaaIaIna any and an IIaInIIIy InaIaaIna wInaII IInnIaIIan spanaI aanaaaaanIaI m InaaanIaI damages ON SemImnduclar dues nn| aanyay any hcense under Ia aaIanI lIghls nan Ina rIng aI aInaIs
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A01 OBSOLETE. NEW STANDARD
419A02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN MAX MIN MAX
MILLIMETERS
1.80 2.200.071 0.087
INCHES
B1.15 1.350.045 0.053
C0.80 1.100.031 0.043
D0.10 0.300.004 0.012
G0.65 BSC0.026 BSC
H--- 0.10---0.004
J0.10 0.250.004 0.010
K0.10 0.300.004 0.012
N0.20 REF0.008 REF
S2.00 2.200.079 0.087
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
B0.2 (0.008) MM
12 3
45
A
G
S
D 5 PL
H
C
N
J
K
B
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
XXXMG
G
XXX = Specific Device Code
M = Date Code
G= PbFree Package
GENERIC MARKING
DIAGRAM*
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
SC88A (SC705/SOT353)
CASE 419A02
ISSUE L
DATE 17 JAN 2013
SCALE 2:1
(Note: Microdot may be in either location)
ǒmm
inchesǓ
SCALE 20:1
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
SOLDER FOOTPRINT
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42984B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
SC88A (SC705/SOT353)
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
0N Semiwndudw" EN; . m 55.1”” i mfiq SOLDERING FOOT 555‘fi H H H H 0.037 4. km (m ncnas “For addmonal mformamn on our Pb-Fr delafls p‘ease download the ON Sem Moummg Techmques Reference Man ON Semxcunduclm and ave Mademavks av Semxcanduclur Campunenls lnduslnes LLC dba ON Semxcanduclar ar \ls suaamanas m xna Umled sxaxas andJm mhev commas ON Semxcunduclar vesewes ma th| to make changes wuhum Yunhev name to any pruduns nanan ON Semanduc‘nv makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv aaas ON Semumnduclm assume any Mammy ansmg mac xna apphcahan m use no any pmduclnv mum and saaamcauy dwsc‘axms any and au Mammy mc‘udmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Semxmnduclar dues nn| aanyay any hcense under Ms pa|em nghls nar xna
TSOP5
CASE 483
ISSUE N
DATE 12 AUG 2020
SCALE 2:1
1
5
XXX MG
G
GENERIC
MARKING DIAGRAM*
1
5
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
XXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= PbFree Package
1
5
XXXAYWG
G
Discrete/Logic
Analog
(Note: Microdot may be in either location)
XXX = Specific Device Code
M = Date Code
G= PbFree Package
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
DIM MIN MAX
MILLIMETERS
A
B
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
M0 10
S2.50 3.00
123
54 S
A
G
B
D
H
C
J
__
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
CSEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
TOP VIEW
SIDE VIEW
A
B
END VIEW
1.35 1.65
2.85 3.15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ARB18753C
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSOP5
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
YEW/a LilLl‘L‘J ; THITH 7 “ Lima t :H 4 ON Semiwndudw" m \ BOTTOM VIEW GB OO ON Sammnuucmn and ngma av n|hers J are Mademavks ac Samanaaaxan Campunenls lnduslnes Lu: dha ON Samaanaaaxan ar us aaaaaanaa m the Umled Slates andJm mhev commas ON Samaanaaaxan vesewes we th| In make changes wuhnm mnhev nauaa In any prnduns nanan ON Semanduc‘m makes m7 wavvamy represenlalmn m guarantee regardmg ma suuahmy a« W; manuals «an any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy ansmg am: the apphcahan m use .7. any pmduclnv mum and aaaanaauy dwsc‘axms any and au Mammy mcmdmg wmham hmma‘mn spema‘ cansequenha‘ m \nudenla‘ damages ON Sanmnaaaxan dues nn| cam/2y any hcense under Ms pa|em thls war the
UDFN8 1.8x1.2, 0.4P
CASE 517AJ01
ISSUE O
DATE 08 NOV 2006
SCALE 4:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM TERMINAL TIP.
4. MOLD FLASH ALLOWED ON TERMINALS
ALONG EDGE OF PACKAGE. FLASH MAY
NOT EXCEED 0.03 ONTO BOTTOM
SURFACE OF TERMINALS.
5. DETAIL A SHOWS OPTIONAL
CONSTRUCTION FOR TERMINALS.
A B
E
D
BOTTOM VIEW
b
e
8X
BAC
CNOTE 3
0.10 C
PIN ONE
REFERENCE
TOP VIEW
0.10 C
A
A1
(A3)
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
L
8X
14
58
1
8
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b0.15 0.25
D1.80 BSC
E1.20 BSC
e0.40 BSC
L0.45 0.55
e/2
b2 0.30 REF
L1 0.00 0.03
L2 0.40 REF
DETAIL A
(L2)
(b2)
NOTE 5
L1
DETAIL A
M
0.10
M
0.05
0.22
0.32
8X
1.50
0.40 PITCH
0.66
DIMENSIONS: MILLIMETERS
MOUNTING FOOTPRINT
7X
1
SOLDERMASK DEFINED
XX = Specific Device Code
M = Date Code
G= PbFree Package
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
XXM
G
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON23417D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
UDFN8 1.8X1.2, 0.4P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" m @ HHHH HHHH HHHH HERE 4 FUDGE] !HHH !HHH gHHH EHHH 1 1 } x ‘ 1 (...... a. ............. ... ......M .. SW. CW ........ .. ... 0. SW .. W- .. ...... ...... ...... ...... 0. SW ...... ... .... .. .... ...... ...... .. ... ...... ...... o. ......m... .. ...... .. ...... ...... ... 5...... .. .. ...... ... .. ...... a. s............ ...... ... ...... ...... ...... .....w... .. .. ... ...... ......w... ....-. ... ... ... ...... ...... ...... ...... ...5......... .. ...... ...... o. 5.--.-. .... ...... ... ...... ...... .... ..............
SOIC8 NB
CASE 75107
ISSUE AK
DATE 16 FEB 2011
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
BS
D
H
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) ZSXS
M
____
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
GENERIC
MARKING DIAGRAM*
1
8
XXXXX
ALYWX
1
8
IC Discrete
XXXXXX
AYWW
G
1
8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXX
AYWW
1
8
(PbFree)
XXXXX
ALYWX
G
1
8
IC
(PbFree)
XXXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G= PbFree Package
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
ON Semxcunduclm and ave hademavks av Semxcanduclur Campunenls lnduslnes. uc dha ON Semxcanduclar Dr K: suhsxdmnes m xna Umled sxaxas andJm mhev cmm‘nes ON Semxcunduclar vesewes me “gm to make changes wuhum mnna. mouse to any pruduns necem ON Semanduc‘m makes nu wanamy. represenlalmn m guarantee regardmg ma sumahmly at W; manual: can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy snsmg mm xna aapncauan m use M any pmduclnv mum and specmcsl‘y dwsc‘axms any and an Mammy mc‘udmg wxlham hmma‘mn spema‘ cansequemm m \nmdeula‘ damages ON Semxmnduclar dues nn| away any hcense under Ms pa|EM nghls Ivar xna ngms av mhers
SOIC8 NB
CASE 75107
ISSUE AK
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. NSOURCE
2. NGATE
3. PSOURCE
4. PGATE
5. PDRAIN
6. PDRAIN
7. NDRAIN
8. NDRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42564B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" m 1% £1 HHHHHHH T ‘5 fl 0 HHHHHHH mmaa mm [H N wn EDD Umm 4 ON Semxcunduchv and are Mademavk: av Semmanduclur Campunenls Inuwnaa LLC dba ON Samanauaxar Dr H: suaamanas m xna Umled sxaxaa andJm mhev comma: ON Semxcunduclar vesewe: we th| [a make change: wuhum Yunhev name [a any prnduns havem ON Semanduc‘m makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at W; manuals can any pamcu‘av purpase nnv dues ON Semumndudm assume any Mammy ansmg mac xna apphcahan m we no any pmduclnv mum and :pecmcafly dwsc‘axms any and au Mammy mcmdmg wmnam hmma‘mn spema‘ cansequenha‘ m \nmdenla‘ damages ON Sammnauaxar dues nn| aanyay any hcense under Ms pa|em thls nar xna ngma av n|hers
SOIC14 NB
CASE 751A03
ISSUE L
DATE 03 FEB 2016
SCALE 1:1
1
14
GENERIC
MARKING DIAGRAM*
XXXXXXXXXG
AWLYWW
1
14
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = PbFree Package
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
STYLES ON PAGE 2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
H
14 8
71
M
0.25 B M
C
h
X 45
SEATING
PLANE
A1
A
M
_
S
A
M
0.25 B S
C
b
13X
B
A
E
D
e
DETAIL A
L
A3
DETAIL A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
D8.55 8.75 0.337 0.344
E3.80 4.00 0.150 0.157
A1.35 1.75 0.054 0.068
b0.35 0.49 0.014 0.019
L0.40 1.25 0.016 0.049
e1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010
A1 0.10 0.25 0.004 0.010
M0 7 0 7
H5.80 6.20 0.228 0.244
h0.25 0.50 0.010 0.019
__ __
6.50
14X
0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
0.10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42565B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOIC14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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SOIC14
CASE 751A03
ISSUE L
DATE 03 FEB 2016
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 2:
CANCELLED
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42565B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOIC14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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Micro8
CASE 846A02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 3:
PIN 1. N-SOURCE
2. N-GATE
3. P-SOURCE
4. P-GATE
5. P-DRAIN
6. P-DRAIN
7. N-DRAIN
8. N-DRAIN
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= PbFree Package
XXXX
AYWG
G
1
8
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB14087C
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
MICRO8
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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TSSOP14 WB
CASE 948G
ISSUE C
DATE 17 FEB 2016
SCALE 2:1
1
14
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
LU
SEATING
PLANE
0.10 (0.004)
T
SECTION NN
DETAIL E
JJ1
K
K1
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
V
14X REFK
N
N
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYWG
G
1
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASH70246A
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
TSSOP14 WB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
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