FE310-G002 Preliminary~ Datasheet by GroupGets LLC

View All Related Products | Download PDF Datasheet
SiFive FE310-G002 Preliminary Datasheet
v1p0
c
SiFive, Inc.
SiFive FE310-G002 Preliminary
Datasheet
Proprietary Notice
Copyright c
2016-2019, SiFive Inc. All rights reserved.
Information in this document is provided “as is”, with all faults.
SiFive expressly disclaims all warranties, representations and conditions of any kind, whether ex-
press or implied, including, but not limited to, the implied warranties or conditions of merchantabil-
ity, fitness for a particular purpose and non-infringement.
SiFive does not assume any liability rising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation indirect, incidental, special,
exemplary, or consequential damages.
SiFive reserves the right to make changes without further notice to any products herein.
Release Information
Version Date Changes
v1p0 April 12, 2019 Initial Release
i
1.1 Features FE310-G002 Pins 2.1 2.3 2.5 2.6 2.8 3.3 3.4 3.5 3.7 FE310-GOOZ Pinout Power Pins JTAG QSPI AON Block Interface Pins CLINT PLIC JTAG Connections Quad-SPI Flash
Contents
SiFive FE310-G002 Preliminary Datasheet i
1 FE310-G002 Description 1
1.1 Features ......................................... 1
1.2 Description........................................ 1
2 FE310-G002 Pins 2
2.1 FE310-G002Pinout................................... 2
2.2 PinDescriptions..................................... 3
2.3 PowerPins........................................ 3
2.4 CrystalDrivers...................................... 4
2.5 JTAG ........................................... 4
2.6 QSPI ........................................... 4
2.7 GPIOMultiplexedOutputs ............................... 4
2.8 AONBlockInterfacePins................................ 5
3 Configuration and Block Diagram 6
3.1 BlockDiagram...................................... 6
3.2 E31 Core Complex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 CLINT .......................................... 6
3.4 PLIC ........................................... 6
3.5 JTAGConnections ................................... 7
3.6 DebugModule...................................... 7
3.7 Quad-SPIFlash..................................... 7
3.8 GPIOComplex ..................................... 8
3.9 Always-On(AON)Block ................................ 8
3.10 PowerSupply ...................................... 8
ii
5.1 Boot Code 5.2 Trimmed Values
Copyright c
2016-2019, SiFive Inc. All rights reserved. iii
4 FE310-G002 Typical Electrical Specifications 9
5 FE310-G002 Application Notes 11
5.1 BootCode ........................................ 11
5.2 TrimmedValues..................................... 12
6 FE310-G002 OTP Application Notes 13
6.1 OTP Programming Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2 OTP Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 FE310-G002 Package Information 15
7.1 Package Outline Drawing - 48QFN . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 Recommended PCB Footprint - 48QFN . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 1
FE310-G002 Description
1.1 Features
SiFive E31 Core Complex up to 320MHz.
Flexible clocking options including inter-
nal PLL, free-running ring oscillator and
external 16MHz crystal.
1.61 DMIPs/MHz, 2.73 Coremark/MHz
RV32IMAC
8kB OTP Program Memory
8kB Mask ROM
16kB Instruction Cache
16kB Data SRAM
3 Independent PWM Controllers
External RESET pin
JTAG, SPI I2C, and UART interfaces.
QSPI Flash interface.
Requires 1.8V and 3.3V supplies.
Hardware Multiply and Divide
1.2 Description
The FE310-G002 is the second Freedom E300
SoC. The FE310-G002 is built around the
E31 Core Complex instantiated in the Freedom
E300 platform.
The FE310-G002 Manual should be read to-
gether with this datasheet. This datasheet pro-
vides electrical specifications and an overview
of the FE310-G002.
The FE310-G002 comes in a convenient, in-
dustry standard 6x6mm 48-lead QFN package
( 0.4mm pad pitch ).
1
Chapter 2
FE310-G002 Pins
2.1 FE310-G002 Pinout
The FE310-G002 is offered in a convenient 48-lead 6x6 QFN package ( 0.4mm lead pitch ). The
exposed paddle ( Pin 49 ) should be connected directly to the ground plane.
2
Mama X21 uvvn (z was az was r mm a! me m cm!) xu‘nmvn a: OMB 195 an 2 szd a: was O Ems \dso E E 2‘ El El E E El El E swogz 0st be 1 1 3S WNU mum SM n 1E 35 WW Q 7 Q7 PWMZ 1 QSPLDDJE Emil“; WE Essie; E SIFIve 36m FE3lO—G002 M’NDDE 6x6 ABrlead QFN Elm mm a (0 40mm Pad PM) 25 65w E 313:?“ E I we 2 xmixo m 27 SP LL53 :l mm; [45 (Expoxed Vaflmz>GND 25 swag vwvn, urmwnn 12 :‘25 own a wan I?‘ E E E E E E num‘Nov Nargm nuA NOV NrNav mnvfi‘asa NOV : mo nwd Nov SWIM nwd Nov 5mm (15:: Nov a mo nwd Nov
Copyright c
2016-2019, SiFive Inc. All rights reserved. 3
SiFive
FE310-G002
6x6 48-lead QFN
(0.40mm Pad Pitch)
[49. (Exposed Paddle) GND
36 GPIO_12
PWM2_2
I2C_SDA
35 GPIO_11
PWM2_1
34 GPIO_10
SPI1_CS3
PWM2_0
33 GPIO_9
SPI1_CS2
32
QSPI_CS
31
VDD
30
PLL_AVDD
29
PLL_AVSS
28
XTAL_XI
27
XTAL_XO
26
IVDD
25
OTP_AIVDD
24
JTAG_TCK
23
JTAG_TDO
22
JTAG_TMS
21
JTAG_TDI
20
AON_PMU_OUT_1
19
AON_PMU_DWAKEUP_N
18
AON_IVDD
17
AON_PSD_LFALTCLK
16
AON_PSD_LFCLKSEL
15
AON_PMU_OUT_0
14
AON_IVDD
13
AON_ERST_N
1
QSPI_DQ_3
2
QSPI_DQ_2
3
QSPI_DQ_2
4
QSPI_DQ_1
5IVDD
6GPIO_5
SPI1_SCK
7VDD
8GPIO_4
SPI1_MISO
9GPIO_3
SPI1_MOSI
PWM0_3
10 GPIO_2
SPI1_CS0
PWM0_2
11 GPIO_1
PWM0_1
12 GPIO_0
PWM0_0
37
QSPI_SCK
38
IVDD
39
VDD
40
GPIO_23
UART1_RX
41
GPIO_22
PWM1_3
42
GPIO_21
PWM1_2 43
GPIO_20
PWM1_0
44
GPIO_19
PWM1_1
45
GPIO_18
UART1_TX
46
GPIO_17
UART0_TX
47
GPIO_16
UART0_RX
48
GPIO_13
PWM2_3
I2C_SCL
Figure 2.1: FE310-G002 Pinout
2.2 Pin Descriptions
2.3 Power Pins
VDD ( 6, 30, 46 ) : Core supply voltage. 1.8V +/- 10%. Recommended 1uF ceramic bypass
capacitor to GND plane mounted close to the device. All VDD pins must be connected externally.
IVDD ( 11, 32, 47 ) : I/O supply voltage. 3.3V +/- 10%. Recommended 1uF ceramic bypass
capacitor to GND plane mounted close to the device. All IVDD pins must be connected externally.
AON VDD ( 23 ) : AON supply voltage. 3.3V +/- 10%. Recommended 1uF ceramic bypass
capacitor to GND plane mounted close to the device. All VDD pins must be connected externally.
AON IVDD ( 19 ) : AON I/O supply voltage. 3.3V +/- 10%. Recommended 1uF ceramic bypass
capacitor to GND plane mounted close to the device. All VDD pins must be connected externally.
OTP AIVDD ( 12 ) : OTP supply voltage. 3.3V +/- 10%. Recommended 1uF ceramic bypass
capacitor to GND plane mounted close to the device. All IVDD pins must be connected externally.
nPLL AVDD ( 7 ) : PLL supply voltage. 1.8V +/- 10%. Recommended 1uF ceramic bypass
capacitor to GND plane mounted close to the device. All VDD pins must be connected externally.
Copyright c
2016-2019, SiFive Inc. All rights reserved. 4
PLL AVSS ( 8 ) : Isolated PLL supply bypass. Connect through a 1uF ceramic capacitor to
PLL AVDD. This pin is not to be connected directly to GND.
GND ( 49 ) : Exposed paddle is a ground return and should be connected directly to the ground
plane.
2.4 Crystal Drivers
XTAL XI ( 9 ) : 16MHz Crystal Input
XTAL XO ( 10 ) : 16MHz Crystal Output
An external 16MHz crystal may be connected between the two XTAL pins. The crystal
should have a capacitive load of 12 pF and an ESR 80 Ohms. An external oscillator
may also be used to drive the FE310-G002 through the XTAL XI input, in which case the
XTAL XO pin should be left floating. The external oscillator should operate between GND
and the 1.8V VDD supply.
2.5 JTAG
JTAG TCK ( 13 ) : JTAG TCK Input
JTAG TDO ( 14 ) : JTAG TDO Output
JTAG TMS ( 15 ) : JTAG TMS Input
JTAG TDI ( 16 ) : JTAG TDI Input
Please refer to the FE310-G002 Manual for information on the JTAG and debug facilities.
2.6 QSPI
QSPI DQ 3 ( 1 ) : Bidirectional Quad SPI Data Line
QSPI DQ 2 ( 2 ) : Bidirectional Quad SPI Data Line
QSPI DQ 1 ( 3 ) : Bidirectional Quad SPI Data Line
QSPI DQ 0 ( 4 ) : Bidirectional Quad SPI Data Line
QSPI CS ( 5 ) : Quad SPI Chip Select OUTPUT, Active Low.
QSPI SCK ( 48 ) : Quad SPI Clock OUTPUT
Please refer to the FE310-G002 Manual for information on the SPI FLASH interface and
to the Applications Notes and Errata section of this datasheet for information in the SPI
implementation.
2.7 GPIO Multiplexed Outputs
The General Purpose Input/Output pins are multiplexed with PWM, SPI and UART func-
tions as described in Table 2.1. GPIO pins may be configured as inputs or outputs, with
a weak pull-up, and with two drive strengths. In addition, PWM, SPI and UART functions
may be multiplexed on the pins through the GPIO control register. Please refer to the
FE310-G002 Manual for information on GPIO capabilities.
Copyright c
2016-2019, SiFive Inc. All rights reserved. 5
Name Pin GPIO PWM SPI UART i2C
GPIO 0 25 0 I/O PWM0 0 O
GPIO 1 26 1 I/O PWM0 1 O
GPIO 2 27 2 I/O PWM0 2 O SPI1 SS0
GPIO 3 28 3 I/O PWM0 3 O SPI1 MOSI
GPIO 4 29 4 I/O SPI1 MISO
GPIO 5 31 5 I/O SPI1 SCK
GPIO 9 33 9 I/O SPI1 SS2
GPIO 10 34 10 I/O PWM2 0 O SPI1 SS3
GPIO 11 35 11 I/O PWM2 1 O
GPIO 12 36 12 I/O PWM2 2 O I2C0 SDA
GPIO 13 37 13 I/O PWM2 3 O I2C0 SCL
GPIO 16 38 16 I/O UART0 RX I
GPIO 17 39 17 I/O UART0 TX O
GPIO 18 40 18 I/O UART1 TX O
GPIO 19 41 19 I/O PWM1 1 O
GPIO 20 42 20 I/O PWM1 0 O
GPIO 21 43 21 I/O PWM1 2 O
GPIO 22 44 22 I/O PWM1 3 O
GPIO 23 45 23 I/O UART1 RX I
Table 2.1: GPIO pin assignments.
2.8 AON Block Interface Pins
The following pins interface to the Always-ON ( AON ) block.
AON PMU OUT 0 ( 22 ) : Programmable SLEEP control OUTPUT
AON PMU OUT 1 ( 17 ) : Programmable SLEEP control OUTPUT
AON PMU DWAKEUP N ( 18 ) : Digital Wake-From-Sleep INPUT, active LOW.
AON ERST N ( 24 ) : External System Reset INPUT, active LOW.
AON PSD LFALTCLK ( 20 ) : Optional 32kHz Clock Input.
AON PSD LFCLKSEL ( 21 ) : 32kHz Clock Source Selector. When driven low, AON
PSD LFALTCLK input is used as the 32 kHz low-frequency clock source. When left
unconnected or driven high, the internal LFROSC source is used.
Chapter 3
Configuration and Block Diagram
3.1 Block Diagram
Figure 3.1 shows the overall block diagram of FE310-G002. FE310-G002 contains an E31 Core
Complex, a selection of flexible I/O peripherals, a dedicated off-chip Quad-SPI flash controller
for execute-in-place, 8 KiB of in-circuit programmable OTP memory, 8 KiB of mask ROM, clock
generation, and an always-on (AON) block including a programmable power-management unit
(PMU).
3.2 E31 Core Complex Configuration
The core is configured to support the RV32IMAC ISA options.
The branch predictor configuration has 40 branch-target buffer (BTB) entries, 128 branch-history
(BHT) entries, and a two-entry return-address stack (RAS).
The integer multiplier completes 8 bits per cycle, so takes up to four clock cycles for a single 32×32
multiply operation.
The integer divider completes one bit per clock cycle, with an early out.
The instruction cache is a 16 KiB two-way set associative with 32-byte lines.
The data SRAM is 16 KiB.
The system mask ROM is 8 KiB in size and contains simple boot code. The system ROM also
holds the platform configuration string and debug ROM routines.
3.3 CLINT
The Core Local Interrupt Controller (CLINT) supports the standard timer and software interrupts.
3.4 PLIC
The platform-level interrupt controller (PLIC) receives interrupt signals from the peripheral devices
and prioritizes these for service by the core. The PLIC supports 7 programmable priority levels.
Please refer to the chapter “FE310-G002 Interrupts” in the SiFive FE310-G002 Manual for more
information on the PLIC implementation.
6
FE3lorGODZ Gwocumv‘ex w mm cm mmucmn cm: Peripheral Huermpl UAR“? 16MB (2'Wfly} UARU r 7M 1 mm W) Bunch Frzmchrm Fle and) mmmmmn mm m amen 5mm mmucunn Decomprexxor m ammo (M my Mumnher/Dmdzl 05pm ospu m: 1 xv map: can L Dad/Slum mm mm Yel may m7 OTF (ENE) 1m: maven" Leve‘ mxevmm Comm sly/{AP Cm oca‘ New»: muck Gznzvalmn A0 Imam/m: ””055 59mm m vddpJJ vsspn hfxoscln hfxuscuut buQ Modu‘e Backup Reamer: mu R2513! Sync h‘LJJu \ mung ‘ PMHJHKJ mamme cm \ w x ‘ ‘ m x x \ Fag-Ems cm rm watchdug muse Reset Um aanuw AABMS Hawkins 2 ‘dwakewm \ \ ‘Jfaltclk \Jfanuksel \ \ersl n \
Copyright c
2016-2019, SiFive Inc. All rights reserved. 7
Figure 3.1: FE310-G002 top-level block diagram.
3.5 JTAG Connections
A four-wire 1149.1 JTAG connection is used to connect the external debugger to the internal debug
module.
3.6 Debug Module
The debug module is accessed over JTAG, and has support for eight programmable hardware
breakpoints.
3.7 Quad-SPI Flash
A dedicated quad-SPI (QSPI) flash interface is provided to hold code and data for the system.
The QSPI interface supports burst reads of 32 bytes over TileLink to accelerate instruction cache
refills. The QSPI can be programmed to support eXecute-In-Place modes to reduce SPI command
overhead on instruction cache refills. The QSPI interface also supports single-word data reads
Copyright c
2016-2019, SiFive Inc. All rights reserved. 8
over the primary TileLink interface, as well as programming operations using memory-mapped
control registers.
3.8 GPIO Complex
The GPIO complex manages the connection of digital I/O pads to digital peripherals, including
SPI, UART, and PWM controllers, as well as for regular programmed I/O operations. FE310-G002
has two additional QSPI controllers in the GPIO block, one with four chip selects and one with
one. FE310-G002 also has two UARTs. FE310-G002 has three PWM controllers, two with 16-bit
precision and one with 8-bit precision.
3.9 Always-On (AON) Block
The AON block contains the reset logic for the chip, an on-chip low-frequency oscillator, a watch-
dog timer, connections for an off-chip low-frequency clock source, the real-time clock, a pro-
grammable power-management unit, and 16×32-bit backup registers that retain state while the
rest of the chip is powered down.
The AON can be instructed to put the system to sleep. The AON can be programmed to exit sleep
mode on a real-time clock interrupt or when the external digital wakeup pin, dwakeup n, is pulled
low. The dwakeup n input supports wired-OR connections of multiple wakeup sources.
3.10 Power Supply
FE310-G002 requires two dedicated power rails providing 1.8 V power to the core logic, and 3.3 V
to the I/O pads and to the always on-block.
Chapter 4
FE310-G002 Typical Electrical
Specifications
Note: These electrical specifications are TYPICAL ONLY, and are not thoroughly tested in engi-
neering sample parts. Production versions of the devices will be provided with a complete elec-
trical specification. Except where otherwise noted, the typical electrical parameters are specified
under the following conditions: Ambient Temperature 27C, VDD Supply Voltage 1.8V, IVDD Sup-
ply Voltage 3.3V, Processor Clock 16MHz crystal. These are preliminary specifications and are
subject to change without notice based on characterization.
Symbol Parameter Conditions Min Typ Max Units
IIVDD IVDD Supply Current ACTIVE, 16MHz 8 mA
ACTIVE, 250MHz 16 mA
IVDD VDD Supply Current ACTIVE, 16MHz 8 mA
ACTIVE, 250MHz 150 mA
Table 4.1: FE310-G002 Supply Voltage and Current Characteristics
9
Copyright c
2016-2019, SiFive Inc. All rights reserved. 10
Symbol Parameter Conditions Min Typ Max Units
VIL Input Voltage LOW Threshold GPIO 0.8 V
VIH Input Voltage HIGH Threshold GPIO 1.0 V
VOL Output Voltage LOW GPIO, DS=0, 1mA DC Load 20 mV
GPIO, DS=1, 1mA DC Load 16 mV
GPIO, DS=0, 20mA DC Load 380 mV
GPIO, DS=1, 20mA DC Load 280 mV
VOH Output Voltage HIGH, with
respect to VDDIO
GPIO, DS=0, 1mA DC Load -18 mV
GPIO, DS=1, 1mA DC Load -14 mV
GPIO, DS=0, 20mA DC Load -400 mV
GPIO, DS=1, 20mA DC Load -290 mV
IOL Output Current LOW GPIO, DS=0, VGPIO=0.3V 16 mA
GPIO, DS=1, VGPIO=0.3V 21 mA
IOH Output Current HIGH GPIO, DS=0, VGPIO=3.0V -15 mA
GPIO, DS=1, VGPIO=3.0V -21 mA
IPUL Output Pull-Up Current GPIO, VGPIO=0V -85 uA
(PUE=1) GPIO, VGPIO=2V -75 uA
ILKH Input Leakage, HIGH GPIO, VGPIO=3.3V 200 pA
ILKL Input Leakage, LOW GPIO, VGPIO=0V -100 pA
Table 4.2: FE310-G002 Input/Output Characteristics
Symbol Parameter Conditions Min Typ Max Units
FLFRO Low Frequency Ring Oscillator
Center Frequency
40 kHz
FHFRO High Frequency Ring Oscillator
Center Frequency
72 MHz
FMAX Maximum Tested Operating
Frequency
320 MHz
Table 4.3: FE310-G002 AC Characteristics
Chapter 5
FE310-G002 Application Notes
5.1 Boot Code
The FE310-G002 boots by jumping to the beginning of the OTP memory and executing code found
there. As shipped, the OTP memory at the boot location is preprogrammed to jump immediately
to the end of the OTP memory, which contains the following code to jump to the beginning of the
SPI-Flash at 0x2000 0000:
fence 0,0
li t0, 0x20000000
jr t0
fence 0,0 is encoded as 0x0000 000F, and the instruction may be modified by burning additional
bits to transform it into a JAL instruction ( opcode 0x6F ) to execute arbitrary code rather than
jumping directly to the beginning of the SPI-Flash.
Please refer to the OTP Memory section of this datasheet for more information on programming
the OTP.
11
Copyright c
2016-2019, SiFive Inc. All rights reserved. 12
5.2 Trimmed Values
As shipped the OTP memory contains the following information:
Item OTP
Address
Factory
Value
Description
BOOT 0 0x7f50 106f Code to jump to LAST FENCE
LIFECYCLE 2044 0x1 OTP Lifecycle Counter
HFROSC TRIM 2043 Varies HFROSC trim value
STAMP 2041 Varies Device ID Stamp, not
guaranteed unique.
LAST FENCE 2045 0x0000 000F
0x2000 02b7
0x0002 8067
Code to jump to SPI-FLASH.
Table 5.1: FE310-G002 OTP Contents as Shipped
Chapter 6
FE310-G002 OTP Application Notes
6.1 OTP Programming Warnings
Warning: Improper use of the One Time Programmable (OTP) memory may result in a nonfunc-
tional device and/or unreliable operation.
OTP Memory must be programmed following the procedure outlined below exactly.
OTP Memory is designed to be programmed or accessed only while the system clock is
running between 1MHz and 37MHz.
OTP Memory must be programmed only while the power supply voltages remain within
specification.
6.2 OTP Programming Procedure
1. LOCK the otp:
(a) Writing 0x1 to otp lock
(b) Check that 0x1 is read back from otp lock.
(c) Repeat this step until 0x1 is read successfully.
2. SET the programming voltages by writing the following values:
otp_mrr=0x4
otp_mpp=0x0
otp_vppen=0x0
3. WAIT 20us for the programming voltages to stabilize
4. ADDRESS the memory by setting otp a
5. WRITE one bit at a time:
(a) set only the bit you want to write high in otp d
(b) Bring otp ck HIGH for 50us
13
Copyright c
2016-2019, SiFive Inc. All rights reserved. 14
(c) Bring otp ck LOW.
Note that this means only one bit of otp d should be high at any time.
6. VERIFY the written bits setting otp mrr=0x9 for read margin.
7. SOAK any verification failures by repeating steps 2-5 using 400us pulses.
8. REVERIFY the rewritten bits setting otp mrr=0xF. Steps 7,8 may be repeated up to 10 times
before failing the part.
9. UNLOCK the otp by writing 0x0 to otp lock.
6mm x 6mm 48»Lead QFN ( 04mm Pad Pitch ) a as : 0 na lq—Gnuuno—p‘ _.| l 4,20:am :7 «a . H J J J , Laser mark E ‘5 I: — 1 In! pm 1 r C C Idenlmcanon r L I: m ms area E I: I: g E I: I: A 5' L C § g E r k a r E I: I. I: I: I I: I: E 25 r 12 NOTE. AII dimensmns ave In mIIIImeIeYS +| 2" A If mums: ozfigaus aw muons 79,, VW Side Wew Eomm VIew
Chapter 7
FE310-G002 Package Information
7.1 Package Outline Drawing - 48QFN
The FE310-G002 is offered in a convenient 48-lead 6x6 QFN package ( 0.4mm lead pitch ). The
exposed paddle ( Pin 49 ) should be connected directly to the ground plane.
Figure 7.1: 48QFN Package Outline Drawing ( 0.4mm pitch )
15
qu mu ********* mflflflflwmflflflb 020 mm mm]; Q . |:J ' |:| “ |:| \ |:J % |:| sasrw AMTVP lir— ______ "T —————— ———- £5in :1 \ |:| \ |:| ‘ |:| ! E 1 WM --------- umfluflmm NOTE AH mensmns m mm
Copyright c
2016-2019, SiFive Inc. All rights reserved. 16
7.2 Recommended PCB Footprint - 48QFN
Figure 7.2: 48QFN PCB Footprint Drawing ( 0.4mm pitch )