STM32F413xG, STM32F413xH Datasheet by STMicroelectronics

This is information on a product in full production.
September 2017 DocID029162 Rev 6 1/208
STM32F413xG STM32F413xH
Arm
®
-Cortex
®
-M4 32b MCU+FPU, 125 DMIPS, up to 1.5MB Flash,
320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs
Datasheet - production data
Features
Dynamic Efficiency Line with eBAM (enhanced
Batch Acquisition Mode)
1.7 V to 3.6 V power supply
-40 °C to 85/105/125 °C temperature range
Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 100 MHz,
memory protection unit, 125 DMIPS/
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
Up to 1.5 Mbytes of Flash memory
320 Kbytes of SRAM
Flexible external static memory controller
with up to 16-bit data bus: SRAM, PSRAM,
NOR Flash memory
Dual mode Quad-SPI interface
LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
1.7 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Power consumption
Run: 112 µA/MHz (peripheral off)
Stop (Flash in Stop mode, fast wakeup
time): 42 µA Typ.; 80 µA max @25 °C
Stop (Flash in Deep power down mode,
slow wakeup time): 15 µA Typ.;
46 µA max @25 °C
Standby without RTC: 1.1 µA Typ.;
14.7 µA max at @85 °C
– V
BAT supply for RTC: 1 µA @25 °C
2x12-bit D/A converters
1×12-bit, 2.4 MSPS ADC: up to 16 channels
6x digital filters for sigma delta modulator,
12x PDM interfaces, with stereo microphone
and sound source localization support
General-purpose DMA: 16-stream DMA
Up to 18 timers: up to twelve 16-bit timers, two
32-bit timers up to 100 MHz each with up to
four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input, two
watchdog timers (independent and window),
one SysTick timer, and a low-power timer
Debug mode
Serial wire debug (SWD) & JTAG
–Cortex
®-M4 Embedded Trace Macrocell™
Up to 114 I/O ports with interrupt capability
Up to 109 fast I/Os up to 100 MHz
Up to 114 five V-tolerant I/Os
Up to 24 communication interfaces
Up to 4x I2C interfaces (SMBus/PMBus)
Up to 10 UARTS: 4 USARTs / 6 UARTs
(2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816
interface, LIN, IrDA, modem control)
Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or
I2S audio protocol), out of which 2 muxed
full-duplex I2S interfaces
SDIO interface (SD/MMC/eMMC)
Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with PHY
3x CAN (2.0B Active)
– 1xSAI
True random number generator
CRC calculation unit
96-bit unique ID
RTC: subsecond accuracy, hardware calendar
All packages are ECOPACK®2
Table 1. Device summary
Reference Part number
STM32F413xH STM32F413CH STM32F413MH STM32F413RH
STM32F413VH STM32F413ZH
STM32F413xG STM32F413CG STM32F413MG STM32F413RG
STM32F413VG STM32F413ZG
)%*$
UFQFPN48
(7x7 mm)
UFBGA100
(7x7mm)
UFBGA144
(10x10mm)
LQFP100 (14x14mm)
LQFP144 (20x20mm)
LQFP64 (10x10mm)
WLCSP81
(4.039x3.951 mm)
www.st.com
Contents STM32F413xG/H
2/208 DocID029162 Rev 6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 19
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
3.3 Enhanced Batch Acquisition mode (eBAM) . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
3.7 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.19 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 31
3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 36
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39
3.30 Dynamic tuning of PDM delays for sound source localization . . . . . . . . . 39
3.31 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.33 Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 40
3.34 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.35 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.36 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.37 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.38 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.39 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.40 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 WLCSP81 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5 LQFP144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.6 UFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Contents STM32F413xG/H
4/208 DocID029162 Rev 6
4.7 UFBGA144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.8 Pins definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.9 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.2 VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . . 85
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 86
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 86
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 116
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 121
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.25 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.26 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.27 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 172
6.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.1 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.6 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.7 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Appendix A Recommendations when using the internal reset OFF . . . . . . . . 201
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
B.1 Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
B.2 Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
B.3 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 204
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
List of tables STM32F413xG/H
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F413xG/H features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 31
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. DFSDM feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10. STM32F413xG/H pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 12. STM32F413xG/H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 13. STM32F413xG/H register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 18. Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 19. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 85
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 86
Table 22. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 23. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 24. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V. . . 90
Table 26. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 91
Table 27. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 92
Table 28. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory - VDD = 1.7 V. . . . . . . . . . . . . . . 93
Table 29. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 94
Table 30. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 1.7 V . . . . . 95
Table 31. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 96
Table 32. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V . . . . . . . . . . . . . 97
Table 33. Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 98
Table 34. Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 98
Table 35. Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 98
Table 36. Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . . 99
Table 37. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 99
Table 38. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 39. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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8
Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 43. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 45. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 47. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 48. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 49. SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 50. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 51. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 52. Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 53. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 54. EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 55. EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 60. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 61. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 62. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 63. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 64. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 65. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 66. FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 67. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 68. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 69. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 70. QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 71. QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 72. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 73. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 74. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 75. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 76. ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 77. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 78. ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 79. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 146
Table 80. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 146
Table 81. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 82. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 83. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 84. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 85. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 86. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 87. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 161
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8/208 DocID029162 Rev 6
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 163
Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165
Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 97. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 100. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 101. eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 102. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 103. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 104. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 177
Table 105. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 106. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 107. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 108. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 109. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 110. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 194
Table 111. UFBGA144 - 144-ball, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid
array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 112. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 197
Table 113. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 114. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 115. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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11
List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. STM32F413xG/H block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. STM32F413xG/H WLCSP81 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. STM32F413xG/H UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 13. STM32F413xG/H LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. STM32F413xG/H LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. STM32F413xG/H LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. STM32F413xG/H UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. STM32F413xG/H UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 20. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 24. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator
“low power” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 25. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator
“high drive” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 26. Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 31. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 32. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 35. FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 38. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 39. FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 43. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 44. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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10/208 DocID029162 Rev 6
Figure 45. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 46. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 47. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 143
Figure 48. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 149
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 150
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 159
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 161
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 57. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 58. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 60. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 61. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 62. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 63. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 64. WLCSP81- 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 65. WLCSP81 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 66. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 67. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 68. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 69. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 182
Figure 70. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 71. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 72. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 186
Figure 73. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 74. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 75. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 189
Figure 76. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 77. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 78. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 79. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 80. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 81. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 82. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 83. UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 84. Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 85. Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 86. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 204
Figure 87. USB peripheral-only Full speed mode with direct connection
DocID029162 Rev 6 11/208
STM32F413xG/H List of figures
11
for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 88. USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 205
Figure 89. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 205
Co'rteX“ Intellwgent Processors by ARM‘ ARM OWERED n.
Introduction STM32F413xG/H
12/208 DocID029162 Rev 6
1 Introduction
This datasheet provides the description of the STM32F413xG/H microcontrollers.
For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming
manual (PM0214) available from www.st.com.
DocID029162 Rev 6 13/208
STM32F413xG/H Description
42
2 Description
The STM32F413XG/H devices are based on the high-performance Arm® Cortex®-M4 32-bit
RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all Arm single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F413XG/H devices belong to the STM32F4 access product lines (with products
combining power efficiency, performance and integration) while adding a new innovative
feature called Batch Acquisition Mode (BAM) allowing to save even more power
consumption during data batching.
The STM32F413XG/H devices incorporate high-speed embedded memories (up to
1.5 Mbytes of Flash memory, 320 Kbytes of SRAM), and an extensive range of enhanced
I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB
bus matrix.
All devices offer a 12-bit ADC, two 12-bit DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timer for motor control, two general-purpose 32-bit timers
and a low power timer.
They also feature standard and advanced communication interfaces.
Up to four I2Cs, including one I2C supporting Fast-Mode Plus
Five SPIs
Five I2Ss out of which two are full duplex. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicate internal audio PLL or via an external clock to
allow synchronization.
Four USARTs and six UARTs
An SDIO/MMC interface
An USB 2.0 OTG full-speed interface
Three CANs
An SAI.
In addition, the STM32F413xG/H devices embed advanced peripherals:
A flexible static memory control interface (FSMC)
A Quad-SPI memory interface
Two digital filter for sigma modulator (DFSDM) supporting microphone MEMs and
sound source localization, one with two filters and up to four inputs, and the second
one with four filters and up to eight inputs
They are offered in 7 packages ranging from 48 to 144 pins. The set of available peripherals
depends on the selected package. The STM32F413xG/H operate in the 40 to + 125 °C
temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of
power-saving mode allows the design of low-power applications.
Description STM32F413xG/H
14/208 DocID029162 Rev 6
These features make the STM32F413xG/H microcontrollers suitable for a wide range of
applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile phone sensor hub
Wearable devices
Connected objects
Wifi modules
DocID029162 Rev 6 15/208
STM32F413xG/H Description
42
Table 2. STM32F413xG/H features and peripheral counts
Peripherals STM32F413xG STM32F413xH
Flash memory (Kbyte) 1024 1536
SRAM
(Kbyte) System 320 (256 + 64) 320 (256 + 64)
Quad-SPI memory
interface -1-1
FSMC memory controller - 1(1) 1(1) 1(1) 1-1
(1) 1(1) 1(1) 1
FSMC LCD parallel
interface Data bus size -8 16 -8 16
Timers
General-
purpose 10(2) 10 10(3) 10 10(2) 10 10(3) 10
Advanced-
control 2(4) 22
(4) 2
Basic 2 2
Low-power
timer 11
Random number generator 1 1
Comm.
interfaces
SPI/ I2S 5/5 (2 full duplex) 5/5 (2 full duplex)
I2C3 3
I2CFMP 1 1
USART/
UART 3/3 4/3 4/6 3/3 4/3 4/6
SDIO/MMC 1 1
USB/OTG FS
Dual power rail
1
No
1
Yes
1
No
1
Yes
1
No
1
Yes
1
No
1
Yes
CAN 3 3
SAI 1 1
Number of digital Filters for
Sigma-delta modulator
Number of channels
66
711 12 711 12
GPIOs 36 50 60 81 114 36 50 60 81 114
12-bit ADC
Number of channels
11
10 16 10 16
12-bit DAC
Number of channels
Yes Yes
22
Maximum CPU frequency 100 MHz 100 MHz
Operating voltage 1.7 to 3.6 V 1.7 to 3.6 V
Operating temperatures
Ambient temperatures:
– 40 to +85 °C / – 40 to +105 °C / – 40 to +125 °C
Ambient temperatures:
– 40 to +85 °C / – 40 to +105 °C / – 40 to +125 °C
Junction temperature: –40 to + 130 °C Junction temperature: –40 to + 130 °C
Package UFQFPN
48
LQFP
64
WLCSP
81
UFBGA/
LQFP100
UFBGA/
LQFP144
UFQFPN
48 LQFP64 WLCSP
81
UFBGA/
LQFP100
UFBGA/
LQFP144
1. 64 pins package: support only 8 bits multiplexed mode interface
81 pins package: support 1 external memory of up to 64KB in multiplexed mode
100 pins: support 2 external memories of up to 64MB in multiplexed mode
Refer to Table 11: FSMC pin definition for more detailed information
2. 48 pins packages: TIM3 and TIM4: ETR pin not available.
3. 81 pins packages: TIM4: ETR pin not available.
4. 48 pins packages: TIM8:CH1, CH2, CH3 and CH4 pins not available.
Description STM32F413xG/H
16/208 DocID029162 Rev 6
2.1 Compatibility with STM32F4 series
The STM32F413xG/H are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F413xG/H can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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STM32F413xG/H Description
42
Figure 2. Compatible board design for LQFP64 package
Figure 3. Compatible board design for LQFP144 package
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Description STM32F413xG/H
18/208 DocID029162 Rev 6
Figure 4. STM32F413xG/H block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 50 MHz.
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DocID029162 Rev 6 19/208
STM32F413xG/H Functional overview
42
3 Functional overview
3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and
SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F413xG/H devices are compatible with all Arm tools and software.
Figure 4 shows the general block diagram of the STM32F413xG/H.
Note: Cortex®-M4 with FPU is binary compatible with Cortex®-M3.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 125 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 100 MHz.
3.3 Enhanced Batch Acquisition mode (eBAM)
The Batch acquisition mode allows enhanced power efficiency during data batching. It
enables data acquisition through any communication peripherals directly to memory using
the DMA in reduced power consumption as well as data processing while the rest of the
system is in low-power mode (including the Flash and ART). For example in an audio
system, a smart combination of PDM audio sample acquisition and processing from the
DFSDM directly to RAM (Flash and ART stopped) with the DMA using BAM followed by
some very short processing from Flash allows to drastically reduce the power consumption
of the application.
The BAM has been enhanced by adding SRAM2 that allows SRAM code to be executed
through the Ibus and Dbus, thus improving code execution performance.
Functional overview STM32F413xG/H
20/208 DocID029162 Rev 6
A dedicated application note (AN4515) describes how to implement the STM32F413xG/H
BAM to allow the best power efficiency.
3.4 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of
addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5 Embedded Flash memory
The devices embed up to 1.5 Mbytes of Flash memory available for storing programs and
data, plus 512 bytes of one-time programmable (OTP) memory organized in 16 blocks of
32 bytes, each which can be independently locked.
The user Flash memory area can be protected against read operations by an entrusted
code (read protection or RDP). Different protection levels are available. The user Flash
memory is divided into sectors, which can be individually protected against write operation.
Flash sectors can also be protected individually against D-bus read accesses by using the
proprietary readout protection (PCROP).
Refer to the product line reference manual for additional information on OTP area and
protection features.
To optimize the power consumption the Flash memory can also be switched off in Run or in
Sleep mode (see Section 3.20: Low-power modes).
Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between
power saving and startup time.
Before disabling the Flash, the code must be executed from the internal RAM.
3.6 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
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DocID029162 Rev 6 21/208
STM32F413xG/H Functional overview
42
3.7 Embedded SRAM
All devices embed 320 Kbytes of system SRAM which can be accessed (read/write) at CPU
clock speed with 0 wait states.
3.8 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 5. Multi-AHB matrix
CPU can access SRAM1 memory via S-bus, when SRAM1 is mapped at the address range:
0x2000 0000 to 0x2003 FFFF.
CPU can access SRAM2 memory via S-bus, when SRAM2 is mapped at the address range:
0x2004 0000 to 0x2004 FFFF.
CPU can access SRAM1 memory via I-bus and D-bus, when SRAM1 is remapped at
address 0x0000 0000 either by booting from RAM memory or by the remap mode.
CPU can access SRAM2 memory via I-bus and D-bus, when SRAM2 is mapped at the
address range: 0x1000 0000 to 0x1000 FFFF.
Performance boosts up, when the CPU access SRAM memory via the I-bus.
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Functional overview STM32F413xG/H
22/208 DocID029162 Rev 6
3.9 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
SPI and I2S
I2C and I2CFMP
USART
General-purpose, basic and advanced-control timers TIMx
SD/SDIO/MMC/eMMC host interface
Quad-SPI
ADC
DAC
Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter
SAI.
3.10 Flexible static memory controller (FSMC)
The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It
features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR
Flash memory.
The main functions are:
8-,16-bit data bus width
Write FIFO
Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
DocID029162 Rev 6 23/208
STM32F413xG/H Functional overview
42
3.11 Quad-SPI memory interface (QUAD-SPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode
through registers, external Flash status register polling mode and memory mapped mode.
Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or
32-bit mode. Code execution is also supported. The opcode and the frame format are fully
programmable. Communication can be performed either in single data rate or dual data
rate.
3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 102 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M4 with FPU.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
3.14 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
Functional overview STM32F413xG/H
24/208 DocID029162 Rev 6
buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the
low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.15 Boot modes
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash memory
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using one of the interface listed in the Table 3 or the USB OTG FS in device mode through
DFU (device firmware upgrade).
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
Table 3. Embedded bootloader interfaces
Package
USART1
PA9/
PA10
USART2
PD6/
PD5
USART3
PB11/
PB10
I2C1
PB6/
PB7
I2C2
PF0/
PF1
I2C3
PA8/
PB4
I2C
FMP1
PB14/
PB15
SPI1
PA4/
PA5/
PA6/
PA7
SPI3
PA15/
PC10/
PC11/
PC12
SPI4
PE11/
PE12/
PE13/
PE14
CAN2
PB5/
PB13
USB
PA11
/P12
UFQFPN48 Y - - Y - Y Y Y - - Y Y
LQFP64 Y - - Y - Y Y Y Y - Y Y
WLCSP81 Y - - Y - Y Y Y Y Y Y Y
LQFP100Y Y - Y-YYYYYYY
LQFP144YYYYYYYYYYYY
UFBGA100 Y Y Y Y - Y Y Y Y Y Y Y
UFBGA144 Y Y Y Y Y Y Y Y Y Y Y Y
DocID029162 Rev 6 25/208
STM32F413xG/H Functional overview
42
3.16 Power supply schemes
VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and NRST pins.
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with
decoupling technique.
Note: The VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply
supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF
and internal power supply supervisor availability to identify the packages supporting this
option.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8 V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
The following conditions VDDUSB must be respected:
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–V
DDUSB rising and falling time rate specifications must be respected.
In operating mode phase, VDDUSB could be lower or higher than VDD:
If USB is used, the associated GPIOs powered by VDDUSB are operating
between VDDUSB_MIN and VDDUSB_MAX.
If USB is not used, the associated GPIOs powered by VDDUSB are operating
between VDD_MIN and VDD_MAX.
DDUSB Mssvagaw
Functional overview STM32F413xG/H
26/208 DocID029162 Rev 6
Figure 6. VDDUSB connected to an external independent power supply
3.17 Power supply supervisor
3.17.1 Internal reset ON
This feature is available for VDD operating voltage range 1.8 V to 3.6 V.
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
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STM32F413xG/H Functional overview
42
3.17.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor VDD and should set the device in reset
mode when VDD is below 1.7 V. NRST should be connected to this external power supply
supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset
OFF.
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
VBAT functionality is no more available and VBAT pin should be connected to VDD.
3.18 Voltage regulator
The regulator has three operating modes:
Main regulator mode (MR)
Low power regulator (LPR)
– Power-down
Figure 7. Power supply supervisor interconnection with internal reset OFF(1)
1. The PRD_ON pin is available only on WLCSP81, UFBGA100, UFBGA144 and LQFP144 packages.
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Functional overview STM32F413xG/H
28/208 DocID029162 Rev 6
3.18.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
MR is used in the nominal regulation mode (With different voltage scaling in Run mode)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
LPR is used in the Stop mode
The LP regulator mode is configured by software when entering Stop mode.
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available on 100- and 144-pin
packages.
All packages have the regulator ON feature.
3.18.2 Regulator OFF
This feature is available only on UFBGA100 and UFBGA144 packages, which feature the
BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator
OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
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STM32F413xG/H Functional overview
42
Figure 8. Regulator OFF
The following conditions must be respected:
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.
CAP 2 VGA? 1 CAP 2 VGA? 1
Functional overview STM32F413xG/H
30/208 DocID029162 Rev 6
Figure 9. Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
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DocID029162 Rev 6 31/208
STM32F413xG/H Functional overview
42
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability
3.19 Real-time clock (RTC) and backup registers
The backup domain includes:
The real-time clock (RTC)
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 byte of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.20: Low-power
modes).
Table 4. Regulator ON/OFF and internal power supply supervisor availability
Package Regulator ON Regulator OFF Power supply
supervisor ON
Power supply
supervisor OFF
UFQFPN48 Yes No Yes No
LQFP64 Yes No Yes No
WLCSP81
Yes
BYPASS_REG
set to VSS
Yes
BYPASS_REG
set to VDD
Yes
PDR_ON
set to VDD
Yes
PDR_ON
set to VSS
LQFP100 Yes No Yes No
LQFP144 Yes No
Yes
PDR_ON
set to VDD
Yes
PDR_ON
set to VSS
UFBGA100
Yes
BYPASS_REG
set to VSS
Yes
BYPASS_REG
set to VDD
UFBGA144
Yes
BYPASS_REG
set to VSS
Yes
BYPASS_REG
set to VDD
Functional overview STM32F413xG/H
32/208 DocID029162 Rev 6
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
The RTC and backup registers are supplied through a switch that is powered either from the
VDD supply when present or from the VBAT pin.
3.20 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
To further reduce the power consumption, the Flash memory can be switched off
before entering in Sleep mode. Note that this requires a code execution from the RAM.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/
tamper/ time stamp events).
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp
event occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.
3.21 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
super-capacitor, or from VDD when no external battery and an external super-capacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC and the backup registers.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal
Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected
to VDD.
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STM32F413xG/H Functional overview
42
3.22 Timers and watchdogs
The devices embed two advanced-control timer, ten general-purpose timers, two basic
timers, one low-power timer, two watchdog timers and a SysTick timer.
All timer counters can be frozen in debug mode.
Table 5 compares the features of the advanced-control and general-purpose timers.
Table 5. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complemen-
tary output
Max.
interface
clock
(MHz)
Max.
timer
clock
(MHz)
Advance
d-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 Yes 100 100
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 50 100
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 50 100
TIM9 16-bit Up
Any
integer
between 1
and
65536
No 2 No 100 100
TIM10,
TIM11 16-bit Up
Any
integer
between 1
and
65536
No 1 No 100 100
TIM12 16-bit Up
Any
integer
between 1
and
65536
No 2 No 50 100
TIM13,
TIM14 16-bit Up
Any
integer
between 1
and
65536
No 1 No 50 100
Functional overview STM32F413xG/H
34/208 DocID029162 Rev 6
3.22.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator
multiplexed on 4 independent channels. They have complementary PWM outputs with
programmable inserted dead times. They can also be considered as complete general-
purpose timers. Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability
(0-100%).
The advanced-control timers can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.22.2 General-purpose timers (TIMx)
There are elven synchronizable general-purpose timers embedded in the STM32F413xG/H
(see Table 5 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F413xG/H devices include 4 full-featured general-purpose timers: TIM2.
TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four
Basic
timers
TIM6,
TIM7 16-bit Up
Any
integer
between 1
and
65536
Yes 0 No 50 100
Low-
power
timer
LPTIM1 16-bit Up Between
1 and 128 No 2 No 50 100
Table 5. Timer feature comparison (continued)
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complemen-
tary output
Max.
interface
clock
(MHz)
Max.
timer
clock
(MHz)
DocID029162 Rev 6 35/208
STM32F413xG/H Functional overview
42
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 15 input capture/output compare/PWMs
TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in
conjunction with the other general-purpose timers and TIM1 advanced-control timer via
the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM output.
TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation.
They are capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 4 hall-effect sensors.
TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and
TIM12 have two independent channels for input capture/output compare, PWM or one-
pulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 full-
featured general-purpose timers or used as simple time bases.
3.22.3 Basic timer (TIM6, TIM7)
TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request
generation.
3.22.4 Low-power timer (LPTIM1)
The low-power timer (LPTIM1) features an independent clock and runs in Stop mode if it is
clocked by LSE, LSI or by an external clock. LPTIM1 is able to wakeup the devices from
Stop mode.
The low-power timer main features are the following:
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one shot mode
Selectable software / hardware input trigger
Selectable clock source
Internal clock source: LSE, LSI, HSI or APB1 clock
External clock source over LPTIM1 input (working even with no internal clock
source running, used by the pulse counter application)
Programmable digital glitch filter
Encoder mode
Active in Stop mode.
3.22.5 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
Functional overview STM32F413xG/H
36/208 DocID029162 Rev 6
3.22.6 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.22.7 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.23 Inter-integrated circuit interface (I2C)
The devices feature up to four I2C bus interfaces which can operate in multimaster and
slave modes:
One I2C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to
400 kHz) modes and Fast-mode plus (up to 1 MHz).
Three I2C interfaces support the Standard mode (up to 100 KHz) and the Fast mode
(up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on
the complete solution, refer to the nearest STMicroelectronics sales office.
All I2C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave)
and embed a hardware CRC generation/verification.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 6).
3.24 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) as well as six universal asynchronous receiver
transmitters (UART4, UART5, UART7, UART8, UART9 and UART10).
These ten interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. USART1, USART6, UART9 and UART10 can
communicate at speeds up to 12.5 Mbit/s. The other interfaces communicate at up to
6.25 bit/s.
Table 6. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes 50 ns Programmable length from 1 to 15 I2C peripheral clocks
DocID029162 Rev 6 37/208
STM32F413xG/H Functional overview
42
USART1, USART2, USART3 and USART6 provide hardware management of the CTS and
RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
Table 7. USART feature comparison
USART
name
Standard
features
Modem
(RTS/CTS) LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud
rate in Mbit/s
(oversampling
by 16)
Max. baud
rate in Mbit/s
(oversampling
by 8)
APB
mapping
USART1 X X X X X X 6.25 12.5
APB2
(max.
100 MHz)
USART2 X X X X X X 3.12 6.25
APB1
(max.
50 MHz)
USART3 X X X X X X 3.12 6.25
APB1
(max.
50 MHz)
UART4 X - X - X - 3.12 6.25
APB1
(max.
50 MHz)
UART5 X - X - X - 3.12 6.25
APB1
(max.
50 MHz)
USART6 X X X X X X 6.25 12.5
APB2
(max.
100 MHz)
UART7 X - X - X - 3.12 6.25
APB1
(max.
50 MHz)
UART8 X - X - X - 3.12 6.25
APB1
(max.
50 MHz)
UART9 X - X - X - 6.25 12.5
APB2
(max.
100 MHz)
UART10 X - X - X - 6.25 12.5
APB2
(max.
100 MHz)
Functional overview STM32F413xG/H
38/208 DocID029162 Rev 6
3.25 Serial peripheral interface (SPI)
The devices feature five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and
SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interfaces can be configured to operate in TI mode for communications in master
mode and slave mode.
3.26 Inter-integrated sound (I2S)
Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be
operated in master or slave mode, in simplex communication mode, and full duplex mode
for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution
as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz
are supported. When either or both of the I2S interfaces is/are configured in master mode,
the master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency.
All I2Sx interfaces can be served by the DMA controller.
3.27 Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
3.28 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
Different sources can be selected for the I2S master clock of the APB1 and the I2S master
clock of the APB2. This gives the flexibility to work with two different audio sampling
frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI
clocks or an external clock provided through a pin (external PLL or CODEC output)
DocID029162 Rev 6 39/208
STM32F413xG/H Functional overview
42
Different sources can also be selected for the SAI. The different possible sources are the
main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin
(external PLL or CODEC output).
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
3.29 Digital filter for sigma-delta modulators (DFSDM)
The device embeds two DFSDMs:
DFSDM1 has 2 digital filters modules and 4 external input serial channels
(transceivers) or alternately 2 internal parallel inputs support.
DFSDM2 features 4 digital filters modules and 8 external input serial channels
(transceivers) or alternately 4 internal parallel inputs support.
The amount of filters defines the number of conversions which can be performed
simultaneously.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. It is also possible to introduce a programmable delay between different
microphones (beamforming feature). DFSDM features optional parallel data stream inputs
from microcontrollers memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
3.30 Dynamic tuning of PDM delays for sound source localization
A mechanism is implemented on top of the DFSDM allowing to dynamically tune PDM
delays of each microphone without the need to add external delay lines.
Audio application with several microphones require strong microphones placement
constraints, as the distance between the microphones must be a multiple of v/F where v is
the speed of the sound and F is the PCM sampling frequency.
The designed mechanism removes this constraint by programming delays for each digital
microphone with the granularity of the PDM clock rate prior to the conversion into PCM rate.
The tuning delay is performed by a clock skipping technique.
Table 8. DFSDM feature comparison
DFSDM instance External input serial
channels
External input parallel
channels Digital filters
DFSDM1 4 2 2
DFSDM2 8 4 4
Functional overview STM32F413xG/H
40/208 DocID029162 Rev 6
The strong benefits of such mechanism coupled with DFSDM are:
Possibility to place the digital microphones close to each other
No need for external delay lines
The delay tuning is done in hardware, preventing the use of MIPs crunching algorithms
Possibility to change the delay tuning on the fly
The low power consumption and CPU time released due to the DFSDM hardware PDM
to PCM conversion
The impacted audio application are beam forming and sound source localization
3.31 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.32 Controller area network (bxCAN)
The three CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2, and 512 bytes for
CAN3.
3.33 Universal serial bus on-the-go full-speed (USB_OTG_FS)
The devices embed a USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with USB 2.0 and OTG 1.0
specifications. It features software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock,
which is generated by a PLL connected to the HSE oscillator. The Battery Charging
Detection (BCD) can detect and identify the type of port it is connected to (standard USB or
charger). The charging type can also be detected: Dedicated Charging Port (DCP),
Charging Downstream Port (CDP) and Standard Downstream Port (SDP).
Some packages provide a dedicated USB power rail allowing to supply the USB from a
different voltage that the rest of the device. As an example, the device can be powered with
the minimum specified supply voltage while the USB runs at the level defined by the
standard.
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STM32F413xG/H Functional overview
42
The main USB OTG FS features are:
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Support of session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed when bus-powered devices are
connected
Link Power Management (LPM)
Battery Charging Detection (BCD) supporting DCP, CDP and SDP
3.34 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.35 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 100 MHz.
3.36 Analog-to-digital converter (ADC)
One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4 or TIM5 timer.
3.37 Digital to analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This digital interface supports the following features:
Two DAC output channels
Functional overview STM32F413xG/H
42/208 DocID029162 Rev 6
8-bit or 12-bit output mode
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Input voltage reference (VREF+)
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA channels.
3.38 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN18 input channel which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.39 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.40 Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F413xG/H through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID029162 Rev 6 43/208
STM32F413xG/H Pinouts and pin description
73
4 Pinouts and pin description
4.1 WLCSP81 pinout description
Figure 11. STM32F413xG/H WLCSP81 pinout
1. The above figure shows the package top view.
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Pinouts and pin description STM32F413xG/H
44/208 DocID029162 Rev 6
4.2 UFQFPN48 pinout description
Figure 12. STM32F413xG/H UFQFPN48 pinout
1. The above figure shows the package top view.
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DocID029162 Rev 6 45/208
STM32F413xG/H Pinouts and pin description
73
4.3 LQFP64 pinout description
Figure 13. STM32F413xG/H LQFP64 pinout
1. The above figure shows the package top view.
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Pinouts and pin description STM32F413xG/H
46/208 DocID029162 Rev 6
4.4 LQFP100 pinout description
Figure 14. STM32F413xG/H LQFP100 pinout
1. The above figure shows the package top view.
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DocID029162 Rev 6 47/208
STM32F413xG/H Pinouts and pin description
73
4.5 LQFP144 pinout description
Figure 15. STM32F413xG/H LQFP144 pinout
1. The above figure shows the package top view.
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4.6 UFBGA100 pinout description
Figure 16. STM32F413xG/H UFBGA100 pinout
1. The above figure shows the package top view.
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3+
26&B
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3+
26&B
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DocID029162 Rev 6 49/208
STM32F413xG/H Pinouts and pin description
73
4.7 UFBGA144 pinout description
Figure 17. STM32F413xG/H UFBGA144 pinout
1. The above figure shows the package top view.
4.8 Pins definition
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3) %227 3% 3*
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Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input/ output pin
I/O structure
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, I2C FM+ option
TC Standard 3.3 V I/O
TTa 3.3 V tolerant I/O directly connected to DAC
B Dedicated BOOT0 pin
NRST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Pinouts and pin description STM32F413xG/H
50/208 DocID029162 Rev 6
Alternate functions Functions selected through GPIOx_AFR registers
Additional functions Functions directly selected/enabled through peripheral registers
Table 9. Legend/abbreviations used in the pinout table (continued)
Name Abbreviation Definition
Table 10. STM32F413xG/H pin definition
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
- - NC 1 B2 A3 1 PE2 I/O FT (2)
TRACECLK,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
UART10_RX,
FSMC_A23,
EVENTOUT
-
- - NC 2 A1 A2 2 PE3 I/O FT (2)
TRACED0, SAI1_SD_B,
UART10_TX,
FSMC_A19,
EVENTOUT
-
- - NC 3 B1 B2 3 PE4 I/O FT (2)(3)
TRACED1,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
SAI1_SD_A,
DFSDM1_DATIN3,
FSMC_A20,
EVENTOUT
-
- - NC 4 C2 B3 4 PE5 I/O FT (2)
TRACED2, TIM9_CH1,
SPI4_MISO,
SPI5_MISO,
SAI1_SCK_A,
DFSDM1_CKIN3,
FSMC_A21,
EVENTOUT
-
- - NC 5 D2 B4 5 PE6 I/O FT (2)(3)
TRACED3, TIM9_CH2,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
SAI1_FS_A,
FSMC_A22,
EVENTOUT
-
1 1 B9 6 E2 C2 6 VBAT S - - - VBAT
22C8 7 C1 A1 7 PC13-
ANTI_TAMP I/O FT (4)(5) EVENTOUT TAMP_1
33C9 8 D1 B1 8 PC14-
OSC32_IN I/O FT (4)(5)(6) EVENTOUT OSC32_IN
DocID029162 Rev 6 51/208
STM32F413xG/H Pinouts and pin description
73
44D9 9 E1 C1 9 PC15-
OSC32_OUT I/O FT (4)(6) EVENTOUT OSC32_OUT
--- - - C310 PF0 I/O FT - I2C2_SDA, FSMC_A0,
EVENTOUT -
--- - - C411 PF1 I/O FT - I2C2_SCL, FSMC_A1,
EVENTOUT -
--- - - D412 PF2 I/O FT - I2C2_SMBA, FSMC_A2,
EVENTOUT -
--- - - E213 PF3 I/O FT - TIM5_CH1, FSMC_A3,
EVENTOUT -
--- - - E314 PF4 I/O FT - TIM5_CH2, FSMC_A4,
EVENTOUT -
--- - - E415 PF5 I/O FT - TIM5_CH3, FSMC_A5,
EVENTOUT -
- - D8 10 F2 D2 16 VSS S - - - -
- - E8 11 G2 D3 17 VDD S - - - -
--- - - F318 PF6 I/O FT -
TRACED0, TIM10_CH1,
SAI1_SD_B,
UART7_Rx,
QUADSPI_BK1_IO3,
EVENTOUT
-
--- - - F219 PF7 I/O FT -
TRACED1, TIM11_CH1,
SAI1_MCLK_B,
UART7_Tx,
QUADSPI_BK1_IO2,
EVENTOUT
-
--- - - G320 PF8 I/O FT -
SAI1_SCK_B,
UART8_RX,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
-
--- - - G221 PF9 I/O FT -
SAI1_FS_B,
UART8_TX,
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
-
--- - - G122 PF10 I/O FT - TIM1_ETR, TIM5_CH4,
EVENTOUT -
5 5 E9 12 F1 D1 23 PH0 - OSC_IN I/O FT (6) EVENTOUT OSC_IN
6 6 F9 13 G1 E1 24 PH1 -
OSC_OUT I/O FT (6) EVENTOUT OSC_OUT
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F413xG/H
52/208 DocID029162 Rev 6
7 7 G9 14 H2 F1 25 NRST I/O RST - - NRST
- 8 F8 15 H1 H1 26 PC0 I/O FT -
LPTIM1_IN1,
DFSDM2_CKIN4,
SAI1_MCLK_B,
EVENTOUT
ADC1_IN10,
WKUP2
- 9 C7 16 J2 H2 27 PC1 I/O FT -
LPTIM1_OUT,
DFSDM2_DATIN4,
SAI1_SD_B,
EVENTOUT
ADC1_IN11,
WKUP3
-10D717 J3 H3 28 PC2 I/O FT -
LPTIM1_IN2,
DFSDM2_DATIN7,
SPI2_MISO,
I2S2ext_SD,
SAI1_SCK_B,
DFSDM1_CKOUT,
FSMC_NWE,
EVENTOUT
ADC1_IN12
-11E718 K2 H4 29 PC3 I/O FT -
LPTIM1_ETR,
DFSDM2_CKIN7,
SPI2_MOSI/I2S2_SD,
SAI1_FS_B, FSMC_A0,
EVENTOUT
ADC1_IN13
---19 - - 30 VDD S - - - -
8 12 H9 20 J1 J1 31 VSSA S - - - -
--- - K1K1 - VREF- S - - - -
- - G8 21 L1 L1 32 VREF+ S - - - -
9 13 F7 22 M1 M1 33 VDDA S - - - -
10 14 G7 23 L2 J2 34 PA0 I/O FT -
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX, EVENTOUT
ADC1_IN0,
WKUP1
11 15 H8 24 M2 K2 35 PA1 I/O FT -
TIM2_CH2, TIM5_CH2,
SPI4_MOSI/I2S4_SD,
USART2_RTS,
UART4_RX,
QUADSPI_BK1_IO3,
EVENTOUT
ADC1_IN1
12 16 J9 25 K3 L2 36 PA2 I/O FT -
TIM2_CH3, TIM5_CH3,
TIM9_CH1, I2S2_CKIN,
USART2_TX,
FSMC_D4/FSMC_DA4,
EVENTOUT
ADC1_IN2
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID029162 Rev 6 53/208
STM32F413xG/H Pinouts and pin description
73
13 17 E6 26 L3 M2 37 PA3 I/O FT -
TIM2_CH4, TIM5_CH4,
TIM9_CH2, I2S2_MCK,
USART2_RX,
SAI1_SD_B,
FSMC_D5/FSMC_DA5,
EVENTOUT
ADC1_IN3
- 18 H7 27 - - 38 VSS S - - - -
--F6- E3H5 - BYPASS_
REG IFT - - -
-19J8 28 - F4 39 VDD S - - - -
14 20 E5 29 M3 J3 40 PA4 I/O TTa -
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
DFSDM1_DATIN1,
FSMC_D6/FSMC_DA6,
EVENTOUT
ADC1_IN4,
DAC_OUT1
15 21 G6 30 K4 K3 41 PA5 I/O TTa -
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
DFSDM1_CKIN1,
FSMC_D7/FSMC_DA7,
EVENTOUT
ADC1_IN5,
DAC_OUT2
16 22 F5 31 L4 L3 42 PA6 I/O FT -
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO, I2S2_MCK,
DFSDM2_CKIN1,
TIM13_CH1,
QUADSPI_BK2_IO0,
SDIO_CMD,
EVENTOUT
ADC1_IN6
17 23 J7 32 M4 M3 43 PA7 I/O FT -
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
DFSDM2_DATIN1,
TIM14_CH1,
QUADSPI_BK2_IO1,
EVENTOUT
ADC1_IN7
-24H633 K5 J4 44 PC4 I/O FT -
DFSDM2_CKIN2,
I2S1_MCK,
QUADSPI_BK2_IO2,
FSMC_NE4,
EVENTOUT
ADC1_IN14
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F413xG/H
54/208 DocID029162 Rev 6
-25J6 34 L5 K4 45 PC5 I/O FT -
DFSDM2_DATIN2,
I2CFMP1_SMBA,
USART3_RX,
QUADSPI_BK2_IO3,
FSMC_NOE,
EVENTOUT
ADC1_IN15
18 26 E4 35 M5 L4 46 PB0 I/O FT -
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
SPI5_SCK/I2S5_CK,
EVENTOUT
ADC1_IN8
19 27 G5 36 M6 M4 47 PB1 I/O FT -
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
SPI5_NSS/I2S5_WS,
DFSDM1_DATIN0,
QUADSPI_CLK,
EVENTOUT
ADC1_IN9
20 28 H5 37 L6 J5 48 PB2 I/O FT -
LPTIM1_OUT,
DFSDM1_CKIN0,
QUADSPI_CLK,
EVENTOUT
BOOT1
- - - - - M5 49 PF11 I/O FT - TIM8_ETR, EVENTOUT -
--- - - L550 PF12 I/O FT - TIM8_BKIN, FSMC_A6,
EVENTOUT -
- - - - - G4 51 VSS S - - - -
--- - - G552 VDD S - - - -
--- - - K553 PF13 I/O FT - I2CFMP1_SMBA,
FSMC_A7, EVENTOUT -
- - - - - M6 54 PF14 I/O FTf - I2CFMP1_SCL,
FSMC_A8, EVENTOUT -
- - - - - L6 55 PF15 I/O FTf - I2CFMP1_SDA,
FSMC_A9, EVENTOUT -
--- - - K656 PG0 I/O FT -
CAN1_RX, UART9_RX,
FSMC_A10,
EVENTOUT
-
--- - - J657 PG1 I/O FT - CAN1_TX, UART9_TX,
FSMC_A11, EVENTOUT -
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID029162 Rev 6 55/208
STM32F413xG/H Pinouts and pin description
73
- - NC 38 M7 M7 58 PE7 I/O FT (2)
TIM1_ETR,
DFSDM1_DATIN2,
UART7_Rx,
QUADSPI_BK2_IO0,
FSMC_D4/FSMC_DA4,
EVENTOUT
-
- - NC 39 L7 L7 59 PE8 I/O FT (2)
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_Tx,
QUADSPI_BK2_IO1,
FSMC_D5/FSMC_DA5,
EVENTOUT
-
- - J5 40 M8 K7 60 PE9 I/O FT -
TIM1_CH1,
DFSDM1_CKOUT,
QUADSPI_BK2_IO2,
FSMC_D6/FSMC_DA6,
EVENTOUT
-
- - - - - H6 61 VSS S - - - -
--- - - G662 VDD S - - - -
- - G4 41 L8 J7 63 PE10 I/O FT -
TIM1_CH2N,
DFSDM2_DATIN0,
QUADSPI_BK2_IO3,
FSMC_D7/FSMC_DA7,
EVENTOUT
-
- - H4 42 M9 H8 64 PE11 I/O FT -
TIM1_CH2,
DFSDM2_CKIN0,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
FSMC_D8/FSMC_DA8,
EVENTOUT
-
- - J4 43 L9 J8 65 PE12 I/O FT -
TIM1_CH3N,
DFSDM2_DATIN7,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
FSMC_D9/FSMC_DA9,
EVENTOUT
-
- - F4 44 M10 K8 66 PE13 I/O FT -
TIM1_CH3,
DFSDM2_CKIN7,
SPI4_MISO,
SPI5_MISO,
FSMC_D10/FSMC_DA1
0, EVENTOUT
-
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F413xG/H
56/208 DocID029162 Rev 6
- - G3 45 M11 L8 67 PE14 I/O FT -
TIM1_CH4,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
DFSDM2_DATIN1,
FSMC_D11/FSMC_DA1
1, EVENTOUT
-
- - J3 46 M12 M8 68 PE15 I/O FT -
TIM1_BKIN,
DFSDM2_CKIN1,
FSMC_D12/FSMC_DA1
2, EVENTOUT
-
21 29 H3 47 L10 M9 69 PB10 I/O FTf -
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
USART3_TX,
I2CFMP1_SCL,
DFSDM2_CKOUT,
SDIO_D7, EVENTOUT
-
- - NC - K9 M10 70 PB11 I/O FT -
TIM2_CH4, I2C2_SDA,
I2S2_CKIN,
USART3_RX,
EVENTOUT
-
22 30 H2 48 L11 H7 71 VCAP_1 S - - - -
23 31 J2 49 F12 - - VSS S - - - -
24 32 J1 50 G12 G7 72 VDD S - - - -
25 33 F3 51 L12 M11 73 PB12 I/O FT -
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SPI4_NSS/I2S4_WS,
SPI3_SCK/I2S3_CK,
USART3_CK,
CAN2_RX,
DFSDM1_DATIN1,
UART5_RX,
FSMC_D13/FSMC_DA1
3, EVENTOUT
-
26 34 G2 52 K12 M12 74 PB13 I/O FT -
TIM1_CH1N,
I2CFMP1_SMBA,
SPI2_SCK/I2S2_CK,
SPI4_SCK/I2S4_CK,
USART3_CTS,
CAN2_TX,
DFSDM1_CKIN1,
UART5_TX, EVENTOUT
-
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID029162 Rev 6 57/208
STM32F413xG/H Pinouts and pin description
73
27 35 E3 53 K11 L11 75 PB14 I/O FTf -
TIM1_CH2N,
TIM8_CH2N,
I2CFMP1_SDA,
SPI2_MISO,
I2S2ext_SD,
USART3_RTS,
DFSDM1_DATIN2,
TIM12_CH1,
FSMC_D0/FSMC_DA0,
SDIO_D6, EVENTOUT
-
28 36 H1 54 K10 L12 76 PB15 I/O FTf -
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
I2CFMP1_SCL,
SPI2_MOSI/I2S2_SD,
DFSDM1_CKIN2,
TIM12_CH2, SDIO_CK,
EVENTOUT
-
--NC55 - L977 PD8 I/O FT (2)
USART3_TX,
FSMC_D13/FSMC_DA1
3, EVENTOUT
-
- - F2 56 K8 K9 78 PD9 I/O FT -
USART3_RX,
FSMC_D14/FSMC_DA1
4, EVENTOUT
-
--G157J12J979 PD10 I/O FT (7)
USART3_CK,
UART4_TX,
FSMC_D15/FSMC_DA1
5, EVENTOUT
-
--NC58J11H980 PD11 I/O FT (2)
DFSDM2_DATIN2,
I2CFMP1_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
FSMC_A16,
EVENTOUT
-
- - NC 59 J10 L10 81 PD12 I/O FTf (2)
TIM4_CH1,
DFSDM2_CKIN2,
I2CFMP1_SCL,
USART3_RTS,
QUADSPI_BK1_IO1,
FSMC_A17,
EVENTOUT
-
- - NC 60 H12 K10 82 PD13 I/O FTf (2)
TIM4_CH2,
I2CFMP1_SDA,
QUADSPI_BK1_IO3,
FSMC_A18,
EVENTOUT
-
- - - - - G8 83 VSS S - - - -
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F413xG/H
58/208 DocID029162 Rev 6
--- - - F884 VDD S - - - -
- - NC 61 H11 K11 85 PD14 I/O FTf (2)
TIM4_CH3,
I2CFMP1_SCL,
DFSDM2_CKIN0,
UART9_RX,
FSMC_D0/FSMC_DA0,
EVENTOUT
-
- - NC 62 H10 K12 86 PD15 I/O FTf (2)
TIM4_CH4,
I2CFMP1_SDA,
DFSDM2_DATIN0,
UART9_TX,
FSMC_D1/FSMC_DA1,
EVENTOUT
-
- - - - - J12 87 PG2 I/O FT - FSMC_A12,
EVENTOUT -
--- - - J1188 PG3 I/O FT - FSMC_A13,
EVENTOUT -
- - - - - J10 89 PG4 I/O FT - FSMC_A14,
EVENTOUT -
- - - - - H12 90 PG5 I/O FT - FSMC_A15,
EVENTOUT -
-- - - - H1191 PG6 I/O FT - QUADSPI_BK1_NCS,
EVENTOUT -
- - - - - H10 92 PG7 I/O FT - USART6_CK,
EVENTOUT -
--- - -G1193 PG8 I/O FT - USART6_RTS,
EVENTOUT -
- - - - - - 94 VSS S - - - -
-- - - - F10- VDD S - - - -
- - F1 - - C11 95 VDDUSB S - - - -
-37D563E12G1296 PC6 I/O FTf -
TIM3_CH1, TIM8_CH1,
I2CFMP1_SCL,
I2S2_MCK,
DFSDM1_CKIN3,
DFSDM2_DATIN6,
USART6_TX,
FSMC_D1/FSMC_DA1,
SDIO_D6, EVENTOUT
-
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID029162 Rev 6 59/208
STM32F413xG/H Pinouts and pin description
73
-38D464E11F1297 PC7 I/O FTf -
TIM3_CH2, TIM8_CH2,
I2CFMP1_SDA,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
DFSDM2_CKIN6,
USART6_RX,
DFSDM1_DATIN3,
SDIO_D7, EVENTOUT
-
-39E165E10F1198 PC8 I/O FT -
TIM3_CH3, TIM8_CH3,
DFSDM2_CKIN3,
USART6_CK,
QUADSPI_BK1_IO2,
SDIO_D0, EVENTOUT
-
-40E266D12E1199 PC9 I/O FT -
MCO_2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S2_CKIN,
DFSDM2_DATIN3,
QUADSPI_BK1_IO0,
SDIO_D1, EVENTOUT
-
29 41 D3 67 D11 E12 100 PA8 I/O FT -
MCO_1, TIM1_CH1,
I2C3_SCL,
DFSDM1_CKOUT,
USART1_CK,
UART7_RX,
USB_FS_SOF,
CAN3_RX, SDIO_D1,
EVENTOUT
-
30 42 D2 68 D10 D12 101 PA9 I/O FT -
TIM1_CH2,
DFSDM2_CKIN3,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
USB_FS_VBUS,
SDIO_D2, EVENTOUT
-
31 43 D1 69 C12 D11 102 PA10 I/O FT -
TIM1_CH3,
DFSDM2_DATIN3,
SPI2_MOSI/I2S2_SD,
SPI5_MOSI/I2S5_SD,
USART1_RX,
USB_FS_ID,
EVENTOUT
-
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F413xG/H
60/208 DocID029162 Rev 6
32 44 C3 70 B12 C12 103 PA11 I/O FT -
TIM1_CH4,
DFSDM2_CKIN5,
SPI2_NSS/I2S2_WS,
SPI4_MISO,
USART1_CTS,
USART6_TX,
CAN1_RX,
USB_FS_DM,
UART4_RX,
EVENTOUT
-
33 45 B3 71 A12 B12 104 PA12 I/O FT -
TIM1_ETR,
DFSDM2_DATIN5,
SPI2_MISO,
SPI5_MISO,
USART1_RTS,
USART6_RX,
CAN1_TX, USB_FS_DP,
UART4_TX, EVENTOUT
-
34 46 C2 72 A11 A12 105 PA13 I/O FT - JTMS-SWDIO,
EVENTOUT -
- - C1 73 C11 G9 106 VCAP_2 S - - - -
35 47 B1 74 F11 G10 107 VSS S - - - -
-48 - 75G11 - - VDD S - - - -
36 - A1 - - F9 108 VDD S - - - -
37 49 B2 76 A10 A11 109 PA14 I/O FT - JTCK-SWCLK,
EVENTOUT -
38 50 A3 77 A9 A10 110 PA15 I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART1_TX,
UART7_TX,
SAI1_MCLK_A,
CAN3_TX, EVENTOUT
-
- 51 A2 78 B11 B11 111 PC10 I/O FT -
DFSDM2_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
QUADSPI_BK1_IO1,
SDIO_D2, EVENTOUT
-
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID029162 Rev 6 61/208
STM32F413xG/H Pinouts and pin description
73
- 52 C4 79 C10 B10 112 PC11 I/O FT -
DFSDM2_DATIN5,
I2S3ext_SD,
SPI3_MISO,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
FSMC_D2/FSMC_DA2,
SDIO_D3, EVENTOUT
-
- 53 B4 80 B10 C10 113 PC12 I/O FT -
SPI3_MOSI/I2S3_SD,
USART3_CK,
UART5_TX,
FSMC_D3/FSMC_DA3,
SDIO_CK, EVENTOUT
-
- - A4 81 C9 E10 114 PD0 I/O FT -
DFSDM2_CKIN6,
CAN1_RX, UART4_RX,
FSMC_D2/FSMC_DA2,
EVENTOUT
-
- - NC 82 B9 D10 115 PD1 I/O FT (2)
DFSDM2_DATIN6,
CAN1_TX, UART4_TX,
FSMC_D3/FSMC_DA3,
EVENTOUT
-
-54C583 C8 E9116 PD2 I/O FT -
TIM3_ETR,
DFSDM2_CKOUT,
UART5_RX,
FSMC_NWE,
SDIO_CMD,
EVENTOUT
-
- - NC 84 B8 D9 117 PD3 I/O FT (2)
TRACED1,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN0,
USART2_CTS,
QUADSPI_CLK,
FSMC_CLK,
EVENTOUT
-
- - NC 85 B7 C9 118 PD4 I/O FT (2)
DFSDM1_CKIN0,
USART2_RTS,
FSMC_NOE,
EVENTOUT
-
--NC86A6B9119 PD5 I/O FT (2)
DFSDM2_CKOUT,
USART2_TX,
FSMC_NWE,
EVENTOUT
-
- - - - - E7 120 VSS S - - - -
- - - - - F7 121 VDD S - - - -
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F413xG/H
62/208 DocID029162 Rev 6
- - NC 87 B6 A8 122 PD6 I/O FT (2)
SPI3_MOSI/I2S3_SD,
DFSDM1_DATIN1,
USART2_RX,
FSMC_NWAIT,
EVENTOUT
-
- - NC 88 A5 A9 123 PD7 I/O FT (2)
DFSDM1_CKIN1,
USART2_CK,
FSMC_NE1,
EVENTOUT
-
- - - - - E8 124 PG9 I/O FT -
USART6_RX,
QUADSPI_BK2_IO2,
FSMC_NE2,
EVENTOUT
-
- - - - - D8 125 PG10 I/O FT - FSMC_NE3,
EVENTOUT -
- - - - - C8 126 PG11 I/O FT -
CAN2_RX,
UART10_RX,
EVENTOUT
-
- - - - - B8 127 PG12 I/O FT -
USART6_RTS,
CAN2_TX, UART10_TX,
FSMC_NE4,
EVENTOUT
-
- - - - - D7 128 PG13 I/O FT -
TRACED2,
USART6_CTS,
FSMC_A24,
EVENTOUT
-
- - - - - C7 129 PG14 I/O FT -
TRACED3,
USART6_TX,
QUADSPI_BK2_IO3,
FSMC_A25,
EVENTOUT
-
- - - - - - 130 VSS S - - - -
- - - - - F6 131 VDD S - - - -
- - - - - B7 132 PG15 I/O FT - USART6_CTS,
EVENTOUT -
39 55 A5 89 A8 A7 133 PB3 I/O FTf -
JTDO-SWO, TIM2_CH2,
I2CFMP1_SDA,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
USART1_RX,
UART7_RX, I2C2_SDA,
SAI1_SD_A, CAN3_RX,
EVENTOUT
-
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
DocID029162 Rev 6 63/208
STM32F413xG/H Pinouts and pin description
73
40 56 B5 90 A7 A6 134 PB4 I/O FT -
JTRST, TIM3_CH1,
SPI1_MISO,
SPI3_MISO,
I2S3ext_SD,
UART7_TX, I2C3_SDA,
SAI1_SCK_A,
CAN3_TX, SDIO_D0,
EVENTOUT
-
41 57 A6 91 C5 B6 135 PB5 I/O FT -
LPTIM1_IN1,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
CAN2_RX, SAI1_FS_A,
UART5_RX, SDIO_D3,
EVENTOUT
-
42 58 B6 92 B5 C6 136 PB6 I/O FT -
LPTIM1_ETR,
TIM4_CH1, I2C1_SCL,
DFSDM2_CKIN7,
USART1_TX, CAN2_TX,
QUADSPI_BK1_NCS,
UART5_TX, SDIO_D0,
EVENTOUT
-
43 59 B7 93 B4 D6 137 PB7 I/O FT -
LPTIM1_IN2,
TIM4_CH2, I2C1_SDA,
DFSDM2_DATIN7,
USART1_RX,
FSMC_NL, EVENTOUT
-
44 60 A7 94 A4 D5 138 BOOT0 I B - - VPP
45 61 C6 95 A3 C5 139 PB8 I/O FT -
LPTIM1_OUT,
TIM4_CH3, TIM10_CH1,
I2C1_SCL,
SPI5_MOSI/I2S5_SD,
DFSDM2_CKIN1,
CAN1_RX, I2C3_SDA,
UART5_RX, SDIO_D4,
EVENTOUT
-
46 62 D6 96 B3 B5 140 PB9 I/O FT -
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
DFSDM2_DATIN1,
CAN1_TX, I2C2_SDA,
UART5_TX, SDIO_D5,
EVENTOUT
-
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Pinouts and pin description STM32F413xG/H
64/208 DocID029162 Rev 6
- - NC 97 C3 A5 141 PE0 I/O FT (2)
TIM4_ETR,
DFSDM2_CKIN4,
UART8_Rx,
FSMC_NBL0,
EVENTOUT
-
- - NC 98 A2 A4 142 PE1 I/O FT (2)
DFSDM2_DATIN4,
UART8_Tx,
FSMC_NBL1,
EVENTOUT
-
47 63 A8 99 D3 E6 - VSS S - - - -
- - B8 - H3 E5 143 PDR_ON I FT - - -
48 64 A9 100 C4 F5 144 VDD S - - - -
1. Function availability depends on the chosen device.
2. NC (Not Connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid extra power consumption in low power mode.
3. Compatibility issue on alternate function pin PE4 SAI1_SD_A and PE6 SAI1_FS_A: Pins have been swapped versus other
MCUs supporting those alternate SAI functions on those pins
4. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F413/423 reference manual.
6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
7. Incompatibility issue on alternate function with other MCUs supporting UART4: UART4_TX wrongly mapped to PD10
instead of PC10
Table 10. STM32F413xG/H pin definition (continued)
Pin Number
Pin name
(function
after
reset)(1)
Pin
type
I/O
structure Notes Alternate functions Additional
functions
UFQFPN48
LQFP64
WLCSP81
LQFP100
UFBGA100
UFBGA144
LQFP144
Table 11. FSMC pin definition
Pins
FSMC
64 pins 81 pins 100 pins 144 pins
LCD/NOR/
PSRAM/SRAM
NOR/PSRAM
Mux
PE2 A23 A23 - - Yes Yes
PE3 A19 A19 - - Yes Yes
PE4 A20 A20 - - Yes Yes
PE5 A21 A21 - - Yes Yes
PE6 A22 A22 - - Yes Yes
PF0 A0 - - - - Yes
DocID029162 Rev 6 65/208
STM32F413xG/H Pinouts and pin description
73
PF1 A1 - - - - Yes
PF2 A2 - - - - Yes
PF3 A3 - - - - Yes
PF4 A4 - - - - Yes
PF5 A5 - - - - Yes
PC2 NWE NWE Yes Yes Yes Yes
PC3 A0 - Yes Yes Yes Yes
PA2 D4 DA4 Yes Yes Yes Yes
PA3 D5 DA5 Yes Yes Yes Yes
PA4 D6 DA6 Yes Yes Yes Yes
PA5 D7 DA7 Yes Yes Yes Yes
PC4 NE4 NE4 Yes Yes Yes Yes
PC5 NOE NOE Yes Yes Yes Yes
PF12 A6 - - - - Yes
PF13 A7 - - - - Yes
PF14 A8 - - - - Yes
PF15 A9 - - - - Yes
PG0 A10 - - - - Yes
PG1 A11 - - - - Yes
PE7 D4 DA4 - - Yes Yes
PE8 D5 DA5 - - Yes Yes
PE9 D6 DA6 - Yes Yes Yes
PE10 D7 DA7 - Yes Yes Yes
PE11 D8 DA8 - Yes Yes Yes
PE12 D9 DA9 - Yes Yes Yes
PE13 D10 DA10 - Yes Yes Yes
PE14 D11 DA11 - Yes Yes Yes
PE15 D12 DA12 - Yes Yes Yes
PB12 D13 DA13 Yes Yes Yes Yes
PB14 D0 DA0 Yes Yes Yes Yes
PD8 D13 DA13 - - - Yes
PD9 D14 DA14 - Yes Yes Yes
PD10 D15 DA15 - Yes Yes Yes
Table 11. FSMC pin definition (continued)
Pins
FSMC
64 pins 81 pins 100 pins 144 pins
LCD/NOR/
PSRAM/SRAM
NOR/PSRAM
Mux
Pinouts and pin description STM32F413xG/H
66/208 DocID029162 Rev 6
PD11 A16 A16 - - Yes Yes
PD12 A17 A17 - - Yes Yes
PD13 A18 A18 - - Yes Yes
PD14 D0 DA0 - - Yes Yes
PD15 D1 DA1 - - Yes Yes
PG2 A12 - - - - Yes
PG3 A13 - - - - Yes
PG4 A14 - - - - Yes
PG5 A15 - - - - Yes
PC6 D1 DA1 Yes Yes Yes Yes
PC11 D2 DA2 Yes Yes Yes Yes
PC12 D3 DA3 Yes Yes Yes Yes
PD0 D2 DA2 - Yes Yes Yes
PD1 D3 DA3 - - Yes Yes
PD2 NWE NWE Yes Yes Yes Yes
PD3 CLK CLK - - Yes Yes
PD4 NOE NOE - - Yes Yes
PD5 NWE NWE - - Yes Yes
PD6 NWAIT NWAIT - - Yes Yes
PD7 NE1 NE1 - - Yes Yes
PG9 NE2 NE2 - - - Yes
PG10 NE3 NE3 - - - Yes
PG12 NE4 NE4 - - - Yes
PG13 A24 A24 - - - Yes
PG14 A25 A25 - - - Yes
PB7 NL NL Yes Yes Yes Yes
PE0 NBL0 NBL0 - - Yes Yes
PE1 NBL1 NBL1 - - Yes Yes
Table 11. FSMC pin definition (continued)
Pins
FSMC
64 pins 81 pins 100 pins 144 pins
LCD/NOR/
PSRAM/SRAM
NOR/PSRAM
Mux
Pinouts and pin description STM32F413xG/H
67/208 DocID029162 Rev 6
4.9 Alternate functions
Table 12. STM32F413xG/H alternate functions
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_
AF
TIM1/2/
LPTIM1 TIM3/4/5 DFSDM2/
TIM8/9/10/11
I2C1/2/3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
SPI3/I2S3/
SAI1/
DFSDM2/
USART1/
USART2/
USART3
DFSDM1/
USART3/4/
5/6/7/8/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
SAI1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
/OTG1_FS
UART4/
UART5/
UART9/
UART10
/CAN3
FSMC /SDIO - RNG SYS_
AF
Port A
PA0 -
TIM2_CH1/
TIM2_
ETR
TIM5_
CH1 TIM8_ETR - - - USART2_
CTS
UART4_
TX ------
EVENT
OUT
PA1 - TIM2_CH2 TIM5_
CH2 --
SPI4_MOSI/I
2S4_SD -USART2_
RTS
UART4_
RX
QUADSPI_
BK1_IO3 -- ---
EVENT
OUT
PA2 - TIM2_CH3 TIM5_
CH3 TIM9_CH1 - I2S2_CKIN - USART2_
TX ----
FSMC_D4/
FSMC_DA4 --
EVENT
OUT
PA3 - TIM2_CH4 TIM5_
CH4 TIM9_CH2 - I2S2_MCK - USART2_
RX --SAI1_SD_B-
FSMC_D5/
FSMC_DA5 --
EVENT
OUT
PA4 - - - - - SPI1_NSS/I2
S1_WS
SPI3_NSS/I
2S3_WS
USART2_
CK
DFSDM1_
DATIN1 ---
FSMC_D6/
FSMC_DA6 --
EVENT
OUT
PA5 -
TIM2_CH1/
TIM2_
ETR
- TIM8_CH1N - SPI1_SCK/I2
S1_CK --
DFSDM1_
CKIN1 ---
FSMC_D7/
FSMC_DA7 --
EVENT
OUT
PA6 - TIM1_
BKIN
TIM3_
CH1 TIM8_BKIN - SPI1_MISO I2S2_MCK DFSDM2_
CKIN1 -TIM13_
CH1
QUADSPI_B
K2_IO0 -SDIO_
CMD --
EVENT
OUT
PA7 - TIM1_
CH1N
TIM3_
CH2
TIM8_
CH1N -SPI1_MOSI/I
2S1_SD -DFSDM2_
DATIN1 -TIM14_
CH1
QUADSPI_B
K2_IO1 ----
EVENT
OUT
PA8 MCO_1 TIM1_CH1 - - I2C3_
SCL -DFSDM1_
CKOUT
USART1_
CK
UART7_
RX -USB_FS_
SOF
CAN3_
RX
SDIO_
D1 --
EVENT
OUT
PA9 - TIM1_CH2 - DFSDM2_
CKIN3
I2C3_
SMBA
SPI2_SCK/I2
S2_CK -USART1_
TX --
USB_FS_
VBUS -SDIO_
D2 --
EVENT
OUT
PA10 - TIM1_CH3 - DFSDM2_
DATIN3 -SPI2_MOSI/I
2S2_SD
SPI5_MOSI/
I2S5_SD
USART1_
RX --
USB_FS_
ID ----
EVENT
OUT
PA11 - TIM1_CH4 - DFSDM2_
CKIN5 -SPI2_NSS/I2
S2_WS SPI4_MISO USART1_
CTS
USART6_
TX CAN1_RX USB_FS_
DM
UART4_
RX ---
EVENT
OUT
PA12 - TIM1_ETR - DFSDM2_
DATIN5 - SPI2_MISO SPI5_MISO USART1_
RTS
USART6_
RX CAN1_TX USB_FS_
DP
UART4_
TX ---
EVENT
OUT
PA13 JTMS-
SWDIO -- - - - - - - - - - ---
EVENT
OUT
PA14 JTCK-
SWCLK -- - - - - - - - - - ---
EVENT
OUT
PA15 JTDI
TIM2_CH1/
TIM2_
ETR
---
SPI1_NSS/
I2S1_WS
SPI3_NSS/
I2S3_WS
USART1_
TX
UART7_
TX -SAI1_
MCLK_A
CAN3_
TX ---
EVENT
OUT
STM32F413xG/H Pinouts and pin description
DocID029162 Rev 6 68/208
Port B
PB0 - TIM1_
CH2N
TIM3_
CH3
TIM8_
CH2N --
SPI5_SCK/I
2S5_CK -- - -----
EVENT
OUT
PB1 - TIM1_
CH3N
TIM3_
CH4
TIM8_
CH3N --
SPI5_NSS/
I2S5_WS -DFSDM1_
DATIN0
QUADSPI_C
LK -- ---
EVENT
OUT
PB2 - LPTIM1_
OUT ----
DFSDM1_
CKIN0 --
QUADSPI_C
LK -- ---
EVENT
OUT
PB3 JTDO-
SWO TIM2_CH2 - - I2CFMP1
_SDA
SPI1_SCK/I2
S1_CK
SPI3_SCK/I
2S3_CK
USART1_
RX
UART7_
RX I2C2_SDA SAI1_SD_A CAN3_
RX ---
EVENT
OUT
PB4 JTRST - TIM3_
CH1 - - SPI1_MISO SPI3_MISO I2S3ext_
SD
UART7_
TX I2C3_SDA SAI1_SCK_
A
CAN3_
TX SDIO_D0 - - EVENT
OUT
PB5 - LPTIM1_
IN1
TIM3_
CH2 -I2C1_
SMBA
SPI1_MOSI/I
2S1_SD
SPI3_MOSI/
I2S3_SD - - CAN2_RX SAI1_FS_A UART5_
RX SDIO_D3 - - EVENT
OUT
PB6 - LPTIM1_
ETR
TIM4_
CH1 - I2C1_SCL - DFSDM2_
CKIN7
USART1_
TX - CAN2_TX QUADSPI_
BK1_NCS
UART5_
TX SDIO_D0 - - EVENT
OUT
PB7 - LPTIM1_
IN2
TIM4_
CH2 -I2C1_
SDA -DFSDM2_
DATIN7
USART1_
RX ----FSMC_NL--
EVENT
OUT
PB8 - LPTIM1_
OUT
TIM4_
CH3
TIM10_
CH1
I2C1_
SCL -SPI5_MOSI/
I2S5_SD
DFSDM2_
CKIN1 CAN1_RX I2C3_SDA - UART5_
RX SDIO_D4 - - EVENT
OUT
PB9 - - TIM4_
CH4
TIM11_
CH1
I2C1_
SDA
SPI2_NSS/I2
S2_WS
DFSDM2_
DATIN1 - CAN1_TX I2C2_SDA - UART5_
TX SDIO_D5 - - EVENT
OUT
PB10 - TIM2_CH3 - - I2C2_
SCL
SPI2_SCK/I2
S2_CK I2S3_MCK USART3_
TX -I2CFMP1_
SCL
DFSDM2_
CKOUT -SDIO_D7--
EVENT
OUT
PB11 - TIM2_CH4 - - I2C2_
SDA I2S2_CKIN - USART3_
RX -------
EVENT
OUT
PB12 - TIM1_
BKIN --
I2C2_
SMBA
SPI2_NSS/I2
S2_WS
SPI4_NSS/
I2S4_WS
SPI3_SCK/
I2S3_CK
USART3_
CK CAN2_RX DFSDM1_
DATIN1
UART5_
RX
FSMC_D13/F
SMC_DA13 --
EVENT
OUT
PB13 - TIM1_
CH1N --
I2CFMP1
_SMBA
SPI2_SCK/I2
S2_CK
SPI4_SCK/
I2S4_CK -USART3_
CTS CAN2_TX DFSDM1_
CKIN1
UART5_
TX ---
EVENT
OUT
PB14 - TIM1_
CH2N -TIM8_
CH2N
I2CFMP1
_SDA SPI2_MISO I2S2ext_SD USART3_
RTS
DFSDM1_
DATIN2 TIM12_CH1 FSMC_D0/
FSMC_DA0 -SDIO_D6--
EVENT
OUT
PB15 RTC_
REFIN
TIM1_
CH3N -TIM8_
CH3N
I2CFMP1
_SCL
SPI2_MOSI/I
2S2_SD --
DFSDM1_
CKIN2 TIM12_CH2 - - SDIO_CK - - EVENT
OUT
Table 12. STM32F413xG/H alternate functions (continued)
Port
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SYS_
AF
TIM1/2/
LPTIM1 TIM3/4/5 DFSDM2/
TIM8/9/10/11
I2C1/2/3/
I2CFMP1
SPI1/I2S1/
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4
SPI2/I2S2/
SPI3/I2S3/
SPI4/I2S4/
SPI5/I2S5/
DFSDM1/2
SPI3/I2S3/
SAI1/
DFSDM2/
USART1/
USART2/
USART3
DFSDM1/
USART3/4/
5/6/7/8/
CAN1
I2C2/I2C3/
I2CFMP1/
CAN1/2/
TIM12/13/14/
QUADSPI
SAI1/
DFSDM1/
DFSDM2/
QUADSPI/
FSMC
/OTG1_FS
UART4/
UART5/
UART9/
UART10
/CAN3
FSMC /SDIO - RNG SYS_
AF
Pinouts and pin description STM32F413xG/H
69/208 DocID029162 Rev 6
Port C
PC0 - LPTIM1_
IN1 -DFSDM2_CK
IN4 -- -
SAI1_
MCLK_B -------
EVENT
OUT
PC1 - LPTIM1_
OUT -DFSDM2_DA
TIN4 - - - SAI1_SD_B - - - - - - - EVENT
OUT
PC2 - LPTIM1_IN
2-DFSDM2_DA
TIN7 - SPI2_MISO I2S2ext_SD SAI1_SCK_
B
DFSDM1_
CKOUT - - - FSMC_NWE - - EVENT
OUT
PC3 - LPTIM1_
ETR -DFSDM2_CK
IN7 -SPI2_MOSI/I
2S2_SD - SAI1_FS_B - - - - FSMC_A0 - - EVENT
OUT
PC4 - - - DFSDM2_CK
IN2 - I2S1_MCK - - - - QUADSPI_
BK2_IO2 -FSMC_NE4- -
EVENT
OUT
PC5 - - - DFSDM2_DA
TIN2
I2CFMP1
_SMBA --
USART3_
RX --
QUADSPI_
BK2_IO3 -FSMC_NOE- -
EVENT
OUT
PC6 - - TIM3_
CH1 TIM8_CH1 I2CFMP1
_SCL I2S2_MCK DFSDM1_
CKIN3
DFSDM2_
DATIN6
USART6_
TX -FSMC_D1/
FSMC_DA1 -SDIO_D6--
EVENT
OUT
PC7 - - TIM3_
CH2 TIM8_CH2 I2CFMP1
_SDA
SPI2_SCK/
I2S2_CK I2S3_MCK DFSDM2_
CKIN6
USART6_
RX -DFSDM1_
DATIN3 -SDIO_D7--
EVENT
OUT
PC8 - - TIM3_
CH3 TIM8_CH3 - - - DFSDM2_
CKIN3
USART6_
CK
QUADSPI_
BK1_IO2 --SDIO_D0--
EVENT
OUT
PC9 MCO_2 - TIM3_
CH4 TIM8_CH4 I2C3_
SDA I2S2_CKIN - DFSDM2_
DATIN3 -QUADSPI_
BK1_IO0 --SDIO_D1--
EVENT
OUT
PC10 - - - DFSDM2_
CKIN5 --
SPI3_SCK/
I2S3_CK
USART3_
TX -QUADSPI_
BK1_IO1 --SDIO_D2--
EVENT
OUT
PC11 - - - DFSDM2_
DATIN5 - I2S3ext_SD SPI3_MISO USART3_
RX
UART4_
RX
QUADSPI_
BK2_NCS
FSMC_D2/
FSMC_DA2 -SDIO_<