Si5348x-D Datasheet by Skyworks Solutions Inc.

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7 E SILICEIN LABS
Si5348 Rev D Data Sheet
Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary
(T-BC) and Slave (T-TSC) Clocks
The Si5348 combines the industry’s smallest footprint and lowest power network syn-
chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The
Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless
communications systems, and data center switches requiring both traditional and packet
based network synchronization.
The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE
1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also
be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digital-
ly controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588
(PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/
OCXO reference input to determine the device’s frequency accuracy and stability. The
Si5348 is programmable via a serial interface with in-circuit programmable non-volatile
memory so it always powers up into a known configuration. Programming the Si5348 is
easy with ClockBuilder Pro software. Factory pre-programmed devices are also availa-
ble.
Applications:
Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
IEEE 1588 (PTP) slave clock synchronization
Stratum 3/3E, G.812, G.813 network synchronization
DSPLL D
IN0
IN1
IN2
IN3
IN4
OUT6
OUT5
OUT1
OUT4
OUT3
OUT2
OUT0
DSPLL C
DSPLL A
I2C / SPI Control NVM
Status Flags Status Monitor
Si5348
÷FRAC
÷FRAC
÷FRAC
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
XBXA
48-54 MHz XTAL
OSC
REFb
TCXO/OCXO
REF
KEY FEATURES
Three independent DSPLLs in a single
monolithic IC supporting flexible SyncE/
IEEE 1588 and SETS architectures
Ultra-low jitter of 100 fs
Input frequency range:
External crystal: 48 to 54 MHz
REF clock: 5 to 250 MHz
Diff clock: 8 kHz to 750 MHz
LVCMOS clock: 8 kHz to 250 MHz
Output frequency range:
Differential: 1 PPS to 718.5 MHz
LVCMOS: 1 PPS to 250 MHz
Meets the requirements of:
ITU-T G.8262 (SyncE) EEC Options 1 &
2
ITU-T G.812 Type III, IV
ITU-T G.813 Option 1
Telcordia GR-1244, GR-253
(Stratum-3/3E)
silabs.com | Building a more connected world. Rev. 1.1
1. Feature List
The Si5348 features are listed below:
Three independent DSPLLs in a single monolithic IC support-
ing flexible SyncE/IEEE 1588 and SETS architectures
Ultra-Low Jitter
100 fs typ (12 kHz to 20 MHz)
Meets the requirements of:
ITU-T G.8273.2 T-BC
ITU-T G.8262 (SyncE) EEC Options 1 & 2
ITU-T G.812 Type III, IV
ITU-T G.813 Option 1
Telcordia GR-1244, GR-253 (Stratum-3/3E)
Each DSPLL generates any output frequency from any input
frequency
Input frequency range:
External crystal: 48-54 MHz
REF clock: 5-250 MHz
Diff clock: 8 kHz-750 MHz
LVCMOS clock: 8 kHz-250 MHz
Output frequency range:
Differential: 1 PPS to 718.5 MHz
LVCMOS: 1 PPS to 250 MHz
Pin or software controllable DCO on each DSPLL with typical
resolution to 1 ppt/step
TCXO/OCXO reference input determines DSPLL free-run/hold-
over accuracy and stability
Programmable jitter attenuation bandwidth per DSPLL:
0.001 Hz to 4 kHz
Highly configurable output drivers: LVDS, LVPECL, LVCMOS,
HCSL, CML
Core voltage:
VDD: 1.8 V ±5%
VDDA: 3.3 V ±5%
Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
Built-in power supply filtering
Status monitoring: LOS, OOF, LOL
Serial Interface: I2C or SPI (3-wire or 4-wire)
ClockBuilderTM Pro software tool simplifies device configura-
tion
5 input, 7 output, 64 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Si5348 Rev D Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 1.1 | 2
.' mily . family member (7, 6) : A, B) .. ................................. .5 . ................
2. Ordering Guide
Table 2.1. Si5348 Ordering Guide
Ordering Part Number # of
DSPLLs
Output Clock Frequency
Range Package RoHS-6, Pb-Free Temperature
Range
Si5348A-D-GM 1, 2
3
1 Hz to 718.5 MHz
64-Lead 9x9 QFN Yes –40 to 85 °C
Si5348B-D-GM 1, 21 Hz to 350 MHz
Si5348-D-EVB Evaluation Board
SiOCXO1-EVB 12.800 MHz OCXO Evaluation
Board — —
Note:
1. Add an R at the end of the device part number to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software.
Part number format is: Si5348A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed
configuration.
Si534fg-Rxxxxx-GM
Timing product family
f = Multi-PLL clock family member (7, 6)
g = Device grade (A, B)
Product Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 2.1. Ordering Part Number Fields
Si5348 Rev D Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 1.1 | 3
Table of Contents
1. Feature List ................................2
2. Ordering Guide ..............................3
3. Functional Description............................6
3.1 Standards Compliance ...........................6
3.2 Frequency Configuration ..........................6
3.3 DSPLL Loop Bandwidth ...........................6
3.3.1 Fastlock Feature ............................6
3.4 Modes of Operation ............................7
3.4.1 Initialization and Reset ..........................7
3.4.2 Free-run Mode ............................7
3.4.3 Lock Acquisition Mode ..........................8
3.4.4 Locked Mode .............................8
3.4.5 Holdover Mode ............................8
3.5 Digitally-Controlled Oscillator (DCO) Mode ....................8
3.5.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC) ..........9
3.5.2 Frequency Increment/Decrement Using the Serial Interface .............9
3.6 External Reference (XA/XB, REF/REFb) .....................10
3.6.1 External Crystal (XA/XB) .........................11
3.6.2 External Reference (REF/REFb) ......................12
3.7 Inputs (IN0, IN1, IN2, IN3, IN4) ........................13
3.7.1 Input Selection ............................13
3.7.2 Manual Input Selection ..........................13
3.7.3 Automatic Input Selection .........................13
3.7.4 Input Configuration and Terminations .....................14
3.7.5 Hitless Input Switching ..........................15
3.7.6 Ramped Input Switching .........................15
3.7.7 Glitchless Input Switching .........................15
3.7.8 Synchronizing to Gapped Input Clocks ....................15
3.8 Fault Monitoring .............................16
3.8.1 Input LOS Detection...........................16
3.8.2 XA/XB LOS Detection ..........................17
3.8.3 OOF Detection ............................17
3.8.4 Precision OOF Monitor ..........................17
3.8.5 Fast OOF Monitor ...........................17
3.8.6 LOL Detection.............................18
3.8.7 Interrupt Pin (INTRb) ..........................19
3.9 Outputs ................................20
3.9.1 Output Crosspoint ...........................20
3.9.2 Support For 1 Hz Output .........................21
3.9.3 Differential Output Terminations.......................22
3.9.4 LVCMOS Output Terminations .......................23
3.9.5 Output Signal Format ..........................23
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3.9.6 Programmable Common Mode Voltage For Differential Outputs ............23
3.9.7 LVCMOS Output Impedance Selection ....................23
3.9.8 LVCMOS Output Signal Swing .......................23
3.9.9 LVCMOS Output Polarity .........................23
3.9.10 Output Enable/Disable .........................24
3.9.11 Output Disable During LOL ........................24
3.9.12 Output Disable During XAXB_LOS .....................24
3.9.13 Output Driver State When Disabled .....................25
3.9.14 Synchronous/Asynchronous Output Disable ..................25
3.9.15 Output Divider (R) Synchronization .....................25
3.10 Power Management ............................25
3.11 In-Circuit Programming...........................25
3.12 Serial Interface .............................25
3.13 Custom Factory Preprogrammed Parts .....................25
3.14 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-programmed Devices ..........................26
4. Register Map ..............................28
5. Electrical Specifications ..........................29
6. Typical Application Schematic ........................44
7. Detailed Block Diagram ..........................45
8. Typical Operating Characteristics (Jitter and Phase Noise) .............46
9. Pin Descriptions .............................47
10. Package Outline .............................51
11. PCB Land Pattern ............................52
12. Top Marking ..............................54
13. Device Errata ..............................55
14. Revision History............................. 56
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3. Functional Description
The Si5348 offers three DSPLLs that have identical performance and flexibility which can be independently configured and controlled
through the serial interface. Each of the DSPLLs support locked, free-run, and holdover modes of operation with an optional DCO mode
for IEEE 1588 applications. The device requires an external crystal and an external reference (TCXO or OCXO) to operate. The refer-
ence input (REF/REFb) determines the frequency accuracy and stability while in free-run and holdover modes. The external crystal
completes the internal oscillator circuit (OSC) which is used by the DSPLL for intrinsic jitter performance. There are three main inputs
(IN0 - IN2) for synchronizing the DSPLLs. Input selection can be manual or automatically controlled using an internal state machine.
Two additional manually selected inputs are available to DSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any
of the DSPLLs using a flexible crosspoint connection. Output 6 is the only output that can be configured for a 1 Hz output to support 1
PPS.
3.1 Standards Compliance
Each of the DSPLLs meet the requirements of ITU-T G.8262 (SyncE), G.812, G.813, G.8273.2 (T-BC), in addition to Telcordia
GR-1244 and GR-253 as shown in the compliance report. The DCO feature enables IEEE1588 (PTP) implementations in addition to
hybrid SyncE + IEEE1588 (T-BC).
3.2 Frequency Configuration
The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile
memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division
(Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a
specific frequency plan are easily determined using the ClockBuilder Pro utility.
3.3 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter and wander attenuation. Register configurable DSPLL loop
bandwidth settings of 1 mHz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,
each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
Table 3.1. Loop Bandwidth Requirements for North America
SONET (Telcordia) SDH (ITU-T) SyncE (ITU-T) Loop Bandwidth
GR-253 Stratum 3E G.812 Type III 0.001 Hz
GR-253 Stratum 3 G.812 Type IV G.8262 EEC Option 2 <0.1 Hz
G.813 Option 1 G.8262 EEC Option 1 1 - 10 Hz
3.3.1 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock
acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The fastlock
feature can be enabled or disabled independently for each of the DSPLLs.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 6
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3.4 Modes of Operation
Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition
Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown below. The following sections de-
scribe each of these modes in greater detail.
No valid
input clocks
selected
Lock Acquisition
(Fast Lock)
Locked
Mode
Holdover
Mode
Phase lock on
selected input
clock is achieved
An input is
qualified and
available for
selection
No valid input
clocks available
for selection
Free-run
Valid input clock
selected
Reset and
Initialization
Power-Up
Selected input
clock fails
Yes
No
Holdover
History
Valid?
Other Valid
Clock Inputs
Available?
No
Yes
Input Clock
Switch
Figure 3.1. Modes of Operation
3.4.1 Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-
stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A
soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs,
while a soft reset can either affect all or each DSPLL individually.
3.4.2 Free-run Mode
Once power is applied to the Si5348 and initialization is complete, all three DSPLLs will automatically enter freerun mode. The frequen-
cy accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the clock source at the
reference inputs (REF/REFb). A TCXO or OCXO is recommended for applications that need frequency accuracy and stability to meet
the synchronization standards as shown in the following table:
Table 3.2. Free-run Accuracy for North American and European Synchronization Standards
SONET (Telcordia) SDH (ITU-T) SyncE (ITU-T) Free-run Accuracy
GR-253 Stratum 3E G.812 Type III ±4.6 ppm
GR-253 Stratum 3 G.812 Type IV G.8262 EEC Option 2
G.813 Option 1 G.8262 EEC Option 1
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 7
3.4.3 Lock Acquisition Mode
Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-
zation, a DSPLL will automatically start the lock acquisition process.If the fast lock feature is enabled, a DSPLL will acquire lock using
the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. Dur-
ing lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.
3.4.4 Locked Mode
Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point,
any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is
achieved. Refer to 3.8.6 LOL Detection for more details on the operation of the loss of lock circuit.
3.4.5 Holdover Mode
Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input
clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the
disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up
to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calcula-
ted from a programmable window within the stored historical frequency data. Both the window size and delay are programmable as
shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring
frequency data that may be corrupt just before the input clock failure.
Programmable delay
Clock Failure and
Entry into Holdover
time
Historical Frequency Data Collected
Programmable historical data window
used to determine the final holdover value
120 seconds
Figure 3.2. Programmable Holdover Window
When entering holdover, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in holdover,
the output frequency drift is entirely dependent on the external reference clock connected to the REF/REFb pins. If the clock input be-
comes valid, a DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves pulling
the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless.
The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference be-
tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-
ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40
values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit
from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on
ramped input switching see 3.7.6 Ramped Input Switching.
Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable
holdover exit BW.
3.5 Digitally-Controlled Oscillator (DCO) Mode
The DSPLLs support a DCO mode where their output frequencies are adjustable in pre-defined steps defined by frequency step words
(FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increments (FINC) or
decrements (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The
DCO mode is available when the DSPLL is operating in locked mode. The DCO mode is mainly used in IEEE1588 (PTP) applications
where a clock needs to be generated based on recovered timestamps. In this case timestamps are recovered by the PHY/MAC. A pro-
cessor containing servo software controls the DCO to close the timing loop between the master and slave nodes. The processor has
the option of using the FINC/FDEC pin controls to update the DCO frequency or by controlling it through the serial interface.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 8
3.5.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC)
Controlling the output frequency with pin controls is available. This feature involves asserting the FINC or FDEC pins to step (increment
or decrement) the DSPLL’s output frequency. Both the step size and DCO selection (A, C, D) is made through the serial interface by
writing to register bits.
0x0622
FSW_MASK_C
DSPLL C
LPF
PD
÷Mn_C
Md_C
Frequency
Step Word
+
-
DSPLL D
LPF
PD
÷Mn_D
Md_D
Frequency
Step Word
+
-
0x0723
FSW_MASK_D
0x0623 0x0629
0x0724 0x072A
0x001D
FDEC
FINC
SDA/SDIO
A1/SDO
SCLK
A0/CSb
I2C_SEL
SPI/
I2C
FDEC
FINC
Si5348
0x0422
FSW_MASK_A
DSPLL A
LPF
PD
÷Mn_A
Md_A
Frequency
Step Word
+
-
0x0423 0x0429
Figure 3.3. Controlling the DCO Mode By Pin Control
3.5.2 Frequency Increment/Decrement Using the Serial Interface
Controlling the DSPLL frequency through the serial interface is available. This feature involves asserting the FINC or FDEC bits to acti-
vate the frequency change defined by the frequency step word. A set of mask bits selects the DSPLL(s) that is affect by the frequency
change.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 9
3.6 External Reference (XA/XB, REF/REFb)
The external crystal at the XA/XB pins determines jitter performance of the output clocks, and the external reference clock at the REF/
REFb pins determines the frequency accuracy, wander and stability during free-run or holdover modes. Jitter from the external clock on
the REF/REFb pins will have little effect on the output jitter performance, depending upon the selected bandwidth.
Si5348
REFbREF
TCXO
XBXA
48-54MHz
XTAL
XTAL + OSC
Determines Output
Jitter Performance
External Reference
Clock Determines
Output Frequency
Accuracy and Stability
OSC
Figure 3.4. External Reference Connections
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 10
5754 MH XTAL
3.6.1 External Crystal (XA/XB)
The external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the
DSPLLs. The device includes internal XTAL loading capacitors which eliminate the need for external capacitors and also has the bene-
fit of reduced noise coupling from external sources. A crystal in the range of 48 to 54 MHz is recommended for best jitter performance.
Although the device includes built-in XTAL load capacitors (CL) of 8 pF, crystals with load capacitances up to 18 pF can also be accom-
modated. The Si5348 Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure opti-
mum jitter performance. Although not recommended, the device can also accommodate an external clock at the XA/XB pins instead of
a crystal. Selection between the external crystal or clock is controlled by register configuration. The internal crystal loading capacitors
(CL) are disabled in this mode. Refer to Table 5.12 Crystal Specifications1 on page 42 for reference clock requirements when using
this mode. The Si5348 Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure
optimum jitter performance.
50
Differential XO/Clock
Connection
2xCL2xCL
XB XA
OSC
50
0.1 uf 0.1 uf
÷ PREF
25-54 MHz
XO/Clock
LVCMOS XO/Clock
Connection
2xCL2xCL
XB XA
OSC ÷ PREF
R2 R1
0.1 uf
0.1 uf
0.1 uf
C1
25-54 MHz
XO/Clock
LVCMOS
Crystal Resonator
Connection
2xCL2xCL
XB XA
OSC ÷ PREF
25-54 MHz
XTAL
0.1 uf
X1
X2 X1 X2
NC NC
X1 X2
NC NC
Note: See Pin
Descriptions for
X1/X2 connections
C1 is recommended to
increase the slew rate
at Xa
See the Reference Manual for the
recommended R1, R2, C1 values
Figure 3.5. Crystal Resonator Connections
Note: See Table 5.3 Input Clock Specifications on page 30 for more information.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 11
3.6.2 External Reference (REF/REFb)
The external reference at the REF/REFb pins is used to determine output frequency accuracy and stability during free-run and holdover
modes. This reference is usually from a TCXO or OCXO and can be connected differentially or single-ended as shown in the figure
below:
Single-ended External Reference Connection
Differential External Reference Connection
Si5348
REF
REFb
50
R2
R1
Rs
C1
0.1 uF
0.1 uF
0.1 uF
(1)
(2) RS matches the CMOS driver to a 50 ohm transmission line (if used)
Note: When 3.3V LVCMOS driver is present, C1, R1 and R2 may be needed to keep
the signal at INx < 3.6 Vpp_se. See the reference manual for details.
3.3V, 2.5V, 1.8V
LVCMOS
5-250 MHz
TCXO/OCXO
Si5348
100
REF
REFb
0.1 uF
0.1 uF
5-250 MHz
TCXO/OCXO
Figure 3.6. External Reference Connections
Note: See Table 5.3 Input Clock Specifications on page 30 for more information.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 12
3.7 Inputs (IN0, IN1, IN2, IN3, IN4)
There are three inputs, IN0, IN1, and IN2, which can be used to synchronize any of the DSPLLs. The inputs accept both differential and
single-ended clocks. A crosspoint between the inputs and the DSPLLs allows inputs IN0–IN2 to connect to any of the DSPLLs as
shown in the figure below. DSPLL D has two additional inputs, IN3–IN4, which can be manually selected. IN3 and IN4 are CMOS only
inputs. If both IN3 and IN4 are used, they must be the same frequency.
Input
Crosspoint
DSPLL
A
DSPLL
C
DSPLL
D
Si5348
÷P0n
P0d
÷P1n
P1d
÷P2n
P2d
IN0
IN0b
IN1
IN1b
IN2
IN2b
0
1
2
4
0
1
2
3
0
1
2
3
3
IN3
IN4
Figure 3.7. DSPLL Input Selection Crosspoint
3.7.1 Input Selection
Input selection for each of the DSPLLs can be made manually through register control or automatically using an internal state machine.
3.7.2 Manual Input Selection
In manual mode the input selection is made by writing to a register. IN0-IN2 and REF is available to DSPLL A and C, IN0-IN4 and REF
is available to DSPLL D. If there is no clock signal on the selected input, the DSPLL will automatically enter holdover mode.
3.7.3 Automatic Input Selection
When configured in this mode, the DSPLLs automatically selects a valid input that has the highest configured priority. The priority
scheme is independently configurable for each DSPLL and supports revertive or non-revertive selection. All inputs are continuously
monitored for loss of signal (LOS) and/or invalid frequency range (OOF). Only inputs that do not assert both the LOS and OOF monitors
can be selected for synchronization by the automatic state machine. The DSPLL(s) will enter either holdover or freerun mode if there
are no valid inputs available. When both IN3 and IN4 are used, all clock selection must be manual and automatic entry into holdover is
not supported, which means that if the Si5348 is locked to either IN3 or IN4 and the input clock fails, the Si5348 will not go into hold-
over. When only one of IN3 or IN4 is used, automatic clock selection is available and automatic entry into holdover is supported. Hitless
switching with IN3-IN4 is not available.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 13
Standard AC-couplad Di'ferential (INO-INZ) slsua 11/25/va lVCMO‘S R2 RS makMs (he (Mos dvlvev n z 50 uhm : tvansmlsslun line (ii usenl Pulsed culos when 3,3v LVCMOS driver is present. use R2 = 345 oh!“ and R1 = 257 ohm ii needed to keep the signal at 1m < 35="" vppje.="" lnduding="" :1="5" pi="" may="" improve="" the="" amp-n="" jitter="" due="" to="" faster="" input="" slew="" rate="" a!="" m»="" u="" men-mien="" .="" noi="" needed="" for=""><3.6vppse, make="" r1="0" ohm="" and="" omit="" c1,="" lu="" and="" me="" capacitor="" below="" in,="" pulsed="" cmos="" dc-coupled="" single-ended="" only="" for="" frequencies="">< 1mhz="" (lno-inz)="" :="" 5="" v,="" 2="" 5="" vi="" i="" a="" v="" chulos="" slaw="" standard="" w:="" names="" me="" (mosdrlverm="" a="" sflahm="" mm="" mm="" line="" in="" usedl="" r2="" xovnn="" m="" r:="" 13v="" 324="" n="" 6650="" »="" 25v="" 511="" n="" 4750="" 3,3v="" 634="" n="" 3650="" in3,="" in4-="" dc-coupled="" lvcmos=""> an 'N‘ - > Now: See banshee: for 1|!qu Clock Specifications
3.7.4 Input Configuration and Terminations
Each of the differential inputs IN0-IN2, and REF are compatible with standard LVDS, LVPECL, HCSL, CML, and single-ended
LVCMOS formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be ac-
coupled and use the “Standard” Input Buffer selection as these pins are internally dc-biased to approximately 0.83 V. The pulsed
CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals having a duty cycle much less
than 50%. These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs
should be terminated near the device input pins as shown in the figure below. The resistor divider values given below will work with up
to 1 MHz pulsed inputs. In general, following the “Standard AC Coupled Single Ended” arrangement shown below will give superior
jitter performance.
Figure 3.8. Termination of Differential and LVCMOS Input Signals
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 14
m»-»Wm
3.7.5 Hitless Input Switching
Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that
have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that
they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled,
the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase differ-
ence between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching
feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be enabled on a per DSPLL
basis. Clock inputs 3 and 4 do not support hitless switching.
3.7.6 Ramped Input Switching
When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input
switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients
and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off
when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp
rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.4.5 Hold-
over Mode.
3.7.7 Glitchless Input Switching
The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to
the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indi-
cator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output
during the transition. All clock inputs, including 3 and 4, support glitchless input switching.
3.7.8 Synchronizing to Gapped Input Clocks
Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose
of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely
increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic
clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For exam-
ple, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is
shown in the figure below:
DSPLL
100 ns 100 ns
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9
100 MHz clock
1 missing period every 10
90 MHz non-gapped clock
10 ns 11.11111... ns
Gapped Input Clock Periodic Output Clock
Period Removed
Figure 3.9. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every eight. Lock-
ing to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the
hitless switching specification in Table 5.8 Performance Characteristics on page 37 when the switch occurs during a gap in either
input clock.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 15
3.8 Fault Monitoring
Three input clocks (IN0, IN1, IN2) and the reference input (REF/REFb) are monitored for loss of signal (LOS) and out-of-frequency
(OOF) as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference
clock for the DSPLLs. Each of the DSPLLs also has an LOL indicator, which is asserted when synchronization is lost with their selected
input clock. Note that IN3 and IN4 are not monitored.
Si5348
XB
XA
OSC
LOS LOS
PREF
÷
DSPLLB
REF REFb
DSPLL D
PD LPF
÷M
LOL
DSPLL C
PD LPF
÷M
LOL
DSPLL A
PD LPF
÷M
LOL
Input
Crosspoint
IN3
IN4
÷P0n
P0d
IN0
IN0b
Precision
Fast
OOF
LOS
÷P1n
P1d
IN1
IN1b
Precision
Fast
OOF
LOS
÷P2n
P2d
IN2
IN2b
Precision
Fast
OOF
LOS
0
1
2
0
1
2
3
4
0
1
2
Figure 3.10. Si5348 Fault Monitors
3.8.1 Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of
the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal
sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status
register. The live LOS register always displays the current LOS state and a sticky register, when set, always stays asserted until
cleared. When DSPLLD is configured to use both IN3 and IN4 the LOS outputs are not connected to the holdover entry/exit logic. When
configured for one of either IN3 or IN4 (but not both) the LOS for the input clock is connected to the holdover entry/exit logic.
LOS
en
Monitor
LOS
LOS
Sticky
Live
Figure 3.11. LOS Status Indicators
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 16
....................
3.8.2 XA/XB LOS Detection
A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when
XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is
detected.
3.8.3 OOF Detection
Input clocks IN0, IN1, IN2 are monitored for frequency accuracy with respect to an OOF reference, which it considers as its “0_ppm”
reference. Since a TCXO or OCXO will be connected to the REF input, most applications will declare the REF input to be the OOF
reference. The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in
the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and
its sticky register bit stays asserted until cleared.
en
en
Precision
Fast
OOF
Monitor
LOS
OOF
Sticky
Live
Figure 3.12. OOF Status Indicator
3.8.4 Precision OOF Monitor
The precision OOF monitor circuit measures the frequency of all input clocks to within ±1/16 ppm accuracy with respect to the selected
OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range, which is register configu-
rable up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from tog-
gling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequen-
cy range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 IN2) as the 0 ppm OOF reference
instead of the REF/REFb pins is available. This option is register-configurable. XA/XB can also be used as the 0 ppm reference.
OOF Reference
Hysteresis Hysteresis
OOF Declared
OOF Cleared
-6 ppm
(Set)
-4 ppm
(Clear)
0 ppm +4 ppm
(Clear)
+6 ppm
(Set)
fIN
Figure 3.13. Example of Precise OOF Monitor Assertion and De-assertion Triggers
3.8.5 Fast OOF Monitor
Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored
input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in
frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quick-
ly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than
±4000 ppm.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 17
3.8.6 LOL Detection
There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts the LOL register bit when a DSPLL has lost synchronization
with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs
(LOL_Ab, LOL_Cb, LOL_Db) and also for the reference. There are two LOL frequency monitors, one that sets the LOL indicator (LOL
Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow addi-
tional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or
chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL
register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the cur-
rent state of the LOL monitor.
LOS
LOL Status Registers
Sticky
Live
DSPLL C
PD LPF
÷M
LOL Monitor
DSPLL A
DSPLL D
LOL_Ab
LOL_Cb
LOL_Db
DSPLL A
t
LOL
Clear
LOL
Set
fIN
Si5348
Figure 3.14. LOL Status Indicators
Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to 10,000 ppm. Having two
separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is
indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is
more than 1 ppm frequency difference is shown in Figure 3.15 LOL Set and Clear Thresholds on page 18.
Phase Detector Frequency Difference (ppm)
Hysteresis
LOL
LOCKED
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
0
Lost Lock
10,0000.1 1
Figure 3.15. LOL Set and Clear Thresholds
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input
clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 18
configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using
the ClockBuilderPro utility.
3.8.7 Interrupt Pin (INTRb)
An interrupt pin (INTRb) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the sticky status registers.
INTRb
LOS_FLG 0x0011[7] IN4
LOS_FLG 0x0011[6] IN3
LOS_FLG 0x0012[3]
IN2
LOL_FLG_PLL[D] 0x0013[3]
LOL_FLG_PLL[C] 0x0013[2]
LOL_FLG_PLL[A] 0x0013[0]
LOL
HOLD_FLG_PLL[D] 0x0013[7]
HOLD_FLG_PLL[C] 0x0013[6]
HOLD_FLG_PLL[A] 0x0013[4]
HOLD
LOL_FLG_PLL[B] 0x0013[1]
OOF_FLG 0x0012[5]
LOS_FLG 0x0012[1]
IN1
OOF_FLG 0x0012[4]
LOS_FLG 0x0012[0]
IN0
OOF_FLG 0x0012[6]
LOS_FLG 0x0012[2]
Si5348
Device
SMBUS_TIMEOUT_FLG 0x0011[5]
LOSXAXB_FLG 0x0011[1]
SYSINCAL_FLG 0x0011[0]
CAL
REF
CAL_FLG_PLL[A] 0x000F[4]
CAL_FLG_PLL[B] 0x000F[5]
CAL_FLG_PLL[C] 0x000F[6]
CAL_FLG_PLL[D] 0x000F[7]
Figure 3.16. Interrupt Triggers and Masks
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 19
3.9 Outputs
The Si5348 supports seven differential output drivers. Each driver has a configurable voltage amplitude and common mode voltage
covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential
signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 14 single-ended outputs,
or a combination of differential and single-ended outputs.
3.9.1 Output Crosspoint
A crosspoint allows any of the output drivers to connect with any of the DSPLLs as shown in the figure below. The crosspoint configura-
tion is programmable and can be stored in NVM so that the desired output configuration is ready at power-up.
Si5348 Output
Crosspoint
DSPLL
D
DSPLL
A
DSPLL
C
A
C
D
A
C
D
A
C
D
A
C
D
A
C
D
OUT0b
OUT0
÷R0
VDDO0
÷R1OUT1b
VDDO1
OUT1
OUT2b
VDDO2
OUT2
÷R2
÷R3OUT3b
VDDO3
OUT3
÷R4OUT4b
VDDO4
OUT4
÷R5OUT5b
VDDO5
OUT5
÷R6OUT6b
VDDO6
OUT6
D
C
A
R5
A
C
D
Figure 3.17. DSPLL to Output Driver Crosspoint
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 20
ours Va 5 ‘RV' ourab
3.9.2 Support For 1 Hz Output
Output 6 of the Si5348 can be configured to generate a 1 Hz clock by cascading the R5 and R6 dividers. Output 5 is still usable in this
case but is limited to a maximum frequency of 33.5 MHz. ClockBuilder Pro automatically determines the optimum configuration when
generating a 1 Hz output (1 PPS).
A
C
D
÷R4OUT4b
VDDO4
OUT4
÷R5OUT5b
VDDO5
OUT5
÷R6OUT6b
VDDO6
OUT6
D
C
A
R5
A
C
D
Figure 3.18. Generating a 1 Hz Output using the Si5348
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 21
3.9.3 Differential Output Terminations
Note: In this document, the terms LVDS and LVPECL refer to driver formats that are compatible with these signaling standards.
The differential output drivers support both ac-coupled and dc-coupled terminations, as shown in the figure below:
DC Coupled LVDS/LVPECL
50
50
100
OUTx
OUTxb
Si5348
LVDS: VDDO = 3.3V, 2.5V, 1.8V
LVPECL: VDDO = 2.5V, 1.8V
AC Coupled LVDS/LVPECL
100
50
50
Internally
self-biased
OUTx
OUTxb
VDDO = 3.3V, 2.5V, 1.8V
Si5348
AC Coupled LVPECL/CML
50
50
VDD – 1.3V
5050
OUTx
OUTxb
VDDO = 3.3V, 2.5V
Si5348
AC Coupled HCSL
VDDRX
Standard
HCSL
Receiver
R1
OUTx
OUTxb
R1
R2 R2
VDDO = 3.3V, 2.5V, 1.8V
50
50
Si5348
Figure 3.19. Supported Differential Output Terminations
Note: See Si5348 Rev D Reference Manual for resistor values.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 22
«MOE \/ WV (250) \/
3.9.4 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled, as shown in the figure below.
3.3V, 2.5V, 1.8V
LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
50
Rs
50
Rs
DC-coupled LVCMOS
OUTx
OUTxb
Si5348
Figure 3.20. LVCMOS Output Terminations
Note: See Si5348 Rev D Reference Manual for resistor values.
3.9.5 Output Signal Format
The differential output amplitude and common mode voltage are both programmable and compatible with a wide variety of signal for-
mats, including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3
V, 2.5 V, or 1.8 V) drivers providing up to 14 single-ended outputs or a combination of differential and single-ended outputs.
3.9.6 Programmable Common Mode Voltage For Differential Outputs
The common mode voltage (VCM) for the differential modes is programmable and depends on the voltage available at the output’s
VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers.
3.9.7 LVCMOS Output Impedance Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-
ble output impedance selections for each VDDO options as shown in the table below. Note that selecting a lower source impedance
may result in higher output power consumption.
Table 3.3. Typical Output Impedance (ZS)
VDDO CMOS_DRIVE_Selection
OUTx_CMOS_DRV=1 OUTx_CMOS_DRV=2 OUTx_CMOS_DRV=3
3.3 V 38 Ω 30 Ω 22 Ω
2.5 V 43 Ω 35 Ω 24 Ω
1.8 V 46 Ω 31 Ω
3.9.8 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.
3.9.9 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-
ble, which enables complementary clock generation and/or inverted polarity with respect to other output drivers.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 23
3.9.10 Output Enable/Disable
The Si5348 allows enabling/disabling outputs by pin or register control, or a combination of both. Three output enable pins are available
(OE0b, OE1b, OE2b). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default
OE0b controls all of the outputs while OE1b and OE2b remain unmapped and has no effect until configured. The figure below shows an
example of an output enable mapping scheme that is register configurable and can be stored in NVM as the default at power-up.
Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OEb pin(s)
has them enabled. By default the output enable register settings are configured to allow the OEb pins to have full control.
Si5348 Output
Crosspoint
DSPLL
D
DSPLL
A
DSPLL
C
A
C
D
A
C
D
A
C
D
A
C
D
A
C
D
OUT0b
OUT0
÷R0
÷R1OUT1b
OUT1
OUT2b
OUT2
÷R2
÷R3OUT3b
OUT3
÷R4OUT4b
OUT4
÷R5OUT5b
OUT5
÷R6OUT6b
OUT6
D
C
A
R5
OE0b
OE1b
OE2b
In its default state the OE0b pin enables/disables all
outputs. The OE1b and OE2b pins are not mapped
and have no effect on outputs.
A
C
D
Si5348
An example of a configurable output enable scheme. In
this case OE0b controls the outputs associated with DSPLL
A, OE1b controls the outputs for DSPLL C, and OE2b
controls the outputs for DSPLL D.
Output
Crosspoint
A
C
D
A
C
DOUT0b
OUT0
÷R0
÷R1OUT1b
OUT1
OE0b
DSPLL
A
DSPLL
C
A
C
D
A
C
D
OUT2b
OUT2
÷R2
÷R3OUT3b
OUT3
DSPLL
D
A
C
D
÷R4OUT4b
OUT4
÷R5OUT5b
OUT5
÷R6OUT6b
OUT6
D
C
A
R5
OE2b
OE1b
A
C
D
Figure 3.21. Example of Configuring Output Enable Pins
3.9.11 Output Disable During LOL
By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to
disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.
3.9.12 Output Disable During XAXB_LOS
The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the
DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during asser-
tion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy
and stability will be indeterminate during this fault condition.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 24
3.9.13 Output Driver State When Disabled
The disabled state of an output driver is register configurable as disable low or high.
3.9.14 Synchronous/Asynchronous Output Disable
Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock
period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In
asynchronous disable mode, the output clock will disable immediately without waiting for the period to complete.
3.9.15 Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable
phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same
result.
3.10 Power Management
Unused inputs, output drivers, and DSPLLs can be powered down when unused.
3.11 In-Circuit Programming
The Si5348 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from
internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate
specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply
voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old
configuration is no longer accessible.
3.12 Serial Interface
Configuration and operation of the Si5348 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin
selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or 3-
wire mode.
3.13 Custom Factory Preprogrammed Parts
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed part will generate clocks at power-up. Custom, factory-pre-
programmed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly
and easily request and generate a custom part number for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your
design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local
Silicon Labs sales representative. Samples of your pre-programmed device will typically ship in about two weeks.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 25
3.14 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices
As with essentially all modern software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.si-
labs.com, you will be notified whenever changes are made and what the impact of those changes are. This update process will ulti-
mately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the Si5348
Reference Manual.
However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register
setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assis-
tance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock
outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro
project file with your specific features and register settings enabled using what is referred to as the manual "settings override" feature of
CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro
design report are shown in the table below:
Table 3.4. Setting Overrides
Location Name Type Target Dec Value Hex Value
0×0435[0] FORCE_HOLD_PLLA No NVM N/A 1 0×1
0×0B48[4:0] OOF_DIV_CLK_DIS User OPN and EVB 31 0×1F
Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the
NVM file. The flowchart for this process is shown in the figure below:
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 26
/\ \ V Contact Silicon Labs Technical Suggort /
Do I need a
pre-programmed device with
a feature or setting which is
unavailable in ClockBuilder
Pro?
No
Yes
Contact Silicon Labs
Technical Support
to submit & review
your
non-standard
configuration
request & CBPro
project file
Configure device
using CBPro
Load project file
into CBPro and test
Receive
updated CBPro
project file
from
Silicon Labs
with “Settings
Override”
Generate
Custom OPN
in CBPro
Does the updated
CBPro Project file
match your
requirements?
Yes
End: Place
sample order
Start
Figure 3.22. Process for Requesting Non-Standard CBPro Features
Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx.
Si5348 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 27
4. Register Map
Refer to the Si5348 Reference Manual for a complete list of register descriptions and settings.
Si5348 Rev D Data Sheet
Register Map
silabs.com | Building a more connected world. Rev. 1.1 | 28
5. Electrical Specifications
Table 5.1. Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Ambient Temperature TA–40 25 85 °C
Junction Temperature TJMAX 125 °C
Core Supply Voltage VDD 1.71 1.80 1.89 V
VDDA 3.14 3.30 3.47 V
Output Driver Supply Voltage VDDO 3.14 3.30 3.47 V
2.37 2.50 2.62 V
1.71 1.80 1.89 V
Status Pin Supply Voltage VDDS 3.14 3.30 3.47 V
1.71 1.80 1.89 V
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-
ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 29
Table 5.2. DC Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Core Supply Current1IDD 290 460 mA
IDDA 125 145 mA
Output Buffer Supply Current IDDOx LVPECL Output2
@ 156.25 MHz
22 26 mA
LVDS Output2
@ 156.25 MHz
15 18 mA
3.3 V LVCMOS3 output
@ 156.25 MHz
22 30 mA
2.5 V LVCMOS3 output
@ 156.25 MHz
18 23 mA
1.8 V LVCMOS3 output
@ 156.25 MHz
12 16 mA
Total Power Dissipation1, 4 PdSi5348 1250 1600 mW
Note:
1. Si5348 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Differential outputs terminated into an AC coupled 100 Ω load.
3. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV
= 3, which is the strongest driver setting. Refer to the Si5348 Reference Manual for more details on register settings.
4. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not
available. All EVBs support detailed current measurements for any configuration.
50
50
100
OUT
OUTb
IDDO
Differential Output Test Configuration
0.1 uF
0.1 uF
OUTx
OUTxb
IDDO
499
56
4.7pF
50 Scope Input
50
499
56
4.7pF
50 Scope Input
50
Trace length 5
inches
LVCMOS Output Test Configuration
Table 5.3. Input Clock Specifications
Parameter Symbol Test Condition Min Typ Max Unit
Standard Input Buffer (IN0, IN1, IN2, REF)
Input Frequency Range fIN_DIFF Differential 0.008 750 MHz
Single-ended/LVCMOS 0.008 250
REF 5 — 250
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 30
Parameter Symbol Test Condition Min Typ Max Unit
Voltage Swing 1VIN Differential AC-coupled
fIN< 250 MHz
100 1800 mVpp_se
Differential AC-coupled
250 MHz < fIN< 750 MHz
225 1800 mVpp_se
Single-ended AC-coupled
fIN < 250 MHz
100 3600 mVpp_se
Slew Rate2,3 SR 400 — V/μs
Duty Cycle DC 40 60 %
Input Capacitance CIN — 2.4 — pF
Input Resistance Differential RIN_DIFF 16 — kΩ
Input Resistance Single-ended RIN_SE 8 — kΩ
Pulsed CMOS Input Buffer - DC-coupled (IN0, IN1, IN2)4
Input Frequency fIN_PULSED_CM
OS
0.008 250 MHz
Input Voltage VIL –0.2 — 0.4 V
VIH 0.8 — V
Slew Rate2,3 SR 400 — V/μs
Minimum Pulse Width PW Pulse Input 1.6 ns
Input Resistance RIN 8 — kΩ
LVCMOS Input Buffer - AC/DC Coupled (IN3, IN4)
Input Frequency fIN_CMOS 0.008 2.048 MHz
Input Voltage VIL 0.3 x VDDIO5V
VIH 0.7 x VDDIO5— — V
Minimum Pulse Width PW Pulse Input 50 ns
Input Resistance RIN 20 — kΩ
REFCLK (Applied to XA/XB)
REFCLK Frequency fIN_REF Full operating range. Jitter
performance may be re-
duced.
24.97 54.06 MHz
Range for best jitter. 48 54 MHz
TCXO frequency for
SyncE applications. Jitter
performance may be re-
duced.
40 — MHz
Input Single-ended Voltage
Swing
VIN_SE 365 2000 mVpp_se
Input Differential Voltage Swing VIN_DIFF 365 2500 mVpp_diff
Slew Rate2, 3 SR 400 — V/µs
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 31
Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Voltage swing is specified as single-ended mVpp.
OUTx
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
Vcm
2. Recommended for specified jitter performance. Jitter performance can degrade if the minimum slew rate specification is not met
(see the Family Reference Manual).
3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) x VIN_Vpp_se) / SR.
4. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because
they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since
the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for
DC-coupled Pulsed LVCMOS in the Si5348 Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard
AC-coupled, Single-ended input mode.
5.
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 32
Table 5.4. Control Input Pin Specifications
Parameter Symbol Test Condition Min Typ Max Unit
Si5348 Control Input Pins (I2C_SEL, A0/CSb, A1/SDO, SDA/SDIO, SCLK, RSTb, OE0b, OE1b, OE2b, FINC)
Input Voltage VIL 0.3 ×
VDDIO1
V
VIH 0.7 ×
VDDIO1
— — V
Input Capacitance CIN — 1.5 — pF
Input Resistance RL 20 — kΩ
Minimum Pulse Width PW RSTb, FINC 100 ns
Update Rate FUR FINC 1 MHz
Si5348 Control Input Pin (FDEC)
Input Voltage VIL 0.3 × VDDS V
VIH 0.7 × VDDS — — V
Input Capacitance CIN — 1.5 — pF
Minimum Pulse Width PW FDEC 100 ns
Update Rate FUR FDEC 1 MHz
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.
Table 5.5. Differential Clock Output Specifications
Parameter Symbol Test Condition Min Typ Max Unit
Output Frequency fOUT 0.0001 718.5 MHz
fOUT1Hz 1 PPS signal only available
on Output 6
1 Hz
Duty Cycle DC fOUT < 400 MHz 48 52 %
400 MHz < fOUT < 718.5
MHz
45 — 55 %
Output-Output Skew
Using Same DSPLL
TSKS Outputs on same DSPLL
(Measured at 712.5 MHz)
0 75 ps
OUT-OUTb Skew TSK_OUT Measured from the positive
to negative output pins
0 50 ps
Output Voltage Amplitude1VOUT VDDO = 3.3 V,
2.5 V, or 1.8 V
LVDS 350 430 510 mVpp_se
LVPECL 640 750 900
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 33
Parameter Symbol Test Condition Min Typ Max Unit
Common Mode Voltage1VCM VDDO = 3.3 V
LVDS 1.10 1.20 1.30 V
LVPECL 1.90 2.00 2.10
VDDO = 2.5 V LVPECL,
LVDS
1.10 1.20 1.30 V
VDDO = 1.8 V sub-LVDS 0.80 0.90 1.00 V
Rise and Fall Times
(20% to 80%)
tR/tF 100 150 ps
Differential Output Impedance ZO— 100 — Ω
Power Supply Noise Rejection2PSRR 10 kHz sinusoidal noise –101 dBc
100 kHz sinusoidal noise –96 dBc
500 kHz sinusoidal noise –99 dBc
1 MHz sinusoidal noise –97 dBc
Output-output Crosstalk3XTALK –72 — dBc
Note:
1. Output amplitude and common mode settings are programmable through register settings and can be stored in NVM. Each out-
put driver can be programmed independently. Note that the maximum LVDS single-ended amplitude can be up to 110 mV higher
than the TIA/EIA-644 maximum. Refer to the Si5348 Reference Manual for recommended settings. Not all combinations of volt-
age amplitude and common mode voltages settings are possible.
2. Measured for 156.25 MHz carrier frequency. 100 mVpp of sinewave noise added to VDDO running at 3.3 V and noise spur ampli-
tude measured.
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz. Refer to "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems" for guidance on
minimizing crosstalk. Note that all active outputs must be terminated when measuring crosstalk.
OUTx
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
Vcm
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 34
Table 5.6. LVCMOS Clock Output Specifications
Parameter Symbol Test Condition Min Typ Max Unit
Output Frequency fOUT 0.0001 — 250 MHz
fOUT1Hz Only Available on Output 6 1 Hz
Duty Cycle DC fOUT <100 MHz 48 52 %
100 MHz < fOUT < 250 MHz 45 55
Output Voltage High1 , 2, 3
VOH VDDO = 3.3 V
OUTx_CMOS_DRV=1 IOH = –10 mA VDDO × 0.85 V
OUTx_CMOS_DRV=2 IOH = –12 mA
OUTx_CMOS_DRV=3 IOH = –17 mA
VDDO = 2.5 V
OUTx_CMOS_DRV=1 IOH = –6 mA VDDO × 0.85 V
OUTx_CMOS_DRV=2 IOH = –8 mA
OUTx_CMOS_DRV=3 IOH = –11 mA
VDDO = 1.8 V
OUTx_CMOS_DRV=2 IOH = –4 mA VDDO × 0.85 V
OUTx_CMOS_DRV=3 IOH = –5 mA
Output Voltage Low1 , 2, 3
VOL VDDO = 3.3 V
OUTx_CMOS_DRV=1 IOL = 10 mA VDDO × 0.15 V
OUTx_CMOS_DRV=2 IOL = 12 mA
OUTx_CMOS_DRV=3 IOL = 17 mA
VDDO = 2.5 V
OUTx_CMOS_DRV=1 IOL = 6 mA VDDO × 0.15 V
OUTx_CMOS_DRV=2 IOL = 8 mA
OUTx_CMOS_DRV=3 IOL = 11 mA
VDDO = 1.8 V
OUTx_CMOS_DRV=2 IOL = 4 mA VDDO × 0.15 V
OUTx_CMOS_DRV=3 IOL = 5 mA
LVCMOS Rise and Fall
Times3
(20% to 80%)
tr/tf VDDO = 3.3 V 400 600 ps
VDDO = 2.5 V 450 600 ps
VDDO = 1.8 V 550 750 ps
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 35
EEZE [ESTES
Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Si5348 Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
Zs
IOL/IOH
VOL/VOH
DC Test Configuration
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, at 156.25 MHz.
50
50
100
OUT
OUTb
IDDO
Differential Output Test Configuration
0.1 uF
0.1 uF
OUTx
OUTxb
IDDO
499
56
4.7pF
50 Scope Input
50
499
56
4.7pF
50 Scope Input
50
Trace length 5
inches
LVCMOS Output Test Configuration
Table 5.7. Output Status Pin Specifications
Parameter Symbol Test Condition Min Typ Max Unit
Si5348 Status Output Pins ( LOL_Cb, LOL_Db, INTRb, LOS1b, LOS2b, SDA/SDIO2, A1/SDO)
Output Voltage VOH IOH = –2 mA VDDIO1 ×
0.85
— — V
VOL IOL = 2 mA VDDIO1 ×
0.15
V
Si5348 Status Output Pins (LOL_Ab, LOS0b)
Output Voltage VOH IOH = –2 mA VDDS × 0.85 V
VOL IOL = 2 mA VDDS × 0.15 V
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Users normally select this option in the ClockBuild-
er Pro GUI. Alternatively, refer to the Si5348 Reference Manual for more details on register settings.
2. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused
with I2C_SEL pulled high. VOL remains valid in all cases.
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 36
Table 5.8. Performance Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
PLL Loop Bandwidth Program-
ming Range1
fBW 0.001 — 4000 Hz
Initial Start-Up Time tSTART Time from power-up to
when the device gener-
ates free-running clocks
30 45 ms
PLL Lock Time2tACQ With Fastlock enabled 280 300 ms
POR to Serial Interface Ready3tRDY 15 ms
Jitter Peaking JPK Measured with a frequen-
cy plan running a 25 MHz
input, 25 MHz output, and
a loop bandwidth of 4 Hz
0.1 dB
Jitter Tolerance JTOL Compliant with G.8262
Options 1&2
Carrier Frequency =
10.3125 GHz
Jitter Modulation Frequen-
cy = 10 Hz
3180 UI pk-pk
Maximum Phase Transient Dur-
ing a Hitless Switch
tSWITCH Manual or automatic
switch between two input
clocks at same frequency.
5
1.2 ns
Pull-in Range ωP 500 — ppm
RMS Phase Jitter4JGEN 12 kHz to 20 MHz 100 150 fs rms
Note:
1. Actual loop bandwidth might be lower; refer to CBPro for actual value on your frequency plan.
2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock
time was measured with fastlock bandwidth set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively, using IN0 as clock
reference by removing the reference and enabling it again, then measuring the delta time between the first rising edge of the
clock reference and the LOL indicator de-assertion.
3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.
4. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL. (Does not include jitter from input reference).
5. For input frequency configurations, which have Fpfd > 1 MHz. Consult your CBPro Design report for the Fpfd frequency of your
configuration.
6. Measured from input to one or more outputs with the same input and output frequencies.
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 37
Table 5.9. I2C Timing Specifications (SCL,SDA)
Parameter Symbol Test Condition Standard Mode
100 kbps
Fast Mode
400 kbps
Unit
Min Max Min Max
SCL Clock Frequency fSCL — 100 — 400 kHz
SMBus Timeout 25 35 25 35 ms
Hold time (repeated) START
condition
tHD:STA 4.0 — 0.6 — μs
Low period of the SCL clock tLOW 4.7 — 1.3 — μs
HIGH period of the SCL
clock
tHIGH 4.0 — 0.6 — μs
Set-up time for a repeated
START condition
tSU:STA 4.7 — 0.6 — μs
Data hold time tHD:DAT 100 — 100 — ns
Data set-up time tSU:DAT 250 — 100 — ns
Rise time of both SDA and
SCL signals
tr 1000 20 300 ns
Fall time of both SDA and
SCL signals
tf— 300 — 300 ns
Set-up time for STOP condi-
tion
tSU:STO 4.0 — 0.6 — μs
Bus free time between a
STOP and START condition
tBUF 4.7 — 1.3 — μs
Data valid time tVD:DAT — 3.45 — 0.9 μs
Data valid acknowledge time tVD:ACK — 3.45 — 0.9 μs
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 38
Figure 5.1. I2C Serial Port Timing Standard and Fast Modes
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 39
Table 5.10. SPI Timing Specifications (4-Wire)
Parameter Symbol Min Typ Max Unit
SCLK Frequency fSPI 20 MHz
SCLK Duty Cycle TDC 40 — 60 %
SCLK Period TC50 — — ns
Delay Time, SCLK Fall to SDIO Turn-on TD1 18 ns
Delay Time, SCLK Fall to SDIO Next-bit TD2 15 ns
Delay Time, CSb Rise to SDIO Tri-State TD3 — 15 ns
Setup Time, CSb to SCLK TSU1 5 — ns
Hold Time, SCLK fall to CSb TH1 5 — ns
Setup Time, SDI to SCLK Rise TSU2 5 — ns
Hold Time, SDI to SCLK Rise TH2 5 — ns
Delay Time Between Chip Selects (CSb) TCS 2 — TC
SCLK
CSb
SDI
SDO
TSU1 TD1
TSU2
TD2
TC
TCS
TD3
TH2
TH1
Figure 5.2. 4-Wire SPI Serial Interface Timing
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 40
Table 5.11. SPI Timing Specifications (3-Wire)
Parameter Symbol Min Typ Max Units
SCLK Frequency fSPI 20 MHz
SCLK Duty Cycle TDC 40 — 60 %
SCLK Period TC50 — ns
Delay Time, SCLK Fall to SDIO Turn-on TD1 20 ns
Delay Time, SCLK Fall to SDIO Next-bit TD2 — 15 ns
Delay Time, CSb Rise to SDIO Tri-State TD3 15 ns
Setup Time, CSb to SCLK TSU1 5 — ns
Hold Time, SCLK Fall to CSb TH1 5 — ns
Setup Time, SDI to SCLK Rise TSU2 5 — ns
Hold Time, SDI to SCLK Rise TH2 5 — ns
Delay Time Between Chip Selects (CSb) TCS 2 — TC
SCLK
SDIO
TSU1
TD1
TSU2
TD2
TC
TCS
TD3
TH2
TH1
CSb
Figure 5.3. 3-Wire SPI Serial Interface Timing
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 41
Table 5.12. Crystal Specifications1
Parameter Symbol Test Condition Min Typ Max Unit
Crystal Frequency Range fXTAL 48 54 MHz
Load Capacitance CL 8 — pF
Crystal Drive Level dL 200 μW
Equivalent Series Resistance
Shunt Capacitance
rESR
CO
Refer to the Family Reference Manual to determine ESR and shunt capacitance.
Note:
1. Refer to the Si534x/8x Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 48 to 54 MHz crystals.
The Si5348 is designed to only work with crystals that meet these specifications and not with XOs.
Table 5.13. Thermal Characteristics
Parameter Symbol Test Condition1Value Unit
Si5348-64QFN
Thermal Resistance
Junction to Ambient
ϴJA Still Air 22 °C/W
Air Flow 1 m/s 19.4
Air Flow 2 m/s 18.3
Thermal Resistance
Junction to Case
ϴJC 9.5
Thermal Resistance
Junction to Board
ϴJB 9.4
ΨJB 9.3
Thermal Resistance
Junction to Top Center
ΨJT 0.2
Note:
1. Based on PCB Dimension: 3" x 4.5", PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4.
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 42
Table 5.14. Absolute Maximum Ratings1, 2, 3, 4,
Parameter Symbol Test Condition Value Unit
Storage Temperature Range TSTG –55 to 150 °C
DC Supply Voltage VDD –0.5 to 3.8 V
VDDA –0.5 to 3.8 V
VDDO –0.5 to 3.8 V
VDDS –0.5 to 3.8 V
Input Voltage Range VI15IN0 - IN4, REF –1.0 to VDDA
+ 0.3
V
VI2 RSTb, OE0b, OE1b, OE2b,
I2C_SEL,FINC, FDEC, A1/
SDO, SDA/SDIO, SCLK, A0/
CSb,
–0.5 to VDDA
+ 0.3
V
VI3 XA/XB –0.5 to 2.7 V
Latch-up Tolerance LU JESD78 Compliant
ESD Tolerance HBM 100 pF, 1.5 kΩ 2.0 kV
Max Junction Temperature in Operation TJCT 125 °C
Soldering Temperature (Pb-free profile)3TPEAK 260 °C
Soldering Temperature Time at TPEAK (Pb-
free profile)4
TP20-40 s
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2. 64-QFN package is RoHS-6 compliant.
3. For detailed MSL and packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. The device is compliant with JEDEC J-STD-020.
5. The minimum voltage at these pins can be as low as –1.0 V when an ac input signal of 8 kHz or greater is applied. See Table
5.3 Input Clock Specifications on page 30 spec for Single-Ended AC-Coupled fIN < 250 MHz.
Si5348 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 43
6. Typical Application Schematic
DSPLL C
SyncE
Recovered
Clock
÷
÷
DSPLL D
÷
1PPS/SYSCLK
Si5348
Serial I/F
uP
Ethernet
Packets
Servo Loop
Software
Ethernet
Packets
SyncE
Slave
Port
Telecom Boundary Clock (T-BC)
SyncE Transmit Clock
SyncE
Time Stamp
Engine
ToD
1588 Stack
FPGA
PHY
MAC
Master
Port
PHY
MAC
Figure 6.1. Using the Si5348 as a Telecom Boundary Clock
Si5348 Rev D Data Sheet
Typical Application Schematic
silabs.com | Building a more connected world. Rev. 1.1 | 44
7. Detailed Block Diagram
Si5348
VDD
VDDA
3
OE0b
OE1b
OE2b
FDEC
FINC
XB
DSPLL_A
LPFPD
f
DCO
DSPLL_C
LPFPD
÷Mn_C
Md_C
f
DCO
IN1
IN1b
IN0b
IN2
IN2b
÷P0n
P0d
÷P1n
P1d
÷P2n
P2d
A1/SDO
LOL_Cb
LOL_Db
INTRb
Status
Monitors
LOL_Ab
LOS0b
LOS1b
LOS2b
RSTb
VDDS
Output
Crosspoint
A
C
D
A
C
D
A
C
D
A
C
D
A
C
D
OUT0b
OUT0
÷R0
VDDO0
÷R1OUT1b
VDDO1
OUT1
OUT2b
VDDO2
OUT2
÷R2
÷R3OUT3b
VDDO3
OUT3
÷R4OUT4b
VDDO4
OUT4
÷R5OUT5b
VDDO5
OUT5
÷R6OUT6b
VDDO6
OUT6
A
C
D
R5
÷Mn_A
Md_A
IN3
IN4
SDA/SDIO
SCLK
A0/CSb
I2C_SEL
SPI/
I2C
NVM
A
C
D
DSPLL_D
LPFPD
÷Mn_D
Md_D
f
DCO
REFb
48-54MHz XTAL
OSC DSPLLB
5 MHz – 250 MHz
TCXO/OCXO
or REFCLK
REF
Figure 7.1. Si5348 Detailed Block Diagram
Si5348 Rev D Data Sheet
Detailed Block Diagram
silabs.com | Building a more connected world. Rev. 1.1 | 45
hase Nose 10.00am Re . 0.00%de 710.00} Camel 156250000 MHz-r a.“ 12 dBm 100 Hz 437.5210 dBc/Nz 1 km -112,6714 dBc/nz 10 hr; 437.0397 dM/NI 100 k»: 7145,5204 dBc/Mz 1 MHZ 450.9353 dsc/nz 10 mm 7157,1515 dBc/Mz 20 MHZ 460.0226 dnc/nz Start 12 kHz Stop 20 um Center 10.006 MHz sqan 19.953 nnz SE N015: g Anz1ysis Rang! Ana'lysis Range Band Marker Band Marker mtg Noise: ~83.3946 mu / 19.69 MHZ ms Noise: 95.6725 urad 5.48163 tldeg m5 Jitter: 97.451 fsec Residual FM: 721.838 HZ
8. Typical Operating Characteristics (Jitter and Phase Noise)
Figure 8.1. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS with Rakon 12.8 MHz Reference
Si5348 Rev D Data Sheet
Typical Operating Characteristics (Jitter and Phase Noise)
silabs.com | Building a more connected world. Rev. 1.1 | 46
mmmmmmmmmmmmmmm DEDEDDEDEEEDDEE DDDDDDDDDDDDDDDD flflflflflflflflflflflflflflflfl m m
9. Pin Descriptions
GND
Pad
IN1
IN1b
IN3
IN4
I2C_SEL
X1
XA
XB
X2
VDDA
IN2
IN2b
SCLK
SDA/SDIO
A1/SDO
VDD
NC
FINC
FDEC
VDDS
NC
OE2b
VDDO0
OUT0b
OUT0
LOS0b
LOS1b
VDD
OUT3
OUT3b
VDDO3
RSVD
RSVD
RSVD
LOL_Ab
OUT2
OUT2b
VDDO2
OUT1
OUT1b
VDDO1
VDDO4
OUT4b
OUT4
VDDO5
OUT5b
OUT5
LOS2b
OUT6b
OUT6
VDD06
VDD
REF
REFb
IN0
IN0b
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
OE1b
Si5348 64QFN
Top View
RSTb
LOL_Cb
OE0b
INTRb
LOL_Db
A0/CSb
RSVD
Figure 9.1. Si5348 Pin Descriptions
Si5348 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 47
Table 9.1. Si5348 Pin Descriptions 1
Pin Name1Pin Number Pin Type 2Function
Inputs
XA 8 I Crystal Input. Input pin for external crystal (XTAL).
XB 9 I
X1 7 I XTAL Shield. Connect these pins directly to the XTAL ground pins. The
XTAL ground pins should be separated from the PCB ground plane. Re-
fer to the Si5348 Reference Manual for layout guidelines.
X2 10 I
IN0 63 I Clock Inputs. IN0-IN2 accept an input clock for synchronizing the device.
They support both differential and single-ended clock signals. Refer to In-
put Configuration and Terminations input termination options. These pins
are high-impedance and must be terminated externally. The negative side
of the differential input must be grounded through a capacitor when ac-
cepting a single-ended clock. IN3 and IN4 only support single ended
LVCMOS signals.These pins are high-impedance and must be termina-
ted externally. Unused inputs can be disabled by register configuration
and the pins left unconnected.
IN0b 64 I
IN1 1 I
IN1b 2 I
IN2 14 I
IN2b 15 I
IN3 4 I
IN4 5 I
REF 61 I Reference Input. This input accepts a reference clock from a stable
source (eg. TCXO or OCXO) that is used to determine free-run frequency
accuracy and stability during free-run or holdover of the DSPLL or DCO.
These inputs can accept differential or single-ended connections. Refer to
the Si5348 Reference Manual for recommended TCXOs and OCXOs.
REFb 62 I
Outputs
OUT0 31 O Output Clocks. These output clocks support a programmable signal am-
plitude and common mode voltage. Desired output signal format is config-
urable using register control.Termination recommendations are provided
in Figure 3.19 Supported Differential Output Terminations on page 22.
Unused outputs should be left unconnected.
OUT0b 30 O
OUT1 35 O
OUT1b 34 O
OUT2 38 O
OUT2b 37 O
OUT3 45 O
OUT3b 44 O
OUT4 51 O
OUT4b 50 O
OUT5 54 O
OUT5b 53 O
OUT6 59 O
OUT6b 58 O
Serial Interface
I2C_SEL 39 I I2C Select3. This pin selects the serial interface mode as I2C (I2C_SEL =
1) or SPI (I2C_SEL = 0). This pin is internally pulled up to the voltage se-
lected by the IO_VDD_SEL register bit. This pin is 3.3 V tolerant.
Si5348 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 48
Pin Name1Pin Number Pin Type 2Function
SDA/SDIO 18 I/O Serial Data Interface3. This is the bidirectional data pin (SDA) for the I2C
mode, or the bidirectional data pin (SDIO) in the 3-wire SPI mode, or the
input data pin (SDI) in 4-wire SPI mode. When not in SPI mode, this pin
must be pulled-up using an external resistor of at least 1 kΩ. No pull-up
resistor is needed when in SPI mode unless the master SPI driver is open
drain. This pin is 3.3 V tolerant.
A1/SDO 17 I/O Address Select 1/Serial Data Output3. In I2C mode this pin functions as
the A1 address input pin and does not have an internal pull up or pull
down resistor. In 4-wire SPI mode, this is the serial data output (SDO)
pin. and drives high to the voltage selected by the IO_VDD_SEL pin. This
pin is 3.3 V tolerant. This pin must be pulled up externally when unused.
SCLK 16 I Serial Clock Input3. This pin functions as the serial clock input for both
I2C and SPI modes. This pin does not have an internal pull-up or pull-
down. When in I2C mode or unused, this pin must be pulled-up using an
external resistor of at least 1 kΩ. No pull-up resistor is needed when in
SPI mode unless the SPI master driver is open drain. This pin is 3.3 V tol-
erant.
A0/CSb 19 I Address Select 0/Chip Select3. This pin functions as the hardware con-
trolled address A0 input pin in I2C mode. In SPI mode, this pin functions
as the chip select input (active low). This pin is internally pulled-up by a
20 kΩ resistor to the voltage selected by the IO_VDD_SEL register bit.
This pin is 3.3 V tolerant.
Control/Status
INTRb 12 O Interrupt3. This pin is asserted low when a change in device status has
occurred. It should be left unconnected when not in use.
RSTb 6 I Device Reset3. Active low input that performs power-on reset (POR) of
the device. Resets all internal logic to a known state and forces the de-
vice registers to their default values. Clock outputs are disabled during re-
set. This pin is internally pulled-up.
OE0b 11 I Output Enable 0-23. These output enable pins have a programmable
register mask which allows them to control any of the output clocks. By
default the OE0b pin enables all output clocks and OE1b, OE2b have no
control over the output clocks until register configured. These pins are in-
ternally pulled low and can be left unconnected when not in use.
OE1b 26 I
OE2b 27 I
LOL_Ab 21 O Loss of Lock_A/C/D. These output pins indicate when DSPLL A, C, D is
out-of-lock (low) or locked (high). They can be left unconnected when not
in use.
For LOL_C and LOL_D, see Note 3.
For LOL_A, see Note 4.
LOL_Cb 3 O
LOL_Db 28 O
LOS0b 20 O Loss of Signal for IN0, IN1, IN2. These pins reflect the loss of signal
register status bits for inputs (IN0, IN1, IN2). These pins can be left un-
connected when not in use.
For LOS_1 and LOS_2, see Note 3.
For LOS_0, see Note 4.
LOS1b 47 O
LOS2b 55 O
FDEC 25 I Frequency Decrement Pin4. This pin is used to step-down the output
frequency of a selected DSPLL. The frequency change step size is regis-
ter configurable. This pin does not have an internal pullup/pulldown and
must be externally pulled when unused.
Si5348 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 49
Pin Name1Pin Number Pin Type 2Function
FINC 48 I Frequency Increment Pin3. This pin is used to step-up the output fre-
quency of a selected DSPLL. The frequency change step size is register
configurable. The DSPLL(s) affected by the frequency change is deter-
mined by the M_FSTEP_MSK_PLLx register settings. This pin is pulled
low internally and can be left unconnected when not in use.
RSVD 24 - Reserved. These pins are connected to the die. Leave disconnected.
40 -
41 -
42 -
NC 23 - No Connect. These pins are not connected to the die. Leave disconnec-
ted.
56 -
Power
VDD 32 P Core Supply Voltage. The device core operates from a 1.8 V supply.
See the Si5348 Reference Manual for power supply filtering recommen-
dations. A 0402 1 μF capacitor should be placed very near each of these
pins.
46
60
VDDA 13 P Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V power
source. See the Si5348 Reference Manual for power supply filtering rec-
ommendations. A 0402 1 μF capacitor should be placed very near each
of these pins.
VDDS 22 P Status Output Voltage. The voltage on this pin determines VOL/VOH on
the LOL and LOS status output pins. Connect to either 3.3 V or 1.8 V. A
0.1 μF bypass capacitor should be placed very close to this pin.
VDDO0 29 P Output Clock Supply Voltage 0-6. Supply voltage (3.3 V, 2.5 V, 1.8 V)
for OUTn outputs. Leave VDDO pins of unused output drivers unconnec-
ted. An alternate option is to connect the VDDO pin to a power supply
and disable the output driver to minimize current consumption. A 0402 1
μF capacitor should be placed very near each of these pins.
VDDO1 33 P
VDDO2 36 P
VDDO3 43 P
VDDO4 49 P
VDDO5 52 P
VDDO6 57 P
GND PAD - P Ground Pad. This pad provides connection to ground and must be con-
nected for proper operation. Use as many vias as practical and keep the
via length to an internal ground plan as short as possible.
Note:
1. Refer to the Si5348 Reference Manual for more information on register setting names.
2. I = Input, O = Output, P = Power.
3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
Si5348 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 50
mum mmzx\ gouaca D3 /’2 uu E \fi. m7 nnnmnnnnn rm : L4 \ SEMING PLANE
10. Package Outline
The figure below illustrates the package details for the Si5348. The table below lists the values for the dimensions shown in the illustra-
tion.
Figure 10.1. Si5348 9x9 mm 64-Pin Quad Flat No-Lead (QFN)
Table 10.1. Package Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 9.00 BSC
D2 5.10 5.20 5.30
e 0.50 BSC
E 9.00 BSC
E2 5.10 5.20 5.30
L 0.30 0.40 0.50
aaa — 0.15
bbb — 0.10
ccc — 0.08
ddd — 0.10
eee — 0.05
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si5348 Rev D Data Sheet
Package Outline
silabs.com | Building a more connected world. Rev. 1.1 | 51
DDDDUDUE E U 52 {EDiUEUUUUQUUUUUJUfi E E %’*+7 § 1 ”Elnumnnm’mmnn JM EEEEUUDE J
11. PCB Land Pattern
The figure below illustrates the PCB land pattern details for the devices. The table below lists the values for the dimensions shown in
the illustration. Refer to the Si5348 Reference Manual for information about thermal via recommendations.
Figure 11.1. Si5348 PCB Land Pattern
Si5348 Rev D Data Sheet
PCB Land Pattern
silabs.com | Building a more connected world. Rev. 1.1 | 52
Table 11.1. PCB Land Pattern Dimensions
Dimension Si5348 (Max)
C1 8.90
C2 8.90
E 0.50
X1 0.30
Y1 0.85
X2 5.30
Y2 5.30
Note:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication
Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si5348 Rev D Data Sheet
PCB Land Pattern
silabs.com | Building a more connected world. Rev. 1.1 | 53
12. Top Marking
TW
YYWWTTTTTT
Rxxxxx-GM
Si5348g-
e4
Figure 12.1. Si5348 Top Marking
Table 12.1. Top Marking
Line Characters Description
1 Si5348g- Base part number and Device Grade.
Si5348: Packet Network Synchronizer for SyncE/1588; 64-QFN
g = Device Grade. See 2. Ordering Guide for more information.
– = Dash character.
2 Rxxxxx-GM R = Product revision. (See 2. Ordering Guide for current revision.)
xxxxx = Customer specific NVM sequence number. (Optional NVM code assigned for
custom, factory pre-programmed devices. Characters are not included for standard,
factory default configured devices). See 2. Ordering Guide for more information.
-GM = Package (QFN) and temperature range (–40 to +85 °C).
3 YYWWTTTTTT YYWW = Characters correspond to the year (YY) and work week (WW) of package
assembly.
TTTTTT = Manufacturing trace code.
4 Circle w/ 1.6 mm (64-QFN) diam-
eter
Pin 1 indicator; left-justified
e4
TW
Pb-free symbol; Center-Justified
TW = Taiwan; Country of Origin (ISO Abbreviation)
Si5348 Rev D Data Sheet
Top Marking
silabs.com | Building a more connected world. Rev. 1.1 | 54
13. Device Errata
Please log in or register at www.silabs.com to access the device errata document.
Si5348 Rev D Data Sheet
Device Errata
silabs.com | Building a more connected world. Rev. 1.1 | 55
14. Revision History
Revision 1.1
October, 2018
Updated Figure 3.5 Crystal Resonator Connections on page 11
Updated Figure 3.6 External Reference Connections on page 12.
Updated Figure 3.8 Termination of Differential and LVCMOS Input Signals on page 14.
Updated Figure 3.19 Supported Differential Output Terminations on page 22.
Updated Figure 3.20 LVCMOS Output Terminations on page 23.
Updated Table 5.3 Input Clock Specifications on page 30.
Updated Input Capacitance specification typical value.
Updated Table 5.5 Differential Clock Output Specifications on page 33.
Update Output-Output Skew Using Same DSPLL specification typical and max values.
Updated Table 5.6 LVCMOS Clock Output Specifications on page 35.
Removed Output-to-Output Skew specification.
Updated Table 5.8 Performance Characteristics on page 37.
Removed Input-to-Output Delay Variation specification.
Updated Table 5.12 Crystal Specifications1 on page 42.
Updated Table 5.14 Absolute Maximum Ratings1, 2, 3, 4, on page 43.
Revision 1.0
July, 2016
Initial release (See "AN1006: Differences between Si534x/8x Revision B and Revision D Silicon" for a list of changes from Rev B to
Rev D.)
Si5348 Rev D Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 1.1 | 56
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
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