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MAX5855 Datasheet by Maxim Integrated

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Ordering Information maxim Integrated”
General Description
The MAX5855 high-performance, interpolating and modu-
lating, 16-bit, 4.9Gsps RF DAC can directly synthesize up
to 1000MHz of instantaneous bandwidth from DC to fre-
quencies greater than 2.45GHz. The device is optimized
for cable access and digital video broadcast applications
and meets spectral emission requirements for a broad
set of radio transmitters and modulators including DOC-
SIS 3.1/3.0, DVB-C/C2, DVB-T2, DVB-S2X, ISDB-T, and
EPoC.
The device integrates interpolation filters, a digital quadra-
ture modulator, a numerically controlled oscillator (NCO),
clock multiplying PLL + VCO and a 14-bit RF DAC core.
The 4x linear phase interpolation filter simplifies recon-
struction filtering, while enhancing passband dynamic per-
formance, and reducing the input data bandwidth required
from an FPGA. The NCO allows for fully agile modulation
of the input baseband signal for direct RF synthesis.
The MAX5855 input interface accepts 16-bit input data by
way of a five-lane, JESD204B SerDes data input inter-
face that is Subclass-0 compliant and operates at a data
rate of 9.8304Gbps.
The MAX5855 clock input has a flexible interface that ac-
cepts a differential sine-wave or square-wave reference
input clock signal at 245.75MHz, 491.52MHz, or
983.04MHz. A clock multiplying PLL and VCO is used to
internally generate the 4.9152GHz sampling clock from
the reference clock. The device provides a divided refer-
ence clock output to ensure synchronization between the
data source and the DAC.
The integrated RF DAC uses a differential current-steering
architecture that includes a differential 50Ω internal termi-
nation and can produce a 3dBm full-scale output signal
level on a 50Ω external load. Operating from 1.0V and
1.8V power supplies, the device consumes 2.7W at
4.9Gsps. The device is offered in a compact 144-pin,
10mm x 10mm, FCCSP package and is specified for the
extended industrial temperature range (-40°C to +85°C).
Applications
DOCSIS 3.1/3.0 Remote PHY and CCAP
Digital Video Broadcast Modulators
• DVB-C/C2/DVB-T2/DVB-S2X/ISDB-T
Ethernet PON Over Coax (EPoC)
Point-to-Point Wireless
● Instrumentation
Benefits and Features
Simplifies RF Design and Enables New
Communication Architectures
Eliminates I/Q Imbalance and LO Feedthrough
Enables Multi-Band RF Modulation
Direct RF Synthesis of 1GHz Bandwidth
4.9152Gsps DAC Output Update Rate
High-Performance 14-Bit RF DAC Core
Digital Baseband I/Q with 4x Interpolation
Digital Quadrature Modulator + NCO for Full Agility
Sub-1Hz NCO Resolution
Integrated Clock Multiplying PLL + VCO
Flexible and Configurable
5-Lane JESD204B Input Data Interface
Subclass-0 Compliant
9.8304Gbps Per Lane
Divided Reference Clock Output
SPI Interface for Device Configuration
Ordering Information appears at end of data sheet.
Click here for production status of specific part numbers.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B
Interface
EVALUATION KIT AVAILABLE
19-100312; Rev 1; 4/19
Simplified Block Diagram
Quadrature
NCO
MOD
OUTP
OUTN
SPI Port
CLKP
CLKN
CSB
SCLK
SDI
SDO
Reference
System
14-BIT
4.9Gsps
RF DAC
16
16
14
RCLKP
RCLKN
JESD
204B
SYNCNP
SYNCNN
DP[4:0]
DN[4:0]
MUTE
RESETB
4
INTB
5
PLL
VCOBYP
PLL_COMP
MAX5855
CSBP
REFIO
FSADJ
DACREF
VDD
AVDD
AVCLK
GND
REFERENCE
SYSTEM
CLOCK
DISTRIBUTION
QUADRATURE
NCO SPI PORT
4
÷ N
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 2
TABLE OF CONTENTS
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
144 FCCSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supported DAC Update Rate and JESD204B Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
JESD204B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
JESD204B Data Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mapping of Physical to Logical Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
High-Speed Input Receiver (Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
JESD204B Receiver Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Lane Skew Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Link Layer (LINK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interface Timing for Subclass-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Digital Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Quadrature Modulator and NCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reference Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DAC Clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
VCO Band Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PLL External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 3
TABLE OF CONTENTS (CONTINUED)
RCLK Description and Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Register Definition and Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI to PCLK Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI to fDAC Frequency Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Frequency Settings and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Configuration Script Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MAX5855 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Register Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
JESD204B LINK and DSP Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Subclass-0 with Device Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Applications Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Power Supply AVCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Power-On RESETB and SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Delay Time TD-DivRst Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Pin DACREF Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
DAC PLL Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Pin SDO Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Clock Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
NCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PRBS Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
DAC Output Impedance Model and Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 4
LIST OF FIGURES
Figure 1. Serial Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Simplified Diagram of JESD204B Internal to MAX5855. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. Octet-To-Sample Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. JESD204B Rx Physical Layer, Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. VGA Gain Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Receiver Equalization Eye Diagram Before and After Lane Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. Channel Loss Curve (30in Nelco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. JESD204B Receive Link Layer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. JESD204B Receive Lane Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10. Interface Timing for Subclass-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. SPI Single Write with MSB-First Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. SPI Single Read with MSB-First Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13. SPI Single Write with LSB-First Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. SPI Single Read with LSB-First Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. SPI Burst Write with MSB-First Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. SPI Burst Read with MSB-First Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. SPI Burst Write with LSB-First Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. SPI Burst Read with LSB-First Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. Interrupt Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Mute Generation Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 21. Effect of DAC Update Rate on Folded HD2 and HD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22. Complex NCO and Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. NCO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 24. Setting the DAC Output Full-Scale Using an (a) Internal or (b) External Reference Voltage . . . . . . . . . . . . 41
Figure 25. Typical DAC Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26. Output Configuration for Low-Frequency Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. MAX5855 Clock Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 28. DAC Clock PLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29. DAC Clock PLL External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 30. Device Configuration Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 31. Rx LINK and DSP Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 32. DAC Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 33. DAC Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 34. DAC Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
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LIST OF TABLES
Table 1. Complex I/Q Base Band Up-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2. Lane Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 4. Digital Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5. Frequency Planning and Configuration with CLKP/N Used as JESD204B Device Clock . . . . . . . . . . . . . . . . . 48
Table 6. Configuration Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
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2170732 9070289 www. maxfmfntegrated. com/gackages www. maxlmmlegraled. oom/ thermal-lulorla/
Absolute Maximum Ratings
VDD2, AVCLK2, AVDD2, AVDD2PLL, VDD2PLL. -0.3V to +2.1V
OUTP, OUTN ...................................... -0.3V to (VAVDD2 + 0.5)V
MUTE, RESETB, CSB, SCLK, SDO, SDI, INTB,TDA .....-0.3V to
(VVDD2 + 0.3, MAX 2.1)V
TESTP, TESTN, SYNCNP, SYNCNN, RCLKP, RCLKN .-0.3V to
(VVDD2 + 0.3, MAX 2.1)V
DP0, DN0, DP1, DN1, DP2, DN2, DP3, DN3, DP4, DN4 -0.3V to
(VVDD2 + 0.3, MAX 1.6)V
JRES, CAPT, TESTEN .... (VVSSPLL - 0.3)V to (VVDD2PLL + 0.3,
MAX 2.1)V
VCOBYP .............................-0.3V to (VAVCLK2 + 0.3, MAX 2.1)V
PLLCOMP ......................-0.3V to (VAVDD2PLL + 0.3, MAX 2.1)V
VSSPLL, TDC, DACREF .......... (VGND – 0.3)V to (VGND + 0.3)V
VDD, AVDD, AVCLK, AVDDPLL ........................... -0.3V to +1.2V
REFIO, FSADJ, CSBP..........-0.3V to (VAVDD2 + 0.3, MAX 2.1)V
CLKP, CLKN ..................... -0.3V to (VAVDDPLL + 0.3, MAX 1.2)V
SDO, INTB Maximum Continuous Current ............................8mA
Continuous Power Dissipation (TA= +85°C) ........................4.0W
Thermal Characteristics
Operating Temperature Range (TA)..................-40°C to +85°C
Operating Junction Temperature (TJ) ...........................+110°C
Maximum Junction Temperature................................... +150°C
Storage Temperature Range...........................-60°C to +150°C
Soldering Temperature (reflow)..................................... +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Package Information
144 FCCSP
Package Code X14400F+1
Outline Number 21-0732
Land Pattern Number 90-0289
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θJA) 16.2°C/W
Junction-to-Case Thermal Resistance (θJC) 2.5°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 7
F‘gure ZS Flgure 26 Flgure 26 F‘gure 26
Electrical Characteristics
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.206V, RSET = 965Ω between
FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on. TA≥ -40°C
and TJ≤ +110°C, unless otherwise noted. Typical values are at TJ= +65 ±15°C. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Input Data Word Width N 16 Bits
DAC Resolution 14 Bits
Differential Non-
Linearity DNL Figure 26 ±1.5 LSB
Integral Non-Linearity INL Figure 26 ±3 LSB
Offset Voltage Error OS 0.003 %FS
Minimum Full-Scale
Output Current IOUTFS 10 mA
Maximum Full-Scale
Output Current IOUTFS 40 mA
Output-Voltage Gain
Error GEFS fOUT = DC, Figure 26 ±3 %FS
Maximum Output
Compliance
VAVDD2
+ 0.4 V
Minimum Output
Compliance
VAVDD2
- 0.4 V
Output Resistance ROUT Differential DAC output resistance 50 Ω
DYNAMIC PERFORMANCE
DAC Sample Rate fDAC 4915.2 Msps
Adjusted DAC Update
Rate AURDAC (Note 2) 1228.8 Msps
Maximum Input Sample
Rate fS_IN For the complex I/Q dataset 1228.8 MHz
SFDR to Nyquist SFDR CW tone, -1dBFS
fOUT = 500MHz 73
dBfOUT = 1000MHz 74
fOUT = 1500MHz 69
Maximum HD2, HD3,
fDAC/2-fOUT, Measured
in 1st Nyquist Zone
CW tone, -3dBFS fOUT = 1842.5MHz -71 dBc
Intermodulation
Distortion IMD
Two-tone signal,
fDAC = 4.9152GHz,
f1= 1842MHz and
f2= 1843MHz
Average total
power -15dBFS -74 dBc
Two-tone signal,
fDAC = 4.9152GHz,
f1= 1842MHz, and
f2= 1843MHz
Average total
power -33dBFS -80 dBFS
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 8
F‘gure ZS
Electrical Characteristics (continued)
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.206V, RSET = 965Ω between
FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on. TA≥ -40°C
and TJ≤ +110°C, unless otherwise noted. Typical values are at TJ= +65 ±15°C. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out-of-Band Noise and
Spurious, Eight 6MHz
256-QAM Carriers (Note
5)
ACPR
fOUT = 575MHz
(Note 3, Note 4)
Adjacent channel -69.8 -62.9
dBc
Next-adjacent
channel -70.5 -63.1
Third-adjacent
channel -70.9 -64.0
fOUT = 575MHz
(Note 3)
Noise in any other
channel -65.4
fOUT = 975MHz,
Average Total
Power =
-12dBFS (Note 6)
Adjacent channel -67.4
Next-adjacent
channel -67.9
Third-adjacent
channel -68.5
Noise in any other
channel -63.8
Out-of-Band Noise and
Spurious, Thirty Two
6MHz 256-QAM
Carriers (Note 5)
ACPR
fOUT = 1100MHz,
Average Total
Power =
-15dBFS (Note 6)
Adjacent channel -64.4
dBc
Next-adjacent
channel -64.1
Third-adjacent
channel -64.1
Noise in any other
channel -57.3
Harmonic Distortion,
Four 6MHz 256-QAM
Carriers
HD
fOUT = 575MHz,
Average Total
Power = -12dBFS
(Note 4, Note 6)
Second Harmonic
Distortion -66.8 -55.4
dBc
Third Harmonic
Distortion -67.7 -60.4
Noise Density ND
CW tone at 1842.5MHz, -15dBFS,
Measured at 10MHz offset from carrier, in
200kHz bandwidth
-157.5 dBm/Hz
DAC RESPONSE CHARACTERISTIC
Output Power (CW)
(Note 7) POUT
0dBFS CW tone at
DAC input, fOUT =
100MHz
Excludes losses 3.2
dBm
Excludes losses,
includes sin(x)/x
roll-off
3.2
0dBFS CW tone at
DAC input, fDAC =
4915.2Msps, fOUT =
2140MHz
Excludes losses 0.4
Excludes losses,
includes sin(x)/x
roll-off
-2.5
Output Bandwidth fDAC = 4915.2Msps, -1dB bandwidth,
excludes losses (Note 7) 2600 MHz
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 9
F‘gure ZS
Electrical Characteristics (continued)
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.206V, RSET = 965Ω between
FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on. TA≥ -40°C
and TJ≤ +110°C, unless otherwise noted. Typical values are at TJ= +65 ±15°C. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Settling Time for
Full-Scale Input Step
(Note 8)
To ±0.024% of output full-scale in 4x
interpolation mode 20 ns
INTERPOLATION FILTERS
Interpolation Rates R Complex path 4x
Passband Width PBW Ripple < 0.01dB 0.407 x
fS_IN MHz
Stopband Rejection 4x interpolation, 0.593 x fS_IN 80 dB
Data Latency (Excluding
JESD204B Latency) 4x interpolation 424
DAC
Clock
Cycles
NCO
Maximum Frequency 2457.6 MHz
Frequency Control Word
Resolution 33 Bits
REFERENCE (REFIO)
Reference Input Range 1.1 1.3 V
Reference Output
Voltage VREFIO Internal Reference 1.1 1.2 1.3 V
Reference Input
Resistance RREFIO 10 kΩ
Reference Voltage Drift ±110 ppm/°C
CMOS LOGIC INPUTS/OUTPUTS (SCLK, CSB, MUTE, RESETB, SDI, SDO, INTB)
Input High Voltage VIH 0.7 x
VDD2 V
Input Low Voltage VIL 0.3 x
VDD2 V
Input Current IIN Excluding RESETB -1 ±0.1 +1 μA
RESETB Input Current IINRB -1 +55 μA
Input Capacitance CIN 3 pF
Output High Voltage VOH ILOAD = 200μA, INTB has a 1kΩ pullup
resistor to VDD2
0.8 x
VDD2 V
Output Low Voltage VOL ISINK = 200μA, INTB has a 1kΩ pullup
resistor to VDD2
0.2 x
VDD2 V
Output Leakage Current Three-state, SDO pin -4 ±2.5 +4 μA
JESD204B INPUTS (DP4-DP0, DN4-DN0)
Differential Input Return
Loss RLDIFF 8 dB
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 10
F‘gure ZS
Electrical Characteristics (continued)
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.206V, RSET = 965Ω between
FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on. TA≥ -40°C
and TJ≤ +110°C, unless otherwise noted. Typical values are at TJ= +65 ±15°C. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Common-mode Input
Return Loss RLCM 6 dB
Receiver Differential
Resistance RRxDIFF At DC 80 120
Minimum Differential
Input Voltage VMIN_IN 110 mVp-p
Maximum Differential
Input Voltage VMAX_IN 1050 mVp-p
Discrete Serial Data
Rate per Lane fSER_IN 9830.4 Mbps
LVDS LOGIC OUTPUT (SYNCNP, SYNCNN, RCLKP, RCLKN)
Differential Output Logic
High Voltage VOH RLOAD = 100Ω differential 250 450 mV
Differential Output Logic
Low Voltage VOL RLOAD = 100Ω differential -450 -250 mV
Output Common Mode
Voltage VOCM 1.125 1.25 1.375 V
Output Maximum
Frequency fRCLK RLOAD = 100Ω differential, CLOAD = 5pF 245.76 MHz
CLOCK INPUT (CLKP, CLKN)
Power Level at
Differential CLKP/CLKN
Clock Input (Note 6)
PCLK Sine-wave input,
PLL on > -3 dBm
Common-Mode Voltage VCOM AC-coupled, internally biased 0.5 V
Differential Input
Resistance RCLK 100 Ω
INTERNAL DAC CLOCK PLL
Internal DAC Clock PLL
Frequency Range fPLL 4915.2 MHz
PLL Input Frequencies fCLK (Note 9) fPLL/
MLT MHz
Minimum PLL Input
Frequency Multiplier MLTMIN (Note 9) 5
Maximum PLL Input
Frequency Multiplier MLTMAX (Note 9) 20
Phase Noise at 6MHz
Offset
Simulated at PLL output, does not include
DAC core phase noise -142 dBc/Hz
Cycle-to-Cycle Jitter Simulated at PLL output, does not include
DAC core jitter 245 fs
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 11
F‘gure ZS
Electrical Characteristics (continued)
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.206V, RSET = 965Ω between
FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on. TA≥ -40°C
and TJ≤ +110°C, unless otherwise noted. Typical values are at TJ= +65 ±15°C. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RESET TIMING
RESET to Ready Delay tRRDY 350000 fCLK
Cycles
SERIAL PORT INTERFACE (Note 4)
SCLK Frequency fSCLK 1/tSCLK 20 MHz
SCLK to CSB Falling
Edge Setup Time tCSS 10 ns
Minimum SCLK to CSB
Falling Edge Hold Time tCSH 40 ns
Minimum SCLK Falling
Edge to CSB Rising
Edge Hold Time
tCRH 9.765 ns
SDI to SCLK Hold Time tSDH Data write 0 ns
SDI to SCLK Setup
Time tSDS Data write 5 ns
Minimum SCLK to SDO
Data Delay tSDD_MIN
Data read, 10pF load from SDO to
ground 1.5
ns
Data read, 100pF load from SDO to
ground 3.5
Maximum SCLK to SDO
Data Delay tSDD_MAX
Data read, 10pF load from SDO to
ground 8
ns
Data read, 100pF load from SDO to
ground 11
POWER SUPPLY
1.0V Supply Voltage
Range
VDD, VAVDD,
VAVDDPLL,
VAVCLK
0.95 1.0 1.05 V
1.8V Supply Voltage
Range
VDD2,
VAVCLK2,
VAVDD2,
VAVDD2PLL,
VDD2PLL
1.71 1.8 1.89 V
1.0V Digital Supply
Current IVDD (Note 3) 550 750 mA
1.8V Digital Supply
Current IVDD2 (Note 3) 500 550 mA
1.0V Clock Supply
Current IAVCLK (Note 3) 350 400 mA
1.8V Clock Supply
Current IAVCLK2 (Note 3) 51 60 mA
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 12
F‘gure ZS AC PLL Verence Tab‘e 5
Electrical Characteristics (continued)
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.206V, RSET = 965Ω between
FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on. TA≥ -40°C
and TJ≤ +110°C, unless otherwise noted. Typical values are at TJ= +65 ±15°C. (Note 1))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
1.0V Analog Supply
Current IAVDD (Note 3) 230 270 mA
1.8V Analog Supply
Current IAVDD2 (Note 3) 270 295 mA
1.0V Clock PLL Supply
Current IAVDDPLL (Note 3) 7 15 mA
1.8V Clock PLL Supply
Current IAVDD2PLL (Note 3) 28 35 mA
1.8V JESD204B PLL
Supply Current IVDD2PLL (Note 3) 27 35 mA
Total Power Dissipation PTOTAL (Note 3) 2700 3100 mW
Note 1: All specifications are guaranteed by test at TJ= +60°C and TJ= +115°C to an accuracy of ±10°C, unless otherwise noted.
Specifications at TJ< +60°C are guaranteed by design and characterization. Timing specifications are guaranteed by design and
characterization.
Note 2: Adjusted DAC update rate is defined as the rate at which the digital signal is converted to an analog signal and the output analog
values are changed by the DAC.
Note 3: Eight 6MHz 256-QAM carriers, fOUT = 575MHz, Average Total Power = -12dBFS, input power is referenced to a 50Ω load.
Note 4: Specification guaranteed by design and characterization and functionally tested during production.
Note 5: Adjacent channel is 750kHz from channel block edge to 6MHz from channel block edge. Next adjacent channel is 6MHz from
channel block edge to 12MHz from channel block edge. Third adjacent channel is 12MHz from channel block edge to 18MHz from
channel block edge.
Note 6: Input power is referenced to a 50Ω load.
Note 7: Excludes losses from cables and matching network at DAC output, also excludes sin(x)/x roll-off unless otherwise noted.
Note 8: Settling time is dominated by the interpolation filter step response.
Note 9: DAC PLL reference input frequency multiplier (MLT), is defined by the ratio of the PLL feedback divide value (M) and the input
reference divide value (N). MLT = M ÷ N, where M is 20 and N can be 1, 2, or 4; consistent with valid configurations listed
in Table 5.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 13
/ \ / \ / \ / \ / \ \
CSB
SDI
SDO
R/W D7
SCLK
1st CLOCK 16th CLOCK 24th CLOCK
tSCLK
tSDS
tCSS
tCSH tCRH
D7 D0
D0
WRITE DATA
READ DATA
tSDH
tSDD
Figure 1. Serial Interface Timing Diagram
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
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Typical Operating Characteristics
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.20625V, RSET = 965Ω
between FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on.
Typical values are at TJ= +65 ±15°C.)
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
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Typical Operating Characteristics (continued)
(VDD = VAVCLK = VAVDD = VAVDDPLL = 1.0V, VDD2 = VAVCLK2 = VAVDD2 = VAVDD2PLL = VDD2PLL = 1.8V, PCLK = 0dBm, fCLK =
983.04MHz, fDAC = 4915.2Msps, 4x interpolation, 5-lanes, 9830.4Mbps per lane, external reference at 1.20625V, RSET = 965Ω
between FSADJ and DACREF, IOUTFS = 40mA, output is 50Ω double-terminated and transformer coupled (see Figure 25), PLL on.
Typical values are at TJ= +65 ±15°C.)
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 16
Pin Configuration
A1 A2 A4 A5 A6 A7 A8 A9
B1 B2 B3 B5 B6 B7 B8 B10
C1 C2 C3 C5 C6 C7 C8 C10
D1 D2 D3 D5 D6 D7 D8 D10
E1 E2 E3 E5 E6 E7 E8 E10
F1 F2 F3 F5 F6 F7 F8 F10
G1 G2 G3 G5 G6 G7 G8 G9
H3 H5 H6 H7 H8 H9 H10
J1 J2 J3 J5 J6 J7 J8 J9 J10
K1 K2 K3 K5 K6 K7 K8 K9 K10
OUTN
FSADJ
CSBP
GND
DACREF
AVDD2OUTP
RCLKN
GND
GND
VDD
VDD
GND
GND
VDD2
VDD2
VDD2
GND
GND
GND
GND
GND
GND
GND
VDD
VDD
GND
GND
GND
GND
GND
VDD
GND
GND
RCLKP
GND
GND
GND
VDD
GND
GND
INTB
RESETB
SCLK
GND
NC
NC
GND
GND
SDO
SDI
CSB
AVDD2
GND
GND
REFIO AVDD2 AVDD2
GND
L1 L3 L5 L6 L7 L8 L9 L10
C11
D11
E11
F11
G11
J11
K11
TDC
GND
AVCLK2
GND
L11
GNDGNDGNDAVDD2
AVDD2
GND
OUTP
GND AVDD2 OUTN AVDD2
M1 M3 M5 M8 M9 M10 M11
B12
C12
D12
E12
G12
K12
GND
GND
GND
CLKN
VCOBYP
CLKP
L12
M12
DIE GND SUPPLIES
CRITICAL
ANALOG
AND RF
RF DATA
AND
CLOCK
ANALOG,
DIGITAL IO
G10
GND
E9
AVDD
F9
GND
GND
F4
A3
AVCLK
A10
AVCLK
MUTE
GND
F12
E4
AVDD
SYNCNN
SYNCNP
GND GND TDA GND
NC
DN4
CAPT DN3
DP3
NC
GND DP4
GND
GND GND
DN1
DN0
DN2 JRES
DP1 DP2
DP0
GND
TESTEN NCNC VDD2PLL
GND GND
NO
CONNECT
AVCLK2
VCORTN
AVCLK
PLLCOMP
GND
GND
H4
VDD2
VDD2
L4
M4
G4
VDD2
GND
GND
K4
GND
J4
B4
AVDD2 AVDD2
B9
GND
GND
C9
D9D4
C4
GND
GND
TESTP
TESTN
H1 H2
J12
H11 H12
TOP VIEW
L2
GND
M2
GND
M6 M7
GND VSSPLL
A12
B11
A11
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 17
Pin Description
PIN NAME FUNCTION
A1 REFIO
Reference Voltage Input/Output. REFIO outputs an internal 1.2V band-gap reference voltage. REFIO
has a 10kΩ series resistance and can be driven using an external 1.2V reference voltage. Connect a
1µF capacitor between REFIO and DACREF.
A2 CSBP DAC Current Source Bypass. Connect 1.0µF capacitor between CSBP and DACREF.
A3, A10 AVCLK 1.0V Supply Input for Clock
A4-A5,
A8-A9,
B4-B5,
B8-B9,
C2-C3
AVDD2 Analog 1.8V Supply Input
A6, B6 OUTP Positive Terminal of Differential DAC Output
A7, B7 OUTN Negative Terminal of Differential DAC Output
A11 VCORTN Ground for VCO Loop Filter
A12 PLLCOMP Analog I/O for DAC PLL Loop Filter Connection
B1 DACREF Internal DAC Reference Ground Used for DAC Current Source Bypass Ground. Do not connect to board
ground (GND).
B2 FSADJ
Analog Input for DAC Full-Scale Output Current Adjustment. A resistor from FSADJ to DACREF sets the
full-scale output current of the DAC. To obtain a 40mA full-scale output current using the internal
reference voltage, connect a 965Ω resistor between FSADJ and DACREF.
B3, B10,
C1,
C4-C12,
D1-D10,
E3, E5-E8,
E10,
F3-F4,
F9-F12,
G6-G7,
G10-G12,
H5-H8,
H10,
J5-J8, J10,
K1-K5,
K8-K10,
K12, L2,
L4, L9,
L11, M2,
M4, M6,
M9
GND Ground
B11 VCOBYP VCO Loop Filter Connection
B12 AVCLK2 1.8V Supply Input for Clock
D11 AVDD2PL
L1.8V DAC Clock PLL Supply
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 18
Pin Description (continued)
PIN NAME FUNCTION
D12, E12 CLKP,
CLKN
Clock Input. Multipurpose pin that generates following internal clocks based on use case:
1) Reference clock for DAC PLL which in turn generates the DACCLK.
2) Device clock (DCLK) for JESD204B interface.
An internal 100Ω termination resistor connects CLKP to CLKN.
E1 SCLK Digital CMOS Input for Serial Port Interface Clock
E2 CSB Digital CMOS Input for Serial Port Interface. MAX5855 is selected when CSB = low.
E4, E9 AVDD Analog 1.0V Supply Input
E11 AVDDPLL 1.0V DAC Clock PLL Supply
F1 SDI Digital CMOS Input/Output for Serial Port Interface. Data input in 4-wire SPI mode and data input/output
in 3-wire SPI mode.
F2 RESETB Digital CMOS Input with an Internal 50kΩ Pulldown Resistor. Device is reset when RESETB is low. Hold
RESETB low during device startup. RESETB must be set high for normal operation after startup.
F5-F8, G5,
G8 VDD 1.0V Supply Input for Digital Core
G1 SDO Digital CMOS Output for Serial Port Interface. Data output in 4-wire SPI mode.
G2 INTB Digital CMOS Output for Interrupt
G3 MUTE Digital CMOS Input. With MUTE high the DAC output is muted and with MUTE low, the DAC output is
active.
G4, G9,
H3-H4,
H9, J3-J4,
J9
VDD2 1.8V Supply Input for Digital I/O
H1, J1 SYNCNP,
SYNCNN
LVDS Output. Active-low JESD204B error reporting signal (SYNC~) from Rx device (DAC) to Tx device
(FPGA/ASIC).
H2, L1, L3,
L10, L12 DP0-DP4 Analog Input. JESD204B Serial Data Positive Input Lanes 0-4.
H3, H11,
J3, J11,
L6, L7
NC No Connect
H12, J12 TESTP,
TESTN Factory Use Only. Connect to GND.
J2, M1,
M3, M10,
M12
DN0-DN4 Analog Input. JESD204B Serial Data Negative Input Lanes 0-4.
K6-K7 RCLKP,
RCLKN
LVDS Reference Clock Output for Sample Rate Synchronization to DAC Clock. If not used, terminate
differential with a 100Ω resistor.
K11 TDA Temperature Sensor Diode Anode. Connect TDC and TDA to ground if not used.
L5 TESTEN Factory Use Only. Connect to GND.
L8 VDD2PLL JESD204B PLL 1.8V Power Supply
M5 JRES Analog Input. JESD204B Current Biasing.
M7 VSSPLL Clock Multiplier Unit (CMU) PLL Ground
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 19
Pin Description (continued)
PIN NAME FUNCTION
M8 CAPT Analog Input. JESD204B PLL Loop Filter Input.
M11 TDC Temperature Sensor Diode Cathode. Connect TDC and TDA to ground if not used.
Functional Diagrams
MOD
OUTP
OUTN
CLKP
CLKN
14-BIT
4.9Gsps
RF DAC
16
16
14
RCLKP
RCLKN
DP[4:0]
DN[4:0]
MUTE
RESETB
2x
INTB
5
PLL
AVDDPLL
PLL_COMP
MAX5855
2x
CSB
SCLK
SDI
SDO
SPI PORT
DCLK
SYNCN P/N
CODE GROUP SYNC
FRAME SYNC/MONITORING
INTERLANE ALIGNMENT
DESCRAMBLER (OPTIONAL)
Rx LINK
Rx FIFO
8B/10B DECODER
Rx MAPPER
Rx PHY
Rx CONTROLLER
VGA
CLOCK
MULTIPLIER
UNIT
DECISION FEEDBACK
EQUALIZER
CLOCK +
DATA
RECOVERY
DEMUX
JESD204B INTERFACE (5 LANES)
CLOCK GENERATION
AND DISTRIBUTION
AVDD2PLL
VDD2PLL
VSSPLL
JRES
CAPT
CHARACTER REPLACEMENT VCOBYP
2x
2x
F1 F2
F1 F2
CSBP
REFIO
FSADJ
DACREF
REFERENCE
SYSTEM
VDD
AVDD
AVCLK
VDD2
AVDD2
AVCLK2
GND
÷ N
QUADRATURE
NCO
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 20
Functional Diagram
Detailed Description
The MAX5855 is a high-performance, interpolating and modulating, 14-bit, 4.9Gsps RF DAC designed for DOCSIS 3.1/
3.0 remote PHY devices, CCAP, digital video broadcast modulators, point-to-point wireless, and instrumentation. The
device can synthesize up to 1GHz of instantaneous bandwidth at frequencies up to the Nyquist bandwidth (fDAC/2) of the
DAC. The major functional blocks of the device include a five-lane JESD204B interface which accepts 16-bit input data,
interpolation filters, a digital quadrature modulator and NCO, clock multiplying PLL + VCO and a 14-bit, 4.9Gsps RF DAC
core. The supporting functional blocks include the clock distribution system, reference system, and SPI interface. See
the detailed Functional Diagram.
The 16-bit input data enhances the accuracy of the interpolation and modulation functions and ensures true 14-bit data
is presented to the RF DAC core. The 16-bit input baseband data is supplied to the device using a five lane JESD204B
(DP[4:0]/DN[4:0]) interface operating at 9.8304Gbps.
The five-lane JESD204B interface has the following major components:
A high-speed input receiver (Rx) consisting of a physical (PHY) layer for each of the five lanes and a common clock
multiplier unit (CMU). The PHY layer contains a variable gain amplifier (VGA) which receives the incoming signal and
decision feedback equalizer (DFE) to suppress inter-symbol interference. The PHY layer also includes a clock and
data recovery (CDR) unit to latch the incoming single-bit data and a de-serializer (DEMUX) to convert the data to a
20-bit parallel data bus.
A receiver link layer (Rx Link) takes the 20 bits from the PHY and restores the 16-bit DAC data for each of the I and
Q channels. The Rx link consists of five Rx lanes, five Rx FIFOs, a Rx mapper and a Rx controller. The five Rx lanes
perform code group synchronization, 8b/10b decoding, frame synchronization and monitoring, interlane alignment and
monitoring, character replacement, and optional descrambling. The five lanes are fed into Rx FIFOs where data is
aligned by the Rx controller. Using the Rx mapper, data from each physical channel is mapped to a logical channel.
The DSP path consists of 4x linear phase interpolation filters for each of the I and Q channels. Interpolation reduces the
required input data rate to the device, relaxing the requirements on the FPGA or ASIC. In addition, interpolation increases
the separation between the desired signal and its aliased image easing filter design requirements.
After passing through the 4x interpolation stage, the complex signal is modulated using the LO signal generated by the
NCO and the digital quadrature modulator. The NCO allows for fully agile modulation of the input baseband signal for
direct RF synthesis with 32 bits of frequency-setting resolution. Placing the modulator at the output of the interpolator
chain allows for fully agile placement of the output carrier frequency within the Nyquist band of the DAC. The quadrature
modulator produces a real signal at its output, which is fed into the 14-bit DAC core where it is converted to an analog
RF signal. The analog output produces a full-scale current between 10mA and 40mA, driving 50Ω differential loads.
The clock distribution system provides a low-noise differential input buffer for the external master DAC clock (CLKP/
CLKN) and delivers all the necessary clocks to the internal blocks. The master DAC clock input accepts a differential sine-
wave or square-wave signal. A clock multiplying PLL and VCO is used to internally generate the 4915.2MHz sampling
clock using reference frequencies of 245.76MHz, 491.52MHz or 983.04MHz. The device provides a divided reference
clock (RCLKP/RCLKN) to ensure synchronization between the data source (FPGA or ASIC) and the DAC. The SYNCN
output can be used for error reporting from the DAC to the data source.
The reference system delivers the reference current to the DAC current source array and all bias currents necessary
for circuit operation. The reference system also includes a bypassable band-gap reference, which can be used as a
reference for the DAC full-scale current.
The SPI port is a bidirectional interface used for reading and writing status and control registers to configure the device.
The device operates from 1.0V and 1.8V power-supply voltages and consumes 2.7W at 4.9Gsps.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 21
(ngure 2
Supported DAC Update Rate and JESD204B Data Rates
Table 1. Complex I/Q Base Band Up-Conversion
DAC Update Rate: DACCLK (Msps) 4915.20
Input Sample Rate – I and Q each (MHz) 1228.8
Instantaneous Bandwidth (MHz) 1000
Table 2. Lane Rate
DACCLK (Msps) 4915.20
Number of JESD204B Lanes 5
Lane Rate (Mbps) 9830.4
JESD204B Interface
The JESD204B interface consists of five PHY lanes with one CMU. Each lane takes a 1-bit stream and converts it to a
20-bit bus. The link layer (LINK) takes the 20-bit bus from the PHY and restores the original 16-bit DAC data for each of
the I and Q channels (Figure 2).
The JESD204B receiver specifications are compliant with LV-OIF-6G-SR and LV-OIF-11G-SR specifications from the
JEDEC standard.
SYNC
LOGIC
LINK
20b
20b
20b
16b DSP AND
NCO
14b RF DAC
CLOCK
GENERATION
PLL
Div
1/2/4
SYNCN P/N
DP[4:0]
DN[4:0]
RCLK
CLK P/N
EXTERNAL DAC CLOCK
SOURCE AND
SYSTEM CLOCK
GENERATION
DACCLK
DCLK
( DEVICE CLOCK )
PHY
CMU
PHY
PHY
5
OUTP
OUTN
PHY
PHY 20b
20b
Figure 2. Simplified Diagram of JESD204B Internal to MAX5855
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 22
JESD204B Data Interface Features
A summary of the MAX5855 PHY and LINK features is provided below:
Rx PHY Features
Programmable gain
LINK Features
8b/10b decoding
Code group synchronization
Inter Lane Alignment (ILA)
1 + x14 + x15 polynomial scrambling
Character replacement
Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) compliant
Subclass-0 support
Number of lanes (L): 5
Number of data converters (M): 2
Number of octets per frame (F): 4
Number of samples per frame (S): 5
Other Features
Disable scramble mode
Elastic buffer depth of 320 serial bit-periods
Detection of following 8b/10b control characters: K28.0, K28.3, K28.4, K28.5, K28.7
Detection of following errors/conditions
8b/10b running disparity error
8b/10b not-in-table error
Unexpected control character detection
Code group synchronization error
Frame realignment detection
Lane realignment detection
Link configuration error
ILA failure detection
ILA sequence error
Various error conditions can be enabled for error reporting through SYNC~ interface
Continuous /K/ and ILA sequence detection
PHY PRBS data detection for debug
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 23
ngure 3 ngure 4 Figure 5
Mapping of Physical to Logical Channels
Each physical channel can be mapped to any logical channel before the octet-to-sample conversion. The octet-to-sample
conversion for the JESD204B link is determined by the number of lanes, number of octets-per-frame (JESD204B), and
number of samples per frame. The mapping required for proper operation of the MAX5855 is shown in Figure 3.
Lane 4
Lane 3
Lane 2
Lane 1
Lane 0
I4[15:8]
I4[7:0]
Q0[15:8]
Q0[7:0]
Q1[15:8]
Q1[7:0]
Q2[15:8]
Q2[7:0]
Q3[15:8]
Q3[7:0]
Q4[15:8]
Q4[7:0] MLFSN’ = 2_5_4_5_16
I0[15:8]
I0[7:0]
I1[15:8]
I1[7:0]
I2[15:8]
I2[7:0]
I3[15:8]
I3[7:0]
I9[15:8]
I9[7:0]
Q5[15:8]
Q5[7:0]
Q6[15:8]
Q6[7:0]
Q7[15:8]
Q7[7:0]
Q8[15:8]
Q8[7:0]
Q9[15:8]
Q9[7:0]
I5[15:8]
I5[7:0]
I6[15:8]
I6[7:0]
I7[15:8]
I7[7:0]
I8[15:8]
I8[7:0]
Figure 3. Octet-To-Sample Conversion
High-Speed Input Receiver (Rx)
As shown in Figure 4, the high-speed input receiver consists of a VGA, DFE (Decision Feedback Equalizer), CDR unit,
and DEMUX. The VGA and DFE provide autonomous adaptive equalization in order to optimize the input receiver filter
coefficients on a per-lane basis. The coefficients are optimized to best recover the data dependent jitter introduced by
the incoming channel. The initial receiver gain and equalization settings are shadowed by internal registers that the user
may override.
CDRDFE
DFE COEFFICIENT
VGA
VGA COEFFICIENT
RxP
RxN
EQUALIZER
COEFFICIENT
CONTROLS
20b
DEMUX
Figure 4. JESD204B Rx Physical Layer, Simplified Block Diagram
The VGA is a high-speed input receiver with high gain, allowing for excellent input sensitivity while still preserving the
linearity required for optimal performance of the DFE. The receiver expects the incoming high-speed signal to be driven
differential and AC-coupled to the transmitter. The receiver's common-mode input voltage is set by a self-biasing network
eliminating the need for any external board circuitry. The receiver provides 100Ω differential on-chip termination between
the true and complement input signals, RxP and RxN. The VGA gain settings are based on the amplitude of the incoming
signal and the optimal setting to the DFE circuitry; the gain range is ±20dB, as shown in Figure 5. In addition to the gain
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 24
function, there is also a boost function in the VGA to compensate for the high-frequency loss in the channel.
The PHY receiver automatically determines and sets the optimized level of equalization to suppress inter-symbol
interference (ISI) caused by a dispersive channel known as decision feedback equalization. The DFE makes use of
previously received data to estimate the current bit. Any trailing ISI caused by a previous bit is reconstructed and then
subtracted. This technique allows for the recovery of very glossy backplane and connector channels. The PHY equalizer
is designed to meet or exceed the JESD204B standard.
The CDR unit is responsible for the centering of the incoming data eye for optimal sampling and error free operation. The
PHY clock and data recovery unit has multiple loop bandwidth settings to aid in achieving optimal performance for jitter
tolerance.
The recovered clock generated from CDR is used to latch in the single bit data, then the DEMUX block de-serializes the
single bit to 20-bit parallel data bus to subsequently be used by the Rx LINK.
1071081091010 1011 1012
FREQUENCY (Hz)
40
20
0
-20
-40
-60
-80
GAIN (dB)
±20dB RANGE
HIGH-FREQUENCY
BOOST
3GHz
UNITY-GAIN BANDWIDTH
±20dB RANGE
Figure 5. VGA Gain Range
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 25
Figure 6 Figure 7 may MES] M M551
JESD204B Receiver Equalization
The MAX5855 JESD204B receiver equalization capability exceeds the JEDEC specification for maximum interconnect
length of 20cm.
The plots in Figure 6 demonstrate that the JESD204B receiver equalization capability over a 30in (76cm) length of cable
using the following test conditions:
Data Rate: 9.8304Gbps
Channel: 30in Nelco 4000-13SI plus cables and FMC connector
30in Nelco Traces = -14.7dB loss at 4.914GHz (see Figure 7)
Cables and connector ~ 3dB loss at 4.914GHz
BEFORE AFTER
Figure 6. Receiver Equalization Eye Diagram Before and After Lane Training
-50
-40
-30
-20
-10
0
201816141210864
20
FREQUENCY (GHz)
LOSS (dB)
4.914GHz, -14.687dB
Figure 7. Channel Loss Curve (30in Nelco)
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 26
Lane Skew Requirement
The skew between the various lanes is absorbed within the FIFOs and through the initial lane alignment process. The
FIFO depth determines the amount of lane skew that can be absorbed for a particular Rx LINK configuration. A FIFO
depth of 32 bytes would account for up to 320 SerDes bit periods of skew between the various lanes. In actuality,
the maximum supported skew is smaller than this due to multiple bytes written to and read from the FIFO in a single
write/read clock cycle in various modes. The maximum supported skew is also reduced due to the write- to read-clock
synchronization uncertainty. A minimum and maximum FIFO depth can be set (CfgRFIFO at address 0x041C) and the
configured FIFO range determines the actual lane skew supported by the MAX5855.
Link Layer (LINK)
The Rx LINK layer for the MAX5855 consists of 5 lanes interfacing to the 5 PHYs. The data from the 5 lanes is passed
through FIFOs in order to align the configured number of lanes in JESD204B Subclass-0 mode. The Rx controller
generates a SYNCN signal for error reporting as specified by the JESD204B standard. The data from the FIFOs are then
mapped into I and Q sample data for the DSP to process.
Each of the 5 lanes in the Rx LINK operates independently and includes code group synchronization operating on
the 20-bit input from the PHY, 8b/10b decoding, frame synchronization and monitoring, lane alignment and monitoring,
character replacement and optional descrambling. All these functions are specified in the JESD204B standard. In
addition to extracting the octets, which are later combined into I and Q samples, the Rx LINK also monitors and acts on
various error conditions. Most error conditions can be enabled for error reporting to the transmit logic service through the
SYNCN signal. See link layer configuration registers for more detail.
Rx LINK
Rx LANE 3 Rx FIFO 3
RX
MAPPER
OCTETS
TO
SAMPLES
PHY 3
SYNC~
DCLK
(DEVICE CLOCK)
DATAI1[15:0]
SAMCLK
DATAQ1[15:0]
VALID
Rx LANE 4 Rx FIFO 4PHY 4
Rx LANE 5 Rx FIFO 5PHY 5
Rx CONTROLLER
(# LANES CONFIGURABLE)
Rx LANE 1 Rx FIFO 1PHY 1
Rx LANE 2 Rx FIFO 2PHY 2
Figure 8. JESD204B Receive Link Layer Block Diagram
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 27
Figure 10 Figure 1 1
Rx LANE
DATA_IN[19:0]
CLOCK
RESET
DATA_OUT[15:0]
FRAME START
MULTIFRAME START
CODE
GROUP
SYNC
8b10b
DECODING
FRAME
SYNC/
MONITORING
CHARACTER
REPLACEMENT
LANE
ALIGNMENT/
MONITORING
OPTIONAL
DESCRAMBLING
Figure 9. JESD204B Receive Lane Block Diagram
On the input-side of the Rx LANE there are 20 bits of data and the CLOCK from the PHY, along with a synchronous
RESET. On the output-side are 16 bits of data (two octets), FRAME START, and MULTIFRAME START signals, which
mark the two bytes of data.
Interface Timing for Subclass-0
The JESD204B LINK layer protocol requires the frame clock of both the transmitter and receiver devices to be
synchronized. Figure 10 shows the JESD204B-TX device’s synchronization with the MAX5855 using the SYNCN signal.
Initially, the internal clocks of the two devices are running independently. As shown, the SYNCN signal is generated by
the MAX5855 using its frame clock which, in turn, is used by the JESD204B-TX device to align its own frame clock.
The Rx Controller waits for the FIFO write to start in all the enabled lanes and then initiates a read start to all the FIFOs.
The FIFO reads start at the Frame/Multiframe boundary following the lane alignment sequence. This process aligns the
data on all enabled lanes with a minimum latency through the Rx LINK.
See JEDEC Standard No. 204B.01, Figure 11.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 28
SP1 to PCLK Frequency Ratio
INTERNAL FRAME INTERNAL FRAME
CLOCK AT RxCLOCK AT Rx
JESD204B SIGNALS AT Rx (RF DAC)JESD204B SIGNALS AT Rx (RF DAC)
HARMONIC DEVICE HARMONIC DEVICE
CLOCK AT RxCLOCK AT Rx
SYNC~ OUTPUT AT RxSYNC~ OUTPUT AT Rx
LAUNCH FROMLAUNCH FROM
DEVICE CLOCKDEVICE CLOCK
FRAME CLOCK PERIOD TFRAME
CAPTURE
HERE
tDS_R(max)
tDS_R(min)
INTERNAL FRAME INTERNAL FRAME
CLOCK AT TxCLOCK AT Tx
DEVICE DEVICE
CLOCK AT TxCLOCK AT Tx
JESD204B SIGNALS AT Tx (FPGA or ASIC)JESD204B SIGNALS AT Tx (FPGA or ASIC)
SYNC~ INPUT AT TxSYNC~ INPUT AT Tx
CAPTURE ONCAPTURE ON
FRAME CLOCKFRAME CLOCK
tSU_T(min) tH_T(min)
VALIDVALID
Figure 10. Interface Timing for Subclass-0
Serial Control Interface
The serial control interface is comprised of the CSB, SCLK, SDI, and SDO pins that support a typical 4-wire SPI interface.
It also supports a 3-wire SPI interface, where the SDI pin acts as both digital data input and output, commonly referred
to as SDIO.
The MAX5855 is always a slave device with the master controlling CSB, SCLK, and SDI. The SPI clock frequency
must meet certain constraints for proper operation and response from the MAX5855. See SPI to PCLK Frequency
Ratio section.
In 4-wire SPI interface mode, CSB, SCLK, and SDI are 1.8V CMOS-level digital input pins. SDO is a 1.8V CMOS output
signal when the MAX5855 is transmitting serial data. SDO is a high impedance output at all other times. CSB is the
chip-select pin. While CSB is low, the MAX5855 device is open to communication through the SCLK, SDI, and SDO
pins. Each communication cycle is comprised of a single read/write bit, a 15-bit address word, and an 8-bit data word.
The serial interface clock, SCLK, latches data into the MAX5855 on the rising edge and clocks data out of the MAX5855
on the falling edge. A logic '1' for the R/W bit signifies a read operation and a logic '0' indicates a write operation.
The R/W bit and the address word are sent to the device through the SDI pin. The R/W bit is transmitted first, followed
by the address word in MSB to LSB order while in the default MSB-first format. In the LSB-first format, the address word
is transmitted first, LSB to MSB, followed by the R/W bit. Input or output data are transmitted MSB or LSB-first order,
based on the format setting. Further descriptions assume MSB-first format.
For a write operation, a data word is immediately written to the SDI after the last bit of the address. For a read operation,
the data word is transmitted from the MAX5855 on the SDO signal line. The transmission starts on the falling edge of
SCLK immediately after the last bit is latched into the device. The SDO driver enters a high-impedance state on the next
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 29
T F WWWWWWM
falling SCLK edge immediately after the bit is transmitted. CSB must toggle from low to high and then back to low before
another communication cycle can resume. An exception is burst mode operation.
When burst mode is enabled, a continued assertion of CSB after the data word will auto decrement/increment the
address word depending on the configuration for a successive read/write. Every 8 cycles of SCLK will access a
successive address for either write or a read based on the R/W bit in the initial command.
CSB
SCLK
SDI
SDO
R/
W
A
14
A
13
A
12
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
A
0
A
1
A
2
A
3
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
Figure 11. SPI Single Write with MSB-First Format
CSB
SCLK
SDI
SDO
R/
W
A
14
A
13
A
12
A
0
A
1
A
2
A
3
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Figure 12. SPI Single Read with MSB-First Format
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 30
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CSB
SCLK
SDI
SDO
R/
W
A
1
A
2
A
3
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
0
A
14
A
13
A
12
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
Figure 13. SPI Single Write with LSB-First Format
CSB
SCLK
SDI
SDO
A
1
A
2
A
3
R/
W
A
14
A
13
A
12
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
0
Figure 14. SPI Single Read with LSB-First Format
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 31
CSB
SCLK
SDI
SDO
R/
W
A
1
4
A
1
3
A
1
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
A
0
A
1
A
2
A
3
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ADDRESS (a ± 1)ADDRESS (a)
Figure 15. SPI Burst Write with MSB-First Format
CSB
SDI
SDO
R/
W
A
1
4
A
1
3
A
1
2
A
0
A
1
A
2
A
3
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ADDRESS (a ± 1)ADDRESS (a)
SCLK
Figure 16. SPI Burst Read with MSB-First Format
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 32
T F j L L L LJ‘FLLflLLLLLflLL LL’L LLJF ‘ L LL LL JL FUN L J/ LJLL FLFLLLLFUFL LL LJ‘J L L J JfilLLflULLLLBULLLLUXLLEUXLLLU: H + % L/"L‘ LLLLJ‘LL a I, L L ‘ L L L L L L j FLL lJLWqflFmUMUMLMH LUFLWLMMULUWflflL LLMMJ MMLLLL— —CPLL]CCDDC}CUILUCLLJL % %
CSB
SCLK
SDI
SDO
R/
W
A
1
A
2
A
3
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
0
A
1
4
A
1
3
A
1
2
A
4
A
5
A
6
A
7
A
8
A
9
A
1
0
A
1
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
ADDRESS (a ± 1)ADDRESS (a)
Figure 17. SPI Burst Write with LSB-First Format
CSB
SCLK
SDI
SDO
A
1
A
2
A
3
R/
W
A
1
4
A
1
3
A
1
2
A
4
A
5
A
6
A
7
A
8
A
9
A
1
0
A
1
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
ADDRESS (a ±1)ADDRESS (a)
Figure 18. SPI Burst Read with LSB-First Format
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 33
Tab‘e 3 Figure 19
Interrupt Control
The INTB pin is a 1.8V CMOS logic output that signals an interrupt condition when in a low state. The interrupt system
is comprised of a status register and an interrupt mask register. The interrupt signal is an 8-input logic NOR of the
EINT register bit-wise ANDed with the DSP status register. The interrupt tree for the device is shown in Figure 19. The
JESD204B interface has its own second level of interrupt registers and interrupt mask registers as defined in the register
map. The interrupt masks and registers can be modified through the serial interface. Table 3 shows all the status register
bits that can be enabled to generate an interrupt.
JESD204B STATUS REGISTERS (5)
JESD204B INTERRUPT MASKS (5)
DSP STATUS REGISTER
EINT REGISTER
BIT-WISE
AND
INTB
7
BIT-WISE
AND
0
70
Figure 19. Interrupt Tree
Table 3. Status Register Bits
DSP Status Register (1st Level Interrupt)
BANK.REGISTER.BIT FUNCTION
DSP.STATUS.JSDIM Real-time, DAC mute from JESD LINK Layer is active
DSP.STATUS.JSDII Real-time, interrupt from JESD LINK Layer is active
DSP.STATUS.TRDY Latched, internal trim load is complete and the SPI
bus is unblocked for external access
DSP.STATUS.PLLlck Latched, DAC PLL was unlocked.
JESD204B Status Registers (2nd Level Interrupt)
BANK.REGISTER.BIT FUNCTION
RLaneRegs0-4.StatRlane.FrNSync Real-time, Frame synchronization state machine is not synchronized on Lane N
RLaneRegs0-4.StatRlane.LnReAlign Latched, lane realignment occured on Lane N
RLaneRegs0-4.StatRlane.FrReAlign Latched, frame realignment occured on Lane N
RLaneRegs0-4.StatRlane.DISP Latched, Disparity error detected on Lane N
RLaneRegs0-4.StatRlane.NIT Latched, NIT error detected on Lane N
RLaneRegs0-4.StatRlane.CGS Latched, Code Group Synchronization state-machine was not synchronized on Lane N
RLaneRegs0-4.StatRlane.FIFOempty Latched, FIFO empty on Lane N
RLaneRegs0-4.StatRlane.FIFOfull Latched, FIFO full on Lane N
RLaneRegs0-4.StatRlane.PRBSerr Latched, PHY interface PRBS monitor detected an error on Lane N
RLaneRegs0-4.StatRlane.KContErr Latched, non-/K/ character detected on Lane N
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 34
Table 3. Status Register Bits (continued)
RLaneRegs0-4.StatRlane.FChkErr Latched, ILA sequence FCHK error detected on Lane N
RLaneRegs0-4.StatRlane.LCfgErr Latched, ILA sequence lane configuration error detected on Lane N
RLaneRegs0-4.StatRlane.ILAerr Latched, ILA sequence decode (/R/, /Q/, /A/ character) error detected on Lane N
RLinkRegs.StatRlinkILA.ILAnsync Real-time, ILA synchronization not achieved
RLinkRegs.StatRlinkILA.ILAfailure Latched, ILA failed, indicates that at least one FIFO in a JESD lane overflowed before the
FIFO reads started.
RLinkRegs.StatRlinkPRBS.PRBSerr1 Latched, Converter 2 (Q-sample) PRBS error detected
RLinkRegs.StatRlinkPRBS.PRBSerr0 Latched, Converter 1 (I-sample) PRBS error detected
RLinkRegs.StatRlinkSTP.STPerr1 Latched, Converter 2 (Q-sample) short test pattern error detected
RLinkRegs.StatRlinkSTP.STPerr0 Latched, Converter 1 (I-sample) short test pattern error detected
Digital Control Pins
The MAX5855 contains two 1.8V CMOS logic input control pins: RESETB and MUTE. The device is placed in a reset
state when RESETB is logic-low. On power-up, RESETB should remain low until all supply voltages have stabilized and
an external clock is applied to CLKP/CLKN.
The MUTE pin and the register-based MUTE control when the device enters the mute mode. In mute mode, the DAC
digital input is set to mid-scale. A logic-high on the MUTE pin will place the device into mute mode while a logic-low may
allow normal operation. The main purpose of MUTE pin is to eliminate any transmit power during the receive time of
a TDMA system while the purpose of the MUTE bit is to protect the system PA during startup or error conditions. The
register-based mute can be configured through the serial interface enabling the mute mode internally regardless of the
state of the MUTE pin. Similar to the interrupt mask registers, there are mute enable registers which generate the internal
mute signal under defined conditions. Table 3 shows all the status register bits that can be used to generate the internal
mute. The states of all registers in the device are preserved while the RF DAC output is muted.
DAC
MUTE
MUTE_PIN
JESD204B STATUS REGISTERS (5)
JESD204B MUTE ENABLE (5)
DSP STATUS REGISTER
DSP EMUTE REGISTER
BIT-WISE
AND
BIT-WISE
AND
7 0 7 0
Figure 20. Mute Generation Logic
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 35
figure 21 figure 21 hown). 'DAC/Z
Frequency Planning
Using a DAC to generate RF transmission signals requires consideration of aliased harmonics and internally generated
divided clocks. To ensure the dominant second (HD2) and third order (HD3) harmonics do not fold back into the signal
band, the DAC update rate needs to be greater than four times the highest frequency in the band of interest.
Figure 21a and Figure 21b show the location of the 2nd and 3rd harmonic distortion products for the case of the DAC
being updated at 2 times and 4 times the maximum desired frequency in the band of interest (DOCSIS 3.1 example
shown).
fDAC/2
fDAC/2
1.25GHz
FREQUENCY
OF HARMONIC
DISTORTION
HD3 HD2
1.25GHz
0.625GHz
CABLE SIGNAL BAND
(54MHz TO 1218MHz)
REDUCES MARGIN
TO DOCSIS 3.1 SPEC
HD3 FOLDS BACK
INTO CABLE BAND
(54MHz TO 1218MHz)
AS fDAC IS LIMITED TO
2.5Gsps
(a) fDAC = 2.0 x fOUT(MAX)
fOUT
fDAC/3
0.833GHz
fDAC/4
0.625GHz
fOUT
FREQUENCY
OF HARMONIC
DISTORTION
fDAC/3
1.66GHz
HD3 HD2
1.25GHz
(b) fDAC ≥ 4.0 x fOUT(MAX)
2.5GHz
CABLE SIGNAL BAND
(54MHz TO 1218MHz)
fDAC/4
1.25GHz
fDAC/2
2.5GHz
HD3 DOES NOT
FOLD BACK INTO
CABLE BAND
(54MHz TO 1218MHz)
FOR fDAC ≥ 4.872Gsps
INCREASES MARGIN
TO DOCSIS 3.1 SPEC
Figure 21. Effect of DAC Update Rate on Folded HD2 and HD3
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 36
(figure 22
Quadrature Modulator and NCO
The device includes a quadrature modulator (Figure 22) that produces an image rejected Real output of the Complex
input I-data and Q-data, utilizing a complex numerically controlled oscillator (NCO).
The complex NCO employs a 33-bit phase accumulator to provide a RF signal frequency programmable from DC (0Hz)
up to fDAC/2. The user needs to calculate and program the following three parameters for proper configuration of the
NCO: the Frequency Control Word (FCW), the Numerator Frequency Word (NFW), and the Denominator Frequency
Word (DFW).
FCWfull =233 x fNCO
fDAC (1)
Where FCWfull is the real, floating point, or integer + fractional value of the Frequency Control Word, fDAC is the DAC
Sample Rate and fNCO is the target output center frequency of the NCO.
The full FCW is made up of the characteristic or Integer part of the quotient and the fractional remainder or mantissa
portion of FCWfull:
FCWfull = FCW + NFW
DFW (2)
Where FCW is represented by a 32-bit word, NFW is the Numerator Frequency Word represented by an 18-bit word and
the DFW is the Denominator Frequency Word represented with a 19-bit word.
The characteristic or integer part of FCWfull is the NCO’s primary Frequency Control Word. The remainder or mantissa
of the FCWfull quotient is converted into two rational integer numbers by removing the common integer multiplication
factor. This can be accomplished through brute-force means to find a numerator less than the decimal value of 262144
(218 – 1 or smaller) and a denominator less than 524288 (219 – 1 or smaller). The easiest way to calculate this fraction
would be to round the decimal remainder to 5 digits and divide by 100,000. Simplifying the fraction will result in valid
programmable values for NFW and DFW.
FCW = int
(
FCWfull
)
(3)
NFW
DFW = rem
(
FCWfull
)
(4)
When setting DFW to 100,000 and rounding the decimal remainder to 5 digits the mantissa can be accurately
represented as a ratio of two numbers: NFW and DFW.
To determine the programming precision of the NCO based on the least-significant bit (LSB) size of the NCO, use the
following equation:
FCW1Hz =233
fDAC (5)
Where FCW1Hz is the LSBs required (whole and fractional) to adjust the NCO frequency by a 1Hz step.
fNCO
/
LSB =1
FCW1Hz =fDAC
233 (6)
Where fNCO/LSB is the frequency change to the NCO (fNCO) given a single, whole LSB step of the NCO control word.
This fNCO/LSB value essentially shows the precision of the NCO with the largest step size being about 0.7Hz per LSB
change in the NCO control word. Using the fractional portion of the FCW will result in precision adjustments as small as
2.7μHz.
Example 1
Use the following system values to calculate the FCW, NFW, and DFW:
fDAC = 4915.2MHz, and fNCO = 575MHz
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 37
Starting with equation (1):
FCWfull =233 x fNCO
fDAC =233 x575M
4915.2M
FCWfull = 1004885333.3...
Using equations (3) and (4):
FCW = int
(
104885333.3333
)
= 1004885333
NFW
DFW = rem
(
1004885333.33333
)
= 0.33333
NFW
DFW =33333
100000 205
615
NFW = 205, DFW = 615
Equation (1) can be used in reverse to find an NCO frequency based off of an integer multiple of FCW (where the
fractional portion does not require programming):
fNCO =fDAC xFCW
233 =4915.2Mx1004885333
233
fNCO = 574.999999809MHz
The above result confirms that the target NCO frequency is produced to a sub-1Hz precision.
Calculating the fNCO/LSB using equation (6):
fNCO
/
LSB =fDAC
233 =4915.2M
233 = 0.5722Hz⁄LSB
Thus, without using the fractional NCO words, the NCO can be adjusted to a resolution of better than 0.6Hz and in this
example, set to a precise value within 0.191Hz of the target frequency.
Example 2
Use the following system values:
fDAC = 4915.20MHz, and fNCO = 573MHz
Using equation (1):
FCWfull =233 x fNCO
fDAC =233 x573M
4915.20M
FCWfull = 1001390080.00000
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 38
fl, FW
Using equations (3) and (4):
FCW = int
(
100390080.00000
)
= 1001390080
NFW
DFW = rem
(
1001390080.00000
)
= 0.00000
NFW = 0, DFW = 0
QUADRATURE
NCO
Figure 22. Complex NCO and Modulator
PHASE ACCUMULATOR
NFW > DFW -DFW REG
DFW
REG
+1
TRUNCATE SIN/COS MAPPING
FUNCTION
SIN
COS
FCW
Figure 23. NCO Block Diagram
The following is example Matlab code for calculating NCO values. When calculating FCW, NFW, and DFW, use long
format types for more precise results.
% Find out MAX5855 NCO values
format long
% Define DAC clock frequency
FDAC = 4915.2e6 x M
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 39
% Define desired NCO frequency
FNCO = 1796.769375e6;
FCW_full = 233 x FNCO/FDAC;
% Calculate FCW, NFW and DFW
FCW = floor(FCW_full)
rats(FCW_full-FCW)
% END
Analog Interface
Reference Interface
The device operates with either the on-chip 1.2V bandgap reference or an external reference voltage source as shown
in [[Setting the DAC Output Full-scale Using an (a) Internal or (b) External Reference Voltage]]a and [[Setting the
DAC Output Full-scale Using an (a) Internal or (b) External Reference Voltage]]b. REFIO serves as the input for an
external, low-impedance reference source, or as the reference output when the internal reference is used. REFIO must
be decoupled to DACREF with a 1μF capacitor when using the internal reference. REFIO must be buffered with an
external amplifier if heavier loading is required, due to the 10kΩ series resistance.
The reference circuit employs a control amplifier designed to regulate the full-scale, differential output current, IOUTFS.
The output current is calculated as follows:
IOUTFS = 32 x IREF (7)
IREF =VREFIO
RSET (8)
Where IREF is the reference output current and IOUTFS is the full-scale output current of the DAC.
In general, the dynamic performance of the DAC improves with increasing full-scale current. Using the 1.2V (typ) internal
reference and RSET of 960Ω results in the maximum full-scale output current of 40mA.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 40
fl? V 777777777
10kΩ
1µF
1.2V
REFERENCE
REFIO
FSADJ
CURRENT
SOURCE
ARRAY
DAC
IREF
DACREF
OUTP
OUTN
MAX5855
IREF = VREFIO
RSET
RSET
10kΩ
1µF
1.2V
REFERENCE
REFIO
FSADJ
CURRENT
SOURCE
ARRAY
DAC
IREF
DACREF
OUTP
OUTN
MAX5855
IREF = VREFIO
RSET
RSET
IN
OUT
2.5V TO 12.6V
MAX6161
0.1µF
GND
1.25V
(a) INTERNAL REFERENCE CONFIGURATION (b) EXTERNAL REFERENCE CONFIGURATION
Figure 24. Setting the DAC Output Full-Scale Using an (a) Internal or (b) External Reference Voltage
Analog Output
The device is a differential current-steering DAC with built-in output termination resistors. The outputs are terminated to
AVDD2 providing a 50Ω differential output resistance. In addition to the signal current, a constant current sink (IFIX) equal
to one half IOUTFS is connected to each differential DAC output. Figure 25 shows an equivalent circuit for the internal
output structure of the device. The circuit has some resistive, capacitive, and inductive elements. These elements have
been minimized in order to achieve the highest possible output bandwidth (2GHz, typical).
In addition, the device requires a differential external termination (i.e., double termination). This external termination can
be accomplished with a differential 50Ω load or a single-ended 50Ω load interfaced through a transformer. RF chokes to
the AVDD2 supply should be used with the transformer coupled output. A typical transformer coupled configuration for
high-frequency operation is shown in Figure 25.
I1 = IFIX + IOUTFS x ((2N – CODE)/2N
I2 = IFIX + IOUTFS x CODE/2N
1µF
2.2µH
AVDD2
2.2µH
0.01µF
0.01µF
6
4
1
3
T1
OUTN
OUTP
25Ω 25Ω
AVDD2
I2I1
MAX5855
Figure 25. Typical DAC Output Configuration
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 41
Clock PLL Figure 27 Figure 25 Electrical Characteristics
I1 = IFIX + IOUTFS x ((2N – CODE)/2N
I2 = IFIX + IOUTFS x CODE/2N
OUTN
OUTP
25Ω 25Ω
AVDD2
I2I1
MAX5855
25Ω 25Ω
AVDD2
Figure 26. Output Configuration for Low-Frequency Operation
For applications where the DC information is important, the output configuration in Figure 26 can be used. 25Ω resistors
to AVDD2 are required for DC coupling. The DC configuration will lower the output common-mode voltage which may
reduce performance slightly. The output termination along with the full-scale current must maintain a voltage swing within
the Output Compliance range of the device (as specified in the Electrical Characteristics table).
Clock Interface
The DAC contains a differential high-frequency clock input, CLKP/CLKN, and an internal clock multiplying PLL to ease
clock distribution. The DAC is updated on the rising edge of CLKP/CLKN at a frequency of 4915.2MHz. See the DAC
Clock PLL section for operation with the PLL.
The high-frequency clock should be a balanced, fully differential signal with a 50%, or near-50% duty cycle. The clock
input has internal (on-chip) 100Ω differential termination. The clock requires a minimum input power of 0dBm. The clock
inputs must be AC-coupled to the source as they are internally self-biased.
Clock Subsystem
Overview
The MAX5855 clock subsystem is outlined in Figure 27. The differential DAC input clock CLKP/N is received through a
differential clock interface buffer.
From the clock buffer output, the signal is used as a reference for the on-chip DAC PLL.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 42
OFF-CHIP DAC CLOCK SOURCE
AND SYSTEM CLOCK GENERATION
RF DAC
CLOCK GENERATION
DACCLK /
DEVICE CLOCK
RCLKP/N
EQUALIZATION
CDR
SERIAL TO PARALLEL
20b RX LINK LAYER
10/8B DECODING
ALIGNMENT
SAMPLE ASSEMBLY
DSP
NCO
DPx
DNx
16b 14b
DACCLK
clk_fx
PLL
CLKP/N
OUTP
OUTN
FRAME CLOCK
SYNC~
GENERATION
SYNCNP/N
DIV
1/2/4
CfgChipOM.RclkM1-0
CfgClkDiv.
RDIV3-0
CfgCMU1.
Cref_divsel1-0
RCLKi
FCLK
MUX
CfgClkDiv.
PCLKS1-0
PCLK
RCLKi
PCLK PCLK is used to program the registers at address 0x0400-0x0DFF
FCLK FCLK is the JESD frame clock divide down from DACCLK
RCLK RCLK is internal PLL reference clock as well as used by external FPGA,
and derived from DACCLK
CLOCK
MANAGEMENT
UNIT
DIV
1/2/4
Figure 27. MAX5855 Clock Subsystem
The DAC output signal phase noise and jitter will mostly be determined by the on-chip PLL performance. The reference
clock phase noise will dominate within the 100kHz PLL loop bandwidth. In that frequency range the input clock phase
noise will be amplified by 20 x log(FDAC/FREF).
DAC Clock PLL
The MAX5855 differential high-frequency clock input (CLKP/CLKN) accepts an external reference clock signal that is
multiplied internally by a phase-locked-loop (PLL). The PLL includes user-programmable multiplication factors which
provide flexibility in the reference clock selection. Figure 28 shows the functional block diagram of the PLL.
PHASE/
FREQUENCY
DETECTOR (PFD)
REFERENCE
DIVIDER
(1/2/4)
VCO/FEEDBACK
DIVIDER
(/20)
CHARGE
PUMP
POST DIVIDER
(/1)
DUAL
BAND
VCO
LOOP
FILTER
(EXTERNAL)
DACCLK
EXTERNAL
REFERENCE
CLOCK
Figure 28. DAC Clock PLL Functional Block Diagram
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 43
figure 29 Agglmat/‘ons Guidelines Frequency Sefiings and Canflgurat/‘on
The reference input signal is divided by 1, 2, or 4 under user control before being applied to the phase/frequency detector
(PFD). The VCO output is divided by a programmable divide-by 20 before it is fed back to the PFD.
VCO Band Select
The VCO has a frequency range that supports 4.9152GHz operation. The combination of reference frequency, reference
divide and feedback divide values, and VCO band select must be chosen to operate the VCO within its allowed frequency
range.
Lock Detect
The DAC clock PLL includes a lock detect indicator which can be read out of the SPI status register (DSP.StatPLL0). Bit
PLL_LOCK is set high when the PLL is locked and low when the PLL is unlocked.
PLL External Components
The DAC clock PLL requires external loop filter components. Figure 29 shows the schematic for the loop filter. The
loop filter components should be placed as close as possible to the MAX5855 to avoid noise coupling into the circuit.
In addition to the loop filter, there is a bypass capacitor that must be placed very close to the MAX5855. The C1 nF
and C2 pF capacitor values strongly depends on system PCB design and are unique for most designs (see Applications
Guidelines).
The user may wish to select different operating conditions for the PLL loop filter than those specified. The following values
may be useful for calculating new compensation component values:
VCO Gain: KVCO = 115MHz/V
Charge Pump Current: ICP = 480µA
PLL Feedback Divider Setting: N = <CfgPLL2.DVAL[3:2] and CfgPLL1.DVAL[1:0]>
Internal Smoothing Capacitance: CS= 43pF
VCOBYP PLL_COMP
MAX5855
C2 2.7kΩ
430pF
0Ω
C1
Figure 29. DAC Clock PLL External Components
RCLK Description and Use
The MAX5855 outputs a divided reference clock RCLK (RCLKP/RCLKN) that is equal to the DAC clock frequency divided
by a factor (Defined by programming the register bits DSP.CfgClkDiv.RDIV) to ensure synchronization with the system
clock. Caution must be exercised when programming the DSP.CfgClkDiv.RDIV register due to its performance impact on
other internal blocks. See Frequency Settings and Configuration section for more details.
The output clock RCLKP/RCLKN frequency can be further lowered by programming the control bits in the
DSP.CfgChipOM.RclkM register.
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 44
Tab‘e 4
Interpolation Filters
The MAX5855 has powerful digital signal process capability with its built-in digital interpolation filters with an interpolation
ratio of 4x (complex path). Table 4 shows the digital filter coefficients of 4x (F1 2x, F2 2x cascaded) interpolation ratios.
Table 4. Digital Filter Coefficients
TAP F1 2x (COMPLEX PATH) F2 2x (COMPLEX PATH)
1 0.00004577636718750 0.00138854980468750
2, 4, 6, 8, 12, 14, 16, 18 0 0
3 -0.00015258789062500 -0.01086425781250000
5 0.00039672851562500 0.04589843750000000
7 -0.00083923339843750 -0.14880371093750000
9 0.00161743164062500 0.61239624023437500
10 0 1
11 -0.00286865234375000 0.61239624023437500
13 0.00479125976562500 -0.14880371093750000
15 -0.00762939453125000 0.04589843750000000
17 0.01168060302734380 -0.01086425781250000
19 -0.01736450195312500 0.00138854980468750
20, 22, 24, 26, 28, 30, 32, 36, 38, 40, 42,
44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66 0
21 0.02522850036621090
23 -0.03616333007812500
25 0.05177307128906250
27 -0.07537841796875000
29 0.11575317382812500
31 -0.20507812500000000
33 0.63421630859375000
34 1
35 0.63421630859375000
37 -0.20507812500000000
39 0.11575317382812500
41 -0.07537841796875000
43 0.05177307128906250
45 -0.03616333007812500
47 0.02522850036621090
49 -0.01736450195312500
51 0.01168060302734380
53 -0.00762939453125000
55 0.00479125976562500
57 -0.00286865234375000
59 0.00161743164062500
61 -0.00083923339843750
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 45
Table 4. Digital Filter Coefficients (continued)
63 0.00039672851562500
65 -0.00015258789062500
67 0.00004577636718750
Register Definition and Description
The detailed description about the configuration registers in the MAX5855 can be found in the Register Map section,
which can be configured through SPI serial control interface.
SPI to PCLK Frequency Ratio
The MAX5855 use a internally generated clock (PCLK) for the configuration of registers with the address between
0x0400 and 0x0DFF (RLinkRegs, RLaneRegs0-4, SerDesRegs, CMURegs, PHY0-4 register banks). PCLK is simply
a divided down version of the internal DAC clock (DACCLK), and varies in proportion to that frequency. PCLK has the
minimum and maximum frequency range required for the proper operation of the device.
PCLK must be at least 14 times faster than the SPI clock.
PCLK frequency cannot be greater than 300MHz.
This clock period relation is not required if the user is accessing any register below the 0x0400 address range (GLBL and
DSP banks). The PCLK can be set in the DSP.CfgClkDiv.PCLK to 0x1, which uses the RCLK as the PCLK source. This
configuration must be performed before accessing any register between addresses 0x0400 and 0x0DFF.
To select RCLK, write the appropriate division factor noted in the DSP.CfgClkDiv.RDIV register description.
SPI to fDAC Frequency Ratio
The DAC clock is used to derive internal functional clocks and these divided-down clocks interact with the SPI clock
(SCLK) during the register configuration. Therefore, the SPI clock frequency selection must not exceed 20MHz.
Note: SPI interface also has hold time requirement for the CSB pin. The hold time between a CSB signal going HIGH
to the falling edge of last SCLK is 48 fDAC clock periods. See Electrical Characteristics notes for other serial interface
timing details.
Device Configuration
The device configuration must be performed using a prescribed sequence.
The first step is to configure the SPI interface format. This is done by writing to the SPI register GLBL.CfgIFA at address
0x00. The control bits in this register form a symmetrical word (palindrome) such that the register can be programmed
regardless of preexisting LSB-first or MSB-first operation. After writing to this register, the SPI interface will be ready for
further programming.
The clock mode and the PLL must be configured immediately after the SPI interface.
The next step in the device configuration involves setting up the internal clocks while the CLKP/CLKN input is active.
Programming and enabling the PLL clock path may result in internal glitches due to the clock path MUX and PLL
settling. Once the PLL is enabled, the user must wait at least 20ms to allow the PLL to settle and lock before continuing
on to the next configuration step.
The final step in configuring the PLL is to reset the internal clock dividers. The states of the dividers may have been
corrupted by clock glitches during the preceding process.
If the device is powered up close to the low limit of the operating temperature range (cold), the digital PLL tuning may
lock into a state which is not optimized for hot operation. To address this issue, it may be necessary to wait until the
device self-heats before a restart of the PLL digital tuning is initiated. A 200ms wait cycle is recommended after the part
is configured to allow for warm-up if needed.
After the PLL digital tuning has been restarted, it is necessary to wait 20ms for the PLL to settle and lock again prior to
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 46
figure 30
resetting the internal clock dividers.
Once these preceding configurations are complete, the user should allow about 1ms for the internal DSP path to clear
out before enabling the DAC output (unmute). If this pause is not included, the DAC output may produce spurious signals
due to erroneous data flushing through the DSP signal path.
The MAX5855 configuration sequence is shown in the flowchart of Figure 30.
START
Perform Soft Reset and Configure
Basic Mode of Operation
(Registers CfgIFA, CfgDACrate,
CfgCLKrate and CfgChipOM)
Configure PLL
(Registers CfgPLL1 and CfgPLL2)
Enable PLL VCO
(CfgPLL1.PLL_BYP = 0)
Enable PLL Digital Tuning
(CfgPLL0 = 0x03)
Wait 20ms for PLL to Lock
Reset Clock Divider by Toggling
CfgDev.CDrst Bit
(CfgDev.CDrst = 1
CfgDev.CDrst = 0)
Configure JESD204B Interface
MLFS.L
Configure DSP Mode and Load the
NCO Configuration
(Register CfgDSP)
Program NCO Frequency
Wait 1ms for the data in the DSP
Path to Flush
Un-Mute the DAC Output
(CfgChipOM.Mute = 0)
End
Wait 200ms for Device to Warm Up
Restart PLL Digital Tuning by
Toggling CfgPLL0.MASTER Bit
(CfgPLL0.MASTER = 0
CfgPLL0.MASTER = 1)
Wait 20ms for PLL to Lock
Reset Clock Divider by Toggling
CfgDev.CDrst Bit
(CfgDev.CDrst = 1
CfgDev.CDrst = 0)
It Will Also Reset FIFO
Configure RCLK and PCLK rate,
after CfgDACrate and CfgCLKrate
(Register CfgClkDiv)
Re-Program CfgClkDiv based on
MLFS.L, which affects the PCLK
Configure JESD204B Interface
Including CMU
Figure 30. Device Configuration Flowchart
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 47
Frequency Settings and Configuration
Table 5. Frequency Planning and Configuration with CLKP/N Used as JESD204B Device
Clock
FRAME/SAMPLE
EXTERNAL FRAME/
SAMPLE
DIV DACCLK
FRAME RATE
DIV 1
FRAME RATE
DIV 2
FRAME RATE
DIV 4
DACCLK
FREQUENCY
(GHz)
UPDATE
RATE
JESD
LANES
SAMPLE/
FRAME
LANE
RATES
(Gbps)
INPUT
CLOCK
(MHz)
CONFIG
CLOCK
RATE
INPUT
CLOCK
(MHz)
CONFIG
CLOCK
RATE
INPUT
CLOCK
(MHz)
CONFIG
CLOCK
RATE
JESD
F-
RATE
(MHz)
CLOCK
DIV F-
RATE
4.91520 5 5 5 9.8304 245.76 0 491.52 3 983.04 5 245.76 20
Update Rate Selected DAC update rate multiplier: GLBL.CfgDACrate.Drate
JESD Lanes Number of JESD Lanes: RLinkRegs.CfgRLinkParam1.CfgL
Sample/Frame Number of JESD Samples Per Frame: RLinkRegs.CfgRLinkParam1.CfgS
Frame/Sample Clock source selection from the External Clock or a divided-down version of DACCLK:
RLinkRegs.CfgRlinkCtrl.rclk = 0 or 1, respectively. For device clock input less than 1GHz, set to 0.
Frame Rate Div X JESD Frame Rate divisor 1, 2, or 4 of the Device Clock with RLinkRegs.CfgRlinkSet.DDIV=0,
1, or 2 respectively
Input Clock External device clock CLKP/CLKN
Config Clock Rate Programmed CLKP configuration value: GLBL.CfgCLKrate.Crate
JESD F-Rate JESD Frame Rate derived from the DAC update rate
Clock Div F-Rate Clock divider setting to generate the JESD Frame Rate: DSP.CfgClkDiv.RDIV
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 48
Table 6
Configuration Script Tool
As noted in other sections of this document, proper sequential configuration of the MAX5855 DAC is essential to
operating the device as intended. To assist the user with this configuration process, a PERL script tool has been
developed which takes ten input parameters and provides an output file containing a sequence of commands that can be
written to the device in order to program it for these user-defined operating conditions.
The user provides the input parameters through a text file (with a .txt extension) and the script will generate a sequence
of SPI commands and stores them in an output text file (with a .cfg extension). The configuration parameters and the
acceptable options used to create the input text file are listed in Table 6.
Table 6. Configuration Input Parameters
ITEM PARAMETER OPTIONS COMMENTS EXAMPLE
1 DAC Rate 4915 Value in Msps, must be used as given in the options column 4915
2CLKPN
Rate 983, 491, 245 CLKP/CLKN clock rate in MHz Device Clock = 1 491
3 INTP Ratio 4 Interpolation Ratio, set to 4 4
4 Lane Count 5 Number of JESD204B lanes to be used 5
5 Subclass 0 JESD204B Subclass selection 0
6 Device Clock 1 JESD204B Frame sample clock derived from... CLKP/CLKN 1
7 SYSREF Mode 0 SYSREF mode, set to 0 0
8 NCO Frequency 0, 1, ..., 2948, 2949 fNCO in MHz, value between DC and the DAC Rate divided by 2 1000
9 RCLK Div 1, 2, 4 Sample-Rate-to-RCLK ratio 1
10 ScrambleDis 0JESD204B lane scrambler enabled 0
1 disabled
Example input file example_config.txt, contains the below parameter settings:
DAC Rate = 4915
CLKPN Rate = 491
INTP Ratio = 4
Lane Count = 5
Subclass = 0
Device Clock = 1
SYSREF Mode = 0
NCO Freq = 1000
RCLK Div = 1
ScrambleDis = 0
To execute the PERL script command line type the following:
perl gen_MAX585x_config.pl example_config.txt
Checking setup ...
Creating example_config.cfg file for following setup:
DAC update Rate ..... 4915MHz
CLKPN Input Rate .... 491MHz
DSP INTP Ratio ...... 4
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 49
RxLink Lane Count ... 5
RxLink Subclass ..... 0
RxLink Clock source . Device Clock
RxLink SYSREF mode .. One-shot
NCO Freq ............ 1000MHz
RCLK Out ............ Frame Rate/1
Scramble Disable .... 0 (1:off, 0:on)
(SERDES = 10G, Full Rate; Frame Rate = 245.75M)
The resulting output command file can be used to configure the device through the SPI. Each line of the .cfg file contains
the register address and the data value to be programmed. Within the output .cfg file, wait statements will be inserted at
the required points in the programming sequence to indicate a need for a pause before the next write command.
The following is list of the first 7 lines of the example_config.cfg output file:
// For Trimmed version of part
// Script version used: v1.0
// SS:MIN:HR:DAY:MM:YY
// 21:12:11:26:10:17
0x0000,0xBD; //GLBL.CfgIFA.AddIncr=1'b1, Wire4=1'b1, SftRst=1'b1 (self-clearing)
0x0010,0x05; //GLBL.CfgDACrate=4'b0101
0x0011,0x03; //GLBL.CfgCLKrate=4'b0011
...
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 50
091FA 7:0 SflRst LSBF Addlncr W1re4 Wire4 0 Addmcro LSEFO SltRstO 090:5 7:0 SIrmD1s rsvds M w M ClgDev[7:0 rsvd[4:0 00m PDM 1:01 ChiQTer[7:0 ‘ | Tyge 3:0 019101 7.0 CIDLSB 1:01 PID 1:0 F1013:0 019102 7.0 CIDMSE 7:0 ChiQRev 7.01 | Rev 3.01 Vend1017:01 VIDLSB 7:0 Vend102 7:01 v10M58 7.0 ClgDACrateUD 0ra1e[3:0 094:LKra1e[7:0 Cra1e13:0 ClgREGSUD M M ClgCh1gOM[7:0 RclkM 1.01 M m DFMT 090513 7.0 m RstDSP RleIFO m NCOLD ClgNCOFO 7:01 ch 7:01 ClgNCOF1 7:01 FCW 15:8 ClgNCOFZ 7:01 FCW[23:16 09NCOF3 7:01 FCW[31:24 0ch010 7:0 NFW 7:01 0ch0011 7:0 NFW 15:8 0ch012 7:0 NFW17,16 09110000 7:0 DFW 7:01 09110001 7:0 DFW 15:8 09110002 7:0 DFW1E,16 0ch00 7,0 RLM 1:01 ClgNCOUTO 7.0 TM 70 ClgNCOUT1 7.0 TM 70 ClgNCOUTZ 7.0 TM 70 ClgPM 7:0 | | | w m M 09pm 7.0 PMT[7:0 0912111100 7.0 PMIC 7:01 ClgPMIC1 7.0 PMIC 7:01 0912111102 7.0 PMIC 7:01 0912111103 7.0 PMIC 7:01 0912111104 7.0 PMIC 7:01
Register Map
MAX5855
ADDRESS NAME MSB LSB
GLBL
0x00 CfgIFA[7:0] SftRst LSBF AddIncr Wire4 Wire4_0 AddIncr0 LSBF0 SftRst0
0x01 CfgIFB[7:0] StrmDis rsvd6 rsvd4 rsvd3 rsvd0
0x02 CfgDev[7:0] rsvd[4:0] CDrst PDM[1:0]
0x03 ChipType[7:0] – – – – Type[3:0]
0x04 ChipID1[7:0] CIDLSB[1:0] PID[1:0] FID[3:0]
0x05 ChipID2[7:0] CIDMSB[7:0]
0x06 ChipRev[7:0] – – – – Rev[3:0]
0x0C VendID1[7:0] VIDLSB[7:0]
0x0D VendID2[7:0] VIDMSB[7:0]
0x10 CfgDACrate[7:0] – – – – Drate[3:0]
0x11 CfgCLKrate[7:0] – – – – Crate[3:0]
0x12 CfgREGS[7:0] – – – – – – rsvd IntCfg
DSP
0x100 CfgChipOM[7:0] RclkM[1:0] INVQ Mute DFMT
0x101 CfgDSP[7:0] R[3:0] RstDSP RstFIFO NCOE NCOLD
0x102 CfgNCOF0[7:0] FCW[7:0]
0x103 CfgNCOF1[7:0] FCW[15:8]
0x104 CfgNCOF2[7:0] FCW[23:16]
0x105 CfgNCOF3[7:0] FCW[31:24]
0x106 CfgNCON0[7:0] NFW[7:0]
0x107 CfgNCON1[7:0] NFW[15:8]
0x108 CfgNCON2[7:0] – – – – – – NFW[17:16]
0x109 CfgNCOD0[7:0] DFW[7:0]
0x10A CfgNCOD1[7:0] DFW[15:8]
0x10B CfgNCOD2[7:0] – – – – – DFW[18:16]
0x10C CfgNCOU[7:0] – – – – – – RLM[1:0]
0x10D CfgNCOUT0[7:0] TIM[7:0]
0x10E CfgNCOUT1[7:0] TIM[7:0]
0x10F CfgNCOUT2[7:0] TIM[7:0]
0x110 CfgPM[7:0] – – – – – Start Mode Reset
0x111 CfgPMT[7:0] PMT[7:0]
0x112 CfgPMIC0[7:0] PMIC[7:0]
0x113 CfgPMIC1[7:0] PMIC[7:0]
0x114 CfgPMIC2[7:0] PMIC[7:0]
0x115 CfgPMIC3[7:0] PMIC[7:0]
0x116 CfgPMIC4[7:0] PMIC[7:0]
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 51
ClgPMICS 7 0 PMIC 7:0 S'atFMO 7:0 FMST 7 0 S'atFM1 7:0 PMDON PMST 3 0 ClgSynC 7 0 CIKDW S m ClgFIFO 7:0 rsvd 4:0 SwaQIQ RevEKOr d ClgRSVO 7:0 RSV70 ClgRSV1 7:0 RSV70 ClgRSVZ 7:0 RSV70 ClgRSV3 7:0 RSV70 EMUTE 7 0 EM70 E1NT7:0 1NT EN 7:0 STATUS17:0] JSD‘M JSDH rsvd12:01 TRDY FLLICk RSVD7 7:0 rsvd 7:0 DEVSNO 7:0 DEVSN1 7:0 SN70 DEVSN2 7:0 ClgPLLO 7:0 MASTE R ClgPLL1 7:0 M DVALO 1 0 PVAL RVALO ClgPLL2 7:0 DVAL1 1:0 RVAL1 VCO SE S'atFLLO 7:0 rsvd 3:0 FLL LO % ClgClka 7 0 RDIV 3:0 RSV10 POLK 1 0 ClgRLmkSe131:24 ClgRLmkSe123:16 Synclnll SyncPo‘ ClgRLmkSe1 15:8 IgnDlsg ScrmD ClgRLmkSe17 0 DDW 1:0 Subc‘ass 1 0 RSISRL RSULA ClgRLmkParam1 31:24 CfgS 4:0 ClgRLmkParam1 23:16 (3ng 7 0 ClgRLmkParam1 15:8 ClgL 4:0 ClgRLmkParam1 7 0 (3ng 7:0 ClgRLmkParamZ 31:24 D1D70 ClgRLmkParamZ 23:16 B|D30 ClgRLmkParamZ 15:8 CngF 2 0 CigN 4 0 ClgRLmkParamZ 7 0 Cng 4:0 ClgRLkalrl 31 :24 ClgRLkalrl 23:16 SCIrI 1 0
ADDRESS NAME MSB LSB
0x117 CfgPMIC5[7:0] PMIC[7:0]
0x118 StatPM0[7:0] PMST[7:0]
0x119 StatPM1[7:0] PMDON
E– – – PMST[3:0]
0x15A CfgSync[7:0] ClkDiv_S
ync – – – – – –
0x15B CfgFIFO[7:0] rsvd[4:0] DupI SwapIQ RevBitOr
d
0x15D CfgRSV0[7:0] RSV[7:0]
0x15E CfgRSV1[7:0] RSV[7:0]
0x15F CfgRSV2[7:0] RSV[7:0]
0x160 CfgRSV3[7:0] RSV[7:0]
0x162 EMUTE[7:0] EM[7:0]
0x163 EINT[7:0] INT_EN[7:0]
0x164 STATUS[7:0] JSDIM JSDII rsvd[2:0] TRDY PLLlck
0x165 RSVD7[7:0] rsvd[7:0]
0x166 DEVSN0[7:0] SN[7:0]
0x167 DEVSN1[7:0] – – – – – – – –
0x168 DEVSN2[7:0] – – – – – – – –
0x180 CfgPLL0[7:0] – – – – – – – MASTER
0x181 CfgPLL1[7:0] PLL_BY
PDVAL0[1:0] PVAL RVAL0 – –
0x182 CfgPLL2[7:0] – – – DVAL1[1:0] RVAL1 VCO_SE
L
0x183 StatPLL0[7:0] rsvd[3:0] PLL_LO
CK – – –
0x185 CfgClkDiv[7:0] RDIV[3:0] RSV[1:0] PCLK[1:0]
RLinkRegs
0x400
CfgRLinkSet[31:24] – – – – – – – –
CfgRLinkSet[23:16] – – – – – – SyncInit SyncPol
CfgRLinkSet[15:8] – – – – – – IgnDisp ScrmD
CfgRLinkSet[7:0] – – DDiv[1:0] Subclass[1:0] RstSRL RstILA
0x404
CfgRLinkParam1[31:24] – – – CfgS[4:0]
CfgRLinkParam1[23:16] CfgF[7:0]
CfgRLinkParam1[15:8] – – – CfgL[4:0]
CfgRLinkParam1[7:0] CfgM[7:0]
0x408
CfgRLinkParam2[31:24] DID[7:0]
CfgRLinkParam2[23:16] HD – – – BID[3:0]
CfgRLinkParam2[15:8] CfgNP[2:0] CfgN[4:0]
CfgRLinkParam2[7:0] – – – CfgK[4:0]
0x410 CfgRLinkCtrl[31:24] – – – – – – – –
CfgRLinkCtrl[23:16] SCtrl[1:0] DFSync – – – –
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 52
ClgRLkalrl 15:8 SErrC ClgRLkalrl 7 0 BItSwaQ AsynCAvl fl ClgRLmkMFrame 31 24 1 SNum 7 ClgRLmkMFrame 2316 1 SNum 6 0 MFSe‘ B ClgRLmkMFrame 15 B MFSeI 7 0 ClgRLmkMFrame 7 0 ILADIy 5 ClgRSYNCN 31 24 ClgRSYNCN 2316 ClgRSYNCN 15 B ReQErr1 ReQErr1 ReQErr1 ReQErM @‘ffl ReQEer RegErr8 ClgRSYNCN 7 0 ReQErr6 ReQErr5 ReQErrZ ReQErr1 RegErrO ClgRFIFO 31 :24 ClgRFIFO 23:16 ClgRFIFO 15:8 MaxFD 4 0 ClgRFIFO 7 0 MmFD 4:0 ClgRTestCtrl 31 24 LnCany QeSe‘ 3 ClgRTestCtrl 23 16 LnCnITerSeI 2 0 RXCMLaneSe‘ 4:0 ClgRTestCtrl 15 B SamLoa d RxLOad CDCorEn Rsde ClgRTestCtrl 7 0 PRBSI 6 1:0 RXPRES w SamPRE S15En ClgRLmkSTP1 31 :24 ClgRLmkSTP1 23:16 ClgRLmkSTP1 15:8 Samp‘e1 15:8 ClgRLmkSTP1 7 0 Samgle1 7 0 ClgRLmkSTP2 31 :24 ClgRLmkSTP2 23:16 ClgRLmkSTP2 15:8 Samp‘e2 15:8 ClgRLmkSTP2 7 0 Samgle2 7 0 ClgRLmklntEn 31:24 ClgRLmklntEn 23:16 ClgRLmklntEn 15:8 ClgRLmklntEn 7 0 \LAnsynC ILAfaII ClgRLmkMuteEn 31 :24 ClgRLmkMuteEn 23:16 ClgRLmkMuteEn 15:8 ClgRLmkMuteEn 7 0 \LAnsynC ILAfaII S'atRLmk‘LA 31 24 S'atRLmk‘LA 23 16
ADDRESS NAME MSB LSB
CfgRLinkCtrl[15:8] – – – – – – – SErrC
CfgRLinkCtrl[7:0] – – – – BitSwap AsyncAvl rclk
0x414
CfgRLinkMFrame[31:24
]– – – – – – SNum[8:7]
CfgRLinkMFrame[23:16
]SNum[6:0] MFSel[8]
CfgRLinkMFrame[15:8] MFSel[7:0]
CfgRLinkMFrame[7:0] – – ILADly[5:0]
0x418
CfgRSYNCN[31:24] – – – – – – – –
CfgRSYNCN[23:16] – – – – – – – –
CfgRSYNCN[15:8] RepErr1
4
RepErr1
3
RepErr1
2
RepErr1
1
RepErr1
0RepErr9 RepErr8
CfgRSYNCN[7:0] RepErr6 RepErr5 RepErr2 RepErr1 RepErr0
0x41C
CfgRFIFO[31:24] – – – – – – – –
CfgRFIFO[23:16] – – – – – – – –
CfgRFIFO[15:8] – – – MaxFD[4:0]
CfgRFIFO[7:0] – – – MinFD[4:0]
0x420
CfgRTestCtrl[31:24] – – – – – – – LnCntTy
peSel[3]
CfgRTestCtrl[23:16] LnCntTypeSel[2:0] RxCntLaneSel[4:0]
CfgRTestCtrl[15:8] SamLoa
dRxLoad CDcorEn Rsvd0 – –
CfgRTestCtrl[7:0] PRBStype[1:0] RxPRBS
en
SamPRB
S15En
0x424
CfgRLinkSTP1[31:24] – – – – – – – –
CfgRLinkSTP1[23:16] – – – – – – – –
CfgRLinkSTP1[15:8] Sample1[15:8]
CfgRLinkSTP1[7:0] Sample1[7:0]
0x428
CfgRLinkSTP2[31:24] – – – – – – – –
CfgRLinkSTP2[23:16] – – – – – – – –
CfgRLinkSTP2[15:8] Sample2[15:8]
CfgRLinkSTP2[7:0] Sample2[7:0]
0x430
CfgRLinkIntEn[31:24] – – – – – – – –
CfgRLinkIntEn[23:16] – – – – – – – –
CfgRLinkIntEn[15:8] – – – – – – – –
CfgRLinkIntEn[7:0] – – – – ILAnsync ILAfail
0x434
CfgRLinkMuteEn[31:24] – – – – – – – –
CfgRLinkMuteEn[23:16] – – – – – – – –
CfgRLinkMuteEn[15:8] – – – – – – – –
CfgRLinkMuteEn[7:0] – – – – ILAnsync ILAfail
0x438 StatRLinkILA[31:24] – – – – – – – –
StatRLinkILA[23:16] – – – – – – – –
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 53
S'atRLmk‘LA 15,8 S'atRLmk‘LA 7:0 \LAnsynC \LNaHur e S'atRLmkSTP 31 :24 S'atRLmkSTP 23:16 S'atRLmkSTP 15:8 S'atRLmkSTP 7:0 STPerr1 STPerrO S'atRLmkPRBS 31 24 S'atRLmkPRBS 23 16 S'atRLmkPRBS 15 E S'atRLmkPRBS 7:0 FRBSerr FRBSerr CMRLane‘m/‘d 31:24 CMRLane‘m/‘d 23:16 CMRLane‘m/‘d 15:8 \nant 15:8 CMRLane‘m/‘d 7,0 InVCM 7 0 CMRLaneDbg 31 24 CMRLaneDbg 23 16 CMRLaneDbg 15 8 DbgCnI 15 E CMRLaneDbg 7:0 DbgCnt 7,0 ClgRLaneSel 31,24 LnSrC 4 LKSe‘ ClgRLaneSe12316 ClgRLaneSel 15,8 ClgRLaneSel 7:0 L|D4 LnRsI ClaRLane‘n1En13124] DCOnIErr PRESerr KContErr FChKErr LClqErr \LAerr ClgRLane‘MEn 23,16 FIFOem IE FIFOIUH ClgRLane‘MEn 15,8 ClgRLane‘MEn 7 0 FrNSynC LnReAllg FrReA‘ \g n n DISP ClgRLaneMuleEn 31 ,24 1 DCOnIErr PRESerr KContErr FChKErr ClgRLaneMuleEn 23,16 1 FIFOIUH ClgRLaneMuleEn 15,8 ClgRLaneMuleEn 7:0 FrNSynC LnReAllg FrReA‘ \g n n DISP r: w S'atRLane 31 :24 DCOnIErr PRESerr KContErr FChKErr E S'atRLane 23:16 FIFOIUH S'atRLane 15:8 FIFODeQm 5 S'atRLane 7 0 FrNSynC LnReAllg FrReA‘ \g DISP CGS
ADDRESS NAME MSB LSB
StatRLinkILA[15:8] – – – – – – – –
StatRLinkILA[7:0] – – – – ILAnsync ILAfailur
e
0x43C
StatRLinkSTP[31:24] – – – – – – – –
StatRLinkSTP[23:16] – – – – – – – –
StatRLinkSTP[15:8] – – – – – – – –
StatRLinkSTP[7:0] – – – – – – STPerr1 STPerr0
0x440
StatRLinkPRBS[31:24] – – – – – – – –
StatRLinkPRBS[23:16] – – – – – – – –
StatRLinkPRBS[15:8] – – – – – – – –
StatRLinkPRBS[7:0] – – – – – – PRBSerr
1
PRBSerr
0
0x460
CntRLaneInvld[31:24] – – – – – – – –
CntRLaneInvld[23:16] – – – – – – – –
CntRLaneInvld[15:8] InvCnt[15:8]
CntRLaneInvld[7:0] InvCnt[7:0]
0x464
CntRLaneDbg[31:24] – – – – – – – –
CntRLaneDbg[23:16] – – – – – – – –
CntRLaneDbg[15:8] DbgCnt[15:8]
CntRLaneDbg[7:0] DbgCnt[7:0]
RLaneRegs 0
0x480
CfgRLaneSet[31:24] LnSrc[4:0] LkSel LnEn
CfgRLaneSet[23:16] – – – – – – – –
CfgRLaneSet[15:8] – – – – – – – –
CfgRLaneSet[7:0] – – LID[4:0] LnRst
0x484
CfgRLaneIntEn[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneIntEn[23:16] – – – – – – FIFOem
pty FIFOfull
CfgRLaneIntEn[15:8] – – – – – – – –
CfgRLaneIntEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x488
CfgRLaneMuteEn[31:24
]DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneMuteEn[23:16
]– – – – – – FIFOem
pty FIFOfull
CfgRLaneMuteEn[15:8] – – – – – – – –
CfgRLaneMuteEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x48C
StatRLane[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
StatRLane[23:16] – – – – – – FIFOem
pty FIFOfull
StatRLane[15:8] – – FIFODepth[5:0]
StatRLane[7:0] FrNSync LnReAlig FrReAlig DISP NIT CGS
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 54
1: 1: ClgRLaneSel 31,24 LnSrC 4 LKSe1 ClgRLaneSel 23,16 ClgRLaneSel 15,8 ClgRLaneSel 7:0 L|D4 LnRsI ClaRLane1mEn131241 DCOnIErr PRESerr KContErr FChKErr LClqErr 1LAerr ClgRLane1mEn 23,16 FIFOem FIFOIUH ClgRLane1mEn 15,8 ClgRLane1mEn 7 0 FrNSynC LnReAllg n FrReA1 19 Z _. ClgRLaneMuleEn 31,24 1 DCOnIErr PRESerr KContErr LClqErr ClgRLaneMuleEn 23,16 1 FlFOem m FIFOIUH ClgRLaneMuleEn 15,8 ClgRLaneMuleEn 7:0 FrNSynC LnReAllg n FrReA1 wg DISP z _. S'atRLane 31 :24 DCOnIErr PRESerr KContErr FChKErr LClqErr S'atRLane 23:16 FIFOem FIFOIUH S'atRLane 15:8 FIFODe 1h 5 S'atRLane 7 0 FrNSynC LnReAllg FrReA1 wg DISP r: w ClgRLaneSel 31,24 LnSrC 4:0 LKSe1 LnEn ClgRLaneSel 23,16 ClgRLaneSel 15,8 ClgRLaneSel 7:0 L|D4 LnRsI ClaRLane1mEn131241 DCOnIErr PRESerr KContErr FChKErr 1LAerr ClgRLane1mEn 23,16 FIFOIUH ClgRLane1mEn 15,8 ClgRLane1mEn 7 0 FrNSynC LnReAllg n FrReA1 wg DISP ClgRLaneMuleEn 31,24 1 DCOnIErr PRESerr KContErr FChKErr A 1LAerr ClgRLaneMuleEn 23,16 1 FIFOIUH ClgRLaneMuleEn 15,8 ClgRLaneMuleEn 7:0 FrNSynC LnReAllg n FrReA1 wg DISP r: w S'atRLane 31 :24 DCOnIErr PRESerr KContErr FChKErr E
ADDRESS NAME MSB LSB
n n
RLaneRegs 1
0x490
CfgRLaneSet[31:24] LnSrc[4:0] LkSel LnEn
CfgRLaneSet[23:16] – – – – – – – –
CfgRLaneSet[15:8] – – – – – – – –
CfgRLaneSet[7:0] – – LID[4:0] LnRst
0x494
CfgRLaneIntEn[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneIntEn[23:16] – – – – – – FIFOem
pty FIFOfull
CfgRLaneIntEn[15:8] – – – – – – – –
CfgRLaneIntEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x498
CfgRLaneMuteEn[31:24
]DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneMuteEn[23:16
]– – – – – – FIFOem
pty FIFOfull
CfgRLaneMuteEn[15:8] – – – – – – – –
CfgRLaneMuteEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x49C
StatRLane[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
StatRLane[23:16] – – – – – – FIFOem
pty FIFOfull
StatRLane[15:8] – – FIFODepth[5:0]
StatRLane[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
RLaneRegs 2
0x4A0
CfgRLaneSet[31:24] LnSrc[4:0] LkSel LnEn
CfgRLaneSet[23:16] – – – – – – – –
CfgRLaneSet[15:8] – – – – – – – –
CfgRLaneSet[7:0] – – LID[4:0] LnRst
0x4A4
CfgRLaneIntEn[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneIntEn[23:16] – – – – – – FIFOem
pty FIFOfull
CfgRLaneIntEn[15:8] – – – – – – – –
CfgRLaneIntEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x4A8
CfgRLaneMuteEn[31:24
]DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneMuteEn[23:16
]– – – – – – FIFOem
pty FIFOfull
CfgRLaneMuteEn[15:8] – – – – – – – –
CfgRLaneMuteEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x4AC StatRLane[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 55
SfiatRLane 23:16] m FIFOluH fl! SfiatRLane 15:8 FIFODe m 5 soatRLane 7 0 FrNSync ”R?" HR?“ DISP E C s ClgRLaneSe13124 LnSrc 4:0 LKSe‘ LnEn ClgRLaneSel 23,16 ClgRLaneSel 15,8 ClgRLaneSel 7:01 LID 4 1 LnRsl cvaRLane1mEn131 ,241 DConlErr PRESerr KContErr FChKErr LClqErr \LAerr ClgRLane‘mEn 23161 M FIFOluH fl! ClgRLane‘mEn 15,8 ClgRLanemEn 7 01 FrNSync ”R?" HR?“ DISP w G J—[é in RLaneMu‘eE" 31 2" DConIErr PRESerr KContErr FChKErr LclqErr \LAerr ClgRLaneMuleEn 23,16 FlFOem FIFOluH 1 fl! ClgRLaneMuleEn 15,8 ClgRLaneMuleEn 7:01 FrNSync ”R?" HR?“ DISP E C s SfiatRLane 31 :241 DConlErr PRESerr KContErr FChKErr LClgErr \LAerr SfiatRLane 23:16] m FIFOluH fl! SfiatRLane 15:8 FIFODe m 5 soatRLane 7 0 FrNSync ”R?" HR?“ DISP E C s ClgRLaneSe13124 LnSrc 4:0 LKSe‘ LnEn ClgRLaneSel 23,16 ClgRLaneSel 15,8 ClgRLaneSel 7:01 LID 4 1 LnRsl cvaRLane1mEn131 ,241 DConlErr PRESerr KContErr FChKErr LClqErr \LAerr ClgRLane‘mEn 23161 M FIFOluH fl! ClgRLane‘mEn 15,8 ClgRLanemEn 7 01 FrNSync ”R?" HR?“ DISP w CGS J—[é in RLaneMu‘eE" 31 24 DConIErr PRESerr KContErr FChKErr LClgErr \LAerr ClgRLaneMuleEn 23,16 FlFOem FIFOluH 1 m
ADDRESS NAME MSB LSB
StatRLane[23:16] – – – – – – FIFOem
pty FIFOfull
StatRLane[15:8] – – FIFODepth[5:0]
StatRLane[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
RLaneRegs 3
0x4B0
CfgRLaneSet[31:24] LnSrc[4:0] LkSel LnEn
CfgRLaneSet[23:16] – – – – – – – –
CfgRLaneSet[15:8] – – – – – – – –
CfgRLaneSet[7:0] – – LID[4:0] LnRst
0x4B4
CfgRLaneIntEn[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneIntEn[23:16] – – – – – – FIFOem
pty FIFOfull
CfgRLaneIntEn[15:8] – – – – – – – –
CfgRLaneIntEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x4B8
CfgRLaneMuteEn[31:24
]DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneMuteEn[23:16
]– – – – – – FIFOem
pty FIFOfull
CfgRLaneMuteEn[15:8] – – – – – – – –
CfgRLaneMuteEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x4BC
StatRLane[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
StatRLane[23:16] – – – – – – FIFOem
pty FIFOfull
StatRLane[15:8] – – FIFODepth[5:0]
StatRLane[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
RLaneRegs 4
0x4C0
CfgRLaneSet[31:24] LnSrc[4:0] LkSel LnEn
CfgRLaneSet[23:16] – – – – – – – –
CfgRLaneSet[15:8] – – – – – – – –
CfgRLaneSet[7:0] – – LID[4:0] LnRst
0x4C4
CfgRLaneIntEn[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneIntEn[23:16] – – – – – – FIFOem
pty FIFOfull
CfgRLaneIntEn[15:8] – – – – – – – –
CfgRLaneIntEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x4C8
CfgRLaneMuteEn[31:24
]DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
CfgRLaneMuteEn[23:16
]– – – – – – FIFOem
pty FIFOfull
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 56
ClgRLaneMuleEn 15 B ClgRLaneMuleEn 7:0 LnReAllg n FrNSynC FrReAhg DISP r: S S'atRLane 31:24 DCOnIErr PRESerr KContErr FChKErr i err S'atRLane 23:16 FIFOIUH S'atRLane 15:8 FIFODe 1h 5 S'atRLane 7 0 FrNS nc LnReAllg FrReAhg DISP r: w ClgSerDes 31 24 ClgSerDes 23 16 RXRate Se‘ ClgSerDes 15 B ClgSerDes 7:0 PhyWMode 1 0 50351 1 )0 E ClgTramACt 31:24 ClgTramACtZ . 6 ClgTramACt 15:8 ClgTramACt 7:0 Ln 4 Ln Ln2 Ln1 LnO ClgTramDeAd 31:24 ClgTramDeAd 23:16 ClgTramDeAd 15:8 ClgTramDeAd 7 0 Ln 4 Ln Ln2 Ln1 LnO Clg‘dleGate 31:24 Clg‘dleGate 23:16 Clg‘dleGate 15:8 Clg‘dleGate 7:0 Ln 4 Ln Ln2 Ln1 LnO ClgDoneGaLe 31 24 ClgDoneGaLe 23 16 ClgDoneGaLe 15 E ClgDoneGaLe 7:0 Ln 4 Ln Ln2 Ln1 LnO ClgResen/ed 31 24 ClgResen/ed 23 16 ClgResen/ed 15 B Rsvd 15:8 ClgResen/ed 7 0 Rsvd 7 0 Clg‘nLEnRLMS 31 :24 Clg‘nLEnRLMS 23:16 Clg‘nLEnRLMS 15:8 Clg‘nLEnRLMS 7 0 Ln 4 Ln Ln2 Ln1 LnO Clg‘nLEnTralnDn 31:24 Clg‘nLEnTralnDn 23:16 Clg‘nLEnTralnDn 15:8 Clg‘nLEnTralnDn 7 0 Ln 4 Ln Ln2 Ln1 LnO
ADDRESS NAME MSB LSB
CfgRLaneMuteEn[15:8] – – – – – – – –
CfgRLaneMuteEn[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
0x4CC
StatRLane[31:24] DContErr PRBSerr KContErr FChkErr LCfgErr ILAerr
StatRLane[23:16] – – – – – – FIFOem
pty FIFOfull
StatRLane[15:8] – – FIFODepth[5:0]
StatRLane[7:0] FrNSync LnReAlig
n
FrReAlig
n DISP NIT CGS
SerDesRegs
0x600
CfgSerDes[31:24] – – – – – – – –
CfgSerDes[23:16] – – – – – – RxRateSel[1:0]
CfgSerDes[15:8] – – – – – – – –
CfgSerDes[7:0] PhyWMode[1:0] BCast[1:0] PhyKill Rst
0x608
CfgTrainAct[31:24] – – – – – – – –
CfgTrainAct[23:16] – – – – – – – –
CfgTrainAct[15:8] – – – – – – – –
CfgTrainAct[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x60C
CfgTrainDeAct[31:24] – – – – – – – –
CfgTrainDeAct[23:16] – – – – – – – –
CfgTrainDeAct[15:8] – – – – – – – –
CfgTrainDeAct[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x610
CfgIdleGate[31:24] – – – – – – – –
CfgIdleGate[23:16] – – – – – – – –
CfgIdleGate[15:8] – – – – – – – –
CfgIdleGate[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x614
CfgDoneGate[31:24] – – – – – – – –
CfgDoneGate[23:16] – – – – – – – –
CfgDoneGate[15:8] – – – – – – – –
CfgDoneGate[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x618
CfgReserved[31:24] – – – – – – – –
CfgReserved[23:16] – – – – – – – –
CfgReserved[15:8] Rsvd[15:8]
CfgReserved[7:0] Rsvd[7:0]
0x61C
CfgIntEnRLMS[31:24] – – – – – – – –
CfgIntEnRLMS[23:16] – – – – – – – –
CfgIntEnRLMS[15:8] – – – – – – – –
CfgIntEnRLMS[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x620
CfgIntEnTrainDn[31:24] – – – – – – – –
CfgIntEnTrainDn[23:16] – – – – – – – –
CfgIntEnTrainDn[15:8] – – – – – – – –
CfgIntEnTrainDn[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 57
Clg‘nLEnSlgDet 31 24 Clg‘nLEnSlgDet 23 16 Clg‘nLEnSlgDet 15 B Clg‘nLEnSlgDet 7:0 Ln4 Ln 3 Ln Ln1 Ln ClgMuteEnRLMS 31 :24 ClgMuteEnRLMS 23:16 ClgMuteEnRLMS15:B ClgMuteEnRLMS 7 0 Ln4 Ln 3 Ln Ln1 Ln ClgMuteEnTralnDn 31 :2 fl ClgMuteEnTralnDn 23:1 Q] ClgMuteEnTralnDn 15:8 1 ClgMuteEnTralnDn 7 0 Ln4 Ln 3 Ln Ln1 Ln ClgMuteEnSlgDel 31 24 1 ClgMuteEnSlgDe123 16 1 ClgMuteEnSlgDel15 E ClgMuteEnSlgDel 7:0 Ln4 Ln 3 Ln Ln1 Ln S'atRLMS 31 :24 S'atRLMS 23:16 S'atRLMS 15:8 S'atRLMS 7 0 Ln4 Ln 3 Ln Ln1 Ln S'atTralnDn 31:24 S'atTralnDn 23:16 S'atTralnDn 15:8 S'atTralnDn 7 0 Ln4 Ln 3 Ln Ln1 Ln S'atSlgDet 31 24 S'atSlgDet 23 16 S'atSlg Del 15 B S'atSlg Del 7 0 Ln4 Ln 3 Ln Ln1 Ln ClgCMU1 31 :24 Rsvd1 Cd lune190 2 0 ClgCMU123:16 Crel dlvse11901:0 Rsde 13:10 ClgCMU1 15:8 Rsvd0 9 ClgCMU1 7 0 Rsde 1 0 FBD‘V 1:0 VCOSEL 1 0 EQU CTRL3 31 24 D1 Coefl 5:0 EQU CTRL3 2316 D2 Coefl 6:0 EQU CTRL3 15 B D3 Coefl 6:0
ADDRESS NAME MSB LSB
0x624
CfgIntEnSigDet[31:24] – – – – – – – –
CfgIntEnSigDet[23:16] – – – – – – – –
CfgIntEnSigDet[15:8] – – – – – – – –
CfgIntEnSigDet[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x628
CfgMuteEnRLMS[31:24] – – – – – – – –
CfgMuteEnRLMS[23:16] – – – – – – – –
CfgMuteEnRLMS[15:8] – – – – – – – –
CfgMuteEnRLMS[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x62C
CfgMuteEnTrainDn[31:2
4] – – – – – – – –
CfgMuteEnTrainDn[23:1
6] – – – – – – – –
CfgMuteEnTrainDn[15:8
]– – – – – – – –
CfgMuteEnTrainDn[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x630
CfgMuteEnSigDet[31:24
]– – – – – – – –
CfgMuteEnSigDet[23:16
]– – – – – – – –
CfgMuteEnSigDet[15:8] – – – – – – – –
CfgMuteEnSigDet[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x634
StatRLMS[31:24] – – – – – – – –
StatRLMS[23:16] – – – – – – – –
StatRLMS[15:8] – – – – – – – –
StatRLMS[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x638
StatTrainDn[31:24] – – – – – – – –
StatTrainDn[23:16] – – – – – – – –
StatTrainDn[15:8] – – – – – – – –
StatTrainDn[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
0x63C
StatSigDet[31:24] – – – – – – – –
StatSigDet[23:16] – – – – – – – –
StatSigDet[15:8] – – – – – – – –
StatSigDet[7:0] Ln__4 Ln__3 Ln__2 Ln__1 Ln__0
CMURegs
0x644
CfgCMU1[31:24] Rsvd1 – – – – cd_tune1p0[2:0]
CfgCMU1[23:16] Cref_divsel1p0[1:0] – – Rsvd0[13:10]
CfgCMU1[15:8] Rsvd0[9:2]
CfgCMU1[7:0] Rsvd0[1:0] FBDIV[1:0] VCOSEL[1:0] – –
PHY 0
0x80C
EQU_CTRL3[31:24] – – D1_coeff[5:0]
EQU_CTRL3[23:16] D2_coeff[6:0]
EQU_CTRL3[15:8] D3_coeff[6:0]
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 58
EQU CTRL3 7:0 D4 Coefl 6:0 EQU CTRL4 31 24 EQU CTRL4 2316 EQU CTRL415 B EQU CTRL4 7:0 AGC Coeff 7 0 EQU CTRL7 31 24 AGC ""1 D1 70 EQU CTRL7 2316 EQU CTRL7 15 B EQU CTRL7 7:0 EQU CTRLA3124 D1 "H150 EQU CTRLA 2316 D2 "H16 0 ECU CTRLA15E D3 "H16 0 ECU CTRLA 7:0 D4 "H16 0 ECU CTRLB 31 24 Capsel 1 0 EQU CTRLB 2316 EQU CTRLB 15 E EQU CTRLB 7:0 EYE MON2 31 :24 D1 ErrChFhPH 7 0 EYE MON2 23:16 D1 ErrChPhSeC 7:0 EYE MON2 15:8 EYE MON2 7 0 TX CTRL1 31 24 TX CTRL1 23 16 TX CTRL1 1523 Cd lune 2 0 TX CTRL1 7:0 EQU CTRLD 3124 DFE2 "H1D3 5:0 EQU CTRLD 2316 DFE2 "H1D2 6:0 EQU CTRLD 15 E DFE1 "H1D3 6:0 EQU CTRLD 7:0 DFE1 "H1D2 6:0 EQU CTRLE 3124 DFE41nI1 D3 6 0 EQU CTRLE 2316 DFE41nI1 D2 6 0 EQU CTRLE 15 E DFE31nI1 D3 6 0 EQU CTRLE 7:0 DFE31nI1 D2 6 0 EQU CTRLG 31 24 EQU CTRLG 23 16 EQU CTRLG 15 E AGCInII D3 7:0 EQU CTRLG 7:0 AGCInII D2 7:0 EQU CTRL3 31 24 D1 Coefl 5:0 EQU CTRL3 23 16 D2 Coefl 6:0
ADDRESS NAME MSB LSB
EQU_CTRL3[7:0] D4_coeff[6:0]
0x810
EQU_CTRL4[31:24] – – – – – – – –
EQU_CTRL4[23:16] – – – – – – – –
EQU_CTRL4[15:8] – – – – – – – –
EQU_CTRL4[7:0] AGC_coeff[7:0]
0x81C
EQU_CTRL7[31:24] AGC_init_D1[7:0]
EQU_CTRL7[23:16] – – – – – – – –
EQU_CTRL7[15:8] – – – – – – – –
EQU_CTRL7[7:0] – – – – – – – –
0x828
EQU_CTRLA[31:24] – – D1_init[5:0]
EQU_CTRLA[23:16] D2_init[6:0]
EQU_CTRLA[15:8] D3_init[6:0]
EQU_CTRLA[7:0] D4_init[6:0]
0x82C
EQU_CTRLB[31:24] – – – – capsel[1:0] Mode6G
phb
EQU_CTRLB[23:16] – – – – – – – –
EQU_CTRLB[15:8] – – – – – – – –
EQU_CTRLB[7:0] – – – – – – – –
0x83C
EYE_MON2[31:24] D1ErrChPhPri[7:0]
EYE_MON2[23:16] D1ErrChPhSec[7:0]
EYE_MON2[15:8] – – – – – – – –
EYE_MON2[7:0] – – – – – – – –
0x864
TX_CTRL1[31:24] – – – – – – – –
TX_CTRL1[23:16] – – – – – – – –
TX_CTRL1[15:8] – – – – – cd_tune[2:0]
TX_CTRL1[7:0] – – – – – – – –
0x880
EQU_CTRLD[31:24] – – DFE2_initD3[5:0]
EQU_CTRLD[23:16] DFE2_initD2[6:0]
EQU_CTRLD[15:8] DFE1_initD3[6:0]
EQU_CTRLD[7:0] DFE1_initD2[6:0]
0x884
EQU_CTRLE[31:24] DFE4Init_D3[6:0]
EQU_CTRLE[23:16] DFE4Init_D2[6:0]
EQU_CTRLE[15:8] DFE3Init_D3[6:0]
EQU_CTRLE[7:0] DFE3Init_D2[6:0]
0x88C
EQU_CTRLG[31:24] – – – – – – – –
EQU_CTRLG[23:16] – – – – – – – –
EQU_CTRLG[15:8] AGCInit_D3[7:0]
EQU_CTRLG[7:0] AGCInit_D2[7:0]
PHY 1
0x90C EQU_CTRL3[31:24] – – D1_coeff[5:0]
EQU_CTRL3[23:16] D2_coeff[6:0]
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 59
EQU CTRL3 15 8 D3 Coefl 6:0 EQU CTRL3 7:0 D4 Coefl 6:0 EQU CTRL4 31 24 EQU CTRL4 23 16 EQU CTRL4 15 B EQU CTRL4 7:0 AGC Coeff 7 0 EQU CTRL7 31 24 AGC ""1 D1 70 EQU CTRL7 2316 EQU CTRL715 B EQU CTRL7 7:0 EQU CTRLA3124 D1 "H150 EQU CTRLA 2316 D2 "H16 0 ECU CTRLA15E D3 "H16 0 EQU CTRLA 7:0 D4 "H16 0 ECU CTRLB 31 24 Capsel 1 0 % EQU CTRLB 2316 EQU CTRLB 15 E EQU CTRLB 7:0 EYE MON2 31:24 D1ErrChPhPH 7 0 EYE MON2 23:16 D1 ErrChPhSeC 7:0 EYE MON2 15:8 EYE MON2 7 0 TX CTRL1 31 24 TX CTRL1 23 16 TX CTRL1 1523 Cd lune 2 0 TX CTRL1 7:0 EQU CTRLD 3124 DFE2 "H1D3 5:0 EQU CTRLD 2316 DFE2 "H1D2 6:0 EQU CTRLD 15 E DFE1 "H1D3 6:0 EQU CTRLD 7:0 DFE1 "H1D2 6:0 EQU CTRLE 3124 DFE4‘nI1 D3 6 0 EQU CTRLE 2316 DFE4‘nI1 D2 6 0 EQU CTRLE 15 E DFE3‘nI1 D3 6 0 EQU CTRLE 7:0 DFE3‘nI1 D2 6 0 EQU CTRLG 31 24 EQU CTRLG 23 16 EQU CTRLG 15 E AGCInII D3 7:0 EQU CTRLG 7:0 AGCInII D2 7:0 EQU CTRL3 31 24 D1 Coefl 5'0
ADDRESS NAME MSB LSB
EQU_CTRL3[15:8] D3_coeff[6:0]
EQU_CTRL3[7:0] D4_coeff[6:0]
0x910
EQU_CTRL4[31:24] – – – – – – – –
EQU_CTRL4[23:16] – – – – – – – –
EQU_CTRL4[15:8] – – – – – – – –
EQU_CTRL4[7:0] AGC_coeff[7:0]
0x91C
EQU_CTRL7[31:24] AGC_init_D1[7:0]
EQU_CTRL7[23:16] – – – – – – – –
EQU_CTRL7[15:8] – – – – – – – –
EQU_CTRL7[7:0] – – – – – – – –
0x928
EQU_CTRLA[31:24] – – D1_init[5:0]
EQU_CTRLA[23:16] D2_init[6:0]
EQU_CTRLA[15:8] D3_init[6:0]
EQU_CTRLA[7:0] D4_init[6:0]
0x92C
EQU_CTRLB[31:24] – – – – capsel[1:0] Mode6G
phb
EQU_CTRLB[23:16] – – – – – – – –
EQU_CTRLB[15:8] – – – – – – – –
EQU_CTRLB[7:0] – – – – – – – –
0x93C
EYE_MON2[31:24] D1ErrChPhPri[7:0]
EYE_MON2[23:16] D1ErrChPhSec[7:0]
EYE_MON2[15:8] – – – – – – – –
EYE_MON2[7:0] – – – – – – – –
0x964
TX_CTRL1[31:24] – – – – – – – –
TX_CTRL1[23:16] – – – – – – – –
TX_CTRL1[15:8] – – – – – cd_tune[2:0]
TX_CTRL1[7:0] – – – – – – – –
0x980
EQU_CTRLD[31:24] – – DFE2_initD3[5:0]
EQU_CTRLD[23:16] DFE2_initD2[6:0]
EQU_CTRLD[15:8] DFE1_initD3[6:0]
EQU_CTRLD[7:0] DFE1_initD2[6:0]
0x984
EQU_CTRLE[31:24] DFE4Init_D3[6:0]
EQU_CTRLE[23:16] DFE4Init_D2[6:0]
EQU_CTRLE[15:8] DFE3Init_D3[6:0]
EQU_CTRLE[7:0] DFE3Init_D2[6:0]
0x98C
EQU_CTRLG[31:24] – – – – – – – –
EQU_CTRLG[23:16] – – – – – – – –
EQU_CTRLG[15:8] AGCInit_D3[7:0]
EQU_CTRLG[7:0] AGCInit_D2[7:0]
PHY 2
0xA0C EQU_CTRL3[31:24] – – D1_coeff[5:0]
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 60
EQU CTRL3 2316 D2 Coefl 6:0 EQU CTRL315 8 D3 Coefl 6:0 EQU CTRL3 7:0 D4 Coefl 6:0 EQU CTRL4 31 24 EQU CTRL4 2316 EQU CTRL4 15 B EQU CTRL4 7:0 AGC Coeff 7 0 EQU CTRL7 31 24 AGC Inlt D1 70 EQU CTRL7 23 16 EQU CTRL7 15 B EQU CTRL7 7:0 EQU CTRLA3124 D1 "71150 EQU CTRLA 2316 D2 "7116 0 EQU CTRLA15E D3 "7116 0 ECU CTRLA 7:0 D4 "7116 0 EQU CTRLB 31 24 Capsel 1 0 iMfie EQU CTRLB 2316 EQU CTRLB15E EQU CTRLB 7:0 EYE MON2 31:24 D1ErrChFhPH 7 0 EYE MON2 23:16 D1 ErrChPhSeC 7:0 EYE MON2 15:8 EYE MON2 7 0 TX CTRL1 31 24 TX CTRL1 23 16 TX CTRL1 1523 Cd lune 2 0 TX CTRL1 7:0 EQU CTRLD 31 24 DFE2 In11D3 5:0 EQU CTRLD 2316 DFE2 InI1D2 6:0 EQU CTRLD 15 E DFE1 InI1D3 6:0 EQU CTRLD 7:0 DFE1 InI1D2 6:0 EQU CTRLE 3124 DFE41nI1 D3 6 0 EQU CTRLE 2316 DFE41nI1 D2 6 0 EQU CTRLE 15 E DFE31nI1 D3 6 0 EQU CTRLE 7:0 DFE31nI1 D2 6 0 EQU CTRLG 31 24 EQU CTRLG 23 16 EQU CTRLG 15 E AGCInII D3 7:0 EQU CTRLG 7:0 AGCInII D2 7:0
ADDRESS NAME MSB LSB
EQU_CTRL3[23:16] D2_coeff[6:0]
EQU_CTRL3[15:8] D3_coeff[6:0]
EQU_CTRL3[7:0] D4_coeff[6:0]
0xA10
EQU_CTRL4[31:24] – – – – – – – –
EQU_CTRL4[23:16] – – – – – – – –
EQU_CTRL4[15:8] – – – – – – – –
EQU_CTRL4[7:0] AGC_coeff[7:0]
0xA1C
EQU_CTRL7[31:24] AGC_init_D1[7:0]
EQU_CTRL7[23:16] – – – – – – – –
EQU_CTRL7[15:8] – – – – – – – –
EQU_CTRL7[7:0] – – – – – – – –
0xA28
EQU_CTRLA[31:24] – – D1_init[5:0]
EQU_CTRLA[23:16] D2_init[6:0]
EQU_CTRLA[15:8] D3_init[6:0]
EQU_CTRLA[7:0] D4_init[6:0]
0xA2C
EQU_CTRLB[31:24] – – – – capsel[1:0] Mode6G
phb
EQU_CTRLB[23:16] – – – – – – – –
EQU_CTRLB[15:8] – – – – – – – –
EQU_CTRLB[7:0] – – – – – – – –
0xA3C
EYE_MON2[31:24] D1ErrChPhPri[7:0]
EYE_MON2[23:16] D1ErrChPhSec[7:0]
EYE_MON2[15:8] – – – – – – – –
EYE_MON2[7:0] – – – – – – – –
0xA64
TX_CTRL1[31:24] – – – – – – – –
TX_CTRL1[23:16] – – – – – – – –
TX_CTRL1[15:8] – – – – – cd_tune[2:0]
TX_CTRL1[7:0] – – – – – – – –
0xA80
EQU_CTRLD[31:24] – – DFE2_initD3[5:0]
EQU_CTRLD[23:16] DFE2_initD2[6:0]
EQU_CTRLD[15:8] DFE1_initD3[6:0]
EQU_CTRLD[7:0] DFE1_initD2[6:0]
0xA84
EQU_CTRLE[31:24] DFE4Init_D3[6:0]
EQU_CTRLE[23:16] DFE4Init_D2[6:0]
EQU_CTRLE[15:8] DFE3Init_D3[6:0]
EQU_CTRLE[7:0] DFE3Init_D2[6:0]
0xA8C
EQU_CTRLG[31:24] – – – – – – – –
EQU_CTRLG[23:16] – – – – – – – –
EQU_CTRLG[15:8] AGCInit_D3[7:0]
EQU_CTRLG[7:0] AGCInit_D2[7:0]
PHY 3
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 61
EQU CTRL3 31 24 D1 Coefl 5:0 EQU CTRL3 23 16 D2 Coefl 6:0 EQU CTRL315 8 D3 Coefl 6:0 EQU CTRL3 7:0 D4 Coefl 6:0 EQU CTRL4 31 24 EQU CTRL4 2316 EQU CTRL4 15 B EQU CTRL4 7:0 AGC Coeff 7 0 EQU CTRL7 31 24 AGC Inlt D1 70 EQU CTRL7 2316 EQU CTRL7 15 B EQU CTRL7 7:0 EQU CTRLA3124 D1 "H150 EQU CTRLA 2316 D2 "7116 0 ECU CTRLA158 D3 "7116 0 ECU CTRLA 7:0 D4 "7116 0 W m % EQU CTRLB 23 16 EQU CTRLB 15 8 ECU CTRLB 7:0 EYE MON2 31:24 D1ErrChPhPr17 0 EYE MON2 23:16 D1 ErrChPhSec 7:0 EYE MON2 15:8 EYE MON2 7 0 TX CTRL1 31 24 TX CTRL1 23 16 TX CTRL1 1523 Cd lune 2 0 TX CTRL1 7:0 EQU CTRLD 3124 DFE2 In11D3 5:0 EQU CTRLD 2316 DFE2 InI1D2 6:0 EQU CTRLD 15 E DFE1 InI1D3 6:0 EQU CTRLD 7:0 DFE1 InI1D2 6:0 EQU CTRLE 31 24 DFE41nI1 D3 6 0 EQU CTRLE 2316 DFE41nI1 D2 6 0 EQU CTRLE 15 E DFE31nI1 D3 6 0 EQU CTRLE 7:0 DFE31nI1 D2 6 0 EQU CTRLG 31 24 EQU CTRLG 23 16 EQU CTRLG 15 E AGCInII D3 7:0 EQU CTRLG 7:0 AGCInII D2 7:0
ADDRESS NAME MSB LSB
0xB0C
EQU_CTRL3[31:24] – – D1_coeff[5:0]
EQU_CTRL3[23:16] D2_coeff[6:0]
EQU_CTRL3[15:8] D3_coeff[6:0]
EQU_CTRL3[7:0] D4_coeff[6:0]
0xB10
EQU_CTRL4[31:24] – – – – – – – –
EQU_CTRL4[23:16] – – – – – – – –
EQU_CTRL4[15:8] – – – – – – – –
EQU_CTRL4[7:0] AGC_coeff[7:0]
0xB1C
EQU_CTRL7[31:24] AGC_init_D1[7:0]
EQU_CTRL7[23:16] – – – – – – – –
EQU_CTRL7[15:8] – – – – – – – –
EQU_CTRL7[7:0] – – – – – – – –
0xB28
EQU_CTRLA[31:24] – – D1_init[5:0]
EQU_CTRLA[23:16] D2_init[6:0]
EQU_CTRLA[15:8] D3_init[6:0]
EQU_CTRLA[7:0] D4_init[6:0]
0xB2C
EQU_CTRLB[31:24] – – – – capsel[1:0] Mode6G
phb
EQU_CTRLB[23:16] – – – – – – – –
EQU_CTRLB[15:8] – – – – – – – –
EQU_CTRLB[7:0] – – – – – – – –
0xB3C
EYE_MON2[31:24] D1ErrChPhPri[7:0]
EYE_MON2[23:16] D1ErrChPhSec[7:0]
EYE_MON2[15:8] – – – – – – – –
EYE_MON2[7:0] – – – – – – – –
0xB64
TX_CTRL1[31:24] – – – – – – – –
TX_CTRL1[23:16] – – – – – – – –
TX_CTRL1[15:8] – – – – – cd_tune[2:0]
TX_CTRL1[7:0] – – – – – – – –
0xB80
EQU_CTRLD[31:24] – – DFE2_initD3[5:0]
EQU_CTRLD[23:16] DFE2_initD2[6:0]
EQU_CTRLD[15:8] DFE1_initD3[6:0]
EQU_CTRLD[7:0] DFE1_initD2[6:0]
0xB84
EQU_CTRLE[31:24] DFE4Init_D3[6:0]
EQU_CTRLE[23:16] DFE4Init_D2[6:0]
EQU_CTRLE[15:8] DFE3Init_D3[6:0]
EQU_CTRLE[7:0] DFE3Init_D2[6:0]
0xB8C
EQU_CTRLG[31:24] – – – – – – – –
EQU_CTRLG[23:16] – – – – – – – –
EQU_CTRLG[15:8] AGCInit_D3[7:0]
EQU_CTRLG[7:0] AGCInit_D2[7:0]
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 62
EQU CTRL3 31 24 D1 Coefl 5:0 EQU CTRL3 23 16 D2 Coefl 6:0 EQU CTRL315 8 D3 Coefl 6:0 EQU CTRL3 7:0 D4 Coefl 6:0 EQU CTRL4 31 24 EQU CTRL4 2316 EQU CTRL4 15 B EQU CTRL4 7:0 AGC Coeff 7 0 EQU CTRL7 31 24 AGC Inlt D1 70 EQU CTRL7 2316 EQU CTRL7 15 B EQU CTRL7 7:0 EQU CTRLA 3124 D1 "71150 EQU CTRLA 2316 D2 "7116 0 ECU CTRLA15E D3 "7116 0 ECU CTRLA 7:0 D4 "7116 0 ECU CTRLB 31 24 Capsel 1 0 iMfiG EQU CTRLB 2316 EQU CTRLB 15 8 ECU CTRLB 7:0 EYE MON2 31:24 D1ErrChPhPH 7 0 EYE MON2 23:16 D1 ErrChPhSeC 7:0 EYE MON2 15:8 EYE MON2 7 0 TX CTRL1 31 24 TX CTRL1 23 16 TX CTRL1 1523 Cd lune 2 0 TX CTRL1 7:0 EQU CTRLD 3124 DFE2 In11D3 5:0 EQU CTRLD 2316 DFE2 InI1D2 6:0 EQU CTRLD 15 E DFE1 InI1D3 6:0 EQU CTRLD 7:0 DFE1 InI1D2 6:0 EQU CTRLE 3124 DFE41nI1 D3 6 0 EQU CTRLE 2316 DFE41nI1 D2 6 0 EQU CTRLE 15 E DFE31nI1 D3 6 0 EQU CTRLE 7:0 DFE31nI1 D2 6 0 EQU CTRLG 31 24 EQU CTRLG 23 16 EQU CTRLG 15 E AGCInII D3 7:0
ADDRESS NAME MSB LSB
PHY 4
0xC0C
EQU_CTRL3[31:24] – – D1_coeff[5:0]
EQU_CTRL3[23:16] D2_coeff[6:0]
EQU_CTRL3[15:8] D3_coeff[6:0]
EQU_CTRL3[7:0] D4_coeff[6:0]
0xC10
EQU_CTRL4[31:24] – – – – – – – –
EQU_CTRL4[23:16] – – – – – – – –
EQU_CTRL4[15:8] – – – – – – – –
EQU_CTRL4[7:0] AGC_coeff[7:0]
0xC1C
EQU_CTRL7[31:24] AGC_init_D1[7:0]
EQU_CTRL7[23:16] – – – – – – – –
EQU_CTRL7[15:8] – – – – – – – –
EQU_CTRL7[7:0] – – – – – – – –
0xC28
EQU_CTRLA[31:24] – – D1_init[5:0]
EQU_CTRLA[23:16] D2_init[6:0]
EQU_CTRLA[15:8] D3_init[6:0]
EQU_CTRLA[7:0] D4_init[6:0]
0xC2C
EQU_CTRLB[31:24] – – – – capsel[1:0] Mode6G
phb
EQU_CTRLB[23:16] – – – – – – – –
EQU_CTRLB[15:8] – – – – – – – –
EQU_CTRLB[7:0] – – – – – – – –
0xC3C
EYE_MON2[31:24] D1ErrChPhPri[7:0]
EYE_MON2[23:16] D1ErrChPhSec[7:0]
EYE_MON2[15:8] – – – – – – – –
EYE_MON2[7:0] – – – – – – – –
0xC64
TX_CTRL1[31:24] – – – – – – – –
TX_CTRL1[23:16] – – – – – – – –
TX_CTRL1[15:8] – – – – – cd_tune[2:0]
TX_CTRL1[7:0] – – – – – – – –
0xC80
EQU_CTRLD[31:24] – – DFE2_initD3[5:0]
EQU_CTRLD[23:16] DFE2_initD2[6:0]
EQU_CTRLD[15:8] DFE1_initD3[6:0]
EQU_CTRLD[7:0] DFE1_initD2[6:0]
0xC84
EQU_CTRLE[31:24] DFE4Init_D3[6:0]
EQU_CTRLE[23:16] DFE4Init_D2[6:0]
EQU_CTRLE[15:8] DFE3Init_D3[6:0]
EQU_CTRLE[7:0] DFE3Init_D2[6:0]
0xC8C
EQU_CTRLG[31:24] – – – – – – – –
EQU_CTRLG[23:16] – – – – – – – –
EQU_CTRLG[15:8] AGCInit_D3[7:0]
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 63
EQU CTRLG7 AGCInII D2 0 CfglFA 0x00) SflRst LSEF Add‘ncr W‘re4 ere4 0 AddlncrO LSEFO SRRSIO CfglFB 0x01) SIrmD‘s
ADDRESS NAME MSB LSB
EQU_CTRLG[7:0] AGCInit_D2[7:0]
Register Details
CfgIFA (0x00)
Configure Interface A
BIT76543210
Field SftRst LSBF AddIncr Wire4 Wire4_0 AddIncr0 LSBF0 SftRst0
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access
Type
Write 1 to
Clear, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write 1 to
Clear, Read
BITFIELD BITS DESCRIPTION DECODE
SftRst 7
Writing a 1 to this bit resets everything except
address 0x0000, 0x0001 and SPI interface.
This bit is self clearing
LSBF 6 Select MSB-LSB first data format
0x0: MSB first for input control/data and output
data
0x1: LSB first for input control/data nad output data
AddIncr 5 Configure the auto-increment or decrement
for address in burst mode
0x0: Decrement address for SPI burst mode
0x1: Increment address for SPI burst mode
Wire4 4 Configure 3 or 4 wire SPI mode
0x0: 3-Wire SPI mode, SDI used for both input and
output
0x1: 4-Wire SPI mode, SDI is input and SDO is
output
Wire4_0 3 Same as Bit4 and both should have the same
value
AddIncr0 2 Same as Bit5 and both should have the same
value
LSBF0 1 Same as Bit6 and both should have the same
value
SftRst0 0 Same as Bit7 and both should have the same
value
CfgIFB (0x01)
Configure Interface B
BIT76543210
Field StrmDis rsvd6 rsvd4 rsvd3 rsvd0
Reset 0b0 0b0 0b0 0b0 0b0
Access
Type Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
StrmDis 7 Configure the Burst SPI mode 0x0: SPI Streaming mode is enabled
0x1: SPI Streaming mode is disabled and
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 64
Cfg Dev 0x02 ChiETyEe 0x03
BITFIELD BITS DESCRIPTION DECODE
continued CSB forces intruction-data format
rsvd6 6 Reserved Bit
rsvd4 4 Reserved Bit
rsvd3 3 Reserved Bit
rsvd0 0 Reserved Bit
CfgDev (0x02)
Device Configuration
BIT76543210
Field rsvd[4:0] CDrst PDM[1:0]
Reset 0x0 0b0 0x0
Access
Type Write, Read Write, Read Write, Read
BITFIELD BITS DESCRIPTION DECODE
rsvd 7:3 Reserved Bits
CDrst 2 Clock Divider Reset 0x0: Clock Divider is not reset
0x1: Clock Divider is reset
PDM 1:0 Power-Down Modes Configuration
0x0: Normal operation mode
0x1: (Optional) Low power normal operation with
reduced power and corresponding performance
0x2: (Optional) Medium power standby mode, non-
operational but return to full operation in minimum
amount of time
0x3: Sleep mode with lowest power dissipation
with chip inactivity except SPI interface
ChipType (0x03)
Chip Type Status
BIT76543210
Field –––– Type[3:0]
Reset – – – – 0x4
Access
Type Read Only
BITFIELD BITS DESCRIPTION DECODE
Type 3:0 Chip Type Status
0x0: Not Assigned
0x1: RF
0x2: IF
0x3: High-Speed ADC
0x4: High-Speed DAC
0x5: Clock Buffer
0x6: PLL
0x7: Precision ADC
0x8: Precision DAC
0x9: RAD
MAX5855 16-Bit, 4.9Gsps Wideband Interpolating
and Modulating RF DAC with JESD204B Interface
www.maximintegrated.com Maxim Integrated | 65