TLV755P Datasheet by Texas Instruments

V'.‘ 1!. B X E I TEXAS INSTRUMENTS 175 f fl
Time (ms)
Voltage (V)
Output Current (mA)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0 0
1 25
2 50
3 75
4 100
5 125
6 150
7 175
VOUT VIN VEN IOUT
TLV755P
IN
EN
OUT
GND
COUT
CIN
ON
OFF
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV755P
SBVS320A –NOVEMBER 2017REVISED MAY 2018
TLV755P 500-mA, Low I
Q
, Small Size, Low Dropout Regulator
1
1 Features
1 Input Voltage Range: 1.45 V to 5.5 V
Low IQ: 25 µA (Typical)
Low Dropout:
238 mV (Maximum) at 500 mA (3.3 VOUT)
Output Accuracy: 1% (Maximum at 85°C)
Built-In Soft-Start With Monotonic VOUT Rise
Foldback Current Limit
Active Output Discharge
High PSRR: 46 dB at 100 kHz
Stable With a 1-µF Ceramic Output Capacitor
• Packages:
2.9-mm × 1.6-mm SOT-23-5
1-mm x 1-mm X2SON-4
2 mm × 2 mm WSON-6
2 Applications
Set-Top Boxes, TV, and Gaming Consoles
Portable and Battery-Powered Equipment
Desktop, Notebooks, and Ultrabooks
Tablets and Remote Controls
White Goods and Appliances
Grid Infrastructure and Protection Relays
Camera Modules and Image Sensors
3 Description
The TLV755P is an ultra-small, low quiescent current,
low-dropout regulator (LDO) that sources 500 mA
with good line and load transient performance. The
TLV755P is optimized for a wide variety of
applications by supporting an input voltage range
from 1.45 V to 5.5 V. To minimize cost and solution
size, the device is offered in fixed output voltages
ranging from 0.6 V to 5 V to support the lower core
voltages of modern microcontrollers (MCUs).
Additionally, the TLV755P has a low IQwith enable
functionality to minimize standby power. This device
features an internal soft-start to lower inrush current,
thus providing a controlled voltage to the load and
minimizing the input voltage drop during start up.
When shutdown, the device actively pulls down the
output to quickly discharge the outputs and ensure a
known start-up state.
The TLV755P is stable with small ceramic output
capacitors allowing for a small overall solution size. A
precision band-gap and error amplifier provides a
typical accuracy of 1%. All device versions have
integrated thermal shutdown, current limit, and
undervoltage lockout (UVLO). The TLV755P has an
internal foldback current limit that helps reduce the
thermal dissipation during short-circuit events.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV755P
X2SON (4) 1.00 mm × 1.00 mm
SOT-23 (5) 2.90 mm × 1.60 mm
SON (6) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Startup Waveform
l TEXAS INSTRUMENTS
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 14
8 Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 20
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 21
11 Device and Documentation Support ................. 22
11.1 Device Support...................................................... 22
11.2 Receiving Notification of Documentation Updates 22
11.3 Community Resources.......................................... 22
11.4 Trademarks........................................................... 22
11.5 Electrostatic Discharge Caution............................ 22
11.6 Glossary................................................................ 22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Original (November 2017) to Revision A Page
Released to production .......................................................................................................................................................... 1
*9 TEXAS INSTRUMENTS
1OUT 6 IN
2NC 5 NC
3GND 4 EN
Not to scale
Thermal
Pad
1IN
2GND
3EN 4 NC
5 OUT
Not to scale
3
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5 Pin Configuration and Functions
DQN Package
4-Pin X2SON
Top View
DBV Package
5-Pin SOT-23
Top View
DRV Package
6-Pin WSON With Exposed Thermal Pad
Top View
NC = no internal connection.
(1) The nominal input and output capacitance must be greater than 0.47 µF; throughout this document the nominal derating on these
capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 0.47 µF.
Pin Functions
PIN I/O DESCRIPTION
NAME DQN DBV DRV
EN 3 3 4 I Enable pin. Drive EN greater than VHI to turn on the regulator.
Drive EN less than VLO to place the LDO into shutdown mode.
GND 2 2 3 Ground pin.
IN 4 1 6 I Input pin. A capacitor with a value of 1 µF or larger is required from
this pin to ground(1). See the Input and Output Capacitor Selection
section for more information.
NC 4 2, 5 No internal connection.
OUT 1 5 1 O Regulated output voltage pin. A capacitor with a value of 1 µF or larger
is required from this pin to ground(1). See the Input and Output
Capacitor Selection section for more information.
Thermal pad Pad Pad Connect the thermal pad to a large-area ground plane.
The thermal pad is internally connected to GND.
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is VIN + 0.3 V or 6.0 V, whichever is smaller
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VIN -0.3 6.0 V
Enable voltage, VEN -0.3 6.0 V
Output voltage, VOUT -0.3 VIN + 0.3(2) V
Operating junction temperature range, TJ-40 150 °C
Storage temperature, Tstg -65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage 1.45 5.5 V
VOUT Output voltage 0.6 5.0 V
VEN Enable voltage 0 5.5 V
IOUT Output current 0 500 mA
CIN Input capacitor 1 μF
COUT Output capacitor 1 200 μF
fEN Enable toggle frequency 10 kHz
TJJunction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
TLV755
UNIT
DQN (X2SON) DBV (SOT-23-
5) DRV (SON)
4 PINS 5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 168.4 231.1 100.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 139.1 118.4 108.5 °C/W
RθJB Junction-to-board thermal resistance 101.4 64.4 64.3 °C/W
ψJT Junction-to-top characterization parameter 5.6 28.4 10.4 °C/W
ψJB Junction-to-board characterization parameter 101.7 63.8 64.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 88.4 N/A 34.7 °C/W
l TEXAS INSTRUMENTS
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6.5 Electrical Characteristics
at operating temperature range (TJ= –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 1.45 5.5 V
VOUT Output voltage 0.6 5.0 V
Output accuracy
-40°C TJ+85°C, DBV and DRV package -1% 1%
VOUT 1.0 V, DQN package -1.2% 1.2%
-40°C TJ+85°C; 0.6 V VOUT < 1.0 V -10 10 mV
VOUT 1 V -1.5% 1.5%
0.6 V VOUT < 1 V -15 15 mV
(ΔVOUT)
ΔVIN Line regulation VOUT + 0.5 V VIN 5.5 V, VOUT > 1.5 V 2 mV
ΔVOUT/
ΔIOUT Load regulation 0.1 mA
IOUT 500
mA
DQN package 0.036
V/ADBV package 0.060
DRV package 0.044
IGND Ground current
TJ= 25°C, IOUT = 0 mA 14 25 31
µA-40°C TJ+85°C, IOUT = 0 mA 33
-40°C TJ+125°C, IOUT = 0 mA 40
ISHDN Shutdown current VEN 0.4 V, 1.4 V VIN 5.5 V, -40°C TJ
+125°C 0.1 1 µA
ICL Output current limit
VIN =
VOUT+
VDO(MAX) +
0.25 V
VOUT = VOUT - 0.2 V, VOUT 1.5V 560 720 865
mA
VOUT = 0.9 x VOUT, 1.5V < VOUT 4.5V 560 720 865
ISC Short circuit current limit VOUT = 0 V 355 mA
VDO Dropout voltage
IOUT =
500mA,
-40°C TJ
+85°C
0.6 V VOUT < 0.8 V 675 1080
mV
0.8 V VOUT < 1.0V 600 930
1.0 V VOUT < 1.2 V 550 780
1.2 V VOUT < 1.5 V 500 630
1.5 V VOUT < 1.8 V 350 400
1.8 V VOUT < 2.5 V 325 380
2.5 V VOUT < 3.3 V 250 300
3.3 V VOUT < 5.0 V 150 215
IOUT =
500mA,
-40°C TJ
+125°C
0.6 V VOUT < 0.8 V 1140
0.8 V VOUT < 1.0 V 985
1.0 V VOUT < 1.2 V 825
1.2 V VOUT < 1.5 V 665
1.5 V VOUT < 1.8 V 425
1.8 V VOUT < 2.5 V 400
2.5 V VOUT < 3.3 V 325
3.3 V VOUT < 5.0 V 238
PSRR Power-supply rejection ratio
f = 1 kHz, VIN = VOUT + 1 V, IOUT = 50 mA 52
dBf = 100 kHz, VIN = VOUT + 1 V, IOUT = 50 mA 46
f = 1 MHz, VIN = VOUT + 1 V, IOUT = 50 mA 52
VNOutput noise voltage BW = 10 Hz to 100 kHz; VOUT = 1.2 V, IOUT = 500
mA 71.5 µVRMS
VUVLO Undervoltage lockout VIN rising 1.21 1.3 1.44 V
VUVLO,HY
ST
Undervoltage lockout
hysteresis VIN falling 40 mV
tSTR Startup time 550 µs
VHI EN pin high voltage (enabled) 1 V
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Electrical Characteristics (continued)
at operating temperature range (TJ= –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 μF, unless otherwise noted. All typical values at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VLO EN pin low voltage (enabled) 0.3 V
IEN Enable pin current EN = 5.5V 10 nA
TSD Thermal shutdown Shutdown, temperature increasing 165 °C
Reset, temperature decreasing 155
RPULLDO
WN Pulldown resistance VIN = 5.5V 120 Ω
l TEXAS INSTRUMENTS mu mu E #3 // mu zzu
Frequency (Hz)
Noise (PV/Hz)
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
10 100 1k 10k 100k 1M 10M
IOUT
10 mA, 140 PVRMS
50 mA, 142 PVRMS
100 mA, 142 PVRMS
500 mA, 143 PVRMS
Output Voltage (V)
Output Noise Voltage (PV
RMS
)
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
40
60
80
100
120
140
160
180
200
220
Frequency (Hz)
Power Supply Rejection Ratio (dB)
0
20
40
60
80
100
10 100 1k 10k 100k 1M 10M
COUT = 1 PF
COUT = 10 PF
COUT = 22 PF
COUT = 100 PF
Frequency (Hz)
Noise (PV/Hz)
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
10 100 1k 10k 100k 1M 10M
COUT
1 PF, 143 PVRMS
10 PF, 150 PVRMS
22 PF, 149 PVRMS
100 PF, 146 PVRMS
Frequency (Hz)
Power Supply Rejection Ratio (dB)
0
20
40
60
80
100
10 100 1k 10k 100k 1M 10M
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 500 mA
Frequency (Hz)
Power Supply Rejection Ratio (dB)
0
20
40
60
80
100
10 100 1k 10k 100k 1M 10M
VIN
3.8 V
4 V
4.3 V
4.5 V
5 V
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6.6 Typical Characteristics
at operating temperature TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
VIN = 4.3 V, VOUT = 3.3 V, COUT = 1 µF
Figure 1. PSRR vs Frequency and IOUT
VOUT = 3.3 V, COUT = 1 µF, IOUT = 500 mA
Figure 2. PSRR vs Frequency and VIN
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 500 mA
Figure 3. PSRR vs Frequency and COUT
VOUT = 3.3 V, VRMS BW = 10 Hz to 100 kHz
Figure 4. Output Spectral Noise Density vs
Frequency and COUT
VOUT = 3.3 V, IOUT = 500 mA, COUT = 1 µF, VRMS BW = 10 Hz to
100 kHz
Figure 5. Output Spectral Noise Density vs
Frequency and IOUT
IOUT = 500 mA, COUT = 1 µF, VRMS BW = 10 Hz to 100 kHz
Figure 6. Output Noise Voltage vs VOUT
l TEXAS INSTRUMENTS 3 328 175
Output Current (mA)
Output Voltage (mV)
0 50 100 150 200 250 300 350 400 450 500
-30
-25
-20
-15
-10
-5
0
5
10
-40°C
0°C
25°C
85°C
125°C
Time (ms)
Voltage (V)
Output Current (mA)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0 0
1 25
2 50
3 75
4 100
5 125
6 150
7 175
VOUT VIN VEN IOUT
Time (ms)
Voltage (V)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
1
2
3
4
5
6VIN
VOUT
Time (ms)
Voltage (V)
0 1 2 3 4 5 6 7 8 9 10
0
1
2
3
4
5
6VIN
VOUT
Time (ms)
Input Voltage (V)
Output Voltage (V)
0 20 40 50
0 3.28
1 3.288
2 3.296
3 3.304
4 3.312
5 3.32
6 3.328
VIN
VOUT
Time (Ps)
Output Voltage (V)
Output Current (A)
0 40 80 120 160 200 240 280 320 360 400 440 480
3.2 0
3.225 80
3.25 160
3.275 240
3.3 320
3.325 400
3.35 480
3.375 560
3.4 640
VOUT
IOUT
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Typical Characteristics (continued)
at operating temperature TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
VOUT = 3.3 V, COUT = 1 µF, VIN slew rate = 1 V/µs
Figure 7. Line Transient
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, IOUT slew rate = 1 A/µs
Figure 8. 3.3-V, 1-mA to 500-mA Load Transient
Figure 9. VIN = VEN Power-Up Figure 10. VIN = VEN Shutdown
VIN = 5 V, IOUT = 100 mA, VEN slew rate = 1 V/µs, VOUT = 3.3 V
Figure 11. EN Startup Figure 12. Load Regulation vs IOUT
l TEXAS INSTRUMENTS 200 200 th
Output Current (mA)
0 50 100 150 200 250 300 350 400 450 500
0
100
200
300
400
500
600
700
800
-40°C
0°C
25°C
85°C
125°C
GND Pin Current (ɥA)
Input Voltage (V)
GND Pin Current (PA)
0 1 2 3 4 5 6
0
50
100
150
200
250
300
350
400
450
500
550
600
650 -40qC
0qC
25qC
85qC
125qC
Input Voltage (V)
Accuracy (%)
3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1-40qC
0qC25qC
85qC125qC
Input Voltage (V)
Accuracy (%)
5 5.1 5.2 5.3 5.4 5.5
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1-40qC
0qC25qC
85qC125qC
Output Current (mA)
Dropout Voltage (mV)
0 50 100 150 200 250 300 350 400 450 500
0
25
50
75
100
125
150
175
200 -40qC
0qC
25qC
85qC
125qC
Output Current (mA)
Dropout Voltage (mV)
0 50 100 150 200 250 300 350 400 450 500
0
40
80
120
160
200 -40qC
0qC
25qC
85qC
125qC
9
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Typical Characteristics (continued)
at operating temperature TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
Figure 13. 3.3-V Dropout Voltage vs IOUT Figure 14. 5.0-V Dropout Voltage vs IOUT
VOUT = 3.3 V, IOUT = 1 mA
Figure 15. 3.3-V Regulation vs VIN (Line Regulation)
IOUT = 1 mA, VOUT = 5 V
Figure 16. 5.0-V Accuracy vs VIN (Line Regulation)
Figure 17. IGND vs IOUT
VOUT = 3.3 V, IOUT = 1 mA
Figure 18. IGND vs VIN
l TEXAS INSTRUMENTS auu 350 180 800 250 14
Input Voltage (V)
Enable Current (PA)
0 1 2 3 4 5 6
0
50
100
150
200
250 -40qC
0qC
25qC
85qC
125qC
Temperature (qC)
UVLO Threshold (V)
-50 -25 0 25 50 75 100 125
1.2
1.24
1.28
1.32
1.36
1.4
UVLO Negative UVLO Positive
Temperature (qC)
Shutdown Current (nA)
-40 -20 0 20 40 60 80 100 120 140
0
20
40
60
80
100
120
140
160
180
Temperature (qC)
Enable Threshold (mV)
-50 -25 0 25 50 75 100 125
500
550
600
650
700
750
800
EN Negative EN Positive
Input Voltage (V)
Shutdown Current (nA)
0 1 2 3 4 5 6
0
50
100
150
200
250
300
350 -40qC
0qC
25qC
85qC
125qC
Input Voltage (V)
Quiescent Current (PA)
0 1 2 3 4 5 6
0
50
100
150
200
250
300 -40qC
0qC
25qC
85qC
125qC
10
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Typical Characteristics (continued)
at operating temperature TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
VOUT = 3.3 V, IOUT = 0 mA
Figure 19. IQvs VIN
VEN = 0 V
Figure 20. ISHDN vs VIN
VEN = 0 V
Figure 21. ISHDN vs Temperature Figure 22. Enable Threshold vs Temperature
VEN = 5.5 V
Figure 23. IEN vs VIN Figure 24. UVLO Threshold vs Temperature
l TEXAS INSTRUMENTS 600
0 100 200 300 400 500 600 700 800
0
0.5
1
1.5
2
2.5
3
3.5
-40°C
0°C
25°C
85°C
125°C
Output Voltage (mV)
Output Current (mA)
Output Current (mA)
Output Voltage (mV)
0 1 2 3 4 5
0
50
100
150
200
250
300
350
400
450
500
550
600 -40qC
0qC
25qC
85qC
125qC
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Typical Characteristics (continued)
at operating temperature TJ= 25°C, VIN = VOUT(NOM) + 0.5 V or 1.45 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
= COUT = 1 µF (unless otherwise noted)
Figure 25. VOUT vs IOUT Pulldown Resistor Figure 26. 3.3-V Foldback Current Limit, VOUT vs IOUT
l TEXAS INSTRUMENTS iAi
t=120·RL
120+RL
·COUT
+±
Bandgap
Thermal
Shutdown
UVLO
Logic
Current
Limit
120 Ÿ
IN
EN GND
OUT
R1
R2
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7 Detailed Description
7.1 Overview
The TLV755P belongs to a family of next-generation, low-dropout regulators (LDOs). This device consumes low
quiescent current and delivers excellent line and load transient performance. The TLV755P is optimized for a
wide variety of applications by supporting an input voltage range from 1.45 V to 5.5 V. To minimize cost and
solution size, the device is offered in fixed output voltages ranging from 0.6 V to 5 V to support the lower core
voltages of modern microcontrollers (MCUs).
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
is –40°C to +125°C.
7.2 Functional Block Diagram
NOTE: R2= 550 kΩ, R1= adjustable.
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit disables the output until the input voltage is greater than the rising UVLO
voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is
connected to ground with a 120-Ωpulldown resistor.
7.3.2 Enable (EN)
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VHI. Turn off the device by
forcing the EN pin below VLO. If shutdown capability is not required, connect EN to IN.
The device has an internal pulldown that connects a 120-Ωresistor to ground when the device is disabled. The
discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel
with the 120-Ωpulldown resistor. Equation 1 calculates the time constant τ:
(1)
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Feature Description (continued)
The EN pin is independent of the input pin (IN), but if the EN pin is driven to a higher voltage than VIN, the
current into the EN pin increases. This effect is illustrated in Figure 23. When the EN voltage is higher than the
input voltage there is an increased current flow into the EN pin. If this increased flow causes problems in the
application, sequence the EN pin after VIN is high, or to tie EN to VIN to prevent this flow increase from
happening. If EN is driven to a higher voltage than VIN, limit the frequency on EN to below 10 kHz.
7.3.3 Internal Foldback Current Limit
The TLV755P has an internal current limit that protects the regulator during fault conditions. The current limit is a
hybrid scheme with brick wall until the output voltage is less than 0.4 V × VOUT(NOM). When the voltage drops
below 0.4 V × VOUT(NOM), a foldback current limit is implemented that scales back the current as the output
voltage approaches GND. When the output shorts, the LDO supplies a typical current of ISC. The output voltage
is not regulated when the device is in current limit. In this condition, the output voltage is the product of the
regulated current and the load resistance. When the device output shorts, the PMOS pass transistor dissipates
power [(VIN – VOUT) × ISC] until thermal shutdown is triggered and the device turns off. After the device cools
down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device
cycles between current limit and thermal shutdown.
The foldback current-limit circuit limits the current that is allowed through the device to current levels lower than
the minimum current limit at nominal VOUT current limit (ICL) during start up. See Figure 26 for typical current limit
values. If the output is loaded by a constant-current load during start up, or if the output voltage is negative when
the device is enabled, then the load current demanded by the load may exceed the foldback current limit and the
device may not rise to the full output voltage. For constant-current loads, disable the output load until the output
has risen to the nominal voltage.
Excess inductance can cause the current limit to oscillate. Minimize the inductance to keep the current limit from
oscillating during a fault condition.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 165°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 155°C, the output circuitry is enabled again. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation that protects the circuit from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to a maximum
of 125°C. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The internal protection circuitry protects against overload conditions but is not intended to be activated in normal
operation. Continuously running the device into thermal shutdown degrades device reliability.
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(1) All table conditions must be met.
(2) The device is disabled when any condition is met.
7.4 Device Functional Modes
Table 1 lists a comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Modes Comparison
OPERATING MODE PARAMETER
VIN EN IOUT TJ
Normal(1) VIN > VOUT(NOM) + VDO VEN > VHI IOUT < ICL TJ< TSD
Dropout(1) VIN < VOUT(NOM) + VDO VEN > VHI — TJ< TSD
Disabled(2) VIN < VUVLO VEN < VLO — TJ> TSD
7.4.1 Normal Operation
The device regulates to the nominal output voltage when all of the following conditions are met.
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO)
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ< TSD)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout. In this mode, the output voltage tracks
the input voltage. During this mode, the transient performance of the device degrades because the pass device
is in a triode state and no longer controls the output voltage of the LDO. Line or load transients in dropout can
result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
right after being in a normal regulation state, but not during startup), the pass-FET is driven as hard as possible
when the control loop is out of balance. During the normal time required for the device to regain regulation, VIN
VOUT(NOM) + VDO, VOUT can overshoot VOUT(NOM) during fast transients.
7.4.3 Disabled
The output is shut down by forcing the enable pin below VLO. When disabled, the pass device is turned off,
internal circuits are shut down, and the output voltage is actively discharged to ground by an internal switch from
the output to ground. The active pulldown is on when sufficient input voltage is provided.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV755P requires an output capacitance of 0.47 µF or larger for stability. Use X5R- and X7R-type ceramic
capacitors because these capacitors have minimal variation in capacitance value and equivalent series
resistance (ESR) over temperature. When selecting a capacitor for a specific application, consider the DC bias
characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. As a
general rule, ceramic capacitors must be derated by 50%. For best performance, TI recommends a maximum
output capacitance value of 200 µF.
Place a 1 µF or greater capacitor on the input pin of the LDO. Some input supplies have a high impedance.
Placing a capacitor on the input supply reduces the input impedance. The input capacitor counteracts reactive
input sources and improves transient response and PSRR. If the input supply has a high impedance over a large
range of frequencies, several input capacitors are used in parallel to lower the impedance over frequency. Use a
higher-value capacitor if large, fast, rise-time load transients are expected, or if the device is located several
inches from the input power source.
8.1.2 Dropout Voltage
The TLV755P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales linearly with the output current because the PMOS device
functions like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation. See Figure 13 and Figure 14 for typical dropout values.
8.1.3 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up when the slew rate and voltage levels are in the correct range; see Figure 27.
Use an enable signal to avoid this condition.
‘5‘ TEXAS INSTRUMENTS ,4,, ,,,L,,,,,,,,,,,,,,,,,,,,,,,,,,,
Input Voltage
Output Voltage
Output Voltage in
normal regulation.
Dropout
VOUT = VIN - VDO
VIN = VOUT(nom) + VDO
Response time for
LDO to get back into
regulation. Load current discharges
output voltage.
Voltage
Time
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Application Information (continued)
Figure 27. Startup Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. Figure 28 illustrates what is happening internally with the gate voltage
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS)
is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a
line transient occurs while the device is in dropout, the loop is not in regulation and can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
‘5‘ TEXAS INSTRUMENTS me
Output Voltage in
normal regulation
Dropout
VOUT = VIN - VDO
Transient response
time of the LDO
Load current
discharges
output
voltage
Voltage
Time
VGS voltage for
normal operation
VGS voltage in
dropout (pass device
fully on)
VDO
Gate Voltage
Input Voltage
VGS voltage for
normal operation
Input Voltage
Output Voltage
VGS voltage
(pass device
fully off)
17
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Application Information (continued)
Figure 28. Line Transients From Dropout
8.1.4 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
Degradation caused by electromigration
Excessive heat dissipation
Potential for a latch-up condition
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
l TEXAS INSTRUMENTS ‘\}_Hil H k
Device
IN OUT
GND
COUT
CIN
Schottky Diode
Internal Body Diode
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Application Information (continued)
If reverse current flow is expected in the application, external protection must be used to protect the device.
Figure 29 shows one approach of protecting the device.
Figure 29. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free of other heat-generating devices as possible that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD= (VIN – VOUT)×IOUT (2)
Power dissipation must be minimized to achieve greater efficiency. This minimizing process is achieved by
selecting the correct system voltage rails. Proper selection helps obtain the minimum input-to-output voltage
differential. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.
The main heat-conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to inner plane areas or to a bottom-side copper plane.
The maximum allowable junction temperature (TJ) determines the maximum power dissipation for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB, device package, and the temperature of the ambient air
(TA).
TJ= TA+ RθJA × PD(3)
Unfortunately, this thermal resistance (RθJA) is dependent on the heat-spreading capability built into the particular
PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes.
The RθJA value is only used as a relative measure of package thermal performance. RθJA is the sum of the
package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the
PCB copper.
l TEXAS INSTRUMENTS ‘P . TJ : Tr + P WJB J E WJB X D E ?
DC/DC
Converter TLV755P
IN
EN
OUT
GND
1 F
1 F
OFF
ON
Load
Y
Y Y ´
JT J T JT D
: T = T + PY ´
JB J B JB D
: T = T + P
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Application Information (continued)
8.1.5.1 Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of
the LDO when in-circuit on a typical PCB board application. These metrics are not thermal resistances, but offer
practical and relative means of estimating junction temperatures. These psi metrics are independent of the
copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are used in accordance with Equation 4 and are
described in the table.
where:
• PDis the power dissipated as shown in Equation 2
• TTis the temperature at the center-top of the device package
• TBis the PCB surface temperature measured 1 mm from the device package and centered on the package
edge (4)
8.2 Typical Application
Figure 30. TLV755P Typical Application
8.2.1 Design Requirements
Table 2 lists the design requirements for this application.
Table 2. Design Parameters
PARAMETER DESIGN REQUIREMENT
Input voltage 4.3 V
Output voltage 3.3 V
Input current 500 mA (maximum)
Output load 250-mA DC
Maximum ambient temperature 70°C
l TEXAS INSTRUMENTS 100
Frequency (Hz)
Power Supply Rejection Ratio (dB)
0
20
40
60
80
100
10 100 1k 10k 100k 1M 10M
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 500 mA
I =
OUT(t)
COUT OUT
´dV (t)
dt
VOUT(t)
RLOAD
+
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8.2.2 Detailed Design Procedure
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use
Equation 5 to calculate the current through the input.
where:
• VOUT(t) is the instantaneous output voltage of the turn-on ramp
• dVOUT(t) / dt is the slope of the VOUT ramp
• RLOAD is the resistive load impedance (5)
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use Equation 6 to calculate the power dissipation. Multiply PDby RθJA as Equation 7
shows and add the ambient temperature (TA) to calculate the junction temperature (TJ).
PD= (IGND+ IOUT) × (VIN – VOUT) (6)
TJ= RθJA × PD+ TA(7)
Calculate the maximum ambient temperature as Equation 8 shows if the (TJ(MAX)) value does not exceed 125°C.
Equation 9 calculates the maximum ambient temperature with a value of 99.95°C.
TA(MAX) = TJ(MAX) – RθJA × PD(8)
TA(MAX) = 125°C – 100.2°C/W × (4.3 V – 3.3 V) × (0.25 A) = 99.95°C (9)
8.2.3 Application Curve
VIN = 4.3 V, VOUT = 3.3 V
Figure 31. PSRR vs Frequency (4.3 V to 3.3 V)
9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV755P. If the input source is
reactive, consider using multiple input capacitors in parallel with the 1-µF input capacitor to lower the input supply
impedance over frequency.
*9 TEXAS INSTRUMENTS 4‘ +4 % \44 \ Em $w : ww % +4 O
VIN
VOUT
GND PLANE
Represents via used for
application specific connections
1
2
34
6
CIN
COUT
EN
5
VOUT
VIN
GND PLANE
Represents via used for
application specific connections
1
2
34
5
COUT
CIN
EN
OUT IN
GND PLANE
Represents via used for application
specific connections
1
23
4
CIN
COUT
EN
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10 Layout
10.1 Layout Guidelines
Place input and output capacitors as close as possible to the device.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
10.2 Layout Examples
Figure 32. Layout Example for the DQN Package
Figure 33. Layout Example for the DBV Package
Figure 34. Layout Example for the DRV Package
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(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 0.6 V to 5 V in 50-mV increments are available. Contact the factory for details and availability.
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature(1)(2)
PRODUCT VOUT
TLV755xx(x)Pyyyz
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
Pindicates an active output discharge feature. All members of the TLV755P family actively discharge
the output when the device is disabled.
yyy is the package designator.
zis the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV75507PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KD
TLV75507PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KD
TLV75509PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1HAF
TLV75509PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AX
TLV75509PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AX
TLV75509PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1HDH
TLV75510PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FPF
TLV75510PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KE
TLV75510PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KE
TLV75510PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GUH
TLV75511PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 E8
TLV75512PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FQF
TLV75512PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AG
TLV75512PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AG
TLV75512PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GVH
TLV75515PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FRF
TLV75515PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KF
TLV75515PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KF
TLV75515PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GWH
TLV755185PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 EZ
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV75518PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FSF
TLV75518PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AI
TLV75518PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AI
TLV75518PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GXH
TLV75519PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1HBF
TLV75519PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 B5
TLV75519PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 B5
TLV75519PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1HEH
TLV75525PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FTF
TLV75525PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AJ
TLV75525PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AJ
TLV75525PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GZH
TLV75528PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FUF
TLV75528PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KG
TLV75528PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KG
TLV75528PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1H1H
TLV75529PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1HCF
TLV75529PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1HFH
TLV75530PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FVF
TLV75530PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KI
TLV75530PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 KI
I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV75530PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1H2H
TLV75533PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1FWF
TLV75533PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AN
TLV75533PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 AN
TLV75533PDRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1H3H
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 4
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV75507PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75507PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75507PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75507PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75509PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75509PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75509PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75509PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75509PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75509PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75509PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75510PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75510PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75510PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75510PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75510PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
Pack Materials-Page 1
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV75510PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75510PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75511PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75512PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75512PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75512PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75512PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75512PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75512PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75512PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75515PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75515PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75515PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75515PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75515PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75515PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75515PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV755185PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75518PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75518PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75518PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75518PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75518PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75518PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75518PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75519PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75519PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75519PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75519PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75519PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75519PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75525PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75525PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75525PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75525PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75525PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75525PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75525PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75528PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75528PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75528PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV75528PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75528PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75528PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75529PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75529PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75529PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75530PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75530PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75530PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75530PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75530PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75530PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV75533PDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV75533PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
TLV75533PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75533PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75533PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
TLV75533PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV75533PDRVR WSON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV75507PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75507PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75507PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75507PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75509PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75509PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75509PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75509PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75509PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75509PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75509PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75510PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75510PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75510PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75510PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75510PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75510PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75510PDRVR WSON DRV 6 3000 210.0 185.0 35.0
Pack Materials-Page 4
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV75511PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75512PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75512PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75512PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75512PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75512PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75512PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75512PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75515PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75515PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75515PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75515PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75515PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75515PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75515PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV755185PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75518PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75518PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75518PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75518PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75518PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75518PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75518PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75519PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75519PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75519PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75519PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75519PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75519PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75525PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75525PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75525PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75525PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75525PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75525PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75525PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75528PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75528PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75528PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75528PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75528PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75528PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75529PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
Pack Materials-Page 5
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV75529PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75529PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75530PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75530PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75530PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75530PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75530PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75530PDRVR WSON DRV 6 3000 210.0 185.0 35.0
TLV75533PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV75533PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV75533PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV75533PDQNR X2SON DQN 4 3000 183.0 183.0 20.0
TLV75533PDQNT X2SON DQN 4 250 183.0 183.0 20.0
TLV75533PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV75533PDRVR WSON DRV 6 3000 210.0 185.0 35.0
Pack Materials-Page 6
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
GENERIC PACKAGE VIEW DQN 4 XZSON - 0.4 mm max heigm PLASTIC SMALL OUTLINE , N0 LEAD Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 4210367”: I TEXAS INSTRI IMFNTS
PACKAGE OUTLINE
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
BA
SEATING PLANE
C
0.08
PIN 1
INDEX AREA
0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL)
NOTE 4
EXPOSED
THERMAL PAD
1
23
4
1
1.05
0.95
1.05
0.95
0.4 MAX
2X 0.65
0.48+0.12
-0.1
3X 0.30
0.15
0.3
0.2
4X 0.28
0.15
0.05
0.00
(0.11)
NOTE 5
NOTE 6
NOTE 6
5
(0.07) TYP
(0.05) TYP
EXAMPLE BOARD LAYOUT
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
LAND PATTERN EXAMPLE
SCALE: 40X
SYMM
SYMM
1
2
3
4
4X (0.21)
4X (0.36)
(0.65)
(0.86)
( 0.48)
SEE DETAIL
4X (0.18)
(0.22) TYP
EXPOSED METAL
CLEARANCE
4X
(0.03)
EXPOSED METAL
5
EXAMPLE STENCIL DESIGN
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
SYMM
SYMM
1
2
3
4
SOLDER MASK
EDGE
4X (0.21)
4X (0.4)
(0.65)
(0.9)
( 0.45)
4X (0.03)
4X (0.235)
4X (0.22)
5
I TEXAS INSTRUMENTS
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
DRV 6 WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4206925/F
% W C :1 v _ W dfiN g}gfi @ DJ
www.ti.com
PACKAGE OUTLINE
C
6X 0.35
0.25
1.6 0.1
6X 0.3
0.2
2X
1.3
1 0.1
4X 0.65
0.8
0.7
0.05
0.00
B2.1
1.9 A
2.1
1.9
(0.2) TYP
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
34
6
(OPTIONAL)
PIN 1 ID
0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
7
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 5.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1)
4X (0.65)
(1.95)
6X (0.3)
6X (0.45)
(1.6)
(R0.05) TYP
( 0.2) VIA
TYP
(1.1)
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
SYMM
1
34
6
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
7
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.3)
6X (0.45)
4X (0.65)
(0.7)
(1)
(1.95)
(R0.05) TYP
(0.45)
WSON - 0.8 mm max heightDRV0006A
PLASTIC SMALL OUTLINE - NO LEAD
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
SYMM
1
34
6
SYMM
METAL
7
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