EPC2045 Datasheet by EPC

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eGaN® FET DATASHEET EPC2045

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very

low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG

and zero QRR. The end result is a device that can handle tasks where very high switching frequency,

and low on-time are beneficial as well as those where on-state losses dominate.

EPC2045 eGaN® FETs are supplied

passivated die form with solder bumps

Die size: 2.5 mm x 1.5 mm

Applications

• Open Rack Server Architectures

• Lidar/Pulsed Power Applications

• USB-C

• Isolated Power Supplies

• Point of Load Converters

• Class D Audio

• LED Lighting

• Low Inductance Motor Drive

Benefits

• Ultra High Efficiency

• No Reverse Recovery

• Ultra Low QG

• Ultra Small Footprint

EFFICIENT POWER CONVERSION

HAL

EPC2045 – Enhancement Mode Power Transistor

VDS , 100 V

RDS(on) , 7 mΩ

ID , 16 A

Maximum Ratings

PARAMETER VALUE UNIT

VDS

Drain-to-Source Voltage (Continuous) 100 V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120

Continuous (TA = 25°C) 16 A

Pulsed (25°C, TPULSE = 300 µs) 130

VGS

Gate-to-Source Voltage 6V

Gate-to-Source Voltage -4

TJOperating Temperature -40 to 150 °C

TSTG Storage Temperature -40 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 1.4

°C/W RθJB Thermal Resistance, Junction-to-Board 8.5

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 64

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.

See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

# Defined by design. Not subject to production test.

Static Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 300 μA 100 V

IDSS Drain-Source Leakage VGS = 0 V, VDS = 80 V 40 250 µA

IGSS

Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25°C 0.01 0.25 mA

Gate-to-Source Forward Leakage#VGS = 5 V, TJ = 125°C 0.1 5 mA

Gate-to-Source Reverse Leakage VGS = -4 V 40 500 µA

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 5 mA 0.8 1.4 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 16 A 5.6 7 mΩ

VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.7 V

eGaN® FET DATASHEET EPC2045

ID – Drain Current (A)

VDS – Drain-to-Source Voltage (V)

120

VGS

= 5 V

V = 4 V

V = 3 V

V = 2 V

ID – Drain Current (A)

VGS – Gate-to-Source Voltage (V)

VGS – Gate-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V)

ID = 16 A

25˚C

125˚C

VDS = 3 V

25˚C

125˚C

Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics

Figure 3: RDS(on) vs. VGS for Various Drain Currents Figure 4: RDS(on) vs. VGS for Various Temperatures

ID = 8 A

ID = 16 A

ID = 24 A

ID = 32 A

2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0

1.0 1.5 2.0 2.5 3.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0 0.5

RDS(on) – Drain-to-Source Resistance (mΩ)

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CISS

Input Capacitance#

VDS = 50 V, VGS = 0 V

767 1016

CRSS

Reverse Transfer Capacitance

COSS

Output Capacitance#

295 443

COSS(ER)

Effective Output Capacitance, Energy Related (Note 2)

VDS = 0 to 50 V, VGS = 0 V 383

COSS(TR)

Effective Output Capacitance, Time Related (Note 3)

500

Gate Resistance

0.6 Ω

Total Gate Charge#

VDS = 50 V, VGS = 5 V, ID = 16 A 6 7.8

QGS

Gate-to-Source Charge

VDS = 50 V, ID = 16 A

1.9

QGD

Gate-to-Drain Charge

0.8

QG(TH)

Gate Charge at Threshold

1.3

QOSS

Output Charge#

VDS = 50 V, VGS = 0 V 25 38

QRR

Source-Drain Recovery Charge

# Defined by design. Not subject to production test.

Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.

Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

eGaN® FET DATASHEET EPC2045

Capacitance (pF)

1000

800

600

400

200

00 25 50 75 100 0 25 50 75 100

Figure 5a: Capacitance (Linear Scale)

Capacitance (pF)

1000

100

Figure 5b: Capacitance (Log Scale)

VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

Normalized On-State Resistance – RDS(on)

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0 25 50 75 100 125 150

Figure 9: Normalized On-State Resistance vs. Temperature

120

Figure 8: Reverse Drain-Source Characteristics

00 1 2 3 4 5 6

Figure 7: Gate Charge

1.6

1.2

0.8

0.4

0.0

Figure 6: Output Charge and C

OSS

Stored Energy

0 20 40 60 80 100

ID = 16 A

VDS = 50 V

ID = 16 A

VGS = 5 V

QOSS – Output Charge (nC)ISD – Source-to-Drain Current (A)

VGS – Gate-to-Source Voltage (V)

EOSS – COSS Stored Energy (µJ)

– Drain-to-Source Voltage (V)

2.5 2.0 3.0 3.5 0.5 0.0 1.0 1.5 4.0 4.5 5.0

25ºC

125ºC

– Gate Charge (nC)

– Source-to-Drain Voltage (V) T

– Junction Temperature (°C)

eGaN® FET DATASHEET EPC2045

Figure 11: Transient Thermal Response Curves

0.001

0.01

0.1

10-5 10-4 10-3 10-2 10-1 1 10

tp - Rectangular Pulse Duration [s]

ZθJB, Normalized Thermal Impedance

Duty Factors:

0.5

0.1

0.05

0.02

0.01

Single Pulse

0.2

Notes:

Duty Factor = tp/T

Peak TJ = PDM x ZθJB x RθJB + TB

Junction-to-Board

0.0001

0.01

0.001

0.1

tp - Rectangular Pulse Duration [s]

ZθC, Normalized Thermal Impedance

Junction-to-Case

Duty Factors:

0.5

0.1

0.05

0.02

0.01

Single Pulse

0.2

Notes:

Duty Factor = tp/T

Peak TJ = PDM x ZθJC x RθJC + TC

10-5 10-4 10-3 10-2 10-1 1 10

0 25 50 75 100 125 150

Figure 10: Normalized Threshold Voltage vs. Temperature

– Junction Temperature (°C)

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

ID = 5 mA

Normalized Threshold Voltage

eGaN® FET DATASHEET EPC2045

DIE MARKINGS

Figure 12: Safe Operating Area

0.1

100

0.1 1 10 100

ID- Drain Current (A)

VDS - Drain-Source Voltage (V)

TJ = Max Rated, TC = +25°C, Single Pulse

Pulse Width

1 ms

100 μs

10 μs

Limited by RDS(on)

2045

YYYY

ZZZZ

TAPE AND REEL CONFIGURATION

4mm pitch, 8mm wide tape on 7”reel

7” reel

d e f g

EPC2045 (note 1)

Dimension (mm) target min max

a 8.00 7.90 8.30

b 1.75 1.65 1.85

c (see note) 3.50 3.45 3.55

d 4.00 3.90 4.10

e 4.00 3.90 4.10

f (see note) 2.00 1.95 2.05

g 1.5 1.5 1.6

Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.

Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,

not the pocket hole.

Die

orientation

dot

Gate

solder bar is

under this

corner

Die is placed into pocket

solder bar side down

(face side down)

Loaded Tape Feed Direction

2045

YYYY

ZZZZ

Part

Number

Laser Markings

Part #

Marking Line 1

Lot_Date Code

Marking line 2

Lot_Date Code

Marking Line 3

EPC2045 2045 YYYY ZZZZ

Die orientation dot

Gate Pad bump is

under this corner

mw vaUU‘ ; 000 03,00 at. no.

eGaN® FET DATASHEET EPC2045

Information subject to

change without notice.

Revised March 19, 2020

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to

improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit

described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.

EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

RECOMMENDED

LAND PATTERN

(units in µm)

Pads 1 is Gate;

Pads 2, 3, 7, 8, 9, 13, 14, 15 are Source;

Pads 4, 5, 6, 10, 11, 12 are Drain;

The land pattern is solder mask defined.

Copper is larger than the solder mask opening.

DIE OUTLINE

Solder Bar View

Side View

DIM MICROMETERS

MIN Nominal MAX

A2470 2500 2530

B1470 1500 1530

c450

d500

e238 264 290

3 6 9 12 15

2 5 8 11 14

1 4 7 10 13

685 +/- 15

200 +/- 20

885

Seating Plane

1500

2500

450

230

500

2 5 8 11 14

3 6 9 12 15

1 4 7 10 13

1500

2500

450

250

300

500

2 5 8 11 14

3 6 9 12 15

1 4 7 10 13

RECOMMENDED

STENCIL DRAWING

(measurements in µm) Recommended stencil should be 4 mil (100 μm) thick,

laser cut. The corner has a radius of R60.

Intended for use with SAC305 Type 4

solder, reference 88.5% metals content.

Additional assembly resources available at

https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

Pads 1 is Gate;

Pads 2, 3, 7, 8, 9, 13, 14, 15 are Source;

Pads 4, 5, 6, 10, 11, 12 are Drain;

EPC2045 Datasheet by EPC

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