UC2906, UC3906 Datasheet by Texas Instruments

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f i" Unitrode Products _ trom Texas Instruments U02906 UC3906 INF:|0 ajva:Ilable Sealed Lead-Acid Battery Charger FEATURES - Optimum Control for Maximum Battery CapaCIty and Life - Internal State Logic Provides Three Charge States . Precision Reference Tracks Battery Requirements Over Temperature . Controls Both Voltage and Current at Charger Output . System Interface Functions . Typical Standby Supply Current of only 1.6mA DESCRIPTION The U02906 series of battery charger controllers contains all of the necessary circuitn/ to optimally control the charge and hold cycle tor sealed lead-acid bat- teries. These integrated circuits monitor and control both the output voltage and current of the charger through three separate charge states; a high current bulk-charge state, a controlled overcharge, and a precision float-charge, or standby. state. Optimum charging conditions are maintained over an extended temperature range with an internal relerence that tracks the nominal temperature characteris tics of the lead-acid cell. A typical standby supply current requirement of only 1.6mA allows these le to predictably monitor ambient temperatures. Separate voltage loop and current limit amplifiers regulate the output voltage and current levels in the charger by controlling the onboard driver. The driver will sup- ply at least 25mA of base drive to an external pass device. Voltage and current sense comparators are used to sense the battery condition and respond with logic inputs to the charge state logic. A charge enable comparator with a trickle bias output can be used to implement a low current turn-on mode 0! the charger, preventing high current charging during abnormal conditions such as a shorted battery cell. Other features include a supply under-voltage sense circuit with a logic output to indicate when input power is present. In addition the over-charge state of the charger can be externally monitored and terminated using the over-charge indi- cate output and overcharge terminate input. BLOCK DIAGRAM SINK souncs COMPENSATION I__I I6 I5 I13 DRNER «VIN CURRENT LIMIT vomzeg f AMPLIFIER 250 mV + , VDLTAGE C/l- ‘ sense + o/s our 7 7 SENSE VREF 0’5 * commence crs- HlGH 0.95 vnEF Low 0 so VREF tfl T‘RlCKLE .VIN —> VREF ems VREF 2.3 v ENABLE a| Va 5 mV/C CUMPARATOR one a , CHARGE J ENABLE + STATE LEVEL CONTROL POWER lNDICATE OVER-CHARGE lNDiCATE OVER-CHARGE TERMINATE SLUS1860 - SEPTEMBER 1996 - REVISED MAY 2005
UC2906 UC3906 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS Supply Voltage (+VIN) ......... .4DV Open Collector Output Voltages. . 40V SLEE'ZO’; LCC-20 (TOP VIEW) Amplifier and Comparator Input Voltages . 413v lo +40v . 3" ages Over- Charge Terminate Input Voltage. . —O.3V to +40V 3 2 ‘ 2019 Current Sense Amplifier Output Current. . BOmA Other Open Collector Output Currents. . .20mA 4 ‘5 Trickle Bias Voltage Dilterentlal with respect to VIN —32V 5 17 Trickle Bias Output Current —40mA 6 16 DrlverCurIent . BOmA 7 15 Power Dissipation at TA 25°C (Note 2). 1000mW B 14 Power Dissipation at T0 = 25%: (Note 2). 200mm 9 10 11 12 13 Operating Junction Temperature . . —55°C to +150°C Storage Temperature 65°C to +150”C Lead Temperature (Soldering. Io Seconds) .......... 300°C III/[:3 FUNCT'ON T" Nate 1: Voltages are referenced to ground (Pin 6). Currents C/S OUT 2 are positive into, negative out of, the specified termi- 0/5- 3 nels. C/S+ 4 Nate 2: Consult Packaging section of Datebook for thermal C/L 5 limitations and considerations of packages. WC 5 +VlN 7 BIL-16, sclc-1e (TOP VIEW) GROUND 8 J or N Package, DW Package POWER INDICATE 9 OVER CHARGE TERMINATE 10 ms our E U E DFilVEFI SINK N“: 11 OVER CHARGE INDICATE 12 WE . E El DRIVER SOURCE STATE LEVEL CONTROL 13 0/5 + [E E COMPENSATION TR'CKLE BIAS 14 CHARGE ENABLE 15 o/L E E VOLTAGE SENSE MC 15 mu I: 1:2] CHARGE ENABLE VOLTAGE SENSE 17 COMPENSATION 18 GROUND [3‘ fl TRICKLE BIAS DRIVER SOURCE 19 W [Z :0! ggfi;%O|_LE\/EL DRIVER SINK 20 OVER CHARGE Em TERMINATE E E liNDICATE ELECTRICAL CHARACTERISTICS: Unless Otherwise stated. these specifications apply Ior TA = 410°C to +70"C for the uczsoe and 0°C to +70°c Ior the Ungos, +vw =1ov,TA : TJ PARAMETER TEST CONDITIONS UCZBOG UCSBDB UNITS MIN I TVP I MAX MIN I we I MAX Input Supply Supply Current +VIN = 10V 1.6 3.3 1.6 3.3 mA +VIN = 40V 1.8 3.6 1.8 3.6 mA +VIN = 40V, TA : —40”C to 85°C 1‘8 4 mA Supply Under—Voltage Threshold +VIN = Low to High 4.2 4.5 4.8 4.2 4.5 4.5 V Supply Under—Voltage 0.20 0.30 0.20 0.80 V Hysteresis Internal Reference IVREF) Voltage Level (Note 3) Measured as Regulating Level at 2.275 2.3 2.325 2.270 2.3 2.330 V Pin 13 w/ Driver Current = 1mA. TJ = 25“C Line Regulation +VIN = 5 to 40V 3 8 3 8 mV Temperature Coefficient 4.5 —a.5 mV/“C
UC2906 UC3906 ELECTRICAL CHARACTERISTICS: Unless otherwise stated. these specifications apply ior TA: —40”c to +70°c for the UC2906 and one to +70%: for the 003906, +viN =10V,TA: T4 PARAMETER TEST CONDITIONS UCZSOS UC3906 UNITS MIN i 'rvp i MAX MIN i TVP i MAX Voltage Amplifier Input Bias Current Total Input Bias at Regulating Level 70.5 —0.2 -0.5 —0.2 1AA Maximum Output Current Source —45 730 —1 5 —45 430 —15 0A Sink 30 60 90 30 60 90 [AA Open Loop Gain Driver current = 1mA 50 65 50 65 dB Output Voltage Swing Volts above GND or below +ViN 0.2 0.2 V Driver Minimum Supply to Source Pin 16 = +ViN, Io :10mA 2.0 2.2 2.0 22 V Dillerential Maximum Output Current Pin 16 to Pin 15 = 2V 25 40 25 40 mA Saturation Voltage 0.2 0.45 0.2 0.45 V Current Limit Amplifier Input Bias Current 0.2 1.0 0.2 1.0 uA Threshold Voltage Offset below +V|N 225 250 275 225 250 275 mV Threshold Supply Sensitivity +ViN : 5 to 40V 0.03 0.25 0.03 0.25 %N Voltage Sense Comparator Threshold Voltage AS a iunction 0t VREFi L1 : RESET 0.94 0.949 0.960 0.94 0,949 0.960 V/V As a function at VHEF. Li = SET 0,095 0.90 0.910 0.895 0.90 0910 VN Input Bias Current Total Input Bias at Thresholds —0.5 70.2 —0.5 $2 uA current Sense Comparator Input Bias Current 0.1 0.5 0.1 0.5 uA Input Otiset Current 0.01 0.2 0.01 0.2 0A Input Oliset Voltage Referenced to Pin 2. louT= 1mA 20 25 30 20 25 30 mV Ottset Supply Sensitivity +V|N = 5 to 40V 0.05 0.35 0.05 0.35 u/a/V Offset Common Mode Sensitivity CMV = 2V to +ViN 0.05 0.35 0.05 0.35 °/e/V Maximum Output Current Vour = 2V 25 40 25 40 mA Output Saturation Voltage IGUT : 10rnA 0.2 0.45 0.2 0.45 V Enable Comparator Threshold Voltage As a function OI VREF 0.99 1.0 1.01 0.99 1.0 1.01 V/V Input Bias Current *05 —0.2 —0.5 —0.2 ILA Trickle Bias Maximum Output Vgu-r: +V|N , av 25 4O 25 40 mA Current Trickle Bias Maximum Output Volts below +ViN, lour= 10mA 2.0 2.6 2.0 2.6 V Voltage Trickle Bias Reverse Hold-Off +viN : 0v, IQUT = 7100A 6.3 7.0 6.3 7.0 V Voltage over-Charge Terminate Input Threshold Voltage 0.7 1.0 1.3 0.7 1.0 1.3 V Internal Pull-Up Current At Threshold 10 10 0A Open Collector Outputs (Pins 7. 9, and 10) Maximum Output Current VDUT = 2V 2.5 5 2.5 5 mA Saturation Voltage IOUT = 1.6mA 0.25 OAS 0.25 0.45 V lou‘r = 50uA 0.03 0.05 0.03 0.05 V Leakage Current Vour = 40V 1 3 1 a 0A Note 3. The relerence voltage will change as a function of power dissipation on the die according to the temperature coefficient 0! the reference and the thermal resistance, junction-tarambi'ent.
OPERATION AND APPLICATION INFORMATION 2.60 VREF GUARANTEED TOL. OVER TEMPERATURE UCZQDB ~40 C TO 70 C UCSQOG 0 C TO 70 C 2.50 2.40 2.30 Typical REFERENCE REGULATING LEVEL AT FIN 13 — (V) Characteristic 2.20 2.10 a , I 2.00 asset’eaeeess TEMPERATURE , l C) Internal reference temperature characteristic and tolerance. Dual Level Float Charger Operations The UC2906 is shown configured as a dual level float charger in Figure 1. All high currents are handled by the external PNP pass transistor with the driver supplying base drive to this device. This scheme uses the TRICKLE BIAS output and the charge enable comparator UC2906 U03906 to give the charger a low current turn on mode. The out- put current of the charger is limited to a low-level until the battery reaches a specified voltage, preventing a high current charging it a battery cell is shorted. Figure 2 shows the state diagram of the charger. Upon turn on the UV sense circuitry puts the charger in state 1, the high rate bulk-charge state. In this state, once the enable threshold has been exceeded, the charger will supply a peak current that is determined by the 250mV offset in the C/L amplifier and the sensing resistor R3. To guarantee full re-charge ol the battery, the Chargers voltage loop has an elevated regulating level, V00, dur- ing state 1 and state 2. When the battery voltage reaches 95% of V09, the charger enters the over-charge state, state 2. The charger stays in this state until the OVER-CHARGE TERMINATE pin goes high. In Figure 1, the charger uses the current sense amplifier to generate this signal by sensing when the charge current has ta» pered to a specified level, IOCT. Alternatively the over-charge could have been controlled by an external source, such as a timer. by using the OVER-CHARGE INDICATE signal at Pin 9. It a load is applied to the bat- tery and begins to discharge it, the charger will contribr ute its full output to the load. It the battery drops 10% below the float level, the charger will reset itself to state 1. When the load is removed a full charge cycle will fol- low. A graphical representation of a charge, and dis— charge, cycle of the dual lever float charger is shown in Figure 3. Rs INPUT suPprv Tuczeas ¢ BATTERY we) Ra Ra CHARGE INPUT _’ STATE LOGIC POWER ‘— MONITOR Figure 1. The U02906 in a dual level float charger.
OPERATION AND APPLICATION INFORMATION (cont) UC2906 U03906 Design Procedure 1) Pick divider current In Recommended value is 5am to 10mm. 2) RC:23VHD A STATE 2 3) FlA+Fl5:Ft5L/M :(vFezavyiD (“5' ( 4) RD=23VoFl5UM/(Voc—VF) '8 > 5) RA=(RsUM +FIX)(I_23VIVT) ,_ STATE 3 WHERE: RX =RC .RD l(Ftc + FID) g '5 5) FIB : Ram in, o _ V I: STATE 1 7) R5 :025VllMAX (”91 EC . STATE 1. BULK CHARGE _ 7 < 8}="" ”vol/”4”="" 25w”="" 5="" state="" 2:="" over="" charge="" l="" state="" 3:="" float="" charge="" g)="" iocr="M" 10="" nate;="" \42="o,gsvcm" charger="" output="" current="" renew»="" '="" for="" further="" design="" and="" application="" inlormatioh="" see="" uicc="" application="" note="" u-104="" figure="" 2.="" state="" diagram="" and="" design="" equations="" for="" the="" dual="" level="" float="" charger.="" input="" supply="" voltage="" charge="" voltage="" charge="" current="" state="" level="" output="" oc="" indicate="" output="" 00="" m7="" terminate="" _="" 7="" 7="" 7="" input="" (c/s="" out)="" state="" 1="" state="" 2="" state="" 3="" state="" i="" explanation:="" dual="" level="" float="" charger="" and="" the="" charge="" current="" begins="" to="" taper,="" a.="" input="" power="" tums="" on.="" battery="" charges="" at="" trickle="" current="" e="" charge="" current="" tapers="" to="" lccr.="" the="" currentsense="" amply?="" rate.="" fier="" output,="" in="" this="" case="" tied="" ta="" the="" oc="" terminate="" in»="" b.="" battery="" voltage="" reaches="" vr="" enabling="" the="" driver="" and="" tumr="" put,="" gees="" high,="" the="" charger="" changes="" to="" the="" float="" state="" rng="" all="" the="" trickle="" bias="" output,="" battery="" charges="" at="" imax="" and="" holds="" the="" battery="" vultage="" at="" vf.="" rate,="" f.="" here="" a="" lead="" (="">IMAx) begins to discharge the battery 0‘ Transition vultage V12 is reached and the charger indi- G The load discharges the battery such that the battery cates that It is now in the over—charge state, state 2, voltage falls below V31, The charger is now in state 1, D. Battery voltage approaches the over-charge level Voc again. Figure 3. Typical charge cycle: 002906 dual level float charger, 5
UCZQOG U03906 OPERATION AND APPLICATION INFORMATION (cont) Compensated Reference Matches Battery Requirements When the charger is in the float state, the battery will be maintained at a precise float voltage, VF. The accuracy of this float state will maximize the standby life of the battery while the bulk-charge and over-charge states guarantee rapid and full re-charge. All of the voltage thresholds on the UC2906 are derived lrorn the internal reference This reference has a temperature coefficient that tracks the temperature characteristic of the optimum-charge and hold levels for sealed lead»acid cells. This further guaran- tees that proper charging occurs, even at temperature extremes. Dual Step Current Charger Operation Figures 4, 5 and 6 illustrate the U02906’s use in a differ- ent charging scheme. The dual step current charger is useful when a large string of series cells must be charged. The holding—charge state maintains a slightly el- evated voltage across the batteries with the holding cur- rent, 1H. This will tend to guarantee equal charge distribution between the cells. The bulk-charge state is similar to that of the float charger with the exception that when V12 is reached, no over-charge state occurs since Pin 8 is tied high at all times. The current sense amplifier is used to regulate the holding current. In some applica- tions a series resistor, or external buffering transistor, may be required at the current sense output to prevent excessive power dissipation on the U02906. A PNP Pass Device Reduces Minimum Input to Out- put Differential The configuration of the driver on the UCZQDG allows a good bit of flexibility when interfacing to an external pass transistor. The two chargers shown in Figures i and 4 both use PNP pass devices, although an NPN device driven from the source output of the UCZQOG driver can also be used. In situations where the charger must oper- ate with low input to output differentials the PNP pass de- vice should be configured as shown in Figure 44 The PNP can be operated in a saturated mode with only the series diode and sense resistor adding to the minimum differen- tial. The series diode, D1, in many applications, can be eliminated. This diode prevents any discharging of the battery, except through the sensing divider, when the charger is attached to the battery with no input supply voltage, If discharging under this condition must be kept to an absolute minimum, the sense divider can be refera enced to the POWER INDICATE pin, Pin 7, instead at ground. In this manner the open collector off state of Pin 7 will prevent the divider resistors from discharging the battery when the input supply is removed. RsM lNPUT SUPFLV ripe BATTERY (Va) ; RA CHARGE STATE LOGIC ENABLE COMP Figure 4. The uczsos in a dual step current charger.
OPERATION AND APPLICATION INFORMATION (cont) UC2906 UC3906 STATE 2 CHARGER OUTPUT VOLTAGE STATE 1: IMAX + IH STATE 1 BULK CHARGE STATE 2! HOLDING CHARGE CHARGER OUTPUT CURRBQT v12 VF 1.) v12 = .95 VREF (1+ %+ 3—3) 2.) VF = VHEF(1+%) a.) v21 : 9 VF 4.) Imx = $2": 5.) [H : gas? Figure 5. State Diagram and design equations [or the dual step current charger: INPUT SUPPLV VOLTAGE CHARGE VOLTAGE CHARGE CURRENT STATE OFF LEVEL ON Explanatian: Dual Step Current Charger A. IMAX. B. the holding current in Input power turns on, battery charges at a rate of lH + *—STATE 1+STATE 2+STATE 1 C. D: Battery vnltage reaches V12 and the vnltage loop swttchss to the lower level VF The battery is new fed with E, An external load starts to discharge the battery When V): is reached the charger will supply the full cur- rent lMAx + lH. The discharge continues and the battery voltage reaches V21 causing the charger to switch back to state 1. Figure 6. Typical charge cycle: UC2906 dual step current charger
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UC2906DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 70 UC2906DW
UC2906DWG4 ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 70 UC2906DW
UC2906DWTR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 70 UC2906DW
UC2906N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 70 UC2906N
UC2906NG4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 70 UC2906N
UC3906DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW
UC3906DWG4 ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW
UC3906DWTR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW
UC3906DWTRG4 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -20 to 70 UC3906DW
UC3906N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -20 to 70 UC3906N
UC3906NG4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -20 to 70 UC3906N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UC2906DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC3906DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2906DWTR SOIC DW 16 2000 853.0 449.0 35.0
UC3906DWTR SOIC DW 16 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
SOIC - 2.65 mm max heightDW 16
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
4224780/A
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PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
14X 1.27
16X 0.51
0.31
2X
8.89
TYP
0.33
0.10
0 - 8 0.3
0.1
(1.4)
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
10.5
10.1
B
NOTE 4
7.6
7.4
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
£3ng
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EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (2)
16X (0.6)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
Egg e %
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EXAMPLE STENCIL DESIGN
R0.05 TYP
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
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