MAX5171/73 Datasheet by Analog Devices Inc./Maxim Integrated

Datasheet Feedback/Errors

[VI/JXI/VI [MAXIM \ \ ﬂﬂﬂﬂﬂﬂﬂﬂ LILILILILILILILI [VI/JXIIVI

General Description

The MAX5171/MAX5173 low-power, serial, voltage-output,

14-bit digital-to-analog converters (DACs) feature a preci-

sion output amplifier in a space-saving 16-pin QSOP

package. The MAX5171 operates from a +5V single sup-

ply, and the MAX5173 operates from a +3V single supply.

The output amplifier’s inverting input is available to allow

specific gain configurations, remote sensing, and high

output current capability. This makes the MAX5171/

MAX5173 ideal for a wide range of applications, including

industrial process control. Both devices draw only 260µA

of supply current, which reduces to 1µA in shutdown

mode. In addition, the programmable power-up reset fea-

ture allows for a user-selectable output voltage of either 0

or midscale.

The 3-wire serial interface is compatible with SPI™,

QSPI™, and MICROWIRE™ standards. An input register

followed by a DAC register provides a double-buffered

input, allowing the input and DAC registers to be updated

independently or simultaneously with a 16-bit serial word.

Additional features include software and hardware shut-

down, shutdown lockout, a hardware clear pin, and a ref-

erence input capable of accepting DC and offset AC

signals. These devices provide a programmable digital

output pin for added functionality and a serial-data output

pin for daisy-chaining. All logic inputs are TTL/CMOS-

compatible and are internally buffered with Schmitt trig-

gers to allow direct interfacing to optocouplers.

The MAX5171/MAX5173 incorporate a proprietary on-chip

circuit that keeps the output voltage virtually “glitch free,”

limiting the glitches to a few millivolts during power-up.

Both devices are available in 16-pin QSOP packages and

are specified for the extended (-40°C to +85°C) tempera-

ture range. The MAX5171/MAX5173 are pin-compatible

upgrades to the 12-bit MAX5175/MAX5177. For 100% pin-

compatible DACs with an internal reference, see the 13-bit

MAX5132/MAX5133 and the 12-bit MAX5122/MAX5123

data sheets.

Applications

Features

♦±1 LSB INL

♦1µA Shutdown Current

♦“Glitch Free” Output Voltage at Power-Up

♦Single-Supply Operation: +5V (MAX5171)

+3V (MAX5173)

♦Full-Scale Output Range:

+2.048V (MAX5173, VREF = +1.25V)

+4.096V (MAX5171, VREF = +2.5V )

♦Rail-to-Rail®Output Amplifier

♦Low THD (-80dB) in Multiplying Operation

♦SPI/QSPI/MICROWIRE-Compatible 3-Wire

Serial Interface

♦Programmable Shutdown Mode and Power-Up

Reset

♦Buffered Output Capable of Driving 5kΩ|| 100pF

Loads

♦User-Programmable Digital Output Pin Allows

Serial Control of External Components

♦Pin-Compatible Upgrade to the 12-Bit

MAX5175/MAX5177

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

________________________________________________________________

Maxim Integrated Products

19-1476; Rev 0; 4/99

Pin Configuration

Functional Diagram appears at end of data sheet.

FB VDD

N.C.

REF

AGND

PDL

UPO

DOUT

DGND

TOP VIEW

MAX5171

MAX5173

QSOP

OUT

SHDN

CLR

DIN

SCLK

Ordering Information

Digitally Programmable 4–20mA Current Loops

Industrial Process Control

Digital Offset and Gain Adjustment

Motion Control

Automatic Test Equipment (ATE)

Remote Industrial Controls

µP-Controlled Systems

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

PART

MAX5171AEEE

MAX5171BEEE

MAX5173AEEE -40°C to +85°C

-40°C to +85°C

TEMP. RANGE PIN-PACKAGE

16 QSOP

MAX5173BEEE -40°C to +85°C 16 QSOP

INL

(LSB)

±1

±2

±4

[MAXI/VI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX5171

(VDD = +5.0V ±10%, VREF = +2.5V, AGND = DGND, FB = OUT, RL= 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX,

unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to AGND, DGND............................................-0.3V to +6.0V

AGND to DGND.....................................................-0.3V to +0.3V

Digital Inputs to DGND..........................................-0.3V to +6.0V

DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V)

FB, OUT, REF to AGND .............................-0.3V to (VDD + 0.3V)

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (TA= +70°C)

16-pin QSOP (derate 8mW/°C above +70°C)..............667mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

Bits14Resolution MAX5171A ±1

MAX5171B LSB

±2

INLIntegral Nonlinearity (Note 1)

LSB±1DNLDifferential Nonlinearity mV±10VOS

Offset Error (Note 2) RL= ∞LSB

-0.6 ±4

GEGain Error RL= 5kΩ-1.6 ±8 µV/V10 120PSRRPower-Supply Rejection Ratio f = 100kHz LSBp-p1Output Noise Voltage nV/√Hz

50Output Thermal Noise Density

V0V

DD - 1.4VREF

Reference Input Range kΩ18RREF

Reference Input Resistance

VREF = 0.5Vp-p + 2.5VDC, slew-rate limited kHz350Reference -3dB Bandwidth

VREF = 1.4Vp-p + 2.5VDC, f = 10kHz,

code = 3FFF hex dB84SINAD

Signal-to-Noise Plus Distortion

Ratio

V3VIH

Input High Voltage V0.8VIL

Input Low Voltage mV200VHYS

Input Hysteresis VIN = 0 or VDD µA0.001 ±1IIN

Input Leakage Current pF8CIN

Input Capacitance

ISOURCE = 2mA VVDD - 0.5VOH

Output High Voltage ISINK = 2mA V0.13 0.4VOL

Output Low Voltage

VREF = 3.6Vp-p + 1.8VDC, f = 1kHz,

code = all 0s dB-84Reference Feedthrough

STATIC PERFORMANCE

REFERENCE

MULTIPLYING-MODE PERFORMANCE

DIGITAL INPUTS

DIGITAL OUTPUTS

lVI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX5171 (continued)

(VDD = +5V ±10%, VREF = +2.5V, AGND = DGND, FB = OUT, RL= 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX,

unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS

V/µs0.6SRVoltage Output Slew Rate

V0V

Output Voltage Swing (Note 3) µA-0.1 0 0.1Current into FB µs40Time Required to Exit Shutdown

UNITSMIN TYP MAXSYMBOLPARAMETER

CS = VDD; fSCLK = 100kHz, VSCLK = 5Vp-p nV-s1Digital Feedthrough

V4.5 5.5VDD

Positive Supply Voltage mA0.26 0.35IDD

Power-Supply Current (Note 4) µA110Shutdown Current (Note 4)

ns100tCP

SCLK Clock Period ns40tCH

SCLK Pulse Width High ns40tCL

SCLK Pulse Width Low

ns40tCSS

CS Fall to SCLK Rise Setup

Time

ns40tDS

SDI Setup Time ns0tDH

SDI Hold Time

CLOAD = 200pF ns80tDO1

SCLK Rise to DOUT Valid

Propagation Delay

CLOAD = 200pF ns80tDO2

SCLK Fall to DOUT Valid

Propagation Delay

ns10tCS0

SCLK Rise to CS Fall Delay

ns100tCSW

CS Pulse Width High

ns0tCSH

SCLK Rise to CS Rise Hold

Time

ns40tCS1

CS Rise to SCLK Rise Hold Time

To ±0.5LSB, from 10mV to full scale µs12Output Settling Time

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

[VIAXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS—MAX5173

(VDD = +2.7V to +3.6V, VREF = 1.25V, AGND = DGND, FB = OUT, RL= 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX,

unless otherwise noted. Typical values are at TA= +25°C).

Bits14Resolution MAX5173A ±2

VREF = 1.6Vp-p + 0.8VDC, f = 1kHz,

code = all 0s dB

MAX5173B LSB

±4

INLIntegral Nonlinearity (Note 5)

LSB±1DNLDifferential Nonlinearity mV±10

CONDITIONS

VOS

Offset Error (Note 2) RL= ∞LSB

-0.6 ±4

GEGain Error RL= 5kΩ-1.6 ±8

-84

µV/V10 120PSRRPower-Supply Rejection Ratio f = 100kHz LSBp-p2Output Noise Voltage nV/√Hz

50Output Thermal Noise Density

V0V

DD - 1.4VREF

Reference Input Range kΩ18RREF

Reference Input Resistance

VREF = 0.5Vp-p + 1.25VDC, slew-rate limited kHz350Reference -3dB Bandwidth

VREF = 0.9Vp-p + 1.25VDC, f = 10kHz,

code = 3 FFF Hex dB78SINAD

Signal-to-Noise Plus Distortion

Ratio

Reference Feedthrough

V2.2VIH

Input High Voltage V0.8VIL

Input Low Voltage mV200VHYS

Input Hysteresis VIN = 0 or VDD µA-1 0.001 ±1IIN

Input Leakage Current

UNITSMIN TYP MAXSYMBOLPARAMETER

pF8CIN

Input Capacitance

ISOURCE = 2mA VVDD - 0.5VOH

Output High Voltage ISINK = 2mA V0.13 0.4VOL

Output Low Voltage

STATIC PERFORMANCE

REFERENCE

MULTIPLYING-MODE PERFORMANCE

DIGITAL INPUTS

DIGITAL OUTPUTS

lVI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

_______________________________________________________________________________________ 5

Note 1: INL guaranteed between codes 64 and 16383.

Note 2: Offset is measured at the code that comes closest to 10mV.

Note 3: Accuracy is better than 1.0 LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points.

Note 4: RL= open and digital inputs are either VDD or DGND.

Note 5: INL guaranteed between codes 128 and 16383.

ELECTRICAL CHARACTERISTICS—MAX5173 (continued)

(VDD = +2.7V to +3.6V, VREF = 1.25V, AGND = DGND, FB = OUT, RL= 5kΩ, CL= 100pF referenced to ground, TA= TMIN to TMAX,

unless otherwise noted. Typical values are at TA= +25°C).

µA110Shutdown Current (Note 4)

ns150tCP

SCLK Clock Period ns75tCH

SCLK Pulse Width High ns75

CONDITIONS

tCL

SCLK Pulse Width Low

ns60tCSS

CS Fall to SCLK Rise Setup

Time

ns0tCSS

SCLK Rise to CS Rise Hold

Time

ns60tDS

SDI Setup Time ns0tDH

SDI Hold Time

CLOAD = 200pF ns200tDO1

SCLK Rise to DOUT Valid

Propagation Delay

ns75tCS1

CS Rise to SCLK Rise Hold Time

CLOAD = 200pF ns200tDO2

SCLK Fall to DOUT Valid

Propagation Delay

To ±0.5LSB, from 10mV to full-scale µs12Output Settling Time

ns10tCS0

SCLK Rise to CS Fall Delay

ns150tCSW

CS Pulse Width High

V/µs0.6SRVoltage Output Slew Rate

V0 VDD

Output Voltage Swing (Note 3) µA-0.1 0 0.1Current into FB µs40Time Required to Exit Shutdown

UNITSMIN TYP MAXSYMBOLPARAMETER

CS = VDD, DIN = 50kHz; fSCLK = 100kHz,

VSCLK = 3Vp-p nV-s1Digital Feedthrough

V2.7 3.6VDD

Positive Supply Voltage mA0.26 0.35IDD

Power-Supply Current (Note 4)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

[VI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

6 _______________________________________________________________________________________

Typical Operating Characteristics

(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA= +25°C,

unless otherwise noted.)

210

240

230

220

250

260

270

280

290

300

310

4.4 4.84.6 5.0 5.2 5.4 5.6

NO LOAD SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX5171 toc01

SUPPLY VOLTAGE (V)

NO-LOAD SUPPLY CURRENT (µA)

248

252

250

258

256

254

264

262

260

266

-50 -10 10-30 30 50 70 90

NO LOAD SUPPLY CURRENT

vs. TEMPERATURE

MAX5171-02

TEMPERATURE (°C)

NO-LOAD SUPPLY CURRENT (µA)

0.8

1.0

0.9

1.2

1.1

1.3

1.4

-50 10 30-30 -10 50 70 90

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

MAX5171 toc03

TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT (µA)

2.49930

2.49934

2.49938

2.49942

2.49946

2.49950

-50 -10 10-30 30 50 70 90

OUTPUT VOLTAGE vs. TEMPERATURE

MAX5171-04

TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

VOUT

1V/div

VCS

5V/div

2.5V

10mV

2µs/div

DYNAMIC RESPONSE

MAX5171-07

10k 100k

0.5

1.0

1.5

2.0

2.5

3.0

10 100 1k

OUTPUT VOLTAGE vs. LOAD RESISTANCE

MAX5171-05

LOAD RESISTANCE (Ω)

OUTPUT VOLTAGE (V)

VOUT

1V/div

VCS

5V/div

2.5V

10mV

2µs/div

DYNAMIC RESPONSE

MAX5171-06

10k 100k

-92

-90

-88

-86

-84

-82

-80

-78

10 100 1k

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

MAX5171-08

FREQUENCY (Hz)

THD + NOISE (dB)

VOUT/VREF

12.5dB/div

20 10k

REFERENCE FEEDTHROUGH

MAX5171 toc9

FREQUENCY (Hz)

VREF = 1.8VDC + 3.6Vp-p at f = 1kHz

MAX5171

[VI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

_______________________________________________________________________________________

VOUT/VREF

12.5dB/div

20 100k

FFT PLOT

MAX5171 toc10

FREQUENCY (Hz)

VREF = 2.5VDC + 1.414Vp-p

VCS

2V/div

VOUT

100mV/div

MAJOR-CARRY TRANSITION

MAX5171 toc11

5µs/div

VOUT

2mV/div

AC-COUPLED

VSCLK

5V/div

DIGITAL FEEDTHROUGH

MAX5171 toc12

400ns/div

-25

-20

-10

-15

-5

0 1000500 1500 2000 2500 3000

REFERENCE VOLTAGE

INPUT FREQUENCY RESPONSE

MAX5171-13

FREQUENCY (kHz)

GAIN (dB)

VREF = 0.67Vp-p + 2.5VDC

252

256

254

260

258

266

264

262

268

-50 -10-30 10 30 50 70 90

NO-LOAD SUPPLY CURRENT

vs. TEMPERATURE

MAX5173-16

TEMPERATURE (°C)

NO-LOAD SUPPLY CURRENT (µA)

VDD

1V/div

VOUT

10mV/div

AC-COUPLED

START-UP GLITCH

MAX5171 toc14

50ms/div

230

240

235

250

245

260

255

265

275

270

280

2.5 2.7 2.8 2.92.6 3 3.1 3.2 3.43.3 3.5

NO-LOAD SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

NO-LOAD SUPPLY CURRENT (µA)

MAX5171 toc15

0.44

0.48

0.46

0.52

0.50

0.58

0.56

0.54

0.60

-50 -10-30 10 30 50 70 90

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

MAX5173 toc17

TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT (µA)

Typical Operating Characteristics (continued)

(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA= +25°C,

unless otherwise noted.) MAX5171

MAX5173

Ac ODUPLED [VI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA= +25°C,

unless otherwise noted.)

10k 100k

0.2

0.4

0.8

0.6

1.0

1.2

1.4

10 100 1k

OUTPUT VOLTAGE vs. LOAD RESISTANCE

MAX5173-19

LOAD (Ω)

OUTPUT VOLTAGE (V)

VOUT

500mV/div

VCS

3V/div

1.25V

10mV

2µs/div

DYNAMIC RESPONSE

MAX5173-20

VOUT

500mV/div

VCS

3V/div

1.25V

10mV

2µs/div

DYNAMIC RESPONSE

MAX5173-21

10k 100k

-88

-84

-86

-82

-78

-80

-74

-76

-72

10 100 1k

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

MAX5173-22

FREQUENCY (Hz)

THD + NOISE (dB)

OUT

100mV/div

AC-COUPLED 5µs/div

MAJOR-CARRY TRANSITION

MAX5173 toc25

2V/div

VOUT/VREF

12.5dB/div

20 10k

REFERENCE FEEDTHROUGH

MAX5173 toc23

FREQUENCY (Hz)

VREF = 0.8VDC =1.6Vp-p at 1kHz

VOUT/VREF

12.5dB/div

20 100k

FFT PLOT

MAX5173 toc24

FREQUENCY (Hz)

VREF = 1.5VDC + 0.848Vp-p, at f = 10kHz

OUT

500µV/div

2µs/div

SCLK

2V/div

DIGITAL FEEDTHROUGH

MAX5173 toc26

AC-COUPLED

12493

1.2494

1.2495

1.2496

1.2497

1.2498

-50 -10 10-30 30 50 70 90

OUTPUT VOLTAGE vs. TEMPERATURE

MAX5173-18

TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

MAX5173

[VI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(MAX5171: VDD = +5V, VREF = 2.5V; MAX5173: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = 3FFF hex, TA= +25°C,

unless otherwise noted.)

-25.0

-20.0

-10.0

-15.0

-5.0

0 1000500 1500 2000 2500 3000

REFERENCE VOLTAGE

INPUT FREQUENCY RESPONSE

MAX5173-27

FREQUENCY (kHz)

GAIN (dB)

VREF = 0.67Vp-p + 1.25VDC

VDD

(1V/div)

VOUT

(10mV/div)

AC-COUPLED

START-UP GLITCH

MAX5173 toc28

50ms/div

Pin Description

Voltage Output. High impedance in shutdown. Output voltage is limited to VDD.OUT2

Power-Down Lockout (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable shut-

down.

PDL

Reset Mode Select (digital input). Connect to VDD to select midscale reset output value. Connect to DGND

to select 0 reset output value.

RS3

Chip-Select Input (digital input)

Serial Clock Input (digital input)SCLK8

Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.DIN7

Clear DAC (digital input). Clears the DAC to its predetermined output state as set by RS.

CLR

Serial-Data OutputDOUT10

Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown mode with a

maximum shutdown current 0f 10µA.

SHDN12

User-Programmable Output. State is set by serial input.UPO11

Reference Input. Maximum VREF is VDD - 1.4V.REF14

Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a 0.1µF capacitor.VDD

Feedback InputFB1

FUNCTIONNAME

No Connection N.C.15

Analog GroundAGND13

Digital GroundDGND9

WT?

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

10 ______________________________________________________________________________________

Detailed Description

The MAX5171/MAX5173 14-bit, serial, voltage-output

DACs operate with a 3-wire serial interface. These

devices include a 16-bit shift register and a double-

buffered input composed of an input register and a

DAC register (see

Functional Diagram

). In addition, the

negative terminal of the output amplifier is available.

The DACs are designed with an inverted R-2R ladder

network (Figure 1), which produces a weighted voltage

proportional to the reference voltage.

Reference Input

The reference input accepts both AC and DC values

with a voltage range extending from 0 to VDD - 1.4V.

The following equation represents the resulting output

voltage:

where N is the numeric value of the DAC’s binary input

code (0 to 16383), VREF is the reference voltage, and

Gain is the externally set voltage gain. The maximum

output voltage is VDD. The reference pin has a mini-

mum impedance of 18kΩand is code dependent.

Output Amplifier

The MAX5171/MAX5173’s DAC output is internally

buffered by a precision amplifier with a typical slew rate

of 0.6V/µs. Access to the output amplifier’s inverting

input provides flexibility in output gain setting and sig-

nal conditioning (see

Applications Information

The output amplifier settles to ±0.5LSB from a full-scale

transition within 12µs, when loaded with 5kΩin parallel

with 100pF. Loads less than 2kΩdegrade performance.

Shutdown Mode

The MAX5171/MAX5173 feature a software- and hard-

ware-programmable shutdown mode that reduces the

typical supply current to 1µA. Enter shutdown by writing

the appropriate input-control word as shown in Table 1,

or by using the hardware shutdown. In shutdown mode,

the reference input and amplifier output become high-

impedance, and the serial interface remains active.

Data in the input register is saved, allowing the

MAX5171/MAX5173 to recall the prior output state

when returning to normal operation. To exit shutdown,

reload the DAC register from the shift register by simul-

taneously loading the input and DAC registers or by

toggling PDL. When returning from shutdown, wait 40µs

for the output to settle.

Power-Down Lockout

Power-down lockout disables the software/hardware

shutdown mode. A high-to-low transition on PDL brings

the device out of shutdown, returning the output to its

previous state.

Shutdown

Pulling SHDN high while PDL is high places the

MAX5171/MAX5173 in shutdown mode. Pulling SHDN

low does not return the device to normal operation. A

high-to-low transition on PDL or an appropriate com-

mand from the serial data line is required to exit shut-

down (see Table 1 for commands).

Serial Interface

The MAX5171/MAX5173 3-wire serial interface is com-

patible with SPI/QSPI (Figure 2) and MICROWIRE

(Figure 3) interface standards. The 16-bit serial input

word consists of two control bits and 14 bits of data

(MSB to LSB).

The control bits determine the MAX5171/MAX5173’s

response as outlined in Table 1. The MAX5171/

MAX5173’s digital inputs are double buffered, which

allows any of the following:

• Loading the input register without updating the DAC

• Updating the DAC register from the input register.

• Updating the input and DAC registers simultaneously.

VV N Gain

OUT REF

=⋅⋅

16384

OUT

SHOWN FOR ALL 1s ON DAC

D11

2R 2R 2R 2R 2R

RRR

REF

AGND

Figure 1. Simplified DAC Circuit Diagram

MAXI/VI [VI/JXIIM lVI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

______________________________________________________________________________________ 11

The MAX5171/MAX5173 accepts one 16-bit packet or

two 8-bit packets sent while CS remains low. The

MAX5171/MAX5173 allow the following to be config-

ured:

• Clock edge on which serial data output (DOUT) is

clocked.

• State of the user-programmable logic output.

• Configuration of the reset state.

Specific commands for setting these are shown in

Table 1.

The general timing diagram in Figure 4 illustrates how

the MAX5171/MAX5173 acquire data. CS must go low

at least tCSS before the rising edge of the serial clock

(SCLK). With CS low, data is clocked into the register on

the rising edge of SCLK. The maximum serial clock fre-

quency guaranteed for proper operation is 10MHz for

the MAX5171 and 6MHz for the MAX5173. See Figure 5

for a detailed timing diagram of the serial interface.

Serial Data Output (DOUT)

The serial-data output, DOUT, is the internal shift regis-

ter’s output; it allows for daisy-chaining of multiple

devices as well as data readback (see

Applications

Information

). By default upon start-up, data shifts out of

DOUT on the serial clock’s rising edge (Mode 0) and

provides a lag of 16 clock cycles, thus maintaining SPI,

QSPI, and MICROWIRE compatibility. However, if the

device is programmed for Mode 1, then the output data

lags DIN by 16.5 clock cycles and is clocked out on the

serial clock’s rising edge. During shutdown, DOUT

retains its last digital state prior to shutdown.

User-Programmable Logic Output (UPO)

The UPO allows control of an external device through

the serial interface, thereby reducing the number of

Load input register; DAC registers are updated (start up DAC with new data).10 Load input register; DAC registers are unchanged.00 14-bit DAC data

14-bit DAC data

16-BIT SERIAL WORD

D13..................D0C1 FUNCTION

No operation (NOP).11 0 0 x xxx xxxx xxxx

x x x xxx xxxx xxxx Update DAC register from input register (start up DAC with data previously

stored in the input registers).

UPO goes low (default).11 1 0 0 xxx xxxx xxxx

0 1 x xxx xxxx xxxx

Mode 1, DOUT clocked out on SCLK’s rising edge.11 1 1 0 xxx xxxx xxxx

1 0 1 xxx xxxx xxxx UPO goes high.11

Shut down DAC (provided PDL = 1).

Mode 0, DOUT clocked out on SCLK’s falling edge (default).11 1 1 1 xxx xxxx xxxx

SCLK

DIN

MOSI

SCK

+5V

I/O

CPOL = 0, CPHA = 0

SPI/QSPI

PORT

MAX5171

MAX5173

Figure 2. Connections for SPI/QSPI

SCLK

DIN

I/O

MICROWIRE

PORT

MAX5171

MAX5173

Figure 3. Connections for MICROWIRE

Table 1. Serial-Interface Programming Commands

1 i I‘—=3 F 1 We» 1 >;< j="" ‘=""><>< v‘="" 5»="" ‘="" 1="" ‘i="" k="" ‘="" 3x="" [maxi/iii="">

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

12 ______________________________________________________________________________________

microcontroller I/O pins required. During power-down,

this output will retain its digital state prior to shutdown.

When CLR is pulled low, UPO will reset to its program-

med default state. See Table 1 for specific commands

to control the UPO.

Reset (RS) and Clear (

CLR

)

The MAX5171/MAX5173 offers a clear pin which resets

the output voltage. If RST = DGND, then CLR resets the

output voltage to the minimum voltage (0 if no offset is

introduced). If RST = VDD, then CLR resets the output

voltage to midscale. In either case, CLR resets UPO to

its programmed default state.

___________Applications Information

Unipolar Output

Figure 6 shows the MAX5171/MAX5173 configured for

unipolar, rail-to-rail operation with a gain of +2V/V. Table 2

lists the codes for unipolar output voltages. The output

voltage is limited to VDD .

Bipolar Output

Figure 7 shows the MAX5171/MAX5173 configured for

bipolar output operation. The output voltage is given by

the following equation (FB = OUT):

where N represents the numeric value of the DAC’s

binary input code and VREF is the voltage of the exter-

nal reference. Table 3 shows digital codes and the cor-

responding output voltage for Figure 7’s circuit.

VV N

OUT REF

=−











⋅

16384 1

SCLK

DIN

COMMAND

EXECUTED

816

C2 S0

C0 D9 D8 D7 D6 D3 D2 D1 D0 S2 S1D5 D4

Figure 4. Serial-Interface Timing Diagram

SCLK

DIN

DOUT

CSW

CS1

CSH

CSS

CSO

D02

D01

tDH

Figure 5. Detailed Serial-Interface Timing Diagram

\ F . MW. $31 W: €51 L j J. [VI/JXIIVI

Daisy-Chaining Devices

The serial data output pin (DOUT) allows multiple

MAX5171/MAX5173s to be daisy-chained together, as

shown in Figure 8. The advantage of this is that only

two lines are needed to control all of the DACs on the

line. The disadvantage is that it takes

commands to

program the DACs. Figure 9 shows several MAX5171/

MAX5173s sharing one common DIN signal line. In this

configuration, the data bus is common to all devices.

However, this configuration uses more I/O lines

because each device requires a dedicated CS line.

The benefit is that only one command is needed to pro-

gram any DAC.

Using an AC Reference

The MAX5171/MAX5173 accepts reference voltages

with AC components as long as the reference voltage

remains between 0 and VDD - 1.4V. Figure 10 shows a

technique for applying a sine-wave signal to the REF.

The reference voltage must remain above AGND.

Digitally Programmable Current Source

The circuit of Figure 11 places an NPN transistor

(2N3904 or similar) within the op amp feedback loop to

implement a digitally programmable, unidirectional cur-

rent source. The output current is calculated with the

following equation:

where N is the numeric value of the DAC’s binary input

code and R is the sense resistor shown in Figure 11.

IVN

OUT REF

=⋅

⋅

16384

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

______________________________________________________________________________________ 13

DAC CONTENTS

MSB LSB

11 1111 1111 1111

10 0000 0000 0001 2 · VREF (8193/16384)

2 · VREF (16383/16384)

ANALOG OUTPUT

10 0000 0000 0000 2 · VREF (8192/16384)

01 1111 1111 1111 2 · VREF (8191/16384)

00 0000 0000 0001 2 · VREF (1/16384)

00 0000 0000 0000 0

DAC VOUT

V+

V-

+5V/+3.3V

REF 10k 10k

OUT

VDD

GND

MAX5171

MAX5173

Figure 7. Bipolar Output Circuit

Table 2. Unipolar Code Table

(Circuit of Figure 6) Table 3. Bipolar Code Table

(Circuit of Figure 7)

MAX5171

MAX5173

DAC

REF

OUT

10k

GND

+5V/+3.3V

VDD FB

Figure 6. Unipolar Output Circuit (Rail-to-Rail)

DAC CONTENTS

MSB LSB

11 1111 1111 1111

10 0000 0000 0001 +VREF [(2 ·8193/16384) - 1]

+VREF [(2 ·16383/16384) - 1]

ANALOG OUTPUT

01 1111 1111 1111 +VREF [(2 ·8191/16384) - 1]

00 0000 0000 0001 +VREF [(2 ·1/16384) - 1]

10 0000 0000 0000 +VREF [(2 ·8192/16384) - 1]

00 0000 0000 0000 -VREF

[MAXI/M [M[IXI[M [MAXI/M [MAXI[M [MAXI[M [MAXI[M [MAXI/III

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

14 ______________________________________________________________________________________

Power-Supply and Layout Considerations

Wire-wrap boards are not recommended. For optimum

system performance, use PC boards with separate

analog and digital ground planes. Connect the two

ground planes together at the low-impedance power-

supply source. Connect the DGND and AGND pins

together at the IC. The best ground connection is

achieved by connecting the DAC’s DGND and AGND

pins together and connecting that point to the system

analog ground plane. If the DAC’s DGND is connected

to the system digital ground, digital noise may get

through to the DAC’s analog portion.

Bypass the power supply with a 4.7µF capacitor in par-

allel with a 0.1µF capacitor to AGND. Minimize the

capacitor lead lengths to reduce inductance. If noise

becomes an issue, use shielding and/or ferrite beads to

increase isolation.

To maintain INL and DNL performance, as well as gain

drift, it is extremely important to provide the lowest pos-

sible reference output impedance at the DAC reference

input pin. INL degrades if the series resistance on the

REF pin exceeds 0.1Ω. The same consideration must

be made for the AGND pin.

TO OTHER

SERIAL DEVICES

MAX5171

MAX5173

DIN

SCLK

MAX5171

MAX5173

DIN

SCLK

MAX5171

MAX5173

DIN

SCLK

DIN

SCLK

CS1

CS2

CS3

Figure 9. Multiple MAX5171/MAX5173s Sharing Common DIN and SCLK Lines

TO OTHER

SERIAL DEVICES

MAX5171

MAX5173

DIN

SCLK

MAX5171

MAX5173 MAX5171

MAX5173

DINDOUT DOUT DOUT

SCLK

DIN

SCLK

Figure 8. Daisy-Chaining MAX5171/MAX5173 Devices

[MAXIM [MAXI/VI E 2N Avmxmn L $ + V lVl/lXI/Vl 7 + + [VI/JXIIVI

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

______________________________________________________________________________________ 15

Figure 10. AC Reference Input Circuit

DAC OUT

MAX5171

MAX5173

REF VDD

GND

+5V/

+3V

REFERENCE

INPUT

500mVp-p

MAX495

+5V/+3V

Figure 11. Digitally Programmable Current Source

DAC

MAX5171

MAX5173

REF

OUT

IOUT

2N3904

+5V/+3.3V

VDD

GND

SHDN

PDL

CLR

SCLKDINCS

MAX5171

MAX5173

SERIAL

CONTROL 16-BIT

SHIFT REGISTER

DECODE

CONTROL

LOGIC

OUTPUT

INPUT

DOUT

UPO

OUT

REF

DGNDAGND

VDD

Functional Diagram

Chip Information

TRANSISTOR COUNT: 3457

‘ INCHES MILLIMEYERS 7 ‘ mm MIN MAX MIN MAX A as; use «as n: [/2 Al am me me new AE D55 D51 Na ‘55 5 ans me man n31 um um um mm: 15D «57 m :99 ass as: nus as: El ' /—\ \/ < i="" uhh="" ht="" w="" c="" l="" a="" h="" w="" um="" ms="" an="" an="" n="" l="" n="" x="" v="" ms="" ass="" on="" use="" 3::="" vmuum="" size="" mmm="" n71="" \="" ”7|="" “am="" 22115="" u~="" \="" a'="" |u~="" \="" a-="" variations="" (nine:="" m="" m="" mamas="" mm="" max="" n="" 430="" 493="" \s="" a="" max="" was="" +="" 1="" j="" e="" h="" x="" 45'*‘="" ‘9="" m="" ‘23="" 272="" 312="" 4="" ndtes="" 1="" d="" l="" e="" dd="" nut="" include="" mdld="" flash="" dr="" prdtrusidns="" mean="" an="" mm="" 257="" n="" m="" s="" as="" a="" me="" 7="" as="" 090?="" as="" e="" mdld="" flash="" dr="" prdtpusidns="" neit="" td="" exceed="" 005'="" per="" :ide="" [vi="" [j="" x="" i="" [vi="" 3="" heat="" slug="" dimensiuns="" x="" and="" v="" apply="" dnly="" :wl'wwwnr-="" te!="" 16="" and="" 28="" lead="" puwep’dsdp="" packages="" ”i="" 4="" cuqulme="" mmensmng="" [nehes="" palkale="" uunw="" dsdp="" lﬁﬂ'="" 025'="" leah="" piycn="" mm="" kacwmm="" m="" 1="" 21*0055="" e="" maxim="">

MAX5171/MAX5173

Low-Power, Serial, 14-Bit DACs

with Force/Sense Voltage Output

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

QSOP.EPS

Package Information

MAX5171/73 Datasheet by Analog Devices Inc./Maxim Integrated

INFORMATION

HELP

CONTACT US

FOLLOW US