TLC372 Datasheet by Texas Instruments

r—rr—rr—rr—r r_rr_rr_rr_r GND 0 High Input Impedance . . . 1012 Q Typ 0 Extremely Low Input Bias Current 5 pA Typ o Ultrastable Low Input Oflset Voltage 0 Input Ottset Voltage Change at Worst-Case Input Conditions Typically 0.23 pV/Month, Including the First 30 Days 0 Common-Mode Input Voltage Range Includes Ground 0 Output Compatible With 1'I'L, MOS, and CMOS 0 Pin-Compatible With LM393 r—Ir—Ii—Ir—Ir—I description This device is fabricated using LinCMOSW technology and consists of two independent voltage comparators, each designed to operate Irom a single power supply. Operation from dual supplies is also possible if the difference between the two supplies is 2 V to 18 V. Each device Ieatures extremely high input impedance (typically greater than 1012 (2), allowing direct interlacing with higheimpedance sources. The outputs are nechannel openedrain configurations 1IN+ and can be connected to achieve positiveelogic GND[ 5 6 wiredeAND relationships. r—rr—rr—rr—r The TLCS72 has internal electrostatic discharge (ESD) protection circuits and has been classified symbol (939“ Comparator) with a 10007V ESD rating using human body model testing. However, care should be exercised I,“ in handling this device as exposure to ESD may result in a degradation of the device parametric perlormance. IN — The TLCS7ZC is characterized Ior operation Irom 0°C to 70°C. The TLC372| is character 740°C to 85°C. The TLC372M is characterized for operation over the full military tempe to 125°C. The TL0372Q is characterized for operation Irom 740°C to 125°C. Please be aware that an important notice concerning availability. standard warranty, and use Texas instruments semiconductor products and disclaimers thereto appears at the end or this data s pannucmu nm rr a current u are Produch mrernreape nsputhemmxol uni 9“,...“ {L‘TEXAS INSTRUMENTS POST OFFICE aox 555303 - DALLAS. TEXAS 75285 Copyrlghl teaseznoa.
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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSingle or Dual-Supply Operation
DWide Range of Supply Voltages 2 V to 18 V
DLow Supply Current Drain
150 µA Typ at 5 V
DFast Response Time . . . 200 ns Typ for
TTL-Level Input Step
DBuilt-in ESD Protection
DHigh Input Impedance ...10
12 Ω Typ
DExtremely Low Input Bias Current
5 pA Typ
DUltrastable Low Input Offset Voltage
DInput Offset Voltage Change at Worst-Case
Input Conditions Typically 0.23 µV/Month,
Including the First 30 Days
DCommon-Mode Input Voltage Range
Includes Ground
DOutput Compatible With TTL, MOS, and
CMOS
DPin-Compatible With LM393
description
This device is fabricated using LinCMOS
technology and consists of two independent
voltage comparators, each designed to operate
from a single power supply. Operation from dual
supplies is also possible if the difference between
the two supplies is 2 V to 18 V. Each device
features extremely high input impedance
(typically greater than 1012 Ω), allowing direct
interfacing with high-impedance sources. The
outputs are n-channel open-drain configurations
and can be connected to achieve positive-logic
wired-AND relationships.
The TLC372 has internal electrostatic discharge
(ESD) protection circuits and has been classified
with a 1000-V ESD rating using human body
model testing. However, care should be exercised
in handling this device as exposure to ESD may
result in a degradation of the device parametric
performance.
The TLC372C is characterized for operation from 0°C to 70°C. The TLC372I is characterized for operation from
−40°C to 85°C. The TLC372M is characterized for operation over the full military temperature range of −55°C
to 125°C. The TLC372Q is characterized for operation from −40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1983−2008, Texas Instruments Incorporated
       !" #$
#     %   & 
## '($ # ) #  "( "#
)  "" $
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VCC
2OUT
2IN−
2IN+
TLC372C, TLC372I, TLC372M, TLC372Q
D, P, OR PW PACKAGE
TLC372M . . . JG PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN−
NC
NC
1IN−
NC
1IN+
NC
TLC372M . . . FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
2IN+
NC NC
NC
GND
NC
OUT
IN+
s
ymbol (each comparator)
IN −
NC − No internal connection
VDD
1
2
3
4
5
10
9
8
7
6
NC
1OUT
1IN−
1IN+
GND
NC
VCC
2OUT
2IN−
2IN+
TLC372M
U PACKAGE
(TOP VIEW)
LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.
‘9 TEXAS INSTRUMENTS
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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent schematic (each comparator)
Common to All Channels
VDD
GND
OUT
IN + IN −
AVAILABLE OPTIONS(1)
V max
PACKAGED DEVICES
TAVIO max
AT 25°CSMALL
OUTLINE
(D)(2)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CERAMIC
FLAT PACK
(U)
0°C to 70°C5 mV TLC372CD — — TLC372CP TLC372CPW —
−40°C to 85°C5 mV TLC372ID — — TLC372IP — —
−55°C to 125°C5 mV TLC372MD TLC372MFK TLC372MJG TLC372MP — TLC372MU
−40°C to 125°C5 mV TLC372QD — — TLC372QP — —
1.For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web
site at www.ti.com.
2.The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR).
Supp‘y vmtage, VDD ‘4‘ TEXAS INSTRUMENTS
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI −0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of output short circuit to ground (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 6 and 7): D package 97.1°C/W. . . . . . . . . . . . . . . . . . . . . . . . . .
P package 84.6°C/W. . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJC (see Notes 6 and 7): FK package 5.6°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
JG package 14.5°C/W. . . . . . . . . . . . . . . . . . . . . . . . .
U package 14.7°C/W. . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC372C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC372I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC372M −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC372Q −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package 260°C. . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U package 300°C. . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 3. All voltage values except differential voltages are with respect to network ground.
4. Differential voltages are at IN+ with respect to IN −.
5. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.
6. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
7. The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).
recommended operating conditions
TLC372C TLC372I TLC372M TLC372Q
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
Supply voltage, VDD 3 16 3 16 4 16 4 16 V
Common-mode input voltage, VIC
VDD = 5 V 0 3.5 0 3.5 0 3.5 0 3.5
V
Common-mode input voltage, VIC VDD = 10 V 0 8.5 0 8.5 0 8.5 0 8.5 V
Operating free-air temperature, TA0 70 −40 85 −55 125 −40 125 °C
lemplate Helease Date: 7711794 .qu m. u 40 a! _.m 3.5:: > m 2 852:8 E 52:6 283 x x, ._0> a; 40, 10> 10> 5a; $053558 INSTRUMENTS {i} TEXAS
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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008
Template Release Date: 7−11−94
****
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC372C TLC372I TLC372M, TLC372Q
PARAMETER
TEST CONDITIONS
T
A
†
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
VIC = VICRmin,
See Note 4
25°C 1 5 1 5 1 5
mV
VIO Input offset voltage VIC = VICRmin
,
See Note 4 Full range 6.5 7 10 mV
25°C 1 1 1 pA
IIO Input offset current MAX 0.3 1 10 nA
IIB
Input bias current
25°C 5 5 5 pA
IIB Input bias current MAX 0.6 2 20 nA
Common-mode input
25°C 0 to
VDD−1 0 to
VDD−1 0 to
VDD−1
VICR
Common-mode input
voltage range Full range 0 to
VDD−1.5 0 to
VDD−1.5 0 to
VDD−1.5
V
VOH = 5 V 25°C 0.1 0.1 0.1 nA
IOH High-level output current VID = 1 V VOH = 15 V Full range 1 1 3 µA
VOL
Low-level output voltage
VID = −1 V,
IOL = 4 mA
25°C 150 400 150 400 150 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 4 mA Full range 700 700 700 mV
IOL Low-level output current VID = −1 V, VOL = 1.5 V 25°C 6 16 6 16 6 16 mA
IDD
Supply current
VID = 1 V,
No load
25°C 150 300 150 300 150 300
µA
I
DD
Supply current
(two comparators)
V
ID
= 1 V,
No load
Full range 400 400 400 µ
A
†All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC372C, −40°C to 85°C for TLC372I, and −55°C to
125°C for TLC372M and −40°C to 125°C for TLC372Q. IMPORTANT: See Parameter Measurement Information.
NOTE 8: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can
be verified by applying the limit value to the input and checking for the appropriate output state.
switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Response time
RL connected to 5 V through 5.1 k
Ω
,C
L = 15 pF
‡
,
100-mV input step with 5-mV overdrive 650
ns
Response time
RL connected to 5 V through 5.1 kΩ,C
L = 15 pF‡,
See Note 5 TTL-level input step 200
ns
‡CL includes probe and jig capacitance.
NOTE 9: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
”mm-"n TEST CONDIYIONST mm V\C:V\CR Appliiit'endflVlo Applied Vlo i v0 L‘mil (a) V|° WITH VIC = D (b) V|° ‘4‘ TEXAS INSTRUMENTS p057 OFFICE aox $553133 - DALLAS IEXAS 752%
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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TLC372Y
UNIT
PARAMETER
TEST CONDITIONS†
MIN TYP MAX
UNIT
VIO Input offset voltage VIC = VICRmin, See Note 4 1 5 mV
IIO Input offset current 1 pA
IIB Input bias current 5 pA
VICR Common-mode input voltage range 0 to
VDD−1 V
IOH High-level output current VID = 1 V, VOH = 5 V 0.1 nA
VOL Low-level output voltage VID = −1 V, IOL = 4 mA 150 400 mV
IOL Low-level output current VID = −1 V, VOL = 1.5 V 6 16 mA
IDD Supply current (two comparators) VID = 1 V, No load 150 300 µA
†All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement
Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor
between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater
accuracy.
5 V
5.1 kΩ
VO
Applied VIO
Limit VO
5.1 kΩ
1 V
−4 V
−
+
−
+
(a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V
Applied VIO
Limit
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
‘9 TEXAS INSTRUMENTS
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PARAMETER MEASUREMENT INFORMATION
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but
opposite in polarity, to the input offset voltage, the output changes states.
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
R6
5.1 kΩ
Buffer
U1b
1/4 TLC274C
R1
240 kΩ
C2
1 µF
R4
47 kΩ
U1a
1/4 TLC274CN
U1c
1/4 TLC274CN
R2
10 kΩ
R3
100 kΩ
C1
0.1 µF
R10
100 Ω, 1%
R9
10 kΩ, 1%
R7
1 MΩ
R8
1.8 kΩ, 1%
R5
1.8 kΩ, 1%
VDD
DUT
Integrator
VIO
(X100)
C3
0.68 µF
C4
0.1 µF
Triangle
Generator
−
+
−
+
−
+
Figure 2. Circuit for Input Offset Voltage Measurement
INSTRUMENTS ‘4; TEXAS
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SLCS114E − NOVEMBER 1983 − REVISED JULY 2008
7
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PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high level output, is measured from the leading
edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The
offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change
state.
Low-to-High-
Level Output
DUT
5.1 kΩ1 µF
0.1 µF
1 kΩ
50 Ω
CL
(see Note A)
VDD
Pulse
Generator
Input Offset Voltage
Compensation Adjustment 10 Ω
10 Turn
1 V
−1 V
Overdrive
Input
100 mV
Overdrive
Input
tf
tPHL
10%
50%
90%
90%
50%
tr
tPLH
High-to-Low-
Level Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
10%
100 mV
NOTE A: CL includes probe and jig capacitance.
Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms
Vss ‘9 TEXAS INSTRUMENTS
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8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
LinCMOS process
The LinCMOS process is a Linear polysilicon-gate complementary-MOS process. Primarily designed for
single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance
analog functions, from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Further questions should be directed to the nearest Texas Instruments field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational
amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision
for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.
To prevent voltage buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, Texas Instruments design engineers developed the patented ESD-protection circuit
shown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating
leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of Texas
Instruments’s ESD- protection circuit is presented on the next page.
All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
D3
R2
Q2
To Protected Circuit
V
DD
D2D1
Q1
R1
Input
V
SS
Figure 4. LinCMOS ESD-Protection Schematic
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
‘4‘ TEXAS INSTRUMENTS

   
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
input protection circuit operation
Texas Instruments’ patented protection circuitry allows for both positive-and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises
above the voltage on the VDD pin by a value equal to the VEB of Q1. The base current increases through R2
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (VT ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS
is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin
continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the
gate oxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is −0.3 V to −1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
±5 mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2
producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input
voltage is below the VT of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 7).
Vnu VDn+4 VDDm VDD. 12 Input Voltage (V) Figure 5 Figure vVI — VDD See Nole A Vref ‘9 TEXAS INSTRUMENTS 10 p057 OFFICE aox $553133 - DALLAS IEXAS 752s5

   
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
circuit-design considerations (continued)
Figure 5
VDD
0
Input Current (mA)
Input Voltage (V)
8
1
2
3
4
5
6
7
VDD + 4 VDD + 8 VDD + 12
TA = 25°C
INPUT CURRENT
vs
POSITIVE INPUT VOLTAGE
Figure 6
TA = 25°C
−0.9−0.7−0.5
Input Voltage (V)
0
−0.3
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
INPUT CURRENT
vs
NEGATIVE INPUT VOLTAGE
Input Current (mA)
−
+
Vref
TLC372
RL
VDD
RI
See Note A
VI
Positive Voltage Input Current Limit:
Negative Voltage Input Current Limit:
RI = +VI − VDD − 0.3 V
5 mA
RI = | −VI | − 0.3 V
5 mA
NOTE A: If the correct output state is required when the negative input is less than GND, a schottky clamp is required.
Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-87658012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
87658012A
TLC372MFKB
5962-8765801PA ACTIVE CDIP JG 8 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8765801PA
TLC372M
5962-9554901NXD ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 Q372M
5962-9554901NXDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 Q372M
TLC372CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 372C
TLC372CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 372C
TLC372CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 372C
TLC372CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC372CP
TLC372CPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372
TLC372CPSG4 ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372
TLC372CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372
TLC372CPSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372
TLC372CPW ACTIVE TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372
TLC372CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372
TLC372CPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P372
TLC372ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 372I
TLC372IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 372I
TLC372IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 372I
TLC372IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC372IP
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLC372MD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 372M
TLC372MDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 372M
TLC372MDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 372M
TLC372MDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 372M
TLC372MFKB ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-
87658012A
TLC372MFKB
TLC372MJG ACTIVE CDIP JG 8 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 TLC372MJG
TLC372MJGB ACTIVE CDIP JG 8 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8765801PA
TLC372M
TLC372MP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 TLC372MP
TLC372MUB ACTIVE CFP U 10 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 TLC372MUB
TLC372QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q
TLC372QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q
TLC372QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q
TLC372QDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 372Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
Addendum-Page 3
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC372, TLC372M :
•Catalog : TLC372
•Enhanced Product : TLC372-EP, TLC372-EP
•Military : TLC372M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width Bo Dimension deSigned to accommodate the component iengtn K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE a O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
5962-9554901NXDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC372CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC372CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1
TLC372CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC372IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC372MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC372MDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC372QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
5962-9554901NXDR SOIC D 8 2500 350.0 350.0 43.0
TLC372CDR SOIC D 8 2500 340.5 336.1 25.0
TLC372CPSR SO PS 8 2000 853.0 449.0 35.0
TLC372CPWR TSSOP PW 8 2000 853.0 449.0 35.0
TLC372IDR SOIC D 8 2500 340.5 336.1 25.0
TLC372MDR SOIC D 8 2500 350.0 350.0 43.0
TLC372MDRG4 SOIC D 8 2500 350.0 350.0 43.0
TLC372QDR SOIC D 8 2500 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2021
Pack Materials-Page 2
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA PS (R-PDSO-GB) PLASTIC SMALL-OUTLINE PACKAGE {XI OAS NOM m1 w 5, 0 7,40 0 I 4 H) 5,90 E if 0,05 Seufing P‘une 7 2,00 MAX 4040063/0 03/03 NOTES. A, NI \inear dimensbns are in mimme|ers B Tm's drawing 15 subjac| |o chowge wwlhou| Hofice. C Endy dimens'mns dc nut incmde mnld flush or prnhusian. rm| |u exceed 0.!5 *1? TEXAS INSTRUMENTS www.li.cnm
PC "RipfliCiGfl FL/“wT‘C SM/LL OdTLVE Exarrpre Board LcyoM Sten(eNmL)epeDn)rnge (\ute c) > \ , em? «*1 BE if *E'H'HEF ' Examp‘e Nun Sodarmask Defined Pad ‘ , 7 Exumse Pad Geomeuy (See Noie c) Exampe Nunesmer Mask Oeemrg (See Nate E] AH hnec' drmensruns c'e rn m'hrmers THs druwmq rs s to Change wrtrrou: rretrce Pubhcahon PCe/Ja rs reccwmended «or aHe'nate desrgns \aser cuflmg apemres wrm rrceemrdur ons cm arse rounqu corners wfl arier bener paste re‘euse (hammers mum cuNad U‘ev buurc ussemb‘y srte for stem: desrqn reca'nmerdm'ms. Refer «0 PC 7525 for uther stenc' rscummendchurs Customers snoum cu'vtuct t've'v board ut'mr site {or seder may lu‘evuuces betweev and «Foam srgrrc pads NO’ES Sam?
*5 TEXAS INSTRUMENTS
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA P (RiPMPi’E) "LAST‘C >4 >4 7 A V A A M Hnear dw‘ensmns are m inches (miH'nem's) B TH: druwmq is s bje“ :0 change thruut nonce C mus wmhm Juli"; Msiom vanmm BA NUTS DKMLiwi, N¥ PAL’KAC: 4 r ( “ V ‘ 7 v m 31H A H ‘ ‘ M H ‘—’ H w: H J; W“ D u‘ L , ,_ , 40mm: 04/2010 INSI'RUMENTS www.mzam
PW0008A '
www.ti.com
PACKAGE OUTLINE
C
TYP
6.6
6.2
1.2 MAX
6X 0.65
8X 0.30
0.19
2X
1.95
0.15
0.05
(0.15) TYP
0 - 8
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
3.1
2.9
B
NOTE 4
4.5
4.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
PW0008A
www.ti.com
EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.5)
8X (0.45)
6X (0.65)
(R )
TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:10X
1
45
8
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
PW0008A
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)
8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
x»
www.ti.com
PACKAGE OUTLINE
.27 MAX
GLASS
.27 MAX
GLASS
.005 MIN
TYP
5X .32 .01.241+.019
-.003
5X .32 .01
10X .017 .002
8X .050 .005
.045 MAX
TYP
.010 .002
.005 .001
.067+.013
-.012
.045
.026
CFP - 2.03 mm max heightU0010A
CERAMIC FLATPACK
4225582/A 01/2020
PIN 1 ID
56
10
1
NOTES:
1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
SCALE 1.400
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
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