THS4130CDGKR Datasheet by Texas Instruments

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−100
−90
−80
−70
−60
−50
−40
−30
−20
100 k 1 M 10 M
f Frequency Hz
THD T
otal Harmonic Distortion dB
VOUT PP
= 2 V
VCC = 5 V to 5 V±
VCC = 15 V±
VDD
DIGITAL
OUTPUT
VIN
+
+
DVDD
VOCM
AVSS
AVDD
AIN
AIN
Vref
5 V
−5 V
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THS413x High-Speed, Low-Noise, Fully-Differential I/O Amplifiers
1 Features 3 Description
The THS413x device is one in a family of fully-
1 High Performance differential input/differential output devices fabricated
150 MHz, –3 dB Bandwidth (VCC = ±15 V) using Texas Instruments' state-of-the-art BiComI
51 V/µs Slew Rate complementary bipolar process.
–100 dB Third Harmonic Distortion at The THS413x is made of a true fully-differential signal
250 kHz path from input to output. This design leads to an
excellent common-mode noise rejection and
Low Noise improved total harmonic distortion.
1.3 nV/Hz Input-Referred Noise
• Differential-Input/Differential-Output Device Information(1)
Balanced Outputs Reject Common-Mode PART NUMBER PACKAGE BODY SIZE (NOM)
Noise SOIC (8) 4.90 mm x 3.91 mm
Reduced Second-Harmonic Distortion Due to THS4130 VSSOP (8) 3.00 mm x 3.00 mm
Differential Output HVSSOP (8) 3.00 mm x 3.00 mm
Wide Power-Supply Range SOIC (8) 4.90 mm x 3.91 mm
– VCC = 5 V Single Supply to ±15 V Dual Supply THS4131 VSSOP (8) 3.00 mm x 3.00 mm
• ICC(SD) = 860 µA in Shutdown Mode (THS4130) HVSSOP (8) 3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.
Single-Ended To Differential Conversion
Differential ADC Driver
Differential Antialiasing
Differential Transmitter And Receiver
Output Level Shifter
Typical A/D Application Circuit Total Harmonic Distortion vs Frequency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
8.4 Device Functional Modes........................................ 16
1 Features.................................................................. 19 Application and Implementation ........................ 18
2 Applications ........................................................... 19.1 Application Information............................................ 18
3 Description ............................................................. 19.2 Typical Application ................................................. 20
4 Revision History..................................................... 210 Power Supply Recommendations ..................... 22
5 Device Comparison Tables................................... 311 Layout................................................................... 22
6 Pin Configuration and Functions......................... 311.1 Layout Guidelines ................................................. 22
7 Specifications......................................................... 411.2 Layout Example .................................................... 23
7.1 Absolute Maximum Ratings ...................................... 411.3 General PowerPAD Design Considerations ......... 24
7.2 ESD Ratings.............................................................. 412 Device and Documentation Support ................. 26
7.3 Recommended Operating Conditions....................... 412.1 Documentation Support ....................................... 26
7.4 Thermal Information.................................................. 512.2 Related Links ........................................................ 26
7.5 Electrical Characteristics........................................... 512.3 Community Resources.......................................... 26
7.6 Dissipation Ratings ................................................... 712.4 Trademarks........................................................... 26
7.7 Typical Characteristics.............................................. 812.5 Electrostatic Discharge Caution............................ 26
8 Detailed Description............................................ 13 12.6 Glossary................................................................ 26
8.1 Overview ................................................................. 13 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram....................................... 15 Information ........................................................... 26
8.3 Feature Description................................................. 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (May 2011) to Revision I Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Changes from Revision G (January 2010) to Revision H Page
Changed footnote A in Figure 45. ........................................................................................................................................ 25
Changes from Revision F (January 2006) to Revision G Page
Changed DGK package specifications in the Dissipation Rating table.................................................................................. 7
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1
2
3
4
8
7
6
5
V -
IN
VOCM
V +
CC
V +
OUT
V +
IN
NC
V -
CC
V -
OUT
1
2
3
4
8
7
6
5
V -
IN
VOCM
V +
CC
V +
OUT
V +
IN
PD
V -
CC
V -
OUT
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5 Device Comparison Tables
Table 1. Available Device Packages
PACKAGED DEVICES
MSOP PowerPAD™ MSOP
SMALL OUTLINE EVALUATION
TA(D) (DGN) SYMBOL (DGK) SYMBOL MODULES
THS4130CD THS4130CDGN AOB THS4130CDGK ATP THS4130EVM
0°C to +70°C THS4131CD THS4131CDGN AOD THS4131CDGK ATQ THS4131EVM
THS4130ID THS4130IDGN AOC THS4130IDGK ASO
–40°C to +85°C THS4131ID THS4131IDGN AOE THS4131IDGK ASP
Table 2. Device Description Table
DEVICE DESCRIPTION
THS412x 100 MHz, 43 V/µs, 3.7 nV/Hz
THS414x 160 MHz, 450 V/µs, 6.5 nV/Hz
THS415x 180 MHz, 850 V/µs, 9 nV/Hz
6 Pin Configuration and Functions
D, DGN, or DGK Package D, DGN, or DGK Package
8-Pin SOIC, VSSOP, or HVSSOP 8-Pin SOIC, VSSOP, or HVSSOP
THS4130 Top View THS4131 Top View
Pin Functions
PIN I/O DESCRIPTION
NAME THS4130 THS4131
NC 7 No connect
PD 7 I Active low powerdown pin
VCC+ 3 3 I/O Positive supply voltage pin
VCC– 6 6 I/O Negative supply voltage pin
VIN– 1 1 I Negative input pin
VOCM 2 2 I Common mode input pin
VOUT+ 4 4 O Positive output pin
VOUT– 5 5 O Negative output pin
VIN+ 8 8 I Positive input pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIInput voltage –VCC +VCC V
VCC– to VCC+ Supply voltage –33 33 V
IO(2) Output current 150 mA
VID Differential input voltage –6 6 V
Continuous total power dissipation See Dissipation Ratings
TJ(3) Maximum junction temperature 150 °C
TJ(4) Maximum junction temperature, continuous operation, long-term reliability 125 °C
C-suffix 0 70 °C
TAOperating free-air temperature I-suffix –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS413x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could
permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD
thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
7.2 ESD Ratings
VALUE UNIT
THS4130: D, DGN, OR DGK PACKAGES
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101(1)
THS4131: D, DGN, OR DGK PACKAGES
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Dual supply ±2.5 ±15
Vcc+ to Vcc– V
Single supply 5 30
C-suffix 0 70
TA°C
I-suffix –40 85
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7.4 Thermal Information
THS413x
D (SOIC) DGN (VSSOP) DGK
THERMAL METRIC(1) UNIT
(HVSSOP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 114.5 55.8 182.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 60.3 61.6 72.3 °C/W
RθJB Junction-to-board thermal resistance 54.8 34.5 103.5 °C/W
ψJT Junction-to-top characterization parameter 14 13.8 11.6 °C/W
ψJB Junction-to-board characterization parameter 54.3 34.4 101.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics(1)
VCC= ±5 V, RL= 800, and TA= +25°C, unless otherwise noted.
MA
PARAMETER TEST CONDITIONS MIN TYP UNIT
X
DYNAMIC PERFORMANCE
Gain = 1, Rf
VCC = 5 125
= 390
Small-signal bandwidth (–3 dB), Gain = 1, Rf
single-ended input, differential VCC = ±5 135
= 390
output, VI= 63 mVPP Gain = 1, Rf
VCC = ±15 150
= 390
BW MHz
Gain = 2, Rf
VCC = 5 80
= 750
Small-signal bandwidth (–3 dB), Gain = 2, Rf
single-ended input, differential VCC = ±5 85
= 750
output, VI= 63 mVPP Gain = 2, Rf
VCC = ±15 90
= 750
SR Slew rate(2) Gain = 1 52 V/µs
Settling time to 0.1% Step voltage = 2 V, gain = 1 78
tsns
Settling time to 0.01% Step voltage = 2 V, gain = 1 213
DISTORTION PERFORMANCE
f = 250 kHz –95
VCC = 5 f = 1 MHz –81
Total harmonic distortion, f = 250 kHz –96
differential input, differential VCC = ±5
output, gain = 1, Rf= 390 , RL=f = 1 MHz –80
800 , VO= 2 VPP f = 250 kHz –97
TH VCC = ±15 dBc
Df = 1 MHz –80
f = 250 kHz –91
VCC = ±5 f = 1 MHz –75
VO= 4 VPP f = 250 kHz –91
VCC = ±15 f = 1 MHz –75
VCC = ±2.5 97
Spurious-free dynamic range, VO= 2 VPP VCC = ±5 98
SF differential input, differential VCC = ±15 99 dB
DR output, gain = 1, Rf= 390 ,VCC = ±5 93
RL= 800 , f = 250 kHz VO= 4 VPP VCC = ±15 95
(1) The full range temperature is 0°C to +70°C for the C-suffix, and –40°C to +85°C for the I-suffix.
(2) Slew rate is measured from an output level range of 25% to 75%.
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Electrical Characteristics(1) (continued)
VCC= ±5 V, RL= 800, and TA= +25°C, unless otherwise noted.
MA
PARAMETER TEST CONDITIONS MIN TYP UNIT
X
Third intermodulation distortion VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz –53 dBc
Third-order intercept VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz 41.5 dB
NOISE PERFORMANCE
nV/
VnInput voltage noise f = 10 kHz 1.3 Hz
pA/
InInput current noise f = 10 kHz 1 Hz
DC PERFORMANCE
TA= +25°C 71 78
Open-loop gain dB
TA= full range 69
TA= +25°C 0.2 2
Input offset voltage TA= full range 3 mV
V(O Common-mode input offset TA= +25°C 0.2 3.5
S) voltage, referred to VOCM
µV/°
Input offset voltage drift TA= full range 4.5 C
IIB Input bias current TA= full range 2 6 µA
IOS Input offset current TA= full range 100 500 nA
nA/°
Offset drift 2 C
INPUT CHARACTERISTICS
CM Common-mode rejection ratio TA= full range 80 95 dB
RR
–3.7
VIC Common-mode input voltage –4 to
7 to V
Rrange 4.5
4.3
RIInput resistance Measured into each input terminal 34 M
CIInput capacitance, closed loop 4 pF
roOutput resistance Open loop 41
OUTPUT CHARACTERISTICS
1.2 0.9
TA= +25°C to to
3.8 4.1
VCC = 5 V 1.3
TA= full to ±4
range 3.7
TA= +25°C ±3.7
Output voltage swing V
VCC = ±5 V TA= full ±3.6
range
±10. ±12.
TA= +25°C 5 4
VCC = ±15 V TA= full ±10.
range 2
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Electrical Characteristics(1) (continued)
VCC= ±5 V, RL= 800, and TA= +25°C, unless otherwise noted.
MA
PARAMETER TEST CONDITIONS MIN TYP UNIT
X
TA= +25°C 25 45
VCC = 5 V, RL= 7 TA= full 20
range
TA= +25°C 30 55
IOOutput current VCC = ±5 V, RL= 7 mA
TA= full 28
range
TA= +25°C 60 85
VCC = ±15 V, RL= 7 TA= full 65
range
POWER SUPPLY
Single supply 4 33
VCSupply voltage range V
±16
CSplit supply ±2 .5
TA= +25°C 12.3 15
VCC = ±5 V TA= full
ICC Quiescent current 16 mA
range
VCC = ±15 V TA= +25°C 14
TA= +25°C 0.86 1.4
ICC( Quiescent current (shutdown) V = –5 V mA
TA= full
SD) (THS4130 only)(3) 1.5
range
TA= +25°C 73 98
PS Power-supply rejection ratio (dc) dB
TA= full
RR 70
range
(3) For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section.
7.6 Dissipation Ratings
POWER RATING(2)
PACKAGE θJA(1) (°C/W) θJC (°C/W) TA= +25°C TA= +85°C
D 97.5 38.3 1.02 W 410 mW
DGN 58.4 4.7 1.71 W 685 mW
DGK 134 72 750 mW 300 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
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−8
−3
2
CL= 10 pF
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Output − dB
Gain = 1,
RL= 800 W,
VCC =±5 V,
VI= 63 mVPP
,
Rf= 390 W
CL= 0 pF
−7
−6
−5
−4
−2
−1
−0
1
3
4
5
Output − dB
−10
−5
0
CF= 0 pF
CF= 1 pF
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
−9
−8
−7
−6
−4
−3
−2
−1
1
2
3
−8
−3
2
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Output − dB
VCC= 5
VCC=±15
Gain = 1,
RL= 800 W,
Rf= 390 W,
VI= 63 mVPP
−7
−6
−5
−4
−2
−1
0
1
−10
−5
0
5
10
15
20
25
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Gain = 5_Rf= 2 kW
Gain = 10_Rf= 4 kW
Gain = 1_Rf= 390 W
Gain = 2_Rf= 750 W
RL= 800 W,
VCC =±5 V,
VI= 63 mVPP
Output −dB
−8
−3
2Gain = 1,
RL= 800 W,
VCC =±5 V,
VI= 63 mVPP
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Output − dB
3
1
0
−1
−2
−4
−5
−6
−7
Rf= 620 W
Rf= 390 W
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7.7 Typical Characteristics
Figure 2. Small-Signal Frequency Response
Figure 1. Small-Signal Frequency Response
Figure 3. Small-Signal Frequency Response (Various Figure 4. Small-Signal Frequency Response (Various CF)
Supplies)
Figure 5. Small-Signal Frequency Response (Various CL) Figure 6. Large-Signal Transient Response (Differential
In/Single Out)
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2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
−50 −25 0 25 50 75 100
IIB+
IIB−
− Input Bias Current −
IIB Am
TA− Free-Air Temperature − °C
1.98
1.96
1.94
1.9
0 25 50 75
2
2.02
2.04
100 125 150
1.92
RF= 510 W
CF= 1 pF,
VCC = 5 V
VO= 4 VPP
RL= 800 W
− Output V
oltage − V
t Time ns
VO
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
−40 −20 0 20 40 60 80 100
VCC =±15 V
VCC =±5 V
− Supply Current − mA
ICC
TA− Free-Air Temperature − °C
800
820
840
860
880
900
920
940
−50 −25 0 25 50 75 100
− Supply Current −
TA− Free-Air Temperature (Shutdown State) − °C
ICC Am
−25
−20
−15
−10
−5
0
5
100 k 10 M 100 M 1 G1 M
VCC =±5 V
VCC =±15 V
VCC = 5 V
Gain = 1
Rf= 390 W,
RL= 800 W,
CF= 0 pF,
VI= 0.2 VRMS
Output − dB
f − Frequency − Hz
−100
−95
−90
−85
−80
−75
−70
−65
−60
−55
−50
CMRR − Common Mode Rejection Ratio − dB
100 k 1 M 10 M 100 M
f − Frequency − Hz
Rf= 1 kW,
VCC =±5 V
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Typical Characteristics (continued)
Figure 7. Large-Signal Frequency Response Figure 8. Common-Mode Rejection Ratio vs Frequency
Figure 9. Supply Current vs Free-Air Temperature Figure 10. Supply Current vs Free-Air Temperature
(Shutdown State)
Figure 12. Settling Time
Figure 11. Input Bias Current vs Free-Air Temperature
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−110
−100
−90
−80
−70
−60
−50
−40
−30
VCC =±5 V
VCC =±15 V
VO= 4 VPP,
RL= 800 W,
Rf= 390 W,
G = 1
100 k 1 M 10 M
f − Frequency − Hz
Second Harmonic Distortion − dBc
Single Ended Input
Differential Output
Second Harmonic Distortion − dBc
−106
−104
−102
−100
−98
−96
−94
−92
0 1 2 3 4 5 6 7
VCC =±5 V
VCC =±15 V
f = 250 KHz
RL= 800 W,
Rf= 390 W,
G = 1
VO− Output Voltage − V
VCC = 5 V
Single Ended Input
Differential Output
−100
−90
−80
−70
−60
−50
−40
−30
−20
100k 1M 10M
VOUT = 2 VPP
VCC = 5 V to ±5 V
VCC =±15 V
THD T
otal Harmonic Distortion dB
f − Frequency − Hz
−110
−100
−90
−80
−70
−60
−50
−40
−30
100 k 1 M 10 M
VCC = 5 V
VCC =±15V, ±5V
Second Harmonic Distortion − dBc
f − Frequency − Hz
VO= 2 VPP,
RL= 800 W,
Rf= 390 W,
G = 1
Single Ended Input
Differential Output
−2.5
−2
−1.5
−1
−5
0
5
1
1.5
2
2.5
0 40 80 120 160 200
VO+
VO
t Time nS
G = 1,
Rf= 390 W,
RL= 800 W,
CF= 0 pF,
CL= 10 pF,
VI_Peak = 2 V,
VCC =±15 V
TA= 25°C
− Output Voltage − V
VO
−100
−90
−80
−70
−60
−50
−40
10 k 100 k 1 M 10 M 100 M
VCC = 5 V
VCC = −5 V
PSRR − Power Supply Rejection Ratio − dB
f − Frequency (Differential Out) − Hz
Gain = 1,
Rf= 330 W,
RL= 400 W
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Typical Characteristics (continued)
Figure 13. Power-Supply Rejection Ratio vs Frequency Figure 14. Large-Signal Transient Response
(Differential Out)
Figure 16. Second-Harmonic Distortion vs Frequency
Figure 15. Total Harmonic Distortion vs Frequency
Figure 17. Second-Harmonic Distortion vs Frequency Figure 18. Second-Harmonic Distortion vs Output Voltage
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10 100 1 k 10 k 100 k
f − Frequency − Hz
10
nV/ Hz
− Voltage Noise −
Vn
1
Third Harmonic Distortion dBc
−106
−104
−102
−100
−98
−96
−94
−92
−90
−88
0 1 2 3 4 5 6 7
VCC = 5 V
VCC =±5 V
f = 250 KHz
RL= 800 W,
Rf= 390 W,
G = 1
VO− Output Voltage − V
VCC =±15 V
Single Ended Input
Differential Output
−110
−100
−90
−80
−70
−60
−50
−40
−30
100 k 1 M 10 M
VCC =±5 V
VCC =±15 V
VCC = 5 V
VO= 2 VPP
,
RL= 800 W,
Rf= 390 W,
Gain = 1
Third Harmonic Distortion dBc
f − Frequency − Hz
Single Ended Input
Differential Output
−106
−104
−102
−100
−98
−96
−94
−92
−90
−88
0 1 2 3 4 5 6 7
VCC =±5 V
VCC = 5 V
f = 500 KHz
RL= 800 W,
Rf= 390 W,
G = 1
Third Harmonic Distortion dBc
VO− Output Voltage − V
VCC =±15 V
Single Ended Input
Differential Output
Second Harmonic Distortion − dBc
−106
−104
−102
−100
−98
−96
−94
−92
−90
−88
0 1 2 3 4 5 6 7
VCC =±15 V
VCC =±5 V
VCC = 5 V
f = 500 KHz
RL= 800 W,
Rf= 390 W,
G = 1
VO− Output Voltage − V
Single Ended Input
Differential Output
−110
−100
−90
−80
−70
−60
−50
−40
−30
100 k 1 M 10 M
VCC =±5 V
VO= 4 VPP
RL= 800 W,
Rf= 390 W,
G = 1
f − Frequency − Hz
VCC =±15 V
Third Harmonic Distortion dBc
Single Ended Input
Differential Output
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Typical Characteristics (continued)
Figure 19. Second-Harmonic Distortion vs Output Voltage Figure 20. Third-Harmonic Distortion vs Frequency
Figure 21. Third-Harmonic Distortion vs Frequency Figure 22. Third-Harmonic Distortion vs Output Voltage
Figure 23. Third-Harmonic Distortion vs Output Voltage Figure 24. Voltage Noise vs Frequency
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l TEXAS INSTRUMENTS VaCM 1w
−15
−10
−5
0
5
10
15
100 1000 10 k 100 k
− Output V
oltage − V
VO
RL− Differential Load Resistance −W
Rf= 1 k
G = 2 VCC =±15 V
VCC =±5 V
VCC =±5 V
VCC =±15 V
VOUT+
VOUT+
VOUT
VOUT
0.1
1
10
100
100 k 1 M 10 M 100 M 1 G
− Output impedance −
f − Frequency − Hz
W
VCC =± 5 V
zo
−600
−400
−200
0
200
400
600
800
1000
−12 −9 −6 −3 0 3 6 9 12
− Input Offset V
oltage −
VCC =±2.5 V
VCC =±5 V
VCC =±15 V
V(OS) Vm
VOCM − Common-Mode Output Voltage − V
Rf= 1 k,
RL= 800 W,
G = 1
0
1E−12
2E−12
3E−12
4E−12
5E−12
6E−12
7E−12
1 10 100 1 k 10 k 100 k
f − Frequency − Hz
In− Current Noise − pA/ Hz
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Typical Characteristics (continued)
Figure 25. Current Noise vs Frequency Figure 26. Input Offset Voltage vs Common-Mode Output
Voltage
Figure 27. Output Voltage vs Differential Load Resistance Figure 28. Output Impedance vs Frequency
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l TEXAS INSTRUMENTS 7 . 7 VD, . ( M > 2 O ( ) < )="" 2="" transfer="" function="" vo="" vi="" a)="" 0="" so:="" 0an="" rejectsi="" 7="" oulput="" n7="" ’="" vo="" +="" c="" vac,="" v="" 1="" o="" 2="" x="" v="" 1="" o="" 2="" \="">
O I
1
V V
2
= -
O I
1
V V
2
=
VOCM
_
+_
+
VCC+
VIN
VIN+
VO+
VO−
Differential Structure Rejects
Coupled Noise at The Output
Differential Structure Rejects
Coupled Noise at The Input
Differential Structure Rejects
Coupled Noise at The Power Supply
VCC
OC OCM
Output common mode voltage V V=
( )
OD ID f
Transfer function V V A= ´
( ) ( ) ( ) ( )
O O
OD O O OC
V V
Output voltage definition V V V V 2
+ -
+ -
+
= - =
( ) ( ) ( ) ( )
I I
ID I I IC
V V
Input voltage definition V V V V 2
+ -
+ -
+
= - =
Rf
R(g)
R(g)
Rf
_
+
Differential Amplifier
VOCM
_
+_
+
VCC+
VIN−
VIN+
VO+
VO
THS413x
Fully differential Amplifier
VCC
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8 Detailed Description
8.1 Overview
The THS413x is a fully-differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully-differential amplifiers are differential in/differential out.
Figure 29. Differential Amplifier Versus a Fully-Differential Amplifier
To understand the THS413x fully-differential amplifiers, the definition for the pin outs of the amplifier are
provided.
(1)
(2)
(3)
(4)
Figure 30. Definition of the Fully-Differential Amplifier
If each output is measured independently, each output is one-half of the input signal when gain is 1. The
following equations express the transfer function for each output:
(5)
The second output is equal and opposite in sign:
(6)
Fully-differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully-differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it is not as practical to feed a 2-VPP signal into the
targeted ADC. Using a fully-differential amplifier enables the user to break down the output into two 1-VPP signals
with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been
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l TEXAS INSTRUMENTS
_
+
_
+
_
+
THS4012
THS4012
VIN1
VIN2
R2
R1
R2
R(g)
R(g)
Rf
Rf
THS413x
( )
OD f
IN1 IN2 g
VR2R2
1
V V R R1
æ ö
= +
ç ÷
-è ø
VOCM
_
+_
+
VCC+
VIN−
VIN+
VO+
VO−
VOD= 1−0 = 1
VOD = 0−1 = 1
a
b
+1
0
+1
0
VCC
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Overview (continued)
able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully-differential amplifier. The
final result indicates twice as much dynamic range. Figure 31 illustrates the increase in dynamic range. The gain
factor should be considered in this scenario. The THS413x fully-differential amplifier offers an improved CMRR
and PSRR due to its symmetrical input and output. Furthermore, second-harmonic distortion is improved. Second
harmonics tend to cancel because of the symmetrical output.
Figure 31. Fully-Differential Amplifier With Two 1-VPP Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully-differential amplifier is selected
by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to implement the
differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the fully-
differential amplifier. Figure 32 depicts the general format of instrumentation amplifiers.
The general transfer function for this circuit is:
(7)
Figure 32. Instrumentation Amplifier
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l TEXAS INSTRUMENTS 34: J :L un % >J VocM m? N setting RI R9 R! Rm R19) We! ”‘19?
Rf
R(g)
+
+
VCC
VCC+
R(g)
Rf
Vs
VIN−
VIN+
VO+
VO−
VOCM
Note: For proper operation, maintain symmetry by setting
Rf1 = Rf2 = Rfand R(g)1 = R(g)2 = R(g) A = Rf/R(g)
_
+
x1
Output Buffer
Vcm Error
Amplifier
C R
CR
x1
Output Buffer
VOUT+
VOUT
VCC+
VCC
VIN−
VIN+
30 kW
30 kW
VCC+
VCC
VOCM
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8.2 Functional Block Diagram
8.3 Feature Description
Figure 33 and Figure 34 depict the differences between the operation of the THS413x fully-differential amplifier in
two different modes. Fully-differential amplifiers can work with differential input or can be implemented as single
in/differential out.
Figure 33. Amplifying Differential Signals
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l TEXAS INSTRUMENTS Vac,
VCC
PD
VCC
To Internal Bias
Circuitry Control
50 kW
Rf
R(g)
+
+
VCC
VCC+
R(g)
Rf
Vs
VIN−
VIN+
VO+
VO−
VOCM
GAIN R(g) WRfW
1
2
5
10
390
374
402
402
390
750
2010
4020
RECOMMENDED RESISTOR VALUES
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Feature Description (continued)
Figure 34. Single In With Differential Out
8.4 Device Functional Modes
8.4.1 Power-Down Mode
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS413x is an active low terminal. If it is left as a no-connect terminal, the device always stays on due to an
internal 50 kresistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC–. This
means that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V
above VCC–, the device is off. For example, if VCC– = –5 V, then the device is on when PD reaches –3.6 V, (–5 V
+ 1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal
to VCC– in order to turn the device off. Figure 35 shows the simplified version of the power-down circuit. While in
the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typically
greater than 1 Min the power-down state.
Figure 35. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very
low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed loop output impedance is shown in Figure 36.
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l TEXAS INSTRUMENTS 2200
200
1200
2200
100 k 1 M 10 M 100 M 1 G
Output Impedance −
f − Frequency − Hz
W
VCC =±5 V
G = 1
Rf= 1 kW
PD = VCC
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Device Functional Modes (continued)
Figure 36. Output Impedance (in Power-Down) vs Frequency
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l TEXAS INSTRUMENTS )( 390
THS413x
Output
Output
20 W
20 W
390 W
390 W
390 W
390 W
( ) ( )
CC CC
V V
2
+ -
+
THS4130
,
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Resistor Matching
Resistor matching is important in fully-differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistor. CMRR, PSRR, and cancellation of the second-harmonic distortion
diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCMpin, it is set to the midrail voltage
internally defined as:
(8)
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation
range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM
pin as a bypass capacitor. The Functional Block Diagram shows the simplified diagram of the THS413x.
9.1.2 Driving a Capacitive Load
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS413x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 37. A minimum value of 20 should work well for most applications. For
example, in 50-transmission systems, setting the series resistor value to 50 both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
Figure 37. Driving a Capacitive Load
9.1.3 Data Converters
Data converters are one of the most popular applications for the fully-differential amplifiers. Figure 38 shows a
typical configuration of a fully-differential amplifier attached to a differential analog-to-digital converter (ADC).
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VIN
+
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 mF
RPU
RPU
THS1206
VCC Rf
Rg
VCC Rf
Rg
VP
VOUT
VOUT
VIN
+
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 mF
VIN
+
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 mF
−5 V
VCC
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Application Information (continued)
Figure 38. Fully-Differential Amplifier Attached to a Differential ADC
Fully-differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit.
If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the
amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input
terminal of the amplifier should not exceed the common-mode input voltage range.
Figure 39. Fully-Differential Amplifier Using a Single Supply
9.1.4 Single-Supply Applications
Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the circuit configuration of Figure 40 is suggested to bring the common-mode input voltage within
the specifications of the amplifier.
Figure 40. Circuit With Improved Common-Mode Input Voltage
Equation 9 is used to calculate RPU:
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VIN
VIN++
+
VOCM
VOCM
VIN
VIN+
VCC
THS1050
THS413x
C3
C3
R4
R(t)
R2
R4
+
C1
+
VCC
C1
R2
R3
R3
C2
R1
R1
Vs
VIC
( ) ( )
P CC
PU
IN P OUT P
V V
R1 1
V V V V
RG RF
-
=
- + -
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Application Information (continued)
(9)
9.2 Typical Application
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 41 presents a
method by which the noise may be filtered in the THS413x.
Figure 41 shows a typical application design example for the THS413x device in active low-pass filter topology
driving and ADC.
Figure 41. Antialias Filtering
9.2.1 Design Requirements
Table 3 shows example design parameters and values for the typical application design example in Figure 41.
Table 3. Design Parameters
DESIGN PARAMETERS VALUE
Supply voltage ±2.5 V to ±15 V
Amplifier topology Voltage feedback
DC coupled with output common
Output control mode control capability
500 kHz, Multiple feedback low pass
Filter requirement filter
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l TEXAS INSTRUMENTS ”d [t J J F V J7 R301
−25
−20
−15
−10
−5
0
5
100 k 10 M 100 M 1 G1 M
VCC =±5 V
VCC =±15 V
VCC = 5 V
Gain = 1
Rf= 390 W,
RL= 800 W,
CF= 0 pF,
VI= 0.2 VRMS
Output − dB
f − Frequency − Hz
( )
1 2 mn
FSF fc and Q
1 m 1 K
2 RC 2 mn
´
´ = = + +
p ´
2
2
2
2Re Im
FSF Re Im and Q
2Re
+
= + =
2 R2R3C1C2
1
FSF fc and Q
R3C1 R2C1 KR3C1
2 2 R2R3C1C2
´
´ = =
+ +
p ´
( )
d2
Rt
K R2
2R4 Rt
H f Where K
j2 fR4RtC3 R1
f 1 jf 1
12R4 Rt
FSF fc Q FSF fc
æ ö æ ö
ç ÷ ç ÷
ç ÷ +
= ´ =
ç ÷
ç ÷ p
ç ÷
æ ö +
ç ÷ ç ÷
- + +
ç ÷
ç ÷ +
è ø
´ ´
è ø
è ø
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9.2.2 Detailed Design Procedure
9.2.2.1 Active Antialias Filtering
Figure 41 shows a multiple-feedback (MFB) lowpass filter. The transfer function for this filter circuit is:
(10)
(11)
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the
quality factor.
(12)
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =
C, and C2 = nC results in:
(13)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
9.2.3 Application Curve
Figure 42. Large-Signal Frequency Response
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10 Power Supply Recommendations
The THS413x device was designed to be operated on power supplies ranging from 2.5V to 15V. Single power
supplies ranging from 5V to 30V can also be used. TI recommends using power-supply accuracy of 5%, or
better. When operated on a board with high-speed digital signals, it is important to provide isolation between
digital signal noise and the analog input pins. The THS413x is connected to power supplies through pin 3 (VCC+)
and pin 6 (VCC-). Each supply pin should be decoupled to GND as close to the device as possible with a low-
inductance, surface-mount ceramic capacitor of approximately 10 nF. When vias are used to connect the bypass
capacitors to a ground plane the vias should be configured for minimal parasitic inductance. One method of
reducing via inductance is to use multiple vias. For broadband systems, two capacitors per supply pin are
advised.
To avoid undesirable signal transients, the THS413x device should not be powered on with large inputs signals
present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs
when an ADC is used in the application.
11 Layout
11.1 Layout Guidelines
To achieve the levels of high-frequency performance of the THS413x device, follow proper printed-circuit board
(PCB) high-frequency design techniques. A general set of guidelines is given below. In addition, a THS413x
device evaluation board is available to use as a guide for layout or for evaluating the device performance.
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
Proper power-supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often lead to stability problems. Surface-mount packages soldered directly to
the printed-circuit board are the best implementation.
Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance
at the input of the amplifier.
Surface-mount passive components—Using surface-mount passive components is recommended for high-
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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l TEXAS INSTRUMENTS V INSERT Ju1 FOI J E; pouEn noun u c— 2' OPEN JUl run | J! L2 JUl “ UIN+ H m L pouzp up (:8 TDI J9 “213 6ND J3 . F11 R3- ) m nxs >< mo="" a:="" x="" a="" -="" .="" 0="" it="" -="" t="" )nnen="" i;="" c!="" nx="" j4="" um="" uin-="" j6="" to="" set="" udch="" direct="" inpu'="">
THS413x
RF
RG
Symmetrical
Input Paths
Symmetrical
Output Paths
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11.2 Layout Example
Figure 43. THS413x EVM Top Layer
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Separate Vcc+ and
Vcc- planes
Vcc+ Vcc-
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Layout Example (continued)
Figure 44. THS413x EVM Layer 3
11.3 General PowerPAD Design Considerations
The THS413x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted (see Figure 45aand Figure 45b). This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package (see Figure 45c). Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the previously awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, (PowerPAD Thermally-Enhanced Package,SLMA002). This document
can be found on the TI website (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to SLMA002 when ordering.
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l TEXAS INSTRUMENTS
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
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General PowerPAD Design Considerations (continued)
A. The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from
VCC– to VCC+. Typically, the thermal pad is connected to the ground plane because this plane tends to physically be
the largest and is able to dissipate the most amount of heat.
Figure 45. Views of Thermally-Enhanced DGN Package
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
EVM User's Guide for High-Speed Fully-Differential Amplifier,SLOU101
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
THS4130 Click here Click here Click here Click here Click here
THS4131 Click here Click here Click here Click here Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26 Submit Documentation Feedback Copyright © 2000–2015, Texas Instruments Incorporated
Product Folder Links: THS4130 THS4131
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
THS4130CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4130C
THS4130CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4130C
THS4130CDGK ACTIVE VSSOP DGK 8 80 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 ATP
THS4130CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AOB
THS4130CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AOB
THS4130CDGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AOB
THS4130ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4130I
THS4130IDGK ACTIVE VSSOP DGK 8 80 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 85 ASO
THS4130IDGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ASO
THS4130IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 85 ASO
THS4130IDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AOC
THS4130IDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AOC
THS4130IDGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AOC
THS4130IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4130I
THS4130IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4130I
THS4131CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4131C
THS4131CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4131C
THS4131CDGK ACTIVE VSSOP DGK 8 80 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 ATQ
THS4131CDGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 ATQ
THS4131CDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM 0 to 70 ATQ
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
THS4131CDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AOD
THS4131CDGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AOD
THS4131CDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 AOD
THS4131CDGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AOD
THS4131CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 4131C
THS4131ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4131I
THS4131IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4131I
THS4131IDGK ACTIVE VSSOP DGK 8 80 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 85 ASP
THS4131IDGKG4 ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ASP
THS4131IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ASP
THS4131IDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AOE
THS4131IDGNG4 ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AOE
THS4131IDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 AOE
THS4131IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 4131I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 3
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I‘KO '«Pt» Reel DlameIer A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component Iength K0 Dimension designed to accommodate the component thickness 7 w Overau Wiotn onhe carrier Iape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE QOODOOOO ,,,,,,,,,,, ‘ User DIreCIIOn 0' Feed SprockeI Hoies Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4130CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4130IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4130IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4130IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4131CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4131IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4130CDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
THS4130IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4130IDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
THS4130IDR SOIC D 8 2500 350.0 350.0 43.0
THS4131CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4131CDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
THS4131CDR SOIC D 8 2500 350.0 350.0 43.0
THS4131IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4131IDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
THS4131IDR SOIC D 8 2500 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
Pack Materials-Page 2
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
PowerPAD VSSOP - 1.1 mm max heightDGN 8
SMALL OUTLINE PACKAGE
3 x 3, 0.65 mm pitch
4225482/A
www.ti.com
PACKAGE OUTLINE
C
6X 0.65
2X
1.95
8X 0.38
0.25
5.05
4.75 TYP
SEATING
PLANE
0.15
0.05
0.25
GAGE PLANE
0 -8
1.1 MAX
0.23
0.13
1.57
1.28
1.89
1.63
B3.1
2.9
NOTE 4
A
3.1
2.9
NOTE 3
0.7
0.4
PowerPAD VSSOP - 1.1 mm max heightDGN0008D
SMALL OUTLINE PACKAGE
4225481/A 11/2019
1
4
5
8
0.13 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
PowerPAD is a trademark of Texas Instruments.
TM
A 20
DETAIL A
TYPICAL
SCALE 4.000
EXPOSED THERMAL PAD
1
45
8
9
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(2)
NOTE 9
(3)
NOTE 9
(1.22)
(0.55)
( 0.2) TYP
VIA
(1.57)
(1.89)
PowerPAD VSSOP - 1.1 mm max heightDGN0008D
SMALL OUTLINE PACKAGE
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SYMM
SYMM
1
4
5
8
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
SEE DETAILS
9
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(1.57)
BASED ON
0.125 THICK
STENCIL
(1.89)
BASED ON
0.125 THICK
STENCIL
PowerPAD VSSOP - 1.1 mm max heightDGN0008D
SMALL OUTLINE PACKAGE
4225481/A 11/2019
1.33 X 1.600.175
1.43 X 1.730.15
1.57 X 1.89 (SHOWN)0.125
1.76 X 2.110.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
SYMM
SYMM
1
45
8
METAL COVERED
BY SOLDER MASK SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
www.ti.com
PACKAGE OUTLINE
C
6X 0.65
2X
1.95
8X 0.38
0.25
5.05
4.75 TYP
SEATING
PLANE
0.15
0.05
0.25
GAGE PLANE
0 -8
1.1 MAX
0.23
0.13
1.846
1.646
2.15
1.95
B3.1
2.9
NOTE 4
A
3.1
2.9
NOTE 3
0.7
0.4
PowerPAD VSSOP - 1.1 mm max heightDGN0008G
SMALL OUTLINE PACKAGE
4225480/A 11/2019
1
4
5
8
0.13 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
PowerPAD is a trademark of Texas Instruments.
TM
A 20
DETAIL A
TYPICAL
SCALE 4.000
EXPOSED THERMAL PAD
1
45
8
9
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(2)
NOTE 9
(3)
NOTE 9
(1.22)
(0.55)
( 0.2) TYP
VIA
(1.846)
(2.15)
PowerPAD VSSOP - 1.1 mm max heightDGN0008G
SMALL OUTLINE PACKAGE
4225480/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SYMM
SYMM
1
4
5
8
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
SEE DETAILS
9
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(1.846)
BASED ON
0.125 THICK
STENCIL
(2.15)
BASED ON
0.125 THICK
STENCIL
PowerPAD VSSOP - 1.1 mm max heightDGN0008G
SMALL OUTLINE PACKAGE
4225480/A 11/2019
1.56 X 1.820.175
1.69 X 1.960.15
1.846 X 2.15 (SHOWN)0.125
2.06 X 2.400.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
SYMM
SYMM
1
45
8
METAL COVERED
BY SOLDER MASK SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2020, Texas Instruments Incorporated

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