SN74LVC2G53 Datasheet by Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2G53
SCES324Q –JULY 2001–REVISED JANUARY 2019
SN74LVC2G53 Single-Pole Double-Throw (SPDT) Analog Switch
2:1 Analog Multiplexer/Demultiplexer
1
1 Features
1• Available in the Texas Instruments
NanoFree™ Package
• 1.65-V to 5.5-V VCC Operation
• High On-Off Output Voltage Ratio
• High Degree of Linearity
• High Speed, Typically 0.5 ns (VCC = 3 V,
CL= 50 pF)
• Low ON-State Resistance, Typically 6.5 Ω
(VCC = 4.5 V)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2 Applications
• Wireless Devices
• Audio and Video Signal Routing
• Portable Computing
• Wearable Devices
• Signal Gating, Chopping, Modulation or
Demodulation (Modem)
• Signal Multiplexing for Analog-to-Digital and
Digital-to-Analog Conversion Systems
3 Description
This single 2:1 analog multiplexer/demultiplexer is
designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G53 device can handle both analog
and digital signals. This device permits signals with
amplitudes of up to 5.5 V (peak) to be transmitted in
either direction.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-analog
conversion systems.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC2G53DCT SM8 (8) 2.95 mm × 2.80 mm
SN74LVC2G53DCU VSSOP (8) 2.30 mm × 2.00 mm
SN74LVC2G53YZP DSBGA (8) 1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram
NOTE: For simplicity, the test conditions shown in
Figure 1 through Figure 4 and Figure 6
through Figure 10 are for the demultiplexer
configuration. Signals can be passed from
COM to Y1 (Y2) or from Y1 (Y2) to COM.
Logic Diagram, Each Switch (SW)
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics ......................................... 6
6.7 Analog Switch Characteristics .................................. 6
6.8 Operating Characteristics.......................................... 7
6.9 Typical Characteristics.............................................. 8
7 Parameter Measurement Information .................. 9
8 Detailed Description............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 15
9 Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1 Documentation Support ........................................ 19
12.2 Receiving Notification of Documentation Updates 19
12.3 Community Resources.......................................... 19
12.4 Trademarks........................................................... 19
12.5 Electrostatic Discharge Caution............................ 19
12.6 Glossary................................................................ 19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (October 2016) to Revision Q Page
• Changed the Thermal Information table................................................................................................................................. 5
Changes from Revision O (December 2015) to Revision P Page
• Added DSBGA package in Pin Functions table ..................................................................................................................... 3
• Added Receiving Notification of Documentation Updates section ...................................................................................... 19
Changes from Revision N (January 2014) to Revision O Page
• Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Feature
Description section, Device Functional Modes,Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. .................................................................................................................... 1
• Moved Tstg to Absolute Maximum Ratings table..................................................................................................................... 4
‘5‘ TEXAS INSTRUMENTS 2\ /fl 1 ,\ , : : , //\/k/k;<\ \jnjnjnj="" \fk/k/k="">
1 2
D
C
B
A
Not to scale
GND A
GND Y2
INH Y1
COM VCC
1COM 8 VCC
2INH 7 Y1
3GND 6 Y2
4GND 5 A
Not to scale
1COM 8 VCC
2INH 7 Y1
3GND 6 Y2
4GND 5 A
Not to scale
3
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5 Pin Configuration and Functions
DCT Package
8-Pin SM8
Top View
DCU Package
8-Pin VSSOP
Top View
YZP Package
8-Pin DSBGA
Bottom View
See Mechanical, Packaging, and Orderable Information for dimensions.
Pin Functions
PIN I/O DESCRIPTION
NAME SM8, VSSOP DSBGA
A 5 D2 I Controls the switch
COM 1 A1 I/O Bidirectional signal to be switched
GND 3 C1 — Ground pin
GND 4 D1 — Ground pin
INH 2 B1 I Enables or disables the switch
VCC 8 A2 — Power pin
Y2 6 C2 I/O Bidirectional signal to be switched
Y1 7 B2 I/O Bidirectional signal to be switched
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(2) –0.5 6.5 V
VIInput voltage(2)(3) –0.5 6.5 V
VI/O Switch I/O voltage(2)(3)(4) –0.5 VCC + 0.5 V
IIK Control input clamp current VI< 0 –50 mA
II/OK I/O port diode current VI/O < 0 or VI/O > VCC ±50 mA
ITON-state switch current VI/O = 0 to VCC ±50 mA
Continuous current through VCC or GND ±100 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
6.3 Recommended Operating Conditions
See note(1).
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VI/O I/O port voltage 0 VCC V
VIH High-level input voltage, control input
VCC = 1.65 V to 1.95 V VCC × 0.65
V
VCC = 2.3 V to 2.7 V VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7
VIL Low-level input voltage, control input
VCC = 1.65 V to 1.95 V VCC × 0.35
V
VCC = 2.3 V to 2.7 V VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3
VIControl input voltage 0 5.5 V
Δt/Δv Input transition rise and fall time
VCC = 1.65 V to 1.95 V 20
ns/V
VCC = 2.3 V to 2.7 V 20
VCC = 3 V to 3.6 V 10
VCC = 4.5 V to 5.5 V 10
TAOperating free-air temperature –40 85 °C
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
6.4 Thermal Information
THERMAL METRIC(1)
SN74LVC2G53
UNITDCT (SM8) DCU (VSSOP) YZP (DSBGA)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(2) 185.9 288.9 98.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 116.3 99.6 1.1 °C/W
RθJB Junction-to-board thermal resistance 98.4 207.3 27.6 °C/W
ψJT Junction-to-top characterization parameter 41.6 22.4 0.6 °C/W
ψJB Junction-to-board characterization parameter 97.3 205.7 27.4 °C/W
(1) TA= 25°C
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
ron ON-state switch resistance
VI= VCC or GND,
VINH = VIL
(see Figure 2
and Figure 1)
IS= 4 mA 1.65 V 13 30
Ω
IS= 8 mA 2.3 V 10 20
IS= 24 mA 3 V 8.5 17
IS= 32 mA 4.5 V 6.5 13
ron(p) Peak ON-state resistance
VI= VCC to GND,
VINH = VIL
(see Figure 2
and Figure 1)
IS= 4 mA 1.65 V 86.5 120
Ω
IS= 8 mA 2.3 V 23 30
IS= 24 mA 3 V 13 20
IS= 32 mA 4.5 V 8 15
Δron Difference of ON-state resistance
between switches
VI= VCC to GND,
VC= VIH
(see Figure 2
and Figure 1)
IS= 4 mA 1.65 V 7
Ω
IS= 8 mA 2.3 V 5
IS= 24 mA 3 V 3
IS= 32 mA 4.5 V 2
IS(off) OFF-state switch leakage current VI= VCC and VO= GND or
VI= GND and VO= VCC,
VINH = VIH (see Figure 3)5.5 V ±1
μA
±0.1(1)
IS(on) ON-state switch leakage current VI= VCC or GND, VINH = VIL,
VO= Open (see Figure 4)5.5 V ±1 μA
±0.1(1)
IIControl input current VC= VCC or GND 5.5 V ±1 μA
±0.1(1)
ICC Supply current VC= VCC or GND 5.5 V 1 μA
ΔICC Supply-current change VC= VCC – 0.6 V 5.5 V 500 μA
Cic Control input capacitance 5 V 3.5 pF
Cio(off) Switch input/output
capacitance
Y5 V 6.5 pF
COM 10
Cio(on) Switch input/output capacitance 5 V 19.5 pF
l TEXAS INSTRUMENTS
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(1) tPLH and tPHL are the same as tpd. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
(2) tPZL and tPZH are the same as ten.
(3) tPLZ and tPHZ are the same as tdis.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC MIN MAX UNIT
tpd(1) COM or Y Y or COM
VCC = 1.8 V ± 0.15 V 2
ns
VCC = 2.5 V ± 0.2 V 1.2
VCC = 3.3 V ± 0.3 V 0.8
VCC = 5 V ± 0.5 V 0.6
ten(2) INH COM or Y
VCC = 1.8 V ± 0.15 V 3.3 9
ns
VCC = 2.5 V ± 0.2 V 2.5 6.1
VCC = 3.3 V ± 0.3 V 2.2 5.4
VCC = 5 V ± 0.5 V 1.8 4.5
tdis(3) INH COM or Y
VCC = 1.8 V ± 0.15 V 3.2 10.9
ns
VCC = 2.5 V ± 0.2 V 2.3 8.3
VCC = 3.3 V ± 0.3 V 2.3 8.1
VCC = 5 V ± 0.5 V 1.6 8
ten(2) A COM or Y
VCC = 1.8 V ± 0.15 V 2.9 10.3
ns
VCC = 2.5 V ± 0.2 V 2.1 7.2
VCC = 3.3 V ± 0.3 V 1.9 5.8
VCC = 5 V ± 0.5 V 1.3 5.4
tdis(3) A COM or Y
VCC = 1.8 V ± 0.15 V 2.1 2.1
ns
VCC = 2.5 V ± 0.2 V 1.4 7.9
VCC = 3.3 V ± 0.3 V 1.1 7.2
VCC = 5 V ± 0.5 V 1 5
(1) Adjust fin voltage to obtain 0 dBm at input.
6.7 Analog Switch Characteristics
TA= 25°C
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS VCC TYP UNIT
Frequency response
(switch on) COM or Y Y or COM
CL= 50 pF, RL= 600 Ω,
fin = sine wave
(see Figure 6)
1.65 V 35
MHz
2.3 V 120
3 V 190
4.5 V 215
CL= 5 pF, RL= 50 Ω,
fin = sine wave
(see Figure 6)
1.65 V >300
2.3 V >300
3 V >300
4.5 V >300
Crosstalk(1)
(between switches) COM or Y Y or COM
CL= 50 pF, RL= 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
1.65 V –58
dB
2.3 V –58
3 V –58
4.5 V –58
CL= 5 pF, RL= 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
1.65 V –42
2.3 V –42
3 V –42
4.5 V –42
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Analog Switch Characteristics (continued)
TA= 25°C
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS VCC TYP UNIT
Crosstalk
(control input to signal output) INH COM or Y CL= 50 pF, RL= 600 Ω,
fin = 1 MHz (square wave)
(see Figure 8)
1.65 V 35
mV
2.3 V 50
3 V 70
4.5 V 100
Feedthrough attenuation
(switch off) COM or Y Y or COM
CL= 50 pF, RL= 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
1.65 V –60
dB
2.3 V –60
3 V –60
4.5 V –60
CL= 5 pF, RL= 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
1.65 V –50
2.3 V –50
3 V –50
4.5 V –50
Sine-wave distortion COM or Y Y or COM
CL= 50 pF, RL= 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 10)
1.65 V 0.1%
2.3 V 0.025%
3 V 0.015%
4.5 V 0.01%
CL= 50 pF, RL= 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 10)
1.65 V 0.15%
2.3 V 0.025%
3 V 0.015%
4.5 V 0.01%
6.8 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd Power dissipation capacitance CL= 50 pF, f = 10 MHz
VCC = 1.8 V 9
pF
VCC = 2.5 V 10
VCC = 3.3 V 10
VCC = 5 V 12
l TEXAS INSTRUMENTS -n \
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6.9 Typical Characteristics
Figure 1. Typical ron as a Function of Input Voltage (VI) for VI=0toVCC
l TEXAS INSTRUMENTS if 740 740 V or GND 7 fv‘ U VINO if 740 \07 40 v 407 com v2 2 (om em) M7 Condilion 2: VI : Vcc. V0
VCC
VI
VO
GND
Y1
(Off)
VCC
VIH
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
A
Condition 1: VI = GND, VO = VCC
Condition 2: VI = VCC, VO = GND
VCC
VI = VCC or GND
VO
ron +VI*VO
IS
W
VI - VO
GND
V
Y1
IS
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
9
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7 Parameter Measurement Information
Figure 2. ON-State Resistance Test Circuit
Figure 3. OFF-State Switch Leakage-Current Test Circuit
l TEXAS INSTRUMENTS COM (0") v2 = Open ”7: GND M7
VCC
VI
VO
GND
Y1
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
A
VI = VCC or GND
VO = Open
10
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Parameter Measurement Information (continued)
Figure 4. ON-State Switch Leakage-Current Test Circuit
l TEXAS INSTRUMENTS “x N }—o fl H \ \ ‘77 m H “—5
VM
th
tsu
FromOutput
UnderTest
CL
(seeNote A)
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
RL
DataInput
TimingInput
VI
0V
VI
0V
0V
tw
Input
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
VOLTAGEWAVEFORMS
PULSEDURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
tPZL
TPZH
tPLZ
tPHZ
V /2
LOAD
0V
V +V
OL D
V -V
OH D
»0V
VI
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
Output
Output
t /t
PLH PHL
t /t
PLZ PZL
t /t
PHZ PZH
Open
VLOAD
GND
TEST S1
NOTES: A.C includesprobeandjigcapacitance.
L
B.Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10Mhz,Z =50£ W
O
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E.t andt arethesameast .
PLZ PHZ dis
F.t andt arethesameast .
PZL PZH en
G.t andt arethesameast .
PLH PHL pd
H. Allparametersandwaveformsarenotapplicabletoalldevices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1k W
500 W
500 W
500 W
VCC RL
2 V´CC
2 V´CC
2 V´CC
2´VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
VCC
VCC
VCC
VCC
VI
V /2
CC
V /2
CC
V /2
CC
V /2
CC
VM
t /t
r f
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
11
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Parameter Measurement Information (continued)
Figure 5. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS f... so 0 COM (0n) V2 (M RL/CL: sun man pF RL/CL: so 015 pF 0 “’7 5 VIL i 0.1 w: W 'm 50 0 V1 GND “’7
VCC
VO1
GND
Y1
VCC
VIL
Y2
VIL or VIH
50 Ω
0.1 µF
fin
CL
50 pF
VCC/2
Rin
600 Ω
RL
600 Ω
VO2
CL
50 pF
VCC/2
RL
600 Ω
VA
VIL
VIH
TEST CONDITION
20log10(VO2/VI)
20log10(VO1/VI)
A
VA
VINH
INH
COM
VCC
VO
GND
Y1
(On)
VCC
VIL
Y2
A
VA
VINH
INH
COM
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
50 Ω
0.1 µF
fin
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
RLCL
VCC/2
12
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Parameter Measurement Information (continued)
Figure 6. Frequency Response (Switch On)
Figure 7. Crosstalk (Between Switches)
l TEXAS INSTRUMENTS v.L or v.N 7 7 7 7o 7 70 v2 2 5n n (On) em: Vcc 7 7o 70 v2 2 “L f... sn 0 (cm Vcc RL/CL: sun man pF RL/CL: so 015 pF M72
VCC
VO
GND
Y1
(Off)
VCC
VIL
Y2
VIL or VIH
S
1
2
50 Ω
0.1 µF
fin
RL/CL: 600 Ω/50 pF
RL/CL: 50 Ω/5 pF
RLCL
VCC/2
RL
VCC/2
A
VA
VINH
INH
COM
S
1
2
VA
VIL
VIH
VCC
VO
GND
Y1
(On)
VCC
Y2
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
50 Ω
VCC/2
Rin
600 Ω
VCC/2
CL
50 pF
RL
600 Ω
A
VA
VINH
INH
COM
13
SN74LVC2G53
www.ti.com
SCES324Q –JULY 2001–REVISED JANUARY 2019
Product Folder Links: SN74LVC2G53
Submit Documentation FeedbackCopyright © 2001–2019, Texas Instruments Incorporated
Parameter Measurement Information (continued)
Figure 8. Crosstalk (Control Input, Switch Output)
Figure 9. Feedthrough (Switch Off)
l TEXAS f". INSTRUMENTS Vcc 5 vA vCC VIL 7 7 2 Vin 60!] Q (0") v1 1 Vcc = 4.50 v, v. : 4.0 v” 0 M7 5 w
VCC
VO
GND
Y1
(On)
VCC
VIL
Y2
VIL or VIH
S
1
2
VA
VIL
VIH
S
1
2
600 Ω
10 µF
fin
RL
10 kΩCL
50 pF
VCC/2
VCC = 1.65 V, VI = 1.4 VP-P
VCC = 2.30 V, VI = 2.0 VP-P
VCC = 3.00 V, VI = 2.5 VP-P
VCC = 4.50 V, VI = 4.0 VP-P
10 µF
A
VA
VINH
INH
COM
14
SN74LVC2G53
SCES324Q –JULY 2001–REVISED JANUARY 2019
www.ti.com
Product Folder Links: SN74LVC2G53
Submit Documentation Feedback Copyright © 2001–2019, Texas Instruments Incorporated
Parameter Measurement Information (continued)
Figure 10. Sine-Wave Distortion
‘5‘ TEXAS INSTRUMENTS
COM Y
Y2
A
INH
Y1
COM
5
2
7
6
1
SW
SW
15
SN74LVC2G53
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SCES324Q –JULY 2001–REVISED JANUARY 2019
Product Folder Links: SN74LVC2G53
Submit Documentation FeedbackCopyright © 2001–2019, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
This dual analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G53 device can handle both analog and digital signals. This device permits signals with
amplitudes of up to 5.5 V (peak) to be transmitted in either direction.
8.2 Functional Block Diagram
NOTE: For simplicity, the test conditions shown in Figure 1 through Figure 4 and Figure 6 through Figure 10 are for the
demultiplexer configuration. Signals can be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.
Figure 11. Logic Diagram
Figure 12. Logic Diagram, Each Switch (SW)
8.3 Feature Description
A high-level voltage applied to INH disables the switches. When INH is low, signals can pass from A to Y or Y to
A. Low ON-resistance of 6.5 Ωat 4.5-V VCC is ideal for analog signal conditioning systems. The control signals
can accept voltages up to 5.5 V without VCC connected in the system. Combination of lower tpd of 0.8 ns at 3.3 V
and low enable and disable time make this part suitable for high-speed signal switching applications.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC2G53.
Table 1. Function Table
CONTROL
INPUTS ON
CHANNEL
INH A
L L Y1
L H Y2
H X None
l TEXAS INSTRUMENTS
A
Device 1
Device 2
INH
Microcontroller
SN74LVC2G53
16
SN74LVC2G53
SCES324Q –JULY 2001–REVISED JANUARY 2019
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Product Folder Links: SN74LVC2G53
Submit Documentation Feedback Copyright © 2001–2019, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC2G53 can be used in any situation where an SPDT switch is required in an application. This switch
helps to select one of two signals of which signals can be either digital or analog.
9.2 Typical Application
Figure 13. Typical Application Schematic
9.2.1 Design Requirements
The SN74LVC2G53 allows on/off control of analog and digital signals with a digital control signal. All input
signals should remain between 0 V and VCC for optimal operation.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/Δv in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs and outputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
– Load currents should not exceed ±50 mA.
3. Frequency Selection Criterion:
– Maximum frequency tested is 150 MHz.
– Added trace resistance or capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout.
l TEXAS INSTRUMENTS cc
Vcc(V)
max
tpd
(ns)
00.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0.5
1
1.5
2
2.5
17
SN74LVC2G53
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Typical Application (continued)
9.2.3 Application Curve
Figure 14. tpd vs VCC
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings .
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual-supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
l TEXAS INSTRUMENTS WORST B ETTER / /
WORST BETTER BEST
1W min.
W
2W
18
SN74LVC2G53
SCES324Q –JULY 2001–REVISED JANUARY 2019
www.ti.com
Product Folder Links: SN74LVC2G53
Submit Documentation Feedback Copyright © 2001–2019, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection.
NOTE
Not all PCB traces can be straight, and so they will have to turn corners. Figure 15 shows
progressively better techniques of rounding corners. Only the last example maintains
constant trace width and minimizes reflections.
11.2 Layout Example
Figure 15. Trace Example
l TEXAS INSTRUMENTS
19
SN74LVC2G53
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SCES324Q –JULY 2001–REVISED JANUARY 2019
Product Folder Links: SN74LVC2G53
Submit Documentation FeedbackCopyright © 2001–2019, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC2G53DCT3 ACTIVE SM8 DCT 8 3000 RoHS &
Non-Green SNBI Level-1-260C-UNLIM -40 to 85 C53
Z
SN74LVC2G53DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C53
Z
SN74LVC2G53DCTRG4 ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C53
Z
SN74LVC2G53DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (53, C53Q, C53R)
CZ
SN74LVC2G53DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C53R
SN74LVC2G53DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (53, C53Q, C53R)
CZ
SN74LVC2G53DCUTG4 ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM C53R
SN74LVC2G53YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C4N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE OOODOODD ,,,,,,,,,,, ‘ User Direcllon 0' Feed Sprocket Hoies Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC2G53DCT3 SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74LVC2G53DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74LVC2G53DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G53DCUR VSSOP DCU 8 3000 180.0 9.0 2.25 3.4 1.0 4.0 8.0 Q3
SN74LVC2G53DCURG4 VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G53DCUTG4 VSSOP DCU 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC2G53YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC2G53DCT3 SM8 DCT 8 3000 182.0 182.0 20.0
SN74LVC2G53DCTR SM8 DCT 8 3000 182.0 182.0 20.0
SN74LVC2G53DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74LVC2G53DCUR VSSOP DCU 8 3000 182.0 182.0 20.0
SN74LVC2G53DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0
SN74LVC2G53DCUTG4 VSSOP DCU 8 250 202.0 201.0 28.0
SN74LVC2G53YZPR DSBGA YZP 8 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
4.25
3.75 TYP
1.3
1.0
6X 0.65
8X 0.30
0.15
2X
1.95
(0.15) TYP
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.2
A
3.15
2.75
NOTE 3
B2.9
2.7
NOTE 4
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
18
0.13 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.500
J
www.ti.com
EXAMPLE BOARD LAYOUT
(3.8)
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.1)
8X (0.4)
6X (0.65)
(R0.05)
TYP
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
1
45
8
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(3.8)
6X (0.65)
8X (0.4)
8X (1.1)
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
WT
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1.5
TYP
0.5 TYP
8X 0.25
0.21
0.5
TYP
B E A
D
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
D
SCALE 8.000
D: Max =
E: Max =
1.918 mm, Min =
0.918 mm, Min =
1.858 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
8X ( 0.23) (0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
D
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
8X ( 0.25) (R0.05) TYP
METAL
TYP
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
D
MECHANICAL DATA DCU (R—PDSO—GB) PLASTIC SMALL—OUTLINE PACKAGE (DIE DOWN) F Wngiw 31117 0,15 \0M 7 7,40 310 2,20 3,00 i Gage Pm J i 3W1 / __'—_“ NDEX AREA 1 99 Do $1212]: : Q% J L W 4200503” z7/05 NOTES, A AH Hnec' dimensmrs in m'hmekers B Tris drawing is sum 0 Change mm: malice, 0 Body dimCHSiOnS do mi inciudc mom flash or oromsm Moid tics» and pvctrusmn srai not cxcccd o it) 30V m D FuHs wiwu JEDEC M0457 vuiiuliovi CA ‘4‘ TEXAS INSTRUMENTS www.(i. com
LAND PATTERN DATA DCU (S—PDSO—G8) PLASTIC SMALL OUTLINE PACKAGE (DH-Z DOWN) Example Board Layout (Nate 0,5) l ihi' 6x 0,5 I 3,1 ( 8% ‘\ / + 0,3 Exampie /Soider Mask Opening \ Pad Geometry Exampie Stencii Design (Nate D) 8x 0,25 —‘ |——‘ Er Eflfii- Bx 0,75 7 ‘|———'- 6x 0,5 HHH%- meow/c 04/12 NOTES: Au Pom .m Ali iinear dimensions are in miiiimeters‘ This drawing is subject to change without notice. Publication iPC—735I is recommended for aiternate designs. Laser cutting aperture5 with trupezoidai wails and also rounding corners wiil ciier better paste reiease. Customers should Contact their haard assembly site for stencii design recommendations. Refer to iFC—7525 for other slencii recommendations. Custamers shauid Contact their board fabrication site for saider mask toierances between and around signai pads. {I} Tums INSTRUMENTS www.li.com
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