SN74LVC2G34 Datasheet by Texas Instruments

V'.‘ ‘F. B X E I TEXAS INSTRUMENTS
1A 1Y
1 6
2A 2Y
3 4
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
SN74LVC2G34
SCES359J –AUGUST 2001REVISED OCTOBER 2015
SN74LVC2G34 Dual Buffer Gate
1 Features 3 Description
The SN74LVC2G34 device is a dual buffer gate
1 Available in the Texas Instruments designed for 1.65-V to 5.5-V VCC operation. The
NanoFree™ Package SN74LVC2G34 device performs the Boolean function
Supports 5.5-V VCC Operation Y = A in positive logic.
Inputs Accept Voltages to 5.5 V NanoFree package technology is a major
Maximum tpd of 4.1 ns at 3.3 V breakthrough in IC packaging concepts, using the die
Low Power Consumption, 10-µA Maximum ICC as the package.
±24-mA Output Drive at 3.3 V This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
Typical VOLP (Output Ground Bounce) outputs, preventing damaging current backflow
<0.8 V at VCC = 3.3 V, TA= 25°C through the device when it is powered down.
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA= 25°C Device Information(1)
• Ioff Supports Live Insertion, Partial-Power-Down PART NUMBER PACKAGE BODY SIZE (NOM)
Mode, and Back-Drive Protection SN74LVC2G34DBV SOT-23 (6) 2.90 mm × 1.60 mm
Can Be Used as a Down Translator to Translate SN74LVC2G34DCK SC70 (6) 2.00 mm × 1.25 mm
Inputs From a Maximum of 5.5 V Down to the VCC SN74LVC2G34DRL SOT (6) 1.60 mm × 1.20 mm
Level SN74LVC2G34YZP DSBGA (6) 1.41 mm × 0.91 mm
Latch-Up Performance Exceeds 100 mA Per (1) For all available packages, see the orderable addendum at
JESD 78, Class II the end of the data sheet.
ESD Protection Exceeds JESD 22 Simplified Schematic
2000-V Human Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
2 Applications
AV Receivers
Audio Docks: Portable
Blu-ray Player and Home Theaters
DVD Recorders and Players
Embedded PCs
MP3 Players and Recorders (Portable Audio)
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid-State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablets: Enterprise
Video Analytics: Servers
Wireless Headsets, Keyboards, and Mice
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
l TEXAS INSTRUMENTS
SN74LVC2G34
SCES359J –AUGUST 2001REVISED OCTOBER 2015
www.ti.com
Table of Contents
8.2 Functional Block Diagram ......................................... 8
1 Features.................................................................. 18.3 Feature Description................................................... 8
2 Applications ........................................................... 18.4 Device Functional Modes.......................................... 8
3 Description ............................................................. 19 Application and Implementation .......................... 9
4 Revision History..................................................... 29.1 Application Information.............................................. 9
5 Pin Configuration and Functions......................... 39.2 Typical Application ................................................... 9
6 Specifications......................................................... 310 Power Supply Recommendations ..................... 10
6.1 Absolute Maximum Ratings ..................................... 311 Layout................................................................... 10
6.2 ESD Ratings.............................................................. 411.1 Layout Guidelines ................................................. 10
6.3 Recommended Operating Conditions ...................... 411.2 Layout Example .................................................... 10
6.4 Thermal Information.................................................. 412 Device and Documentation Support ................. 11
6.5 Electrical Characteristics........................................... 512.1 Documentation Support ........................................ 11
6.6 Switching Characteristics.......................................... 512.2 Community Resources.......................................... 11
6.7 Operating Characteristics.......................................... 512.3 Trademarks........................................................... 11
6.8 Typical Characteristics.............................................. 612.4 Electrostatic Discharge Caution............................ 11
7 Parameter Measurement Information .................. 712.5 Glossary................................................................ 11
8 Detailed Description.............................................. 813 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................... 8Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (December 2013) to Revision J Page
Added Applications,Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal
Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
Deleted part number from Switching Characteristics table headers. ..................................................................................... 5
Changes from Revision H (February 2007) to Revision I Page
Updated document to new TI data sheet format.................................................................................................................... 1
Removed Ordering Information table. .................................................................................................................................... 1
Updated Features section ...................................................................................................................................................... 1
Updated operating temperature range. .................................................................................................................................. 4
2Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G34
l TEXAS INSTRUMENTS HHH Hljlj 0 WWW l_l n
3
2
4
61
1A 1Y
2Y
GND
2A
VCC
5
1A
2A
1Y
2Y
GND
1
4
2
3
6
5VCC
3
2
4
61
1A 1Y
2Y
GND
2A
VCC
5
SN74LVC2G34
www.ti.com
SCES359J –AUGUST 2001REVISED OCTOBER 2015
5 Pin Configuration and Functions
DBV Package DCK Package
6-Pin SOT-23 6-Pin SC70
Top View Top View
YZP Package
6-Pin DSBGA
Bottom View
DRL Package
6-Pin SOT
Top View
Pin Functions(1)
PIN I/O DESCRIPTION
NAME NO.
1A 1 I Buffer Input 1
1Y 6 O Buffer Output 1
2A 3 I Buffer Input 2
2Y 4 O Buffer Output 2
GND 2 Ground pin
VCC 5 Power pin
(1) See mechanical drawings for dimensions.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VIInput voltage(2) –0.5 6.5 V
VOVoltage applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V
VOVoltage applied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN74LVC2G34
l TEXAS INSTRUMENTS
SN74LVC2G34
SCES359J –AUGUST 2001REVISED OCTOBER 2015
www.ti.com
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2500
Electrostatic
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V –24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V 24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
Δt/Δv Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
DBV, DCK, DRL Package –40 125
TAOperating free-air temperature °C
YZP Package -40 85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Semiconductor and Implications of Slow or Floating CMOS Inputs,SCBA004.
6.4 Thermal Information
SN74LVC2G34
THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) DRL (SOT) YZP (DSBGA) UNIT
6 PINS 6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 165 259 142 123 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G34
l TEXAS INSTRUMENTS
SN74LVC2G34
www.ti.com
SCES359J –AUGUST 2001REVISED OCTOBER 2015
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 2.4
3 V
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 0.4
3 V
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.55
IIA inputs VI= 5.5 V or GND 0 to 5.5 V ±5 µA
Ioff VIor VO= 5.5 V 0 ±10 µA
ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 µA
One input at VCC – 0.6 V,
ΔICC 3 V to 5.5 V 500 µA
Other inputs at VCC or GND
CiVI= VCC or GND 3.3 V 3.5 pF
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
FROM TO OPERATING FREE-AIR
PARAMETER VCC MIN MAX UNIT
(INPUT) (OUTPUT) TEMPERATURE (TA)
VCC = 1.8 V ± 0.15 V 3.2 8.6
VCC = 2.5 V ± 0.2 V 1.5 4.4
tpd A Y –40°C to 85°C ns
VCC = 3.3 V ± 0.3 V 1.4 4.1
VCC = 5 V ± 0.5 V 1 3.2
VCC = 1.8 V ± 0.15 V 3.2 9.6
VCC = 2.5 V ± 0.2 V 1.5 4.9
tpd A Y –40°C to 125°C ns
VCC = 3.3 V ± 0.3 V 1.2 4.6
VCC = 5 V ± 0.5 V 1 3.7
6.7 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
VCC = 1.8 V 14
VCC = 2.5 V 14
Cpd Power dissipation capacitance f = 10 MHz pF
VCC = 3.3 V 15
VCC = 5 V 17
Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN74LVC2G34
l TEXAS INSTRUMENTS 25
Temperature - °C
TPD - ns
-100 -50 0 50 100 150
0
0.5
1
1.5
2
2.5
D001
TPD
SN74LVC2G34
SCES359J –AUGUST 2001REVISED OCTOBER 2015
www.ti.com
6.8 Typical Characteristics
Figure 1. TPD Across Temperature at 3.3-V VCC
6Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G34
*9 TEXAS INSTRUMENTS «H ; H; ‘ll‘ 1
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC2G34
www.ti.com
SCES359J –AUGUST 2001REVISED OCTOBER 2015
7 Parameter Measurement Information
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN74LVC2G34
l TEXAS INSTRUMENTS _> _ _>_2Y
1A 1Y
1 6
2A 2Y
3 4
SN74LVC2G34
SCES359J –AUGUST 2001REVISED OCTOBER 2015
www.ti.com
8 Detailed Description
8.1 Overview
The SN74LVC2G34 device contains two buffer gates that each perform the Boolean function Y = A. This device
is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing
damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
8.3 Feature Description
The SN74LVC2G34 device has a wider operating voltage range, operating from 1.65 V to 5.5 V, and allows
down voltage translation. The SN74LVC2G34 Ioff feature allows voltages on the inputs and outputs when VCC is
0 V.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC2G34.
Table 1. Function Table
INPUT OUTPUT
A Y
H H
L L
8Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G34
‘5‘ TEXAS INSTRUMENTS
SN74LVC2G34 SN74LVC2G34
Buffer Function Basic LED Driver VCC
VCC
Microcontroller or
Logic
Microcontroller or
Logic Microcontroller or
Logic
SN74LVC2G34
www.ti.com
SCES359J –AUGUST 2001REVISED OCTOBER 2015
9 Application and Implementation
9.1 Application Information
The SN74LVC2G34 is a high-drive CMOS device that can be used as a buffer with a high output drive, such as
an LED application. It can produce 24 mA of drive current at 3.3 V, making it ideal for driving multiple outputs
and good for high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant allowing it to translate down
to VCC.
9.2 Typical Application
Figure 3. Typical Application
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommended Output Conditions
Load currents must not exceed (IOmax) per output and must not exceed (Continuous current through VCC
or GND) total current for the part. These limits are located in the Recommended Operating Conditions
table.
Outputs much not be pulled above VCC under normal operating conditions.
Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: SN74LVC2G34
l TEXAS INSTRUMENTS
VCC
Unused Input
Input
Output Output
Input
Unused Input
Vcc - V
TPD - ns
0 1 2 3 4 5 6
0
1
2
3
4
5
D002
TPD
SN74LVC2G34
SCES359J –AUGUST 2001REVISED OCTOBER 2015
www.ti.com
Typical Application (continued)
9.2.3 Application Curve
Figure 4. TPD Across VCC at 25°C
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF capacitor is
recommended for each power pin. It is ok to parallel multiple bypass caps to reject different frequencies of noise.
0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to
the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on
the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient.
11.2 Layout Example
10 Submit Documentation Feedback Copyright © 2001–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G34
l TEXAS INSTRUMENTS
SN74LVC2G34
www.ti.com
SCES359J –AUGUST 2001REVISED OCTOBER 2015
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Documentation Support
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs,SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: SN74LVC2G34
{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Jul-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC2G34DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C345, C34F, C34K,
C34O, C34R) Samples
SN74LVC2G34DBVRE4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C34F, C34R) Samples
SN74LVC2G34DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C34F, C34R) Samples
SN74LVC2G34DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C345, C34F, C34K,
C34R) Samples
SN74LVC2G34DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C34F, C34R) Samples
SN74LVC2G34DCK3 ACTIVE SC70 DCK 6 3000 RoHS &
Non-Green SNBI Level-1-260C-UNLIM -40 to 85 C9Z Samples
SN74LVC2G34DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C95, C9F, C9K, C9
R) Samples
SN74LVC2G34DCKRE4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C95 Samples
SN74LVC2G34DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C95 Samples
SN74LVC2G34DRLR ACTIVE SOT-5X3 DRL 6 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (1K8, C97, C9R) Samples
SN74LVC2G34YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 C9N Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 14-Jul-2022
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2G34 :
Enhanced Product : SN74LVC2G34-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC2G34DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G34DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3
SN74LVC2G34DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G34DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G34DBVTG4 SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC2G34DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G34DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74LVC2G34DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3
SN74LVC2G34DCKRG4 SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC2G34DRLR SOT-5X3 DRL 6 4000 180.0 8.4 2.0 1.8 0.75 4.0 8.0 Q3
SN74LVC2G34DRLR SOT-5X3 DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC2G34YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC2G34DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74LVC2G34DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC2G34DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC2G34DBVT SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC2G34DBVTG4 SOT-23 DBV 6 250 180.0 180.0 18.0
SN74LVC2G34DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G34DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G34DCKR SC70 DCK 6 3000 202.0 201.0 28.0
SN74LVC2G34DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC2G34DRLR SOT-5X3 DRL 6 4000 210.0 185.0 35.0
SN74LVC2G34DRLR SOT-5X3 DRL 6 4000 202.0 201.0 28.0
SN74LVC2G34YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
1.7
1.5
4X 0.5
2X 1
6X 0.3
0.1
0.6 MAX
6X 0.18
0.08
6X 0.4
0.2
0.05
0.00 TYP
6X 0.27
0.15
B1.3
1.1
A
1.7
1.5
NOTE 3
SOT - 0.6 mm max heightDRL0006A
PLASTIC SMALL OUTLINE
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
16
PIN 1
ID AREA
34
SEATING PLANE
0.05 C
SCALE 8.000
0.1 C A B
0.05
SYMM
SYMM
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
AROUND 0.05 MIN
AROUND
6X (0.67)
6X (0.3)
(1.48)
4X (0.5)
(R0.05) TYP
4223266/C 12/2021
SOT - 0.6 mm max heightDRL0006A
PLASTIC SMALL OUTLINE
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
SYMM
1
34
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
(1.48)
4X (0.5)
6X (0.67)
6X (0.3)
(R0.05) TYP
SOT - 0.6 mm max heightDRL0006A
PLASTIC SMALL OUTLINE
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
SYMM
SYMM
1
34
6
MECHANICAL DATA DCK (R-PDSO-GS) PLASTIC SMALL-OUTLINE PACKAGE E 18’) 6 4 7 H Fl H ‘fi «40 1233 \ ’i’ To enugemane Seanng Mane Pm 1/ ' ‘ ' ‘ ‘ maexArea Wm H m} j; / ‘ u / Um "4L 1—]; f Scamg Mane \\ \ / 31 409555574/8 U‘ /200/ , m m hmeters AH \mec' mmens‘mrs Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m FuHs an JFDFC M07763 vunuhcn AB NO'FS Umm> INSrRUMEm-s www.1i.com
LAND PATTERN DATA 7PJSOiC6> PLASTC SMALL OU’LME NOTES' maop> Exc'm‘e Boc'd Luyum stem Openings Based or a stencfl hickncss uf 127mm (005mm) * 1* :E /23\\der Musk Cpen‘wg “ 2m Geometry M \meur dimensmns are m m'flhrvete's Th's drawqu is sweat (a chc'vge mm: 'vuhce Custume's shoud p‘uce a new 01 We cvcmt buurd (abr'cahun c'awmg rm :0 uHer the ce'fle' smder musk defined and, ”Jbficuhon \PC77351 is reco'n'nended (Dr uHernme designs Laser cumrg opc'mvcs mm "apczmda wuHs and mo rouncmq corners wm am bcncr aosxc recuscv mstomcrs show can thew Guard assemwy sue for gene design recommencnmons Exomme sxercu deswgw basec on a 50% vo‘umemc bad My paste M‘cr m M4523 var other new rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
3: fig,
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50
0.25
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
6
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
6X (1.1)
6X (0.6)
(2.6)
2X (0.95)
(R0.05) TYP
4214840/C 06/2021
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
2X(0.95)
6X (1.1)
6X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
6
www.ti.com
PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1
TYP
0.5 TYP
6X 0.25
0.21
0.5
TYP
B E A
D
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
NanoFree Is a trademark of Texas Instruments.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
A
12
0.015 C A B
SYMM
SYMM
C
SCALE 9.000
D: Max =
E: Max =
1.418 mm, Min =
0.918 mm, Min =
1.358 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
6X ( )0.225 (0.5) TYP
(0.5) TYP
()
METAL
0.225 0.05 MAX
SOLDER MASK
OPENING
METAL
UNDER
MASK
()
SOLDER MASK
OPENING
0.225
0.05 MIN
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
6X ( 0.25) (R ) TYP0.05
METAL
TYP
4219524/A 06/2014
DSBGA - 0.5 mm max heightYZP0006
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated