SN54HCT244, SN74HCT244 Datasheet by Texas Instruments

V'.‘ ‘F. B X E I TEXAS INSTRUMENTS
1
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19
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17 3
5
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18
1A1
1A2
1A3
1A4
1Y1 2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
2OE
1OE
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HCT244
,
SN74HCT244
SCLS175E –MONTH 2003–REVISED AUGUST 2016
SNx4HCT244 Octal Buffers and Line Drivers With 3-State Outputs
1
1 Features
1• Operating Voltage Range of 4.5 V to 5.5 V
• High-Current Outputs Drive up to 15 LSTTL Loads
• Low Power Consumption: 80-µA Maximum ICC
• Typical tpd = 13 ns
• ±6-mA Output Drive at 5 V
• Low Input Current of 1 µA Maximum
• Inputs Are TTL-Voltage Compatible
• 3-State Outputs Drive Bus Lines and Buffer
Memory Address Registers
2 Applications
• Servers
• LED Displays
• Network Switches
• Telecom Infrastructure
• Motor Drivers
• I/O Expanders
3 Description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers,
clockdrivers, and bus-oriented receivers and
transmitters. The SNx4HCT244 devices are
organized as two 4-bit buffers or drivers with separate
output-enable (OE) inputs. When OE is low, the
device passes noninverted data from the A inputs to
the Y outputs. When OE is high, the outputs are in
the high-impedance state.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HCT244DB SSOP (20) 7.20 mm × 5.30 mm
SN74HCT244DW SOIC (20) 12.80 mm × 7.50 mm
SN74HCT244N PDIP (20) 24.33 mm × 6.35 mm
SN74HCT244NS SO (20) 12.60 mm × 5.30 mm
SN74HCT244PW TSSOP (20) 6.50 mm × 4.40 mm
SN54HCT244 CDIP (20) 24.20 mm × 6.92 mm
LCCC (20) 8.89 mm × 8.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
l TEXAS INSTRUMENTS
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SN54HCT244
,
SN74HCT244
SCLS175E –MONTH 2003–REVISED AUGUST 2016
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics: CL= 50 pF ...................... 6
6.7 Switching Characteristics: CL= 150 pF .................... 6
6.8 Operating Characteristics.......................................... 7
6.9 Typical Characteristics.............................................. 7
7 Parameter Measurement Information .................. 8
8 Detailed Description.............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9 Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1 Documentation Support ........................................ 12
12.2 Related Links ........................................................ 12
12.3 Receiving Notification of Documentation Updates 12
12.4 Community Resource............................................ 12
12.5 Trademarks........................................................... 12
12.6 Electrostatic Discharge Caution............................ 12
12.7 Glossary................................................................ 12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2013) to Revision E Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
• Changed Thermal Information table....................................................................................................................................... 5
• Added ESD warning ............................................................................................................................................................... 9
l TEXAS INSTRUMENTS
Not to scale
41A2
52Y3
61A3
72Y2
81A4
92Y1
10GND
112A1
121Y4
132A2
14 1Y3
15 2A3
16 1Y2
17 2A4
18 1Y1
19 2OE
20 VCC
1 1OE
2 1A1
3 2Y4
11OE 20 VCC
21A1 19 2OE
32Y4 18 1Y1
41A2 17 2A4
52Y3 16 1Y2
61A3 15 2A3
72Y2 14 1Y3
81A4 13 2A2
92Y1 12 1Y4
10GND 11 2A1
Not to scale
3
SN54HCT244
,
SN74HCT244
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5 Pin Configuration and Functions
J, W, DB, DW, N, NS, or PW Packages
20-Pin CDIP, CFP, SSOP, SOIC, PDIP, SO, or TSSOP
Top View
FK Package
20-Pin LCCC
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 1OE I Output enable
2 1A1 I Input
3 2Y4 O Output
4 1A2 I Input
5 2Y3 O Output
6 1A3 I Input
7 2Y2 O Output
8 1A4 I Input
9 2Y1 O Output
10 GND — Ground
11 2A1 I Input
12 1Y4 O Output
13 2A2 I Input
14 1Y3 O Output
15 2A3 I Input
16 1Y2 O Output
17 2A4 I Input
18 1Y1 O Output
19 2OE I Output enable
20 VCC — Power pin
l TEXAS INSTRUMENTS
4
SN54HCT244
,
SN74HCT244
SCLS175E –MONTH 2003–REVISED AUGUST 2016
www.ti.com
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI< 0 or VI> VCC ±20 mA
IOK Output clamp current(2) VO< 0 or VO> VCC ±20 mA
IOContinuous output current VO= 0 to VCC ±35 mA
Continuous channel current through VCC or GND ±70 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
SN74HCT244 in DB, DW, N, NS, or PW package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
SN54HCT244 in J, W, or FK package
V(ESD) Electrostatic discharge Human-body model (HBM) ±1500 V
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or Floating
CMOS Inputs application report.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
∆t/∆v Input transition rise and fall time 500 ns
TAOperating free-air temperature SN54HCT244 –55 125 °C
SN74HCT244 –40 85
l TEXAS INSTRUMENTS
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SN54HCT244
,
SN74HCT244
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
SN74HCT244
UNIT
DB
(SSOP) DW
(SOIC) N
(PDIP) NS
(SO) PW
(TSSOP)
20 PINS 20 PINS 20 PINS 20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 89.4 76.6 44.8 71.8 97.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.8 42.1 30.9 38.1 32.5 °C/W
RθJB Junction-to-board thermal resistance 44.5 44.5 25.7 39.2 49.3 °C/W
ψJT Junction-to-top characterization parameter 16.9 15.9 16.3 14.9 1.7 °C/W
ψJB Junction-to-board characterization parameter 44.1 44 25.6 38.8 47.7 °C/W
(1) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VOH VI= VIH or VIL
IOH = –20 µA
TA= 25°C
4.5 V
4.4 4.499
V
SN54HCT244 4.4
SN74HCT244 4.4
IOH = –6 mA
TA= 25°C 3.98 4.3
SN54HCT244 3.7
SN74HCT244 3.84
VOL VI= VIH or VIL
IOL = 20 µA
TA= 25°C
4.5 V
0.001 0.1
V
SN54HCT244 0.1
SN74HCT244 0.1
IOL = 6 mA
TA= 25°C 0.17 0.26
SN54HCT244 0.4
SN74HCT244 0.33
IIVI= VCC or 0
TA= 25°C
5.5 V
±0.1 ±100
nASN54HCT244 ±1000
SN74HCT244 ±1000
IOZ
VO= VCC or 0,
VI= VIH or VIL
TA= 25°C
5.5 V
±0.01 ±0.5
µASN54HCT244 ±10
SN74HCT244 ±5
ICC VI= VCC or 0,
IO= 0
TA= 25°C
5.5 V
8
µASN54HCT244 160
SN74HCT244 80
∆ICC(1)
One input at 0.5 V
or 2.4 V,
Other inputs at 0 or
VCC
TA= 25°C
5.5 V
1.4 2.4
mA
SN54HCT244 3
SN74HCT244 2.9
Ci
TA= 25°C 4.5 V to
5.5 V
3 10
pFSN54HCT244 10
SN74HCT244 10
l TEXAS INSTRUMENTS
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SN54HCT244
,
SN74HCT244
SCLS175E –MONTH 2003–REVISED AUGUST 2016
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Product Folder Links: SN54HCT244 SN74HCT244
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6.6 Switching Characteristics: CL= 50 pF
over recommended operating free-air temperature range, CL= 50 pF (unless otherwise noted) (see Figure 2 )
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC TEST
CONDITIONS MIN TYP MAX UNIT
tpd A Y
4.5 V
TA= 25°C 15 28
ns
SN54HCT244 42
SN74HCT244 35
5.5 V
TA= 25°C 13 25
SN54HCT244 38
SN74HCT244 32
ten OE Y
4.5 V
TA= 25°C 21 35
ns
SN54HCT244 53
SN74HCT244 44
5.5 V
TA= 25°C 19 32
SN54HCT244 48
SN74HCT244 40
tdis OE Y
4.5 V
TA= 25°C 19 35
ns
SN54HCT244 53
SN74HCT244 44
5.5 V
TA= 25°C 18 32
SN54HCT244 48
SN74HCT244 40
ttY
4.5 V
TA= 25°C 8 12
ns
SN54HCT244 18
SN74HCT244 15
5.5 V
TA= 25°C 7 11
SN54HCT244 16
SN74HCT244 14
6.7 Switching Characteristics: CL= 150 pF
over recommended operating free-air temperature range, CL= 150 pF (unless otherwise noted) (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC TEST
CONDITIONS MIN TYP MAX UNIT
tpd A Y
4.5 V
TA= 25°C 21 45
ns
SN54HCT244 68
SN74HCT244 56
5.5 V
TA= 25°C 18 40
SN54HCT244 61
SN74HCT244 51
ten OE Y
4.5 V
TA= 25°C 25 52
ns
SN54HCT244 79
SN74HCT244 65
5.5 V
TA= 25°C 22 47
SN54HCT244 71
SN74HCT244 59
l TEXAS INSTRUMENTS
22
23
23
24
24
25
25
4.5 4.7 4.9 5.1 5.3 5.5
ten (ns)
VCC (V)
7
SN54HCT244
,
SN74HCT244
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SCLS175E –MONTH 2003–REVISED AUGUST 2016
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Switching Characteristics: CL= 150 pF (continued)
over recommended operating free-air temperature range, CL= 150 pF (unless otherwise noted) (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC TEST
CONDITIONS MIN TYP MAX UNIT
ttY
4.5 V
TA= 25°C 17 42
ns
SN54HCT244 63
SN74HCT244 53
5.5 V
TA= 25°C 14 38
SN54HCT244 57
SN74HCT244 48
6.8 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per buffer or driver No load 40 pF
6.9 Typical Characteristics
Figure 1. Enable Time vs VCC
‘5‘ TEXAS INSTRUMENTS r t a :1 fl 1% 1L: 1L ‘ F 4 1 J (pd IF’HL PLH
1.3 V
10%
90%
3 V
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
tPZL tPLZ
VOH
≈0 V
1.3 V
1.3 V
tPZH tPHZ
Output
Waveform 2
(See Note B)
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF
Open Open––
NOTES: A. CLincludes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤1 MHz, ZO= 50 Ω, tr= 6 ns, tf= 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
CL
(see Note A)
Test
Point
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.3 V1.3 V 0.3 V0.3 V
2.7 V 2.7 V 3 V
0 V
trtf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V1.3 V 10%10%
90% 90%
3 V
VOH
VOL
0 V
trtf
Input
In-Phase
Output
1.3 V
tPLH tPHL
1.3 V 1.3 V
10% 10%
90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
8
SN54HCT244
,
SN74HCT244
SCLS175E –MONTH 2003–REVISED AUGUST 2016
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7 Parameter Measurement Information
Figure 2. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS
1
2
4
6
8
19
11
13
15
17 3
5
7
9
12
14
16
18
1A1
1A2
1A3
1A4
1Y1 2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
2OE
1OE
Copyright © 2016, Texas Instruments Incorporated
9
SN54HCT244
,
SN74HCT244
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8 Detailed Description
8.1 Overview
The SNx4HCT244 device is organized as two 4-bit buffers and line drivers with separate output-enable (OE)
inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE must
be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking
capability of the driver.
8.2 Functional Block Diagram
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The SN74HCT244 device can drive up to 15 LSTTL loads. This device has low power consumption of 80-µA ICC.
The SN74HCT244 also has 3 state outputs that allow the outputs to go to high impedance, low or high.
8.4 Device Functional Modes
Table 1 lists the functions of the SNx4HC244.
Table 1. Function Table
INPUTS OUTPUT
Y
OE A
L H H
L L L
H X Z
l TEXAS INSTRUMENTS ‘W’Ww
1OE
A1
x
x
x
A4
GND
VCC
SN74HCT244
MCU or
System
Logic
Regulated 5V
MCU
System
Logic
LEDS
Y1
x
x
x
Y4
x
x
x
x
x
x
Copyright © 2016, Texas Instruments Incorporated
10
SN54HCT244
,
SN74HCT244
SCLS175E –MONTH 2003–REVISED AUGUST 2016
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HC244 is a high-drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern.
9.2 Typical Application
Figure 4. Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Avoid bus contention because it can drive
currents in excess of maximum limits. The high drive creates fast edges into light loads, so consider routing and
load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/ΔVinRecommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
2. Recommend output conditions:
– Load currents must not exceed the IOmaximum per output and must not exceed the continuous current
through VCC or GND total current for the part. These limits are located in Absolute Maximum Ratings.
– Outputs must not be pulled above VCC.
l TEXAS INSTRUMENTS
VCC
Unused Input
Input
Output Output
Input
Unused Input
17
18
19
20
21
22
4.5 4.7 4.9 5.1 5.3 5.5
tpd (ns)
VCC (V)
11
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Typical Application (continued)
9.2.3 Application Curve
Figure 5. Propagation Delay vs VCC
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC terminal must have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC terminals, then TI recommends 0.01-µF or
0.022-µF capacitors for each power terminal. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of noise. The
bypass capacitor must be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input and gate are used, or
when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
Figure 6. Layout Diagram
l TEXAS INSTRUMENTS
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SN54HCT244
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
SN54HCT244 Click here Click here Click here Click here Click here
SN74HCT244 Click here Click here Click here Click here Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Dec-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8513001VRA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8513001VR
A
SNV54HCT244J
5962-8513001VSA ACTIVE CFP W 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8513001VS
A
SNV54HCT244W
85130012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 85130012A
SNJ54HCT
244FK
8513001RA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8513001RA
SNJ54HCT244J
JM38510/65755B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65755B2A
JM38510/65755BRA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65755BRA
M38510/65755B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65755B2A
M38510/65755BRA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65755BRA
SN54HCT244J ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN54HCT244J
SN74HCT244DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT244
SN74HCT244DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT244
SN74HCT244DWE4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT244
SN74HCT244DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT244
SN74HCT244DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT244
SN74HCT244DWRE4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT244
SN74HCT244DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT244
SN74HCT244N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT244N
I TEXAS INSTRUMENTS Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Dec-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HCT244NE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT244N
SN74HCT244NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT244
SN74HCT244PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT244
SN74HCT244PWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT244
SN74HCT244PWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT244
SN74HCT244PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HT244
SN74HCT244PWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT244
SN74HCT244PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT244
SNJ54HCT244FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 85130012A
SNJ54HCT
244FK
SNJ54HCT244J ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8513001RA
SNJ54HCT244J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 28-Dec-2021
Addendum-Page 3
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HCT244, SN54HCT244-SP, SN74HCT244 :
•Catalog : SN74HCT244, SN54HCT244
•Automotive : SN74HCT244-Q1, SN74HCT244-Q1
•Enhanced Product : SN74HCT244-EP, SN74HCT244-EP
•Military : SN54HCT244
•Space : SN54HCT244-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width Bo Dimension deSigned to accommodate the component iengtn K0 Dimension designed to accommodate the component thickness 7 w OveraH Wiotn ot the carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HCT244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HCT244DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74HCT244NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74HCT244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74HCT244PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HCT244PWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HCT244PWT TSSOP PW 20 250 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Mar-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT244DBR SSOP DB 20 2000 853.0 449.0 35.0
SN74HCT244DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74HCT244NSR SO NS 20 2000 367.0 367.0 45.0
SN74HCT244PWR TSSOP PW 20 2000 364.0 364.0 27.0
SN74HCT244PWR TSSOP PW 20 2000 853.0 449.0 35.0
SN74HCT244PWRG4 TSSOP PW 20 2000 853.0 449.0 35.0
SN74HCT244PWT TSSOP PW 20 250 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Mar-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8513001VSA W CFP 20 1 506.98 26.16 6220 NA
85130012A FK LCCC 20 1 506.98 12.06 2030 NA
JM38510/65755B2A FK LCCC 20 1 506.98 12.06 2030 NA
M38510/65755B2A FK LCCC 20 1 506.98 12.06 2030 NA
SN74HCT244DW DW SOIC 20 25 507 12.83 5080 6.6
SN74HCT244DWE4 DW SOIC 20 25 507 12.83 5080 6.6
SN74HCT244DWG4 DW SOIC 20 25 507 12.83 5080 6.6
SN74HCT244N N PDIP 20 20 506 13.97 11230 4.32
SN74HCT244NE4 N PDIP 20 20 506 13.97 11230 4.32
SN74HCT244PW PW TSSOP 20 70 530 10.2 3600 3.5
SN74HCT244PWE4 PW TSSOP 20 70 530 10.2 3600 3.5
SN74HCT244PWG4 PW TSSOP 20 70 530 10.2 3600 3.5
SNJ54HCT244FK FK LCCC 20 1 506.98 12.06 2030 NA
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Mar-2022
Pack Materials-Page 3
MECHANICAL DATA W (R—GDFP—FZO) CERAWC DUAL FLATPACK Base and Szafing Hana (114111045 0.500 (7.62) f7 [1026 (0 as) 0.245 (6.22) f .: i ‘ ‘ 0.009 (023) fl? 0.004 0.10 <7 0.520="" (0.13)="" max="" 4»="" i="" 20="" :3="" i3:="" 0.022="" 0.56="" i:="" 3="" e="" )="" :i="" i:="" i="" 0.015="" (0.30)="" :3="" i:="" t="" :3="" ::i="" :3="" ::i="" 0.540="" (13.72)="" max="" [:3="" |::l="" [:3="" |::l="" [:3="" |::l="" [:3="" |::l="" “-005="" (m)="" m="" 4="" race:="" [:3="" i3:="" i="" 10="" i1="" 0="" 370="" (9,40)="" 0.370="" (9.40)="" 0.250="" (6.35)="" 0,250="" (5.35)="" 404013074/r="" 04/14="" notes:="" a.="" wpflw="" f0”:="" wilhin="" mh—std="" 1835="" gdfpz—fzo="" ah="" hnear="" dimensions="" are="" in="" inches="" (mhhmeters).="" this="" drawing="" ts="" sumeu="" \o="" cnange="" wunom="" nofice.="" this="" package="" can="" be="" hermelicahy="" semi="" win="" a="" ceramic="" lid="" using="" glass="" iril="" )ndex="" point="" is="" provided="" on="" cup="" (or="" lermina)="" identifica‘ion="" any.="" i="" texas="" instruments="" www.mmm="">
--I L J f T , g T Q f fl g
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
6.6
6.4
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
1
10 11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
““‘w‘+‘w““‘
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
gmgmmj r Egg;
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.5)
20X (0.45)
18X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0020A
SMALL OUTLINE PACKAGE
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
LAND PATTERN DATA PW (R7PDSOmGZO) PLAST‘C SMALL OUTLINE Exam ‘9 Board LG I“ F W Based on o stencii thickness oi .127mm (.oosinen). -—iiiiii‘fli*m -—iiiifi°fi°’i”ii ——U/,'Efli‘iiiiii -—HHHH1QXQBQHJH« A , Pad Geometry “\ 0,07 /’ ‘ ‘AH Arourig/ 421128475/6 08/15 NOTES: A. AH iineor dimensions are in miiiimeters. B. Inis drawing is subject to change without notice. c. Publication iPcr735i is recommended for aitemate design. D Laser cutting apertures witn trapezoidoi wuHs and oiso rounding earners wiii oiier aetter paste reieose. Customers should contact tneir board assembiy site (or stencii design recommendations. Reier to iPc—7525 (or otner stencii recommendations. E. Cusmmers shuuid Contact ‘heir hoard fubr‘icufiun site for solder musk tolerances beLween and nruund signal pads. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
I-III
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10
11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2.000
“‘w“‘+“‘w“‘
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
mi: 2.5%
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
DW0020A I
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
DW0020A
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DW0020A $$$$$fififiifi%
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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