SN54/SN74HC595 Datasheet by SparkFun Electronics

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SNx4HC595 8-Bit Shift Registers With 3-State Output Registers

1 Features

• 8-bit serial-in, parallel-out shift

• Wide operating voltage range of 2 V to 6 V

• High-current 3-state outputs can drive up to 15

LSTTL loads

• Low power consumption: 80-μA (maximum) ICC

• tpd = 13 ns (typical)

• ±6-mA output drive at 5 V

• Low input current: 1 μA (maximum)

• Shift register has direct clear

• On products compliant to MIL-PRF-38535,

all parameters are tested unless otherwise noted.

On all other products, production processing does

not necessarily include testing of all parameters.

2 Applications

• Network switches

• Power infrastructure

• LED displays

• Servers

3 Description

The SNx4HC595 devices contain an 8-bit, serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. The storage register has parallel 3-

state outputs. Separate clocks are provided for both

the shift and storage register. The shift register has

a direct overriding clear (SRCLR) input, serial (SER)

input, and serial outputs for cascading. When the

output-enable (OE) input is high, the outputs are in

the high-impedance state.

Device Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM)

SN54HC595FK LCCC (20) 8.89 mm × 8.89 mm

SN54HC595J CDIP (16) 21.34 mm × 6.92 mm

SN74HC595N PDIP (16) 19.31 mm × 6.35 mm

SN74HC595D SOIC (16) 9.90 mm × 3.90 mm

SN74HC595DW SOIC (16) 10.30 mm × 7.50 mm

SN74HC595DB SSOP (16) 6.20 mm × 5.30 mm

SN74HC595PW TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

QH′

SRCLR

RCLK

SRCLK

SER

Pin numbers shown are for the D, DB, DW, J, N, NS, PW, and W packages.

Functional Block Diagram

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Requirements.................................................. 6

6.7 Switching Characteristics............................................8

6.8 Operating Characteristics........................................... 8

6.9 Typical Characteristics................................................ 9

7 Parameter Measurement Information.......................... 10

8 Detailed Description...................................................... 11

8.1 Overview................................................................... 11

8.2 Functional Block Diagram......................................... 11

8.3 Feature Description...................................................12

8.4 Device Functional Modes..........................................12

9 Application and Implementation.................................. 13

9.1 Application Information............................................. 13

9.2 Typical Application.................................................... 13

10 Power Supply Recommendations..............................15

11 Layout........................................................................... 15

11.1 Layout Guidelines................................................... 15

11.2 Layout Example...................................................... 15

12 Device and Documentation Support..........................16

12.1 Documentation Support.......................................... 16

12.2 Support Resources................................................. 16

12.3 Trademarks............................................................. 16

12.4 Electrostatic Discharge Caution..............................16

12.5 Glossary..................................................................16

13 Mechanical, Packaging, and Orderable

Information.................................................................... 16

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (November 2009) to Revision I (August 2015) Page

• Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings

table, Thermal Information table, Feature Description section, Device Functional Modes, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1

• Deleted Ordering Information table. ...................................................................................................................1

• Added Military Disclaimer to Features list...........................................................................................................1

Changes from Revision I (August 2015) to Revision J (October 2021) Page

• Updated the device information table, ESD ratings table, and the device functional modes table to fit modern

data sheet standards.......................................................................................................................................... 1

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I TEXAS INSTRUMENTS O QBE1U1BJVCC 5329; QC[2 1510A 3212019 QD[3 14]SER gm 2 13% g — E QEE“ 13105 NC e 15[ No OF E 5 121RCLK Q; 7 15[ RCLK QG [ 6 11 ] SRCLK Ge 8 9 14E SRCLK QH[7 1OJSRCLR Iowa GNDEB SJQH' <35ng m="">

5 Pin Configuration and Functions

D, N, NS, J, DB, or PW Package

16-Pin SOIC, PDIP, SO, CDIP, SSOP, or TSSOP

Top View

FK Package

20-Pin LCCC

Top View

Table 5-1. Pin Functions

I/O(1) DESCRIPTION

NAME

SOIC, PDIP,

SO, CDIP,

SSOP, or

TSSOP

LCCC

GND 8 10 — Ground Pin

OE 13 17 I Output Enable

QA15 19 O QA Output

QB1 2 O QB Output

QC2 3 O QC Output

QD3 4 O QD Output

QE4 5 O QE Output

QF5 7 O QF Output

QG6 8 O QG Output

QH7 9 O QH Output

QH' 9 12 O QH' Output

RCLK 12 14 I RCLK Input

SER 14 18 I SER Input

SRCLK 11 14 I SRCLK Input

SRCLR 10 13 I SRCLR Input

NC —

— No Connection

VCC — 20 — Power Pin

(1) Signal Types: I = Input, O = Output, I/O = Input or Output.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC Supply voltage –0.5 7 V

IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA

IOK Output clamp current (2) VO < 0 or VO > VCC ±20 mA

IOContinuous output current VO = 0 to VCC ±35 mA

Continuous current through VCC or GND ±70 mA

TJJunction temperature 150 °C

Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) 1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

SN54HC595 SN74HC595 UNIT

MIN NOM MAX MIN NOM MAX

VCC Supply voltage 2 5 6 2 5 6 V

VIH High-level input voltage

VCC = 2 V 1.5 1.5

VVCC = 4.5 V 3.15 3.15

VCC = 6 V 4.2 4.2

VIL Low-level input voltage

VCC = 2 V 0.5 0.5

VVCC = 4.5 V 1.35 1.35

VCC = 6 V 1.8 1.8

VIInput voltage 0 VCC 0 VCC V

VOOutput voltage 0 VCC 0 VCC V

Δt/Δv Input transition rise or fall time(2)

VCC = 2 V 1000 1000

nsVCC = 4.5 V 500 500

VCC = 6 V 400 400

TAOperating free-air temperature –55 125 –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,

Implications of Slow or Floating CMOS Inputs, SCBA004.

(2) If this device is used in the threshold region (from VILmax = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state

from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;

however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

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6.4 Thermal Information

THERMAL METRIC(1)

SN74HC595

UNITD (SOIC) DB (SSOP) DW (SOIC) N (PDIP) NS (SO) PW

(TSSOP)

16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 73 82 57 67 64 108 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC

TA = 25°C SN54HC595 SN74HC595 UNIT

MIN TYP MAX MIN MAX MIN MAX

VOH VI = VIH or VIL

IOH = –20 μA

2 V 1.9 1.998 1.9 1.9

4.5 V 4.4 4.499 4.4 4.4

6 V 5.9 5.999 5.9 5.9

QH′, IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84

QA – QH, IOH = –6 mA 3.98 4.3 3.7 3.84

QH′, IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34

QA – QH, IOH = –7.8 mA 5.48 5.8 5.2 5.34

VOL VI = VIH or VIL

IOL = 20 μA

2 V 0.002 0.1 0.1 0.1

4.5 V 0.001 0.1 0.1 0.1

6 V 0.001 0.1 0.1 0.1

QH′, IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33

QA – QH, IOL = 6 mA 0.17 0.26 0.4 0.33

QH′, IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33

QA – QH, IOL = 7.8 mA 0.15 0.26 0.4 0.33

IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA

IOZ VO = VCC or 0, QA – QH6 V ±0.01 ±0.5 ±10 ±5 µA

ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA

2 V to

6 V 3 10 10 10 pF

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6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

VCC

TA = 25°C SN54HC595 SN74HC595 UNIT

MIN MAX MIN MAX MIN MAX

fclock Clock frequency

2 V 6 4.2 5

MHz4.5 V 31 21 25

6 V 36 25 29

twPulse duration

SRCLK or RCLK high or low

2 V 80 120 100

4.5 V 16 24 20

6 V 14 20 17

SRCLR low

2 V 80 120 100

4.5 V 16 24 20

6 V 14 20 17

tsu Set-up time

SER before SRCLK↑

2 V 100 150 125

4.5 V 20 30 25

6 V 17 25 21

SRCLK↑ before RCLK↑(1)

2 V 75 113 94

4.5 V 15 23 19

6 V 13 19 16

SRCLR low before RCLK↑

2 V 50 75 65

4.5 V 10 15 13

6 V 9 13 11

SRCLR high (inactive) before SRCLK↑

2 V 50 75 60

4.5 V 10 15 12

6 V 9 13 11

thHold time, SER after SRCLK↑

2 V 0 0 0

ns4.5 V 0 0 0

6 V 0 0 0

(1) This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case

the shift register is one clock pulse ahead of the storage register.

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SRCLK

SER

RCLK

SRCLR

QH’

implies that the output is in 3-State mode.NOTE:

Figure 6-1. Timing Diagram

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6.7 Switching Characteristics

Over recommended operating free-air temperature range.

PARAMETER FROM

(INPUT)

(OUTPUT)

LOAD

CAPACITANCE VCC

TA = 25°C SN54HC595 SN74HC595 UNIT

MIN TYP MAX MIN MAX MIN MAX

fmax 50 pF

2 V 6 26 4.2 5

MHz4.5 V 31 38 21 25

6 V 36 42 25 29

tpd

SRCLK QH′ 50 pF

2 V 50 160 240 200

4.5 V 17 32 48 40

6 V 14 27 41 34

RCLK QA – QH50 pF

2 V 50 150 225 187

4.5 V 17 30 45 37

6 V 14 26 38 32

tPHL SRCLR QH′ 50 pF

2 V 51 175 261 219

ns4.5 V 18 35 52 44

6 V 15 30 44 37

ten OE QA – QH50 pF

2 V 40 150 255 187

ns4.5 V 15 30 45 37

6 V 13 26 38 32

tdis OE QA – QH50 pF

2 V 42 200 300 250

ns4.5 V 23 40 60 50

6 V 20 34 51 43

QA – QH50 pF

2 V 28 60 90 75

4.5 V 8 12 18 15

6 V 6 10 15 13

QH′ 50 pF

2 V 28 75 110 95

4.5 V 8 15 22 19

6 V 6 13 19 16

tpd RCLK QA – QH150 pf

2 V 60 200 300 250

ns4.5 V 22 40 60 50

6 V 19 34 51 43

ten OE QA – QH150 pf

2 V 70 200 298 250

ns4.5 V 23 40 60 50

6 V 19 34 51 43

ttQA – QH150 pf

2 V 45 210 315 265

ns4.5 V 17 42 63 53

6 V 13 36 53 45

6.8 Operating Characteristics

TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance No load 400 pF

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6.9 Typical Characteristics

0 1 2 3 4 5 6

VCC(V)

ICC(nA)

-5

OUTPUTS = µ+,¶

OE = µ/2:¶

Figure 6-2. SN74HC595 ICC vs. VCC

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7 Parameter Measurement Information

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

tsu

50%

50%50% 10%10%

90% 90%

VCC

0 V

trtf

Reference

Input

Data

Input

50%

High-Level

Pulse 50%

VCC

0 V

50% 50%

VCC

0 V

Low-Level

Pulse

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

50%50% 10%10%

90% 90%

VCC

VOH

VOL

0 V

trtf

Input

In-Phase

Output

50%

tPLH tPHL

50% 50%

10% 10%

90%90% VOH

VOL

tPHL tPLH

Out-of-

Phase

Output

50%

10%

90%

VCC

≈VCC

VOL

0 V

Output

Control

(Low-Level

Enabling)

Output

Waveform 1

(See Note B)

50%

tPZL tPLZ

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

VOH

≈0 V

50%

tPZH tPHZ

Output

Waveform 2

(See Note B)

≈VCC

Test

Point

From Output

Under Test

VCC

LOAD CIRCUIT

PARAMETER CL

tPZH

tpd or tt

tdis

ten tPZL

tPHZ

tPLZ

1 kΩ

50 pF

150 pF

50 pF

Open Closed

RLS1

Closed Open

Open Closed

Closed Open

50 pF

150 pF

Open Open

NOTES: A. CLincludes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤1 MHz, ZO= 50 Ω, tr= 6 ns, tf= 6 ns.

D. For clock inputs, fmax is measured when the input duty cycle is 50%.

E. The outputs are measured one at a time, with one input transition per measurement.

F. tPLZ and tPHZ are the same as tdis.

G. tPZL and tPZH are the same as ten.

H. tPLH and tPHL are the same as tpd.

(see Note A)

Figure 7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The SNx4HC595 is part of the HC family of logic devices intended for CMOS applications. The SNx4HC595 is

an 8-bit shift register that feeds an 8-bit D-type storage register.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both

clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

8.2 Functional Block Diagram

QH′

SRCLR

RCLK

SRCLK

SER

Pin numbers shown are for the D, DB, DW, J, N, NS, PW, and W packages.

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8.3 Feature Description

The SNx4HC595 devices are 8-bit Serial-In, Parallel-Out Shift Registers. They have a wide operating current of

2 V to 6 V, and the high-current 3-state outputs can drive up to 15 LSTTL Loads. The devices have a low power

consumption of 80-μA (Maximum) ICC. Additionally, the devices have a low input current of 1 μA (Maximum) and

a ±6-mA Output Drive at 5 V.

8.4 Device Functional Modes

Table 8-1 lists the functional modes of the SNx4HC595 devices.

Table 8-1. Function Table

INPUTS FUNCTION

SER SRCLK SRCLR RCLK OE

X X X X H Outputs QA – QH are disabled.

X X X X L Outputs QA – QH are enabled.

X X L X X Shift register is cleared.

L ↑ H X X

First stage of the shift register goes low.

Other stages store the data of previous stage,

respectively.

H ↑ H X X

First stage of the shift register goes high.

Other stages store the data of previous stage,

respectively.

X X X ↑ X Shift-register data is stored in the storage register.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The SNx4HC595 is a low-drive CMOS device that can be used for a multitude of bus interface type applications

where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on

the outputs.

9.2 Typical Application

Controller

SRCLR

SRCLK

RCLK

SER

VCC

0.1 F

GND

7QH

9Q+¶

560 

+5V

Figure 9-1. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because

it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads

so routing and load conditions should be considered to prevent ringing.

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9.2.2 Detailed Design Procedure

• Recommended input conditions

– Specified high and low levels. See (VIH and VIL) in Section 6.3 table.

– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC

• Recommend output conditions

– Load currents should not exceed 35 mA per output and 70 mA total for the part

– Outputs should not be pulled above VCC

9.2.3 Application Curves

0 2 468

VCC(V)

tpd(ns)

Figure 9-2. SN75HC595 tpd vs. VCC

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in

Section 6.3 table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each

power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and

a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple-bit logic devices, inputs should never float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two

inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not

be left unconnected because the undefined voltages at the outside connections result in undefined operational

states. Figure 11-1 specifies the rules that must be observed under all circumstances. All unused inputs of digital

logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should

be applied to any particular unused input depends on the function of the device. Generally they will be tied to

GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,

unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the

part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.

11.2 Layout Example

Vcc

Unused Input

Input

Output

Input

Unused Input Output

Figure 11-1. Layout Diagram

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Implications of Slow or Floating CMOS Inputs application brief

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser based versions of this data sheet, refer to the left hand navigation.

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I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-86816012A ACTIVE LCCC FK 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-

86816012A

SNJ54HC

595FK

5962-8681601EA ACTIVE CDIP J 16 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8681601EA

SNJ54HC595J

5962-8681601VEA ACTIVE CDIP J 16 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8681601VE

SNV54HC595J

5962-8681601VFA ACTIVE CFP W 16 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8681601VF

SNV54HC595W

SN54HC595J ACTIVE CDIP J 16 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 SN54HC595J

SN74HC595D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DBRE4 ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DBRG4 ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DRE4 ACTIVE SOIC D 16 2500 TBD Call TI Call TI -40 to 85

SN74HC595DRG3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN74HC595DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DWRE4 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595DWRG4 ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -40 to 85 SN74HC595N

SN74HC595NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC595N

SN74HC595NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC595

SN74HC595PWRE4 ACTIVE TSSOP PW 16 2000 TBD Call TI Call TI -40 to 85

SN74HC595PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC595

SNJ54HC595FK ACTIVE LCCC FK 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-

86816012A

SNJ54HC

595FK

SNJ54HC595J ACTIVE CDIP J 16 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8681601EA

SNJ54HC595J

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 14-Aug-2021

Addendum-Page 3

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC595, SN54HC595-SP, SN74HC595 :

•Catalog : SN74HC595, SN54HC595

•Enhanced Product : SN74HC595-EP, SN74HC595-EP

•Military : SN54HC595

•Space : SN54HC595-SP

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Width onhe carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O D O O D O iSDrOckethes —> User Dtrecllnn 0' Feed \i/ Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74HC595DBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

SN74HC595DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1

SN74HC595DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

SN74HC595DRG3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1

SN74HC595DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

SN74HC595DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

SN74HC595DWRG4 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

SN74HC595NSR SO NS 16 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1

SN74HC595NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

SN74HC595PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

SN74HC595PWR TSSOP PW 16 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1

SN74HC595PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

SN74HC595PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Mar-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74HC595DBR SSOP DB 16 2000 853.0 449.0 35.0

SN74HC595DR SOIC D 16 2500 364.0 364.0 27.0

SN74HC595DR SOIC D 16 2500 853.0 449.0 35.0

SN74HC595DRG3 SOIC D 16 2500 364.0 364.0 27.0

SN74HC595DRG4 SOIC D 16 2500 853.0 449.0 35.0

SN74HC595DRG4 SOIC D 16 2500 340.5 336.1 32.0

SN74HC595DWR SOIC DW 16 2000 350.0 350.0 43.0

SN74HC595DWRG4 SOIC DW 16 2000 350.0 350.0 43.0

SN74HC595NSR SO NS 16 2000 853.0 449.0 35.0

SN74HC595NSR SO NS 16 2000 367.0 367.0 38.0

SN74HC595PWR TSSOP PW 16 2000 364.0 364.0 27.0

SN74HC595PWR TSSOP PW 16 2000 366.0 364.0 50.0

SN74HC595PWR TSSOP PW 16 2000 853.0 449.0 35.0

SN74HC595PWRG4 TSSOP PW 16 2000 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Mar-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

5962-86816012A FK LCCC 20 1 506.98 12.06 2030 NA

5962-8681601EA J CDIP 16 1 506.98 15.24 13440 NA

5962-8681601VEA J CDIP 16 1 506.98 15.24 13440 NA

5962-8681601VFA W CFP 16 1 506.98 26.16 6220 NA

SN74HC595D D SOIC 16 40 507 8 3940 4.32

SN74HC595D D SOIC 16 40 506.6 8 3940 4.32

SN74HC595DE4 D SOIC 16 40 506.6 8 3940 4.32

SN74HC595DE4 D SOIC 16 40 507 8 3940 4.32

SN74HC595DG4 D SOIC 16 40 507 8 3940 4.32

SN74HC595DG4 D SOIC 16 40 506.6 8 3940 4.32

SN74HC595DW DW SOIC 16 40 506.98 12.7 4826 6.6

SN74HC595N N PDIP 16 25 506 13.97 11230 4.32

SN74HC595N N PDIP 16 25 506.1 9 600 5.4

SN74HC595N N PDIP 16 25 506 13.97 11230 4.32

SN74HC595NE4 N PDIP 16 25 506.1 9 600 5.4

SN74HC595NE4 N PDIP 16 25 506 13.97 11230 4.32

SN74HC595PW PW TSSOP 16 90 530 10.2 3600 3.5

SNJ54HC595FK FK LCCC 20 1 506.98 12.06 2030 NA

SNJ54HC595J J CDIP 16 1 506.98 15.24 13440 NA

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Mar-2022

Pack Materials-Page 3

www.ti.com

PACKAGE OUTLINE

8.2

7.4 TYP

14X 1.27

16X 0.51

0.35

8.89

0.15 TYP

0 - 10

0.3

0.1

2.00 MAX

(1.25)

0.25

GAGE PLANE

1.05

0.55

10.4

10.0

NOTE 3

B5.4

5.2

NOTE 4

4220735/A 12/2021

SOP - 2.00 mm max heightNS0016A

SOP

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

116

0.25 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.500

£353 RE Vi“““‘ ““““““ WEECE = Era ,MQL 1"

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

14X (1.27)

(R0.05) TYP

(7)

16X (1.85)

16X (0.6)

4220735/A 12/2021

SOP - 2.00 mm max heightNS0016A

SOP

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

SCALE:7X

SYMM

SEE

DETAILS

SYMM

Eﬁmﬁﬁj v¢\‘\‘\‘\

www.ti.com

EXAMPLE STENCIL DESIGN

(7)

(R0.05) TYP

16X (1.85)

16X (0.6)

14X (1.27)

4220735/A 12/2021

SOP - 2.00 mm max heightNS0016A

SOP

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:7X

SYMM

MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" ﬂﬂﬂﬂﬂﬂ\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qﬁjrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiﬂﬁiﬂﬁzj="" vvwwttﬂﬂ="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">

MECHANICAL DATA D ( *"iﬁ O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nﬂhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm ﬁsh. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: ﬂash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com

LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eiﬂ{iEr-Hﬂ-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com

www.ti.com

PACKAGE OUTLINE

14X 0.65

4.55

16X 0.30

0.19

TYP

6.6

6.2

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

NOTE 4

4.5

4.3

NOTE 3

5.1

4.9

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.500

v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

YL““‘+““‘ ﬁmmamﬂ J

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jﬁ/—\ % lgLLLLLiLLL/ﬁif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom ﬂash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m

www.ti.com

GENERIC PACKAGE VIEW

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

SOIC - 2.65 mm max heightDW 16

SMALL OUTLINE INTEGRATED CIRCUIT

7.5 x 10.3, 1.27 mm pitch

4224780/A

www.ti.com

PACKAGE OUTLINE

TYP

10.63

9.97

2.65 MAX

14X 1.27

16X 0.51

0.31

8.89

TYP

0.33

0.10

0 - 8 0.3

0.1

(1.4)

0.25

GAGE PLANE

1.27

0.40

NOTE 3

10.5

10.1

NOTE 4

7.6

7.4

4220721/A 07/2016

SOIC - 2.65 mm max heightDW0016A

SOIC

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

116

0.25 C A B

PIN 1 ID

AREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.500

£3ng

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

(9.3)

14X (1.27)

R0.05 TYP

16X (2)

16X (0.6)

4220721/A 07/2016

SOIC - 2.65 mm max heightDW0016A

SOIC

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

LAND PATTERN EXAMPLE

SCALE:7X

SYMM

SEE

DETAILS

SYMM

Egg e %

www.ti.com

EXAMPLE STENCIL DESIGN

R0.05 TYP

16X (2)

16X (0.6)

14X (1.27)

(9.3)

4220721/A 07/2016

SOIC - 2.65 mm max heightDW0016A

SOIC

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:7X

SYMM

MECHANICAL DATA W (R—GDFP—FWB) CERAM‘C DUAL FLATPACK Base and Seaﬁng Piane 0045 (114) “85 (7-24) I 0.020 (0156) 0.245 (6.22) f I: i i i 0.008 0.20 _ 0.080 2.03) 0.004 (0,i0) 0,055 1.40 47 0,305 (7.75) MAX 4» 0.019 0,48 1 ‘6 i 0.0i5 $0.35; I::I I: T I::I I::I I: :1 3 C I: :1 0430 (i092 : I: 0.370 (9.40) :I I: I: :1 [:3 |::l [:3 |::l “-005 (0-13) MW 4 Piaces [:3 I: i 8 9 T 0350 (9.14) 0.360 (9.14) 0.250 (0.35) 0,250 (6.35) 404018073/F 04/14 NOTES: A. Ail iinsar dimensions are in inches (miiiinisieis). inis drawing is subjeci io cnange wiinoui noiice. This package can be henneiicaiiy seaied Min 0 ceramic Ii'd using glass irit. index point is provided on cap (or lerminai identification oniy. rails wiinin MiL STD i035 00mins r0909? i TEXAS INSTRUMENTS www.mmm

J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass ﬂ ﬂ m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120

oo A‘ioyi 55 ﬁHHHHHHHHHHHHﬁ {'3 TEXAS INSTRUMENTS

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘ﬁ: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): noﬁce /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmﬂder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkﬂh INSI'RUMENTS www.1i.com

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