SN54HC00, SN74HC00 Datasheet by Texas Instruments

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SNx4HC00 Quadruple 2-Input NAND Gates
1 Features
Buffered inputs
Wide operating voltage range: 2 V to 6 V
Wide operating temperature range:
–40°C to +85°C
Supports fanout up to 10 LSTTL loads
Significant power reduction compared to LSTTL
logic ICs
2 Applications
Alarm / tamper detect circuit
S-R latch
3 Description
This device contains four independent 2-input NAND
Gates. Each gate performs the Boolean function
Y = A ● B in positive logic.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN74HC00D SOIC (14) 8.70 mm × 3.90 mm
SN74HC00DB SSOP (14) 6.50 mm × 5.30 mm
SN74HC00N PDIP (14) 19.30 mm × 6.40 mm
SN74HC00NS SO (14) 10.20 mm × 5.30 mm
SN74HC00PW TSSOP (14) 5.00 mm × 4.40 mm
SN54HC00FK LCCC (20) 8.90 mm × 8.90 mm
SN54HC00J CDIP (14) 21.30 mm × 7.60 mm
SN54HC00W CFP (14) 9.20 mm × 6.29 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
2
3
7
4
5
6
14
13
12
8
11
10
9
1A
1B
1Y
2A
2B
2Y
GND
4B
4A
4Y
3B
3A
VCC
3Y
Device Functional Pinout
SN74HC00, SN54HC00
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics - Commercial (74xx) .......... 5
6.6 Electrical Characteristics - Military (54xx) .................. 6
6.7 Switching Characteristics - Commercial (74xx) ......... 6
6.8 Switching Characteristics - Military (54xx) ................. 6
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Balanced CMOS Push-Pull Outputs........................... 9
8.4 Standard CMOS Inputs...............................................9
8.5 Clamp Diode Structure................................................9
8.6 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................14
11 Layout........................................................................... 14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 Receiving Notification of Documentation Updates..15
12.3 Support Resources................................................. 15
12.4 Trademarks.............................................................15
12.5 Electrostatic Discharge Caution..............................15
12.6 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2021) to Revision H (August 2021) Page
Increased D and PW package thermal values...................................................................................................5
Changes from Revision F (July 2016) to Revision G (January 2021) Page
Updated to new data sheet format......................................................................................................................1
Updated D and PW package thermals to new standards................................................................................... 5
Changes from Revision E (August 2003) to Revision F (July 2016) Page
Added Applications section, Device Information table, ESD Ratings table, Typical Characteristics section,
Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.............................................................................. 1
Added Military Disclaimer to Features list...........................................................................................................1
Removed Ordering Information table; see POA at the end of data sheet.......................................................... 1
Changed values in the Thermal Information table to align with JEDEC standards............................................ 5
Deleted Operating Characteristics table; moved Cpd row to Electrical Characteristics .................................... 5
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5 Pin Configuration and Functions
1
2
3
7
4
5
6
14
13
12
8
11
10
9
1A
1B
1Y
2A
2B
2Y
GND
4B
4A
4Y
3B
3A
VCC
3Y
D, DB, N, NS, PW, J, or W Package
14-Pin SOIC, SSOP, PDIP, SO, TSSOP, CDIP, or CFP
Top View
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Y
NC
2A
NC
2B
1B 1A NC VCC 4B
2Y GND NC 3Y 3A
4A
NC
4Y
NC
3B
FK Package
20-Pin LCCC
Top View
Table 5-1. Pin Functions
PIN
I/O DESCRIPTION
NAME
D, DB, N,
NS, PW, J,
or W
FK
1A 1 2 Input Channel 1, Input A
1B 2 3 Input Channel 1, Input B
1Y 3 4 Output Channel 1, Output Y
2A 4 6 Input Channel 2, Input A
2B 5 8 Input Channel 2, Input B
2Y 6 9 Output Channel 2, Output Y
3A 9 13 Input Channel 3, Input A
3B 10 14 Input Channel 3, Input B
3Y 8 12 Output Channel 3, Output Y
4A 12 18 Input Channel 4, Input A
4B 13 19 Input Channel 4, Input B
4Y 11 16 Output Channel 4, Output Y
GND 7 10 — Ground
NC 1, 5, 7, 11, 15,
17 Not internally connected
VCC 14 20 Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < –0.5 V or VI > VCC +
0.5 V ±20 mA
IOK Output clamp current(2) VO < –0.5 V or VO > VCC +
0.5 V ±20 mA
IOContinuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature(3) 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VIH High-level input voltage
VCC = 2 V 1.5
VVCC = 4.5 V 3.15
VCC = 6 V 4.2
VIL Low-level input voltage
VCC = 2 V 0.5
VVCC = 4.5 V 1.35
VCC = 6 V 1.8
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
ttInput transition rise and fall time
VCC = 2 V 1000
nsVCC = 4.5 V 500
VCC = 6 V 400
TAOperating free-air temperature SN54HC00 –55 125 °C
SN74HC00 –40 85
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6.4 Thermal Information
THERMAL METRIC(1)
SN74HC00
UNITD (SOIC) DB (SSOP) N (PDIP) NS (SOP) PW (TSSOP)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA
Junction-to-ambient thermal
resistance 133.6 108.3 57.5 91.0 151.7 °C/W
Rθ
JC(top)
Junction-to-case (top) thermal
resistance 89.0 60.3 45.1 48.8 79.4 °C/W
RθJB
Junction-to-board thermal
resistance 89.5 55.7 37.3 49.8 94.7 °C/W
ΨJT
Junction-to-top characterization
parameter 45.5 25 30.3 18.4 25.2 °C/W
ΨJB
Junction-to-board
characterization parameter 89.1 55.2 37.2 49.5 94.1 °C/W
Rθ
JC(bot)
Junction-to-case (bottom)
thermal resistance N/A N/A N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics - Commercial (74xx)
over operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER TEST CONDITIONS VCC
Operating free-air temperature (TA)
UNIT25°C -40°C to 85°C
MIN TYP MAX MIN TYP MAX
VOH
High-level
output voltage
VI = VIH
or VIL
IOH = -20 µA
2 V 1.9 1.998 1.9
V
4.5 V 4.4 4.499 4.4
6 V 5.9 5.999 5.9
IOH = -4 mA 4.5 V 3.98 4.3 3.84
IOH = -5.2 mA 6 V 5.48 5.8 5.34
VOL
Low-level output
voltage
VI = VIH
or VIL
IOL = 20 µA
2 V 0.002 0.1 0.1
V
4.5 V 0.001 0.1 0.1
6 V 0.001 0.1 0.1
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.33
II
Input leakage
current VI = VCC or 0 6 V ±0.1 ±100 ±1000 µA
ICC Supply current VI = VCC
or 0 VI = VCC or 0 6 V 2 20 µA
Ci
Input
capacitance 2 V to 6 V 3 10 10 pF
Cpd
Power
dissipation
capacitance per
gate
No load 2 V to 6 V 20 pF
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
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6.6 Electrical Characteristics - Military (54xx)
over operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER TEST CONDITIONS VCC
Operating free-air temperature (TA)
UNIT25°C -55°C to 125°C
MIN TYP MAX MIN TYP MAX
VOH
High-level
output voltage
VI = VIH
or VIL
IOH = -20 µA
2 V 1.9 1.998 1.9
V
4.5 V 4.4 4.499 4.4
6 V 5.9 5.999 5.9
IOH = -4 mA 4.5 V 3.98 4.3 3.7
IOH = -5.2 mA 6 V 5.48 5.8 5.2
VOL
Low-level output
voltage
VI = VIH
or VIL
IOL = 20 µA
2 V 0.002 0.1 0.1
V
4.5 V 0.001 0.1 0.1
6 V 0.001 0.1 0.1
IOL = 4 mA 4.5 V 0.17 0.26 0.4
IOL = 5.2 mA 6 V 0.15 0.26 0.4
II
Input leakage
current VI = VCC or 0 6 V ±0.1 ±100 ±1000 nA
ICC Supply current VI = VCC
or 0 VI = VCC or 0 6 V 2 40 µA
Ci
Input
capacitance 2 V to 6 V 3 10 10 pF
Cpd
Power
dissipation
capacitance per
gate
No load 2 V to 6 V 20 pF
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
6.7 Switching Characteristics - Commercial (74xx)
over operating free-air temperature range (unless otherwise noted)
PARAMETER FROM TO VCC
Operating free-air temperature (TA)
UNIT25°C –40°C to 85°C
MIN TYP MAX MIN TYP MAX
tpd Propagation delay A or B Y
2 V 45 90 115
ns4.5 V 9 18 23
6 V 8 15 20
ttTransition-time Y
2 V 38 75 95
ns4.5 V 8 15 19
6 V 6 13 16
6.8 Switching Characteristics - Military (54xx)
over operating free-air temperature range (unless otherwise noted)
PARAMETER FROM TO VCC
Operating free-air temperature (TA)
UNIT25°C –55°C to 125°C
MIN TYP MAX MIN TYP MAX
tpd Propagation delay A or B Y
2 V 45 90 135
ns4.5 V 9 18 27
6 V 8 15 23
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over operating free-air temperature range (unless otherwise noted)
PARAMETER FROM TO VCC
Operating free-air temperature (TA)
UNIT25°C –55°C to 125°C
MIN TYP MAX MIN TYP MAX
ttTransition-time Y
2 V 38 75 110
ns4.5 V 8 15 22
6 V 6 13 19
6.9 Typical Characteristics
TA = 25°C
IOH Output High Current (mA)
VOH Output High Voltage (V)
0 1 2 3 4 5 6
0
1
2
3
4
5
6
7
2-V
4.5-V
6-V
Figure 6-1. Typical Output Voltage in the High State (VOH)
IOL Output Low Current (mA)
VOL Output Low Voltage (V)
0 1 2 3 4 5 6
0
0.05
0.1
0.15
0.2
0.25
0.3
2-V
4.5-V
6-V
Figure 6-2. Typical Output Voltage in the Low State (VOL)
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
CL(1)
From Output
Under Test
Test
Point
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
50%Input 50%
VCC
0 V
50% 50%
VOH
VOL
tPLH(1) tPHL(1)
VOH
VOL
tPHL(1) tPLH(1)
Output
Output 50% 50%
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms Propagation Delays
VOH
VOL
Output
VCC
0 V
Input
tf(1)
tr(1)
90%
10%
90%
10%
tr(1)
90%
10%
tf(1)
90%
10%
(1) The greater between tr and tf is the same as tt.
Figure 7-3. Voltage Waveforms, Input and Output Transition Times
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8 Detailed Description
8.1 Overview
This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B
in positive logic.
8.2 Functional Block Diagram
8.3 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.4 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst
case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated
at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can
be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
8.5 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
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GND
Logic
Input Output
VCC
Device
-IIK
+IIK +IOK
-IOK
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.6 Device Functional Modes
Table 8-1. Function Table
INPUTS OUTPUT
A B Y
H H L
L X H
X L H
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the SN74HC00 is used to create an active-low SR latch. The two additional gates can be
used for a second active-low SR latch, individually used for their logic function, or the inputs can be grounded
and both channels left unused. This device is used to drive the tamper indicator LED and provide one bit of
data to the system controller. When the tamper switch outputs LOW, the output Q becomes HIGH. This output
remains HIGH until the system controller addresses the event and sends a LOW signal to the R input which
returns the Q output back to LOW.
9.2 Typical Application
System
Controller
Tamper
Switch
R
S
Q
R1
Tamper
Indicato r
R2
Figure 9-1. Typical Application Diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HC00 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HC00 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current
required for switching. The logic device can only sink as much current as can be sunk into its ground connection.
Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
The SN74HC00 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the
data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50
pF.
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The SN74HC00 can drive a load with total resistance described by RL VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HC00, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The SN74HC00 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
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9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC00
to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
Q
R
S
Figure 9-2. Application Timing Diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
0.1 F Bypass capacitor
placed close to the
device
Avoid 90°
corners for
signal lines
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused input
tied to GND
VCC
2A1
Unused output
left floating
GND
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
1OE
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
1 20
10 11
2
3
4
5
6
7
8
9 12
13
14
15
16
17
18
19
GNDVCC
GND
Figure 11-1. Example layout for the SN74HC00 in the RKS Package
SN74HC00, SN54HC00
SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021 www.ti.com
14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC00 SN54HC00
l TEXAS INSTRUMENTS
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E support forums are an engineer's go-to source for fast, verified answers and design help straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com
SN74HC00, SN54HC00
SCLS181H – DECEMBER 1982 – REVISED AUGUST 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15
Product Folder Links: SN74HC00 SN54HC00
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8403701VCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8403701VC
A
SNV54HC00J
5962-8403701VDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8403701VD
A
SNV54HC00W
84037012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 84037012A
SNJ54HC
00FK
8403701CA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8403701CA
SNJ54HC00J
8403701DA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8403701DA
SNJ54HC00W
JM38510/65001B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65001B2A
JM38510/65001BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65001BCA
JM38510/65001BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65001BDA
M38510/65001B2A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65001B2A
M38510/65001BCA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65001BCA
M38510/65001BDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65001BDA
SN54HC00J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN54HC00J
SN74HC00D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC00DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00DTE4 ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00DTG4 ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -40 to 85 SN74HC00N
SN74HC00NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC00N
SN74HC00NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SN74HC00PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC00
SNJ54HC00FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 84037012A
SNJ54HC
00FK
SNJ54HC00J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8403701CA
SNJ54HC00J
SNJ54HC00W ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8403701DA
SNJ54HC00W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2021
Addendum-Page 3
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC00, SN54HC00-SP, SN74HC00 :
Catalog : SN74HC00, SN54HC00
Automotive : SN74HC00-Q1, SN74HC00-Q1
Military : SN54HC00
Space : SN54HC00-SP
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2021
Addendum-Page 4
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter A0 Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 w Overau Width onhe carrier tape i P1 Pitch between successive cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O D O O D O SprocketHotes ,,,,,,,,,,, ‘ User Dtrecllon 0' Feed Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC00DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC00DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC00DR SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC00DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC00DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC00DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC00DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC00NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC00PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC00PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC00PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1
SN74HC00PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC00PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC00DBR SSOP DB 14 2000 853.0 449.0 35.0
SN74HC00DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC00DR SOIC D 14 2500 366.0 364.0 50.0
SN74HC00DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC00DRG4 SOIC D 14 2500 340.5 336.1 32.0
SN74HC00DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC00DT SOIC D 14 250 210.0 185.0 35.0
SN74HC00NSR SO NS 14 2000 853.0 449.0 35.0
SN74HC00PWR TSSOP PW 14 2000 853.0 449.0 35.0
SN74HC00PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74HC00PWR TSSOP PW 14 2000 366.0 364.0 50.0
SN74HC00PWRG4 TSSOP PW 14 2000 853.0 449.0 35.0
SN74HC00PWT TSSOP PW 14 250 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width $ — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8403701VDA W CFP 14 1 506.98 26.16 6220 NA
84037012A FK LCCC 20 1 506.98 12.06 2030 NA
JM38510/65001B2A FK LCCC 20 1 506.98 12.06 2030 NA
M38510/65001B2A FK LCCC 20 1 506.98 12.06 2030 NA
SN74HC00D D SOIC 14 50 506.6 8 3940 4.32
SN74HC00D D SOIC 14 50 507 8 3940 4.32
SN74HC00DE4 D SOIC 14 50 507 8 3940 4.32
SN74HC00DE4 D SOIC 14 50 506.6 8 3940 4.32
SN74HC00DG4 D SOIC 14 50 506.6 8 3940 4.32
SN74HC00DG4 D SOIC 14 50 507 8 3940 4.32
SN74HC00N N PDIP 14 25 506 13.97 11230 4.32
SN74HC00N N PDIP 14 25 506.1 9 600 5.4
SN74HC00N N PDIP 14 25 506 13.97 11230 4.32
SN74HC00NE4 N PDIP 14 25 506.1 9 600 5.4
SN74HC00NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC00NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC00PW PW TSSOP 14 90 530 10.2 3600 3.5
SNJ54HC00FK FK LCCC 20 1 506.98 12.06 2030 NA
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Mar-2022
Pack Materials-Page 3
MECHANICAL DATA W (R—GDFP—F14) CERAM‘C DUAL FLATPACK Ease and Seating Wane 0.250 (6.60) 00‘5 (W) 0235 (5.97) f 0. 026 (0 as) ‘ ‘ 0.005 0.20 _ 00 2.03) 0.004 (0.10) 0,045 1.14 47 0,280 (7.11) MAX 4» 0.019 0.48 1 H i 0.015 50.35; :3 I: T I: :1 :I I: 0.050 (1.27) (:3 ::I 0.390 (9 91) 7' I: :1 0.335 (0.51) :l I: 1:3 ::1 1:3 ::1 “-005 (0-13) “‘N 4 Manes 1:3 I: i 7 E f 0.560 (9.11) 0.360 (0.14) 0.250 (0.35) 0,250 (6.35) 404013072/r 01/11 NOTES: A. AH Hnear dimensions are in inches (m1111meters). B. This dram’ng 1: 5mm \0 change mm nofice. c, This package can be hermeticany sea1ed mm 0 ceramic lid usmg glass iriL 0, \ndex paint '15 pmw'ded an cap for terminm idenmcutiun omy. E. Faus within M1L STD 1835 GDFPW’FH i TEXAS INSTRUMENTS www.mmm
GENERIC PACKAGE VIEW J 14 CDIP - 5.08 mm max heigm CERAMIC DUAL IN LINE PACKAGE [I l l 'I I.“ Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the produd dala sheel for package details. 4040053756 I TEXAS INSTRI IMFNTS
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
fi©©©©©©© ““w“‘¢‘w‘w““‘ ,w@@@@@@ A RLr
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA D U1 4)} 0 (3'4) DLASHC SMALL 0U ¥N¥ 4040047 5/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam AB, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {If TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (R7PDSOmGl4) PLASTlC SMALL OUTLINE Example Board Layout Sterlazlogpeulyngs (Mole c) —— <—14x0,55 -hhheb&&t="" tmedddifi§n%="" 5.40="" 5,40="" @eeeeeej="" rfihfl§eflhj="" —=""> ——l 2x1,27 Example Non Soldermask Delined Pad Example Pad Geometry (See Note c) F Example l / Solder Mask Opening 7 0 07 f (See Note E) All Armlnd ,/ tzllmss/E oa/lz NOTES: A. All linear dimensions are in millimeters. a, Tnis drawan is subject to cnonae wl'lhuul notice. c. Publlcutl’on chs7351 is recommended tor alternate desl’gns. D. Laser ctming apertures w‘lth trapezoidal walls and also roundlng comers wlll otter better paste release. Customers should contact their board assembly site for stencil design recommendations, Reter tc ch—7525 lor otner stencil recommendations. E. Customers snoola contact their ooard looricotion site lor solder musk tolerances between ond oroond signol oods. {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA "7’7 : 3‘ AST‘C SMAH CJ’ N7 HHHHHHH . . ‘7,4’ 44*, A f;—‘ NO'ES' A AH Hnec' dimensmrs c'e m m'\\me(ers Dwmens'amnq cnd tu‘erc'vcmg per ASME w 5M 1994, Tm drawer ‘5 subje», ,o "hangs wnrau: Home, Budy \evvgih ‘ues m W" Le mom Hush, pyuws‘m Ur guts Ms M exceed 0,15 each m & Rudy wde does NM Wands \Mer end flair \Mefiead 'Wclsh shaH um exceed 0‘75 each S‘de E Fa‘s WM" JEDEC M07153 MUM "\u>h, main: bus, 01 guie buns shuH {if TEXAS INSTRUMENTS www.ci.com
PW (RiPDsoicM) LAND PATTERN DATA PLASTHC SMALL OUTLINE Example Board Layout (Male 0) —>| ‘,——12x0 65 HHHHHHHi 5,60 HHHHHHHHi l“ l l l Example Non So‘dermask Defined Pad 4 x 1,60 / H l <—0,07 y/="" ah="" around="" pad="" seamelry="" (see="" nale="" c)="" solder="" mask="" opening="" (see="" note="" e)="" stencil="" 0="" en'ln="" s="" (notepd)="" ‘3="" 14x0="" 30="" h="" '«,lzxo="" 65="" ~hhhhhh~="" 5,60="" hhhhhhh—="" example="" example="" 421128472/6="" 08/15="" notes:="" ah="" h‘lneor="" dimensions="" one="" in="" rnihll'rneters.="" tn‘ls="" dvowing="" is="" subject="" lp="" change="" wltnoul="" nallee.="" publl'cotlon="" hpcjssh="" is="" recommended="" lar="" allemale="" deslgns.="" laser="" cutllng="" apertures="" wch="" tropexoidm="" walls="" and="" also="" raund‘lna="" comers="" wlll="" we!="" better="" pasle="" release="" customers="" show="" contact="" their="" board="" assembly="" sl’te="" (ov="" stenci‘="" design="" recommendations.="" reler="" to="" ”50—7525="" lur="" other="" stencl‘="" recommendotluns="" customers="" shou‘d="" contact="" their="" board="" hoercot'lon="" shte="" (or="" solder="" musk="" tolerances="" between="" and="" around="" s'lgnol="" pods.="" *1?="" tums="" instruments="" www.ti.com="">
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
oo A‘ioyi 55 fiHHHHHHHHHHHHfi {'3 TEXAS INSTRUMENTS
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
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