SN74AVCH2T45 Datasheet by Texas Instruments

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B1
DIR 5
7
A1 2
VCCA VCCB
B2
6
A2 3
18
VCCA VCCB
GND
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VCCA VCCB
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SN74AVCH2T45
SCES582H –JULY 2004–REVISED APRIL 2015
SN74AVCH2T45 2-Bit, 2-Supply, Bus Transceiver with Configurable Level-Shifting and
Translation and 3-State Outputs
1 Features 3 Description
This 2-bit non-inverting bus transceiver uses two
1• Available in the Texas Instruments NanoFree™ separate configurable power-supply rails. The A ports
Package are designed to track VCCA and accepts any supply
• VCC Isolation voltage from 1.2 V to 3.6 V. The B ports are designed
• 2-Rail Design to track VCCB and accepts any supply voltage from
1.2 V to 3.6 V. This allows for universal low-voltage
• I/Os are 4.6 V Tolerant bidirectional translation and level-shifting between
• Partial Power-Down-Mode Operation any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V
• Bus Hold on Data Inputs voltage nodes.
• Maximum Data Rates The SN74AVCH2T45 is designed for asynchronous
– 500 Mbps (1.8 V to 3.3 V) communication between two data buses. The logic
levels of the direction-control (DIR pin) input activate
– 320 Mbps (< 1.8 V to 3.3 V) either the B-port outputs or the A-port outputs. The
– 320 Mbps (Level-Shifting to 2.5 V or 1.8 V) device transmits data from the A bus to the B bus
– 280 Mbps (Level-Shifting to 1.5 V) when the B-port outputs are activated and from the B
bus to the A bus when the A-port outputs are
– 240 Mbps (Level-Shifting to 1.2 V) activated. The SN74AVCH2T45 features active bus-
• Latch-Up Performance Exceeds 100 mA Per hold circuitry, which holds unused or un-driven inputs
JESD 78, Class II at a valid logic state. TI does not recommend using
• ESD Protection Exceeds JESD 22 pull-up or pull-down resistors with the bus-hold
circuitry.
2 Applications Device Information(1)
• Smartphone PART NUMBER PACKAGE BODY SIZE (NOM)
• Servers SSOP (8) 2.95 mm × 2.80 mm
• Desktop PCs and Notebooks SN74AVCH2T45 VSSOP (8) 2.30 mm × 2.00 mm
• Other Portable Devices DSBGA (8) 1.89 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features.................................................................. 18 Parameter Measurement Information ................ 13
2 Applications ........................................................... 19 Detailed Description............................................ 14
9.1 Overview ................................................................. 14
3 Description ............................................................. 19.2 Functional Block Diagram....................................... 14
4 Revision History..................................................... 39.3 Feature Description................................................. 15
5 Description (Continued)........................................ 49.4 Device Functional Modes........................................ 15
6 Pin Configurations and Functions....................... 410 Application and Implementation........................ 16
7 Specifications......................................................... 510.1 Application Information.......................................... 16
7.1 Absolute Maximum Ratings ...................................... 510.2 Typical Applications .............................................. 16
7.2 ESD Ratings.............................................................. 511 Power Supply Recommendations ..................... 20
7.3 Recommended Operating Conditions ...................... 612 Layout................................................................... 20
7.4 Thermal Information.................................................. 712.1 Layout Guidelines ................................................. 20
7.5 Electrical Characteristics .......................................... 712.2 Layout Example .................................................... 20
7.6 Switching Characteristics: VCCA = 1.2 V................... 813 Device and Documentation Support ................. 21
7.7 Switching Characteristics: VCCA = 1.5 V .................. 913.1 Documentation Support ....................................... 21
7.8 Switching Characteristics: VCCA = 1.8 V................. 10 13.2 Trademarks........................................................... 21
7.9 Switching Characteristics: VCCA = 2.5 V................. 10 13.3 Electrostatic Discharge Caution............................ 21
7.10 Switching Characteristics: VCCA = 3.3 V............... 11 13.4 Glossary................................................................ 21
7.11 Operating Characteristics...................................... 11
7.12 Typical Characteristics.......................................... 12 14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
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4 Revision History
Changes from Revision G (April 2015) to Revision H Page
• Added additional applications................................................................................................................................................. 1
• Updated Overview section. .................................................................................................................................................. 14
• Updated Layout Guidelines section. .................................................................................................................................... 20
Changes from Revision F (November 2007) to Revision G Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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4
3
2
1
5
6
7
8
GND
A2
A1
VCCA
DIR
B2
B1
VCCB
D1 D2
C2C1
B1 B2
A1 A2
1
2
3
4
8
7
6
5
VCCA
A1
A2
GND
VCCB
B1
B2
DIR
SN74AVCH2T45
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5 Description (Continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. The VCC isolation feature
ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold
circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. NanoFree package technology is
a major breakthrough in IC packaging concepts, using the die as the package.
6 Pin Configurations and Functions
DCT and DCU Packages
8-Pin SSOP and VSSOP
Top View
YZP Package
8-Pin DSBGA
Bottom View
Pin Functions
PIN
DESCRIPTION
SSOP,
NAME DSBGA
VSSOP
VCCA 1 A1 Supply Voltage A
VCCB 8 A2 Supply Voltage B
GND 4 D1 Ground
A1 2 B1 Output or input depending on state of DIR. Output level depends on VCCA.
A2 3 C1 Output or input depending on state of DIR. Output level depends on VCCA.
B1 7 B2 Output or input depending on state of DIR. Output level depends on VCCB.
B2 6 C2 Output or input depending on state of DIR. Output level depends on VCCB.
DIR 5 D2 Direction Pin, Connect to GND or to VCCA.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCCA Supply voltage –0.5 4.6 V
VCCB
I/O ports (A port) –0.5 4.6
VIInput voltage(2) I/O ports (B port) –0.5 4.6 V
Control inputs –0.5 4.6
A port –0.5 4.6
Voltage range applied to any output
VOV
in the high-impedance or power-off state(2) B port –0.5 4.6
A port –0.5 VCCA + 0.5
VOVoltage range applied to any output in the high or low state(2)(3) V
B port –0.5 VCCB + 0.5
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCCA, VCCB, or GND ±100 mA
TJJunction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
7.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000
Charged-device model (CDM), per JEDEC specification JESD22-
V(ESD) Electrostatic discharge ±1000 V
C101(2)
Machine Model (MM), Per JEDEC specification JESD22-A115-A ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
VCCI(4) VCCO(5) MIN NOM MAX UNIT
VCCA Supply voltage 1.2 3.6 V
VCCB Supply voltage 1.2 3.6 V
1.2 V to 1.95 V VCCI(4) × 0.65
High-level
VIH input Data inputs(2) 1.95 V to 2.7 V 1.6 V
voltage 2.7 V to 3.6 V 2
1.2 V to 1.95 V VCCI(4) × 0.35
Low-level
VIL input Data inputs(2) 1.95 V to 2.7 V 0.7 V
voltage 2.7 V to 3.6 V 0.8
1.2 V to 1.95 V VCCA × 0.65
High-level DIR
VIH input (referenced to 1.95 V to 2.7 V 1.6 V
voltage VCCA)(3) 2.7 V to 3.6 V 2
1.2 V to 1.95 V VCCA × 0.35
Low-level DIR
VIL input (referenced to 1.95 V to 2.7 V 0.7 V
voltage VCCA)(3) 2.7 V to 3.6 V 0.8
VIInput voltage 0 3.6 V
Active state 0 VCCO(5)
Output
VOV
voltage 3-state 0 3.6
1.2 V –3
1.4 V to 1.6 V –6
1.65 V to 1.95
IOH High-level output current –8 mA
V
2.3 V to 2.7 V –9
3 V to 3.6 V –12
1.2 V 3
1.4 V to 1.6 V 6
1.65 V to 1.95
IOL Low-level output current 8 mA
V
2.3 V to 2.7 V 9
3 V to 3.6 V 12
Δt/Δv Input transition rise or fall rate 5 ns/V
TAOperating free-air temperature –40 85 °C
(1) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,SCBA004.
(2) For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
(3) For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
(4) VCCI is the voltage associated with the input port supply VCCA or VCCB.
(5) VCCO is the voltage associated with the output port supply VCCA or VCCB.
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7.4 Thermal Information
SN74AVCH2T45
THERMAL METRIC(1) DCT (SSOP) DCU (VSSOP) YZP (DSBGA) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 194.4 199.3 105.8
RθJC(top) Junction-to-case (top) thermal resistance 124.7 76.2 1.6
RθJB Junction-to-board thermal resistance 106.8 80.6 10.8 °C/W
ψJT Junction-to-top characterization parameter 49.8 7.1 3.1
ψJB Junction-to-board characterization parameter 105.8 80.1 10.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)(1)(2)
TA= 25°C –40°C to 85°C
PARAMETER TEST CONDITIONS VCCA VCCB UNIT
MIN TYP MAX MIN TYP MAX
IOH = –100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V VCCO – 0.2
IOH = –3 mA 1.2 V 1.2 V 0.95
IOH = –6 mA 1.4 V 1.4 V 1.05
VOH(3) VI= VIH V
IOH = –8 mA 1.65 V 1.65 V 1.2
IOH = –9 mA 2.3 V 2.3 V 1.75
IOH = –12 mA 3 V 3 V 2.3
IOL = 100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V 0.2
IOL = 3 mA 1.2 V 1.2 V 0.15
IOL = 6 mA 1.4 V 1.4 V 0.35
VOL(3) VI= VIL V
IOL = 8 mA 1.65 V 1.65 V 0.45
IOL = 9 mA 2.3 V 2.3 V 0.55
IOL = 12 mA 3 V 3 V 0.7
II(3) DIR input VI= VCCA or GND 1.2 V to 3.6 V 1.2 V to 3.6 V ±0.025 ±0.25 ±1 μA
VI= 0.42 V 1.2 V 1.2 V 25
VI= 0.49 V 1.4 V 1.4 V 15
IBHL(4) VI= 0.58 V 1.65 V 1.65 V 25 μA
VI= 0.7 V 2.3 V 2.3 V 45
VI= 0.8 V 3.3 V 3.3 V 100
VI= 0.78 V 1.2 V 1.2 V –25
VI= 0.91 V 1.4 V 1.4 V –15
IBHH(5) VI= 1.07 V 1.65 V 1.65 V –25 μA
VI= 1.6 V 2.3 V 2.3 V –45
VI= 2 V 3.3 V 3.3 V –100
1.2 V 1.2 V 50
1.6 V 1.6 V 125
IBHLO(6) VI= 0 to VCC 1.95 V 1.95 V 200 μA
2.7 V 2.7 V 300
3.6 V 3.6 V 500
(1) VCCO is the voltage associated with the output port supply VCCA or VCCB.
(2) VCCI is the voltage associated with the input port supply VCCA or VCCB.
(3) VOH: Output High Voltage; VOL: Output Low Voltage; II: Control Input Current.
(4) The bus-hold circuit can sink at least the minimum low sustaining current at VIL maximum. IBHL should be measured after lowering VIN to
GND and then raising it to VIL maximum.
(5) The bus-hold circuit can source at least the minimum high sustaining current at VIH mininum. IBHH should be measured after raising VIN
to VCC and then lowering it to VIH minimum.
(6) An external driver must source at least IBHLO to switch this node from low to high.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)(1)(2)
TA= 25°C –40°C to 85°C
PARAMETER TEST CONDITIONS VCCA VCCB UNIT
MIN TYP MAX MIN TYP MAX
1.2 V 1.2 V –50
1.6 V 1.6 V –125
IBHHO(7) VI= 0 to VCC 1.95 V 1.95 V –200 μA
2.7 V 2.7 V –300
3.6 V 3.6 V –500
A port 0 V 0 V to 3.6 V ±0.1 ±1 ±5
Ioff(8) VIor VO= 0 to 3.6 V μA
B port 0 V to 3.6 V 0 V ±0.1 ±1 ±5
B port 0 V 3.6 V ±0.5 ±2.5 ±5
VO= VCCO or GND,
IOZ(8) VI= VCCI or GND
A port 3.6 V 0 V ±0.5 ±2.5 ±5 μA
1.2 V to 3.6 V 1.2 V to 3.6 V 10
ICCA(8) VI= VCCI or GND, IO= 0 0 V 3.6 V –2 μA
3.6 V 0 V 10
1.2 V to 3.6 V 1.2 V to 3.6 V 10
ICCB(8) VI= VCCI or GND, IO= 0 0 V 3.6 V 10 μA
3.6 V 0 V –2
ICCA + ICCB VI= VCCI or GND, IO= 0 1.2 V to 3.6 V 1.2 V to 3.6 V 20 μA
Control
CiVI= 3.3 V or GND 3.3 V 3.3 V 2.5 pF
inputs
Cio A or B port VI= 3.3 V or GND 3.3 V 3.3 V 6 pF
(7) An external driver must sink at least IBHHO to switch this node from high to low.
(8) Ioff: Partial Power Down Output current; IOZ: Hi-Z Output Current; ICCA: Supply A Current; ICCB: Supply B Current.
7.6 Switching Characteristics: VCCA = 1.2 V
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 7)
VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
FROM TO
PARAMETER UNIT
(INPUT) (OUTPUT) TYP TYP TYP TYP TYP
tPLH(1) 3.1 2.6 2.4 2.2 2.2
A B ns
tPHL(1) 3.1 2.6 2.4 2.2 2.2
tPLH(1) 3.4 3.1 3 2.9 2.9
B A ns
tPHL(1) 3.4 3.1 3 2.9 2.9
tPHZ(1) 5.2 5.2 5.1 5 4.8
DIR A ns
tPLZ(1) 5.2 5.2 5.1 5 4.8
tPHZ(1) 5 4 3.8 2.8 3.2
DIR B ns
tPLZ(1) 5 4 3.8 2.8 3.2
tPZH(1)(2) 8.4 7.1 6.8 5.7 6.1
DIR A ns
tPZL(1)(2) 8.4 7.1 6.8 5.7 6.1
tPZH(1)(2) 8.3 7.8 7.5 7.2 7
DIR B ns
tPZL(1)(2) 8.3 7.8 7.5 7.2 7
(1) tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
(2) The enable time is a calculated value derived using the formula shown in the Enable Times section.
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7.7 Switching Characteristics: VCCA = 1.5 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 7)
VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
VCCB = 1.2 V
FROM TO ± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 V
PARAMETER UNIT
(INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH(1) 2.8 0.7 5.4 0.5 4.6 0.4 3.7 0.3 3.5
A B ns
tPHL(1) 2.8 0.7 5.4 0.5 4.6 0.4 3.7 0.3 3.5
tPLH(1) 2.7 0.8 5.4 0.7 5.2 0.6 4.9 0.5 4.7
B A ns
tPHL(1) 2.7 0.8 5.4 0.7 5.2 0.6 4.9 0.5 4.7
tPHZ(1) 3.9 1.3 8.5 1.3 7.8 1.1 7.7 1.4 7.6
DIR A ns
tPLZ(1) 3.9 1.3 8.5 1.3 7.8 1.1 7.7 1.4 7.6
tPHZ(1) 4.7 1.1 7 1.4 6.9 1.2 6.9 1.7 7.1
DIR B ns
tPLZ(1) 4.7 1.1 7 1.4 6.9 1.2 6.9 1.7 7.1
tPZH(1)(2) 7.4 12.4 12.1 11.8 11.8
DIR A ns
tPZL(1)(2) 7.4 12.4 12.1 11.8 11.8
tPZH(1)(2) 6.7 13.9 12.4 11.4 11.1
DIR B ns
tPZL(1)(2) 6.7 13.9 12.4 11.4 11.1
(1) tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
(2) The enable time is a calculated value derived using the formula shown in the Enable Times section.
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7.8 Switching Characteristics: VCCA = 1.8 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 7)
VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
VCCB = 1.2 V
FROM TO ± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 V
PARAMETER UNIT
(INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH(1) 2.7 0.5 5.2 0.4 4.3 0.2 3.4 0.2 3.1
A B ns
tPHL(1) 2.7 0.5 5.2 0.4 4.3 0.2 3.4 0.2 3.1
tPLH(1) 2.4 0.7 4.7 0.5 4.4 0.5 4 0.4 3.8
B A ns
tPHL(1) 2.4 0.7 4.7 0.5 4.4 0.5 4 0.4 3.8
tPHZ(1) 3.7 1.3 8.1 0.7 6.9 1.4 5.3 1.1 5.2
DIR A ns
tPLZ(1) 3.7 1.3 8.1 0.7 6.9 1.4 5.3 1.1 5.2
tPHZ(1) 4.4 1.3 5.8 1.3 5.9 0.8 5.7 1.5 5.9
DIR B ns
tPLZ(1) 4.4 1.3 5.8 1.3 5.9 0.8 5.7 1.5 5.9
tPZH(1)(2) 6.8 10.5 10.3 9.7 9.7
DIR A ns
tPZL(1)(2) 6.8 10.5 10.3 9.7 9.7
tPZH(1)(2) 6.4 13.3 11.2 8.7 8.3
DIR B ns
tPZL(1)(2) 6.4 13.3 11.2 8.7 8.3
(1) tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
(2) The enable time is a calculated value derived using the formula shown in the Enable Times section.
7.9 Switching Characteristics: VCCA = 2.5 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 7)
VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
VCCB = 1.2 V
FROM TO ± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 V
PARAMETER UNIT
(INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH(1) 2.6 0.4 4.9 0.2 4 0.2 3 0.2 2.6
A B ns
tPHL(1) 2.6 0.4 4.9 0.2 4 0.2 3 0.2 2.6
tPLH(1) 2.1 0.6 3.8 0.5 3.4 0.4 3 0.3 2.8
B A ns
tPHL(1) 2.1 0.6 3.8 0.5 3.4 0.4 3 0.3 2.8
tPHZ(1) 2.4 0.7 7.9 0.8 6.4 0.8 5 0.5 4.3
DIR A ns
tPLZ(1) 2.4 0.7 7.9 0.8 6.4 0.8 5 0.5 4.3
tPHZ(1) 3.8 1 4.3 0.6 4.3 0.5 4.2 1.1 4.1
DIR B ns
tPLZ(1) 3.8 1 4.3 0.6 4.3 0.5 4.2 1.1 4.1
tPZH(1)(2) 5.9 8.5 7.7 7.2 6.9
DIR A ns
tPZL(1)(2) 5.9 8.5 7.7 7.2 6.9
tPZH(1)(2) 5 12.8 10.4 8 6.9
DIR B ns
tPZL(1)(2) 5 12.8 10.4 8 6.9
(1) tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
(2) The enable time is a calculated value derived using the formula shown in the Enable Times section.
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7.10 Switching Characteristics: VCCA = 3.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 7)
VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
VCCB = 1.2 V
FROM TO ± 0.1 V ± 0.15 V ± 0.2 V ± 0.3 V
PARAMETER UNIT
(INPUT) (OUTPUT) TYP MIN MAX MIN MAX MIN MAX MIN MAX
tPLH(1) 2.5 0.3 4.7 0.2 3.8 0.2 2.8 0.2 2.4
A B ns
tPHL(1) 2.5 0.3 4.7 0.2 3.8 0.2 2.8 0.2 2.4
tPLH(1) 2.1 0.6 3.6 0.4 3.1 0.3 2.6 0.3 2.4
B A ns
tPHL(1) 2.1 0.6 3.6 0.4 3.1 0.3 2.6 0.3 2.4
tPHZ(1) 2.9 1.1 8 1 6.5 1.3 4.7 1.2 4
DIR A ns
tPLZ(1) 2.9 1.1 8 1 6.5 1.3 4.7 1.2 4
tPHZ(1) 3.4 0.5 6.6 0.3 5.6 0.3 4.6 1.1 4.2
DIR B ns
tPLZ(1) 3.4 0.5 6.6 0.3 5.6 0.3 4.6 1.1 4.2
tPZH(1)(2) 5.5 10.2 8.7 7.2 6.6
DIR A ns
tPZL(1)(2) 5.5 10.2 8.7 7.2 6.6
tPZH(1)(2) 5.4 12.7 10.3 7.5 6.4
DIR B ns
tPZL(1)(2) 5.4 12.7 10.3 7.5 6.4
(1) tPLH: Low-to-high Propagation Delay; tPHL: High-to-Low Propagation Delay; tPHZ: High-to-Hi-Z Propagation Delay; tPLZ: Low-to-Hi-Z
Propagation Delay; tPZH: Hi-Z-to-High Propagation Delay; tPZL: Hi-Z-to-Low Propagation Delay
(2) The enable time is a calculated value derived using the formula shown in the Enable Times section.
7.11 Operating Characteristics
TA= 25°C
VCCA = VCCA = VCCA = VCCA = VCCA =
TEST VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
PARAMETER UNIT
CONDITIONS TYP TYP TYP TYP TYP
A-port input, 33334
CL= 0,
B-port output
CpdA(1) f = 10 MHz, pF
B-port input, tr(2) = tf(2) = 1 ns 13 13 14 15 15
A-port output
A-port input, 13 13 14 15 15
CL= 0,
B-port output
CpdB(1) f = 10 MHz, pF
B-port input, tr(2) = tf(2) = 1 ns 33334
A-port output
(1) Power dissipation capacitance per transceiver
(2) tr: Rise time; tf: Fall time
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Product Folder Links: SN74AVCH2T45
l TEXAS INSTRUMENTS HH“ m \\ cL
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH - ns
CL - pF
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH (ns)
CL(pF)
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
tPHL (ns)
CL(pF)
0
1
2
3
4
5
6
0 10 20 30 40 50 60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50
tPLH (ns)
CL(pF)
60
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
0
1
2
3
4
5
6
0 10 20 30 40 50 60
tPHL (ns)
CL(pF)
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.5 V
VCCB = 1.2 V
SN74AVCH2T45
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7.12 Typical Characteristics
7.12.1 Typical Propagation Delay (A to B) vs Load Capacitance, TA= 25°C, VCCA = 1.8 V
Figure 2. Typical A-to-B Propagation Delay, High to Low
Figure 1. Typical A-to-B Propagation Delay, Low to High
7.12.2 Typical Propagation Delay (A to B) vs Load Capacitance, TA= 25°C, VCCA = 2.5 V
Figure 4. Typical A-to-B Propagation Delay, High to Low
Figure 3. Typical A-to-B Propagation Delay, Low to High
7.12.3 Typical Propagation Delay (A to B) vs Load Capacitance, TA= 25°C, VCCA = 3.3 V
Figure 6. Typical A-to-B Propagation Delay, High to Low
Figure 5. Typical A-to-B Propagation Delay, Low to High
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l TEXAS INSTRUMENTS 2 x O 51 0 From Outpul Under Test CL (see Note A) ‘\}—o LOAD CIRCUIT vcco ws me vac
VOH
VOL
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2 × VCCO
Open
GND
RL
RL
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2VCCA/2
VCCI/2 VCCI/2 VCCI
0 V
VCCO/2 VCCO/2
VOH
VOL
0 V
VCCO/2 VOL + VTP
VCCO/2 VOH - VTP
0 V
VCCI
0 V
VCCI/2 VCCI/2
tw
Input
VCCA
VCCO
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
VCCO RL
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VTP
CL
15 pF
15 pF
15 pF
15 pF
15 pF
SN74AVCH2T45
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SCES582H –JULY 2004–REVISED APRIL 2015
8 Parameter Measurement Information
Figure 7. Load Circuit and Voltage Waveforms
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B1
DIR 5
7
A1 2
VCCA VCCB
B2
6
A2 3
18
VCCA VCCB
GND
4
VCCA VCCB
SN74AVCH2T45
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www.ti.com
9 Detailed Description
9.1 Overview
This dual-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB
and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation
and level-shifting between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits
data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when
the A-port outputs are activated.
The SN74AVCH2T45 features active bus-hold circuitry.
The DIR input is powered by supply voltage from VCCA.
This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance
state. This will prevent a false high or low logic being presented at the output.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
9.2 Functional Block Diagram
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9.3 Feature Description
9.3.1 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance
state (IOZ shown in the Functional Block Diagram). This prevents false logic levels from being presented to either
bus.
9.3.2 2-Rail Design
Fully configurable 2-rail design allows each port to operate over the full 1.2 V to 3.6 V power-supply range.
9.3.3 IO Ports are 4.6 V Tolerant
The IO ports are up to 4.6 V tolerant
9.3.4 Partial Power Down Mode
This device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
9.3.5 Bus Hold on Data Inputs
Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. TI does not recommend using
pull-up or pull-down resistors with the bus-hold circuitry.
9.4 Device Functional Modes
Table 1. Function Table (Each Transceiver)
INPUT OPERATION
DIR
L B data to A bus
H A data to B bus
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{yfimfi INSTRUMENTS ______________1 1J Wllll I ll IIIIA
VCCA
VCCA VCCB
SYSTEM-1 SYSTEM-2
VCCA
1
2
3
4
8
7
6
5
VCCB
VCCB
VCCB
B1
B2
DIR
VCCA
A2
A1
GND
SN74AVCH2T45
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www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74AVCH2T45 is used to shift IO voltage levels from one voltage domain to another. Each bus (bus A and
bus B) have independent power supplies, and a direction pin is used to control the direction of data flow.
10.2 Typical Applications
10.2.1 Unidirectional Logic Level-Shifting Application
Figure 8 is an example of the SN74AVCH2T45 circuit used in a unidirectional logic level-shifting application.
Figure 8. Unidirectional Logic Level-Shifting Application
10.2.1.1 Design Requirements
This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the
intended flow of data and take care not to violate any of the high or low logic levels. Active bus-hold circuitry
holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down
resistors with the bus-hold circuitry.
10.2.1.2 Detailed Design Procedure
Table 2 lists the pins and pin descriptions of the SN74AVCH2T45 connections with SYSTEM-1 and SYSTEM-2.
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l TEXAS INSTRUMENTS
Magnitude (V)
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
D002
Input
Output
SN74AVCH2T45
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Typical Applications (continued)
Table 2. SN74AVCH2T45 Pin Connections With SYSTEM-1 and SYSTEM-2
PIN NAME DESCRIPTION
1 VCCA SYSTEM-1 supply voltage (1.2 V to 3.6 V)
2 A1 Output level depends on VCCA.
3 A2 Output level depends on VCCA.
4 GND Device GND
5 DIR The GND (low-level) determines B-port to A-port direction.
6 B2 Input threshold value depends on VCCB.
7 B1 Input threshold value depends on VCCB.
8 VCCB SYSTEM-2 supply voltage (1.2 V to 3.6 V)
10.2.1.3 Application Curve
Figure 9. 3.3- to 1.8-V Level-Shifting With 1-MHz Square Wave
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‘5‘ TEXAS INSTRUMENTS SYSTEM -2 SYSTEM-1
VCCA VCCA VCCB
SYSTEM-1 SYSTEM-2
1
2
3
4
8
7
6
5
DIR CTRL
IO-1
VCCB
IO-2
VCCB
B1
B2
DIR
VCCA
A2
A1
GND
Pull-up/Pull-down
or Bus Hold
Pull-up/Pull-down
or Bus Hold
SN74AVCH2T45
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10.2.2 Bidirectional Logic Level-Shifting Application
Figure 10 shows the SN74AVCH2T45 used in a bidirectional logic level-shifting application. Because the
SN74AVCH2T45 does not have an output-enable (OE) pin, system designers should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Figure 10. Bidirectional Logic Level-Shifting Application
10.2.2.1 Design Requirements
This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the
intended flow of data and take care not to violate any of the high or low logic levels. Active bus-hold circuitry
holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down
resistors with the bus-hold circuitry.
10.2.2.2 Detailed Design Procedure
Table 3 lists a sequence that shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2
to SYSTEM-1.
Table 3. Data Transmission Sequence
STATE DIR CTRL IO-1 IO-2 DESCRIPTION
1 H Output Input SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. IO-1 and IO-2 are
2 H Hi-Z Hi-Z disabled.
The bus-line state depends on pull-up or pull-down.(1)
DIR bit is flipped. IO-1 and IO-2 still are disabled.
3 L Hi-Z Hi-Z The bus-line state depends on pull-up or pull-down.(1)
4 L Input Output SYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
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10.2.2.2.1 Enable Times
Calculate the enable times for the SN74AVCH2T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) (1)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) (2)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) (3)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) (4)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH2T45 initially is transmitting from A to B, the
DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port
has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
10.2.2.3 Application Curve
Refer to Figure 9.
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l TEXAS INSTRUMENTS
A1
A2
VCCA
B1
B2
DIR
VCCB
GND
VIA to GND Plane
B2 B1
A1A2
C2 C1
D2 D1
SN74AVCH2T45
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www.ti.com
11 Power Supply Recommendations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
Table 4. Typical Total Static Power Consumption (ICCA + ICCB)
VCCA
VCCB UNIT
0 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V
0 V 0 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5
1.2 V < 0.5 < 1 < 1 < 1 < 1 1
1.5 V < 0.5 < 1 < 1 < 1 < 1 1 μA
1.8 V < 0.5 < 1 < 1 < 1 < 1 < 1
2.5 V < 0.5 1 < 1 < 1 < 1 < 1
3.3 V < 0.5 1 < 1 < 1 < 1 < 1
12 Layout
12.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies. Place the capacitors as close as possible to the VCCA,
VCCB pin and GND pin.
• Short trace lengths should be used to avoid excessive loading.
12.2 Layout Example
Figure 11. Layout Example for YZP Package
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•Implications of Slow or Floating CMOS Inputs,SCBA004
13.2 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 22-Sep-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74AVCH2T45DCTTE4 ACTIVE SM8 DCT 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ET2
Z
SN74AVCH2T45DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ET2
Z
SN74AVCH2T45DCTT ACTIVE SM8 DCT 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ET2
Z
SN74AVCH2T45DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (ET2R, T2)
EZ
SN74AVCH2T45DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ET2R
SN74AVCH2T45DCUT ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (ET2R, T2)
EZ
SN74AVCH2T45YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TFN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 22-Sep-2021
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Dlameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component iengtn K0 Dimension designed to accommodate the component Ihlckness 7 W OveraH wtdlh loe Gamer tape i P1 Pitch between successive cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE OOODOODD ,,,,,,,,,,, ‘ User Direcllon 0' Feed Sprocket Hoies Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AVCH2T45DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74AVCH2T45DCTT SM8 DCT 8 250 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74AVCH2T45DCUR VSSOP DCU 8 3000 180.0 9.0 2.25 3.4 1.0 4.0 8.0 Q3
SN74AVCH2T45DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74AVCH2T45DCURG4 VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74AVCH2T45YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AVCH2T45DCTR SM8 DCT 8 3000 182.0 182.0 20.0
SN74AVCH2T45DCTT SM8 DCT 8 250 182.0 182.0 20.0
SN74AVCH2T45DCUR VSSOP DCU 8 3000 182.0 182.0 20.0
SN74AVCH2T45DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74AVCH2T45DCURG4 VSSOP DCU 8 3000 202.0 201.0 28.0
SN74AVCH2T45YZPR DSBGA YZP 8 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 25-Jul-2020
Pack Materials-Page 2
MECHANICAL DATA DCU (R—PDSO—GB) PLASTIC SMALL—OUTLINE PACKAGE (DIE DOWN) F Wngiw 31117 0,15 \0M 7 7,40 310 2,20 3,00 i Gage Pm J i 3W1 / __'—_“ NDEX AREA 1 99 Do $1212]: : Q% J L W 4200503” z7/05 NOTES, A AH Hnec' dimensmrs in m'hmekers B Tris drawing is sum 0 Change mm: malice, 0 Body dimCHSiOnS do mi inciudc mom flash or oromsm Moid tics» and pvctrusmn srai not cxcccd o it) 30V m D FuHs wiwu JEDEC M0457 vuiiuliovi CA ‘4‘ TEXAS INSTRUMENTS www.(i. com
LAND PATTERN DATA DCU (S—PDSO—G8) PLASTIC SMALL OUTLINE PACKAGE (DH-Z DOWN) Example Board Layout (Nate 0,5) l ihi' 6x 0,5 I 3,1 ( 8% ‘\ / + 0,3 Exampie /Soider Mask Opening \ Pad Geometry Exampie Stencii Design (Nate D) 8x 0,25 —‘ |——‘ Er Eflfii- Bx 0,75 7 ‘|———'- 6x 0,5 HHH%- meow/c 04/12 NOTES: Au Pom .m Ali iinear dimensions are in miiiimeters‘ This drawing is subject to change without notice. Publication iPC—735I is recommended for aiternate designs. Laser cutting aperture5 with trupezoidai wails and also rounding corners wiil ciier better paste reiease. Customers should Contact their haard assembly site for stencii design recommendations. Refer to iFC—7525 for other slencii recommendations. Custamers shauid Contact their board fabrication site for saider mask toierances between and around signai pads. {I} Tums INSTRUMENTS www.li.com
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PACKAGE OUTLINE
C
4.25
3.75 TYP
1.3
1.0
6X 0.65
8X 0.30
0.15
2X
1.95
(0.15) TYP
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.2
A
3.15
2.75
NOTE 3
B2.9
2.7
NOTE 4
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
18
0.13 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.500
J
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EXAMPLE BOARD LAYOUT
(3.8)
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.1)
8X (0.4)
6X (0.65)
(R0.05)
TYP
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
1
45
8
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
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EXAMPLE STENCIL DESIGN
(3.8)
6X (0.65)
8X (0.4)
8X (1.1)
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
WT
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PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1.5
TYP
0.5 TYP
8X 0.25
0.21
0.5
TYP
B E A
D
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
D
SCALE 8.000
D: Max =
E: Max =
1.918 mm, Min =
0.918 mm, Min =
1.858 mm
0.858 mm
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EXAMPLE BOARD LAYOUT
8X ( 0.23) (0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
D
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
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EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
8X ( 0.25) (R0.05) TYP
METAL
TYP
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
D
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