SN65HVD230-32 Datasheet by Texas Instruments

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

SN65HVD23x 3.3-V CAN Bus Transceivers

1 Features

1• Operates with a single 3.3 V Supply

• Compatible With ISO 11898-2 Standard

• Low Power Replacement for the PCA82C250

Footprint

• Bus Pin ESD Protection Exceeds ±16 kV HBM

• High Input Impedance Allows for Up to 120 Nodes

on a Bus

• Adjustable Driver Transition Times for Improved

Emissions Performance

– SN65HVD230 and SN65HVD231

• SN65HVD230: Low Current Standby Mode

– 370 μA Typical

• SN65HVD231: Ultra Low Current Sleep Mode

– 40 nA Typical

• Designed for Data Rates(1) up to 1 Mbps

• Thermal Shutdown Protection

• Open Circuit Fail-Safe Design

• Glitch Free Power Up and Power Down Protection

for Hot Plugging Applications

(1) The signaling rate of a line is the number of voltage

transitions that are made per second expressed in the units

bps (bits per second).

2 Applications

• Industrial Automation, Control, Sensors and Drive

Systems

• Motor and Robotic Control

• Building and Climate Control (HVAC)

• Telecom and Basestation Control and Status

• CAN Bus Standards Such as CANopen,

DeviceNet, and CAN Kingdom

3 Description

The SN65HVD230, SN65HVD231, and SN65HVD232

controller area network (CAN) transceivers are

compatible to the specifications of the ISO 11898-2

High Speed CAN Physical Layer standard

(transceiver). These devices are designed for data

rates up to 1 megabit per second (Mbps), and include

many protection features providing device and CAN

network robustness. The SN65HVD23x transceivers

are designed for use with the Texas Instruments 3.3

V µPs, MCUs and DSPs with CAN controllers, or with

equivalent protocol controller devices. The devices

are intended for use in applications employing the

CAN serial communication physical layer in

accordance with the ISO 11898 standard.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN65HVD230

SOIC (8) 4.90 mm × 3.91 mmSN65HVD231

SN65HVD232

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Equivalent Input and Output Schematic Diagrams

l TEXAS INSTRUMENTS

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

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Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 4

6 Device Comparison Table..................................... 4

7 Pin Configuration and Functions......................... 5

8 Specifications......................................................... 5

8.1 Absolute Maximum Ratings ...................................... 5

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 6

8.5 Electrical Characteristics: Driver............................... 7

8.6 Electrical Characteristics: Receiver .......................... 7

8.7 Switching Characteristics: Driver .............................. 8

8.8 Switching Characteristics: Receiver.......................... 8

8.9 Switching Characteristics: Device............................. 8

8.10 Device Control-Pin Characteristics ......................... 9

8.11 Typical Characteristics.......................................... 10

9 Parameter Measurement Information ................ 13

10 Detailed Description ........................................... 19

10.1 Overview ............................................................... 19

10.2 Functional Block Diagram ..................................... 19

10.3 Feature Description .............................................. 20

10.4 Device Functional Modes...................................... 20

11 Application and Implementation........................ 25

11.1 Application Information.......................................... 25

11.2 Typical Application ................................................ 26

11.3 System Example ................................................... 30

12 Power Supply Recommendations ..................... 32

13 Layout................................................................... 33

13.1 Layout Guidelines ................................................. 33

13.2 Layout Example .................................................... 34

14 Device and Documentation Support ................. 35

14.1 Related Links ........................................................ 35

14.2 Receiving Notification of Documentation Updates 35

14.3 Community Resources.......................................... 35

14.4 Trademarks........................................................... 35

14.5 Electrostatic Discharge Caution............................ 35

14.6 Glossary................................................................ 35

15 Mechanical, Packaging, and Orderable

Information ........................................................... 35

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision N (July 2015) to Revision O Page

• Changed Slope Control Resistance - kW To: Slope Control Resistance - kΩin Figure 33................................................. 22

• Changed Driver Output Signal Slope - V/ms To: Driver Output Signal Slope - V/µs in Figure 33....................................... 22

Changes from Revision M (May 2015) to Revision N Page

• Changed the data sheet title From; SN65HVD230x 3.3-V CAN Bus Transceivers To: SN65HVD23x 3.3-V CAN Bus

Transceivers .......................................................................................................................................................................... 1

Changes from Revision L (January 2015) to Revision M Page

• Changed Figure 44 title From: "Layout Example Schematic" To: "SN65HVD23x Board Layout"........................................ 34

Changes from Revision K (February 2011) to Revision L Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Changed the list of Features, Applications, and Description.................................................................................................. 1

• Added THERMAL SHUTDOWN TEMPERATURE AND HYSTERESIS in the Recommended Operating Conditions table. 6

• Added the THERMAL SHUTDOWN paragraph to the Application Information section....................................................... 20

• Added Figure 34 and Figure 35............................................................................................................................................ 25

• Added the CAN TERMINATION paragraph to the Application Information section............................................................. 26

• Added the BUS LOADING, LENGTH AND NUMBER OF NODES paragraph to the Application Information section........ 28

l TEXAS INSTRUMENTS

SN65HVD230

SN65HVD231

SN65HVD232

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Changes from Revision J (January 2009) to Revision K Page

• Replaced the DISSIPATION RATING TABLE with the Thermal Information table................................................................ 6

Changes from Revision I (October 2007) to Revision J Page

• Deleted Low-to-High Propagation Delay Time vs Common-Mode Input Voltage Characteristics ....................................... 12

• Deleted Driver Schematic Diagram ...................................................................................................................................... 12

• Added Figure 38................................................................................................................................................................... 32

l TEXAS INSTRUMENTS

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SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

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Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

5 Description (continued)

Designed for operation in especially harsh environments, these devices feature cross wire protection, loss of

ground and overvoltage protection, overtemperature protection, as well as wide common mode range of

operation.

The CAN transceiver is the CAN physical layer and interfaces the single ended host CAN protocol controller with

the differential CAN bus found in industrial, building automation, and automotive applications. These devices

operate over a -2 V to 7 V common mode range on the bus, and can withstand common mode transients of ±25

The RSpin (pin 8) on the SN65HVD230 and SN65HVD231 provides three different modes of operation: high

speed mode, slope control mode, and low-power mode. The high speed mode of operation is selected by

connecting the RSpin to ground, allowing the transmitter output transistors to switch on and off as fast as

possible with no limitation on the rise and fall slopes. The rise and fall slopes can also be adjusted by connecting

a resistor in series between the RSpin and ground. The slope will be proportional to the pin's output current. With

a resistor value of 10 kΩthe device will have a slew rate of ~15 V/μs, and with a resistor value of 100 kΩthe

device will have a slew rate of ~2 V/μs. See Application Information for more information.

The SN65HVD230 enters a low current standby mode (listen only) during which the driver is switched off and the

receiver remains active if a high logic level is applied to the RSpin. This mode provides a lower power

consumption mode than normal mode while still allowing the CAN controller to monitor the bus for activity

indicating it should return the transceiver to normal mode or slope control mode. The host controller (MCU, DSP)

returns the device to a transmitting mode (high speed or slope control) when it wants to transmit a message to

the bus or if during standby mode it received bus traffic indicating the need to once again be ready to transmit.

The difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver are

switched off in the SN65HVD231 when a high logic level is applied to the RSpin. In this sleep mode the device

will not be able to transmit messages to the bus or receive messages from the bus. The device will remain in

sleep mode until it is reactivated by applying a low logic level on the RSpin.

(1) For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information, or see the TI web site

at www.ti.com.

6 Device Comparison Table

PART NUMBER(1) LOW POWER MODE INTEGRATED SLOPE

CONTROL Vref PIN TAMARKED AS:

SN65HVD230 Standby mode Yes Yes

40°C to 85°C

VP230

SN65HVD231 Sleep mode Yes Yes VP231

SN65HVD232 No standby or sleep mode No No VP232

*9 TEXAS INSTRUMENTS

1D 8 RS

2GND 7 CANH

VCC 6 CANL

4R 5 Vref

Not to scale

1D 8 NC

2GND 7 CANH

VCC 6 CANL

4R 5 NC

Not to scale

SN65HVD230

SN65HVD231

SN65HVD232

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7 Pin Configuration and Functions

SN65HVD230D (Marked as VP230)

SN65HVD231D (Marked as VP231)

Top View

SN65HVD232D (Marked as VP232)

Top View

Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

D 1 I CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called TXD, driver

input

GND 2 GND Ground connection

VCC 3 Supply Transceiver 3.3V supply voltage

R 4 O CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called RXD, receiver

output

Vref 5O SN65HVD230 and SN65HVD231: VCC / 2 reference output pin

NC NC SN65HVD232: No Connect

CANL 6 I/O Low level CAN bus line

CANH 7 I/O High level CAN bus line

RS8ISN65HVD230 and SN65HVD231: Mode select pin: strong pull down to GND = high speed mode, strong

pull up to VCC = low power mode, 10kΩto 100kΩpull down to GND = slope control mode

NC I SN65HVD232: No Connect

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

Supply voltage, VCC –0.3 6 V

Voltage at any bus terminal (CANH or CANL) –4 16 V

Voltage input, transient pulse, CANH and CANL, through 100 Ω(see Figure 24) –25 25 V

Digital Input and Output voltage, VI(D or R) –0.5 VCC + 0.5 V

Receiver output current, IO–11 11 mA

Continuous total power dissipation See Thermal Information

Storage temperature, Tstg –40 85 °C

l TEXAS INSTRUMENTS

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SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

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Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-

001(1) CANH, CANL and GND ±16000

VAll pins ±4000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

8.3 Recommended Operating Conditions

MIN NOM MAX UNIT

Supply voltage, VCC 3 3.6 V

Voltage at any bus terminal (common mode) VIC –2(1) 7 V

Voltage at any bus terminal (separately) VI–2.5 7.5 V

High-level input voltage, VIH D, R 2 V

Low-level input voltage, VIL D, R 0.8 V

Differential input voltage, VID (see Figure 22) –6 6 V

Input voltage, V(Rs) 0 VCC V

Input voltage for standby or sleep, V(Rs) 0.75 VCC VCC V

Wave-shaping resistance, Rs 0 100 kΩ

High-level output current, IOH Driver –40 mA

Receiver –8

Low-level output current, IOL Driver 48 mA

Receiver 8

Thermal shutdown temperature 165

°CThermal shutdown hysteresis 10

Operating free-air temperature, TA–40 85

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.4 Thermal Information

THERMAL METRIC(1)

SN65HVD230 SN65HVD231 SN65HVD232

UNITD

8 PINS

RθJA Junction-to-ambient thermal resistance 76.8 101.5 101.5 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 33.4 43.3 43.3 °C/W

RθJB Junction-to-board thermal resistance 15.3 42.2 42.4 °C/W

ψJT Junction-to-top characterization parameter 1.4 4.8 4.8 °C/W

ψJB Junction-to-board characterization parameter 14.9 41.8 41.8 °C/W

l TEXAS INSTRUMENTS

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SN65HVD231

SN65HVD232

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Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

(1) All typical values are at 25°C and with a 3.3-V supply.

8.5 Electrical Characteristics: Driver

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

VOH Bus output

voltage

Dominant VI= 0 V,

See Figure 18 and

Figure 20

CANH 2.45 VCC

CANL 0.5 1.25

VOL Recessive VI= 3 V,

See Figure 18 and

Figure 20

CANH 2.3

CANL 2.3

VOD(D) Differential

output voltage

Dominant VI= 0 V, See Figure 18 1.5 2 3 V

VI= 0 V, See Figure 19 1.2 2 3

VOD(R) Recessive VI= 3 V, See Figure 18 –120 0 12 mV

VI= 3 V, No load –0.5 –0.2 0.05 V

IIH High-level input current VI= 2 V –30 μA

IIL Low-level input current VI= 0.8 V –30 μA

IOS Short-circuit output current VCANH = -2 V –250 250 mA

VCANL = 7 V –250 250

CoOutput capacitance See receiver

ICC Supply

current

Standby SN65HVD230 V(Rs) = VCC 370 600 μA

Sleep SN65HVD231 V(Rs) = VCC, D at VCC 0.04 1

All devices Dominant VI= 0 V, No load Dominant 10 17 mA

Recessive VI= VCC, No load Recessive 10 17

(1) All typical values are at 25°C and with a 3.3-V supply.

8.6 Electrical Characteristics: Receiver

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

VIT+ Positive-going input threshold voltage See Table 1 750 900 mV

VIT- Negative-going input threshold voltage 500 650 mV

Vhys Hysteresis voltage (VIT+ – VIT–) 100

VOH High-level output voltage –6 V ≤VID ≤500 mV, IO= –8 mA, See Figure 22 2.4 V

VOL Low-level output voltage 900 mV ≤VID ≤6 V, IO= 8 mA, See Figure 22 0.4

IIBus input current

VIH = 7 V

Other input at 0 V,

D = 3 V

100 250 μA

VIH = 7 V, VCC = 0 V 100 350

VIH = -2 V –200 –30 μA

VIH = -2 V, VCC = 0 V –100 –20

CICANH, CANL input capacitance Pin-to-ground,

VI= 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 32 pF

CDiff Differential input capacitance Pin-to-pin,

VI= 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 16 pF

RDiff Differential input resistance Pin-to-pin, V(D) = 3 V 40 70 100 kΩ

RICANH, CANL input resistance 20 35 50 kΩ

ICC Supply current See driver

l TEXAS INSTRUMENTS

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

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Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

8.7 Switching Characteristics: Driver

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST

CONDITIONS MIN TYP MAX UNIT

SN65HVD230 AND SN65HVD231

tPLH Propagation delay time, low-to-high-level

output

V(Rs) = 0 V

CL= 50 pF,

See Figure 21

35 85

nsRSwith 10 kΩto ground 70 125

RSwith 100 kΩto ground 500 870

tPHL Propagation delay time, high-to-low-level

output

V(Rs) = 0 V 70 120

nsRSwith 10 kΩto ground 130 180

RSwith 100 kΩto ground 870 1200

tsk(p) Pulse skew (|tPHL - tPLH|)

V(Rs) = 0 V 35

nsRSwith 10 kΩto ground 60

RSwith 100 kΩto ground 370

trDifferential output signal rise time V(Rs) = 0 V 25 50 100 ns

tfDifferential output signal fall time 40 55 80 ns

trDifferential output signal rise time RSwith 10 kΩto ground 80 120 160 ns

tfDifferential output signal fall time 80 125 150 ns

trDifferential output signal rise time RSwith 100 kΩto ground 600 800 1200 ns

tfDifferential output signal fall time 600 825 1000 ns

SN65HVD232

tPLH Propagation delay time, low-to-high-level output

CL= 50 pF,

See Figure 21

35 85

tPHL Propagation delay time, high-to-low-level output 70 120

tsk(p) Pulse skew (|tPHL - tPLH|) 35

trDifferential output signal rise time 25 50 100

tfDifferential output signal fall time 40 55 80

8.8 Switching Characteristics: Receiver

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH Propagation delay time, low-to-high-level output

See Figure 23

35 50 ns

tPHL Propagation delay time, high-to-low-level output 35 50 ns

tsk(p) Pulse skew (|tPHL - tPLH|) 10 ns

trOutput signal rise time See Figure 23 1.5 ns

tfOutput signal fall time 1.5 ns

8.9 Switching Characteristics: Device

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t(LOOP1) Total loop delay, driver input to receiver

output, recessive to dominant

V(Rs) = 0 V, See Figure 26 70 115

nsRSwith 10 kΩto ground, See Figure 26 105 175

RSwith 100 kΩto ground, See Figure 26 535 920

t(LOOP2) Total loop delay, driver input to receiver

output, dominant to recessive

V(Rs) = 0 V, See Figure 26 100 135

nsRSwith 10 kΩto ground, See Figure 26 155 185

RSwith 100 kΩto ground, See Figure 26 830 990

l TEXAS INSTRUMENTS

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SN65HVD231

SN65HVD232

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(1) All typical values are at 25°C and with a 3.3-V supply.

8.10 Device Control-Pin Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

t(WAKE)

SN65HVD230 wake-up time from standby mode

with RSSee Figure 25

0.55 1.5 μs

SN65HVD231 wake-up time from sleep mode

with RS3 5 μs

Vref Reference output voltage -5 μA < I(Vref) < 5 μA 0.45 VCC 0.55 VCC V

-50 μA < I(Vref) < 50 μA 0.4 VCC 0.6 VCC

I(Rs) Input current for high-speed V(Rs) < 1 V –450 0 μA

l TEXAS INSTRUMENTS n

0.5

1.5

2.5

−55 −40 0 25 70 85 125

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

VOD

− Dominant Voltage − V

TA − Free-Air Temperature − °C

100

120

0 0.5 1 1.5 2 2.5 3 3.5

− Driver High-Level Output Current − mA

VO(CANH) − High-Level Output Voltage − V

IOH

0 1 2 3 4

IOL− Driver Low-Level Output Current − mA

VO(CANL)− Low-Level Output Voltage − V

100

120

140

160

−400

−300

−200

−100

100

200

300

400

−7 −6 −4 −3 −1 0 1 3 4 6 7 8 10 11 12

VCC = 0 V

VCC = 3.6 V

II− Bus Input Current − Aµ

VI − Bus Input Voltage − V

−16

−14

−12

−10

−8

−6

−4

−2

0 0.6 1.1 1.6 2.1 2.6 3.1 3.6

II(L) − Logic Input Current − Aµ

VI − Input Voltage − V

13 0 250 500

f − Frequency − kbps

750 1000

ICC − Supply Current (RMS) − mA

VCC = 3.3 V

60-Ω Load

RS at 0 V

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

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Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

8.11 Typical Characteristics

Figure 1. Supply Current (RMS) vs Frequency Figure 2. Logic Input Current (Pin D) vs Input Voltage

Figure 3. Bus Input Current vs Bus Input Voltage Figure 4. Driver Low-Level Output Current vs Low-Level

Output Voltage

Figure 5. Driver High-Level Output Current vs High-Level

Output Voltage Figure 6. Dominant Voltage (VOD) vs Free-Air Temperature

l TEXAS INSTRUMENTS

−55 −40 0 25 70 85 125

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

RS = 10 kΩ

tPLH − Driver Low-to-High Propagation Delay Time − ns

TA − Free-Air Temperature − °C

100

110

120

130

140

150

−55 −40 0 25 70 85 125

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V RS = 10 kΩ

tPHL − Driver High-to-Low Propagation Delay Time − ns

TA − Free-Air Temperature − °C

−55 −40 0 25 70 85 125

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

RS = 0

tPLH − Driver Low-to-High Propagation Delay Time − ns

TA − Free-Air Temperature − °C

−55 −40 0 25 70 85 125

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V RS = 0

tPHL− Driver High-to-Low Propagation Delay Time − ns

TA − Free-Air Temperature − °C

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

−55 −40 0 25 70 85 125

RS = 0

tPHL− Receiver High-to-Low Propagation Delay Time − ns

TA − Free-Air Temperature − °C

−55 −40 0 25 70 85 125

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

RS = 0

tPLH − Receiver Low-to-High Propagation Delay Time − ns

TA − Free-Air Temperature − °C

SN65HVD230

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Typical Characteristics (continued)

Figure 7. Receiver Low-to-High Propagation Delay Time vs

Free-Air Temperature Figure 8. Receiver High-to-Low Propagation Delay Time vs

Free-Air Temperature

Figure 9. Driver Low-to-High Propagation Delay Time vs

Free-Air Temperature Figure 10. Driver High-to-Low Propagation Delay Time vs

Free-Air Temperature

Figure 11. Driver Low-to-High Propagation Delay Time vs

Free-Air Temperature Figure 12. Driver High-to-Low Propagation Delay Time vs

Free-Air Temperature

l TEXAS INSTRUMENTS

0.5

1.5

2.5

−50 −5 5 50

VCC = 3 V

VCC = 3.6 V

Vref − Reference Voltage − V

Iref − Reference Current − µA

1 1.5 2 2.5 3 3.5 4

IO− Driver Output Current − mA

VCC − Supply Voltage − V

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

1.10

1.20

1.30

1.40

0 50 100 150 200

1.50

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

tf− Differential Driver Output Fall Time − sµ

Rs − Source Resistance − kΩ

100

200

300

400

500

600

700

800

−55 −40 0 25 70 85 125

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

RS = 100 kΩ

tPLH − Driver Low-to-High Propagation Delay Time − ns

TA − Free-Air Temperature − °C

700

750

800

850

900

950

1000

−55 −40 0 25 70 85 125

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

RS = 100 kΩ

tPHL− Driver High-to-Low Propagation Delay Time − ns

TA − Free-Air Temperature − °C

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

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Typical Characteristics (continued)

Figure 13. Driver Low-to-High Propagation Delay Time vs

Free-Air Temperature Figure 14. Driver High-to-Low Propagation Delay Time vs

Free-Air Temperature

Figure 15. Driver Output Current vs Supply Voltage Figure 16. Differential Driver Output Fall Time vs Source

Resistance (Rs)

Figure 17. Reference Voltage vs Reference Current

l TEXAS INSTRUMENTS OVDVGV NH

≈ 2.3 V

Dominant

Recessive

CANL

VOL

≈ 3 V VOH

≈ 1 V VOH

CANH CANH

CANL

167 Ω

–2 V ≤ VTEST ≤ 7 V

VOD

0 V 60 Ω167 Ω

VOD

0 V or 3 V

CANL

60 ΩCANH

VCC

SN65HVD230

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SN65HVD232

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9 Parameter Measurement Information

Figure 18. Driver Voltage and Current Definitions

Figure 19. Driver VOD

Figure 20. Driver Output Voltage Definitions

l TEXAS INSTRUMENTS Signal Generator (see Nole A) R5 : 0 I) In 100 k0 for SNSEHVD230 and SNESHVD23I lnpul Oulpul : VCANH + VCANL VCANH Vlc 2 VEANL \ —J7—

VIC +

VCANH )VCANL

VID

VCANL

VCANH

RL = 60 Ω

50 Ω

Signal

Generator

(see Note A)

CL = 50 pF

(see Note B)

90%

Output 0.9 V

10%

VOD(R)

VOD(D)

Input

0 V

3 V

tPHL

1.5 V

tPLH

RS = 0 Ω to 100 kΩ for SN65HVD230 and SN65HVD231

N/A for SN65HVD232

0.5 V

SN65HVD230

SN65HVD231

SN65HVD232

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Parameter Measurement Information (continued)

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤500 kHz, 50% duty cycle, tr≤6

ns, tf≤6 ns, Zo= 50 Ω.

B. CLincludes probe and jig capacitance.

Figure 21. Driver Test Circuit and Voltage Waveforms

Figure 22. Receiver Voltage and Current Definitions

l TEXAS INSTRUMENTS 500 cL :15 pF I (see Note B) 1000 Pulse Generator, 15 us Duration, 1% Duly Cycle %

100 Ω

Pulse Generator,

15 µs Duration,

1% Duty Cycle

50 Ω

Signal

Generator

(see Note A) CL = 15 pF

(see Note B)

1.5 V

90%

Output 1.3 V

10%

VOL

VOH

Input

1.5 V

2.9 V

tPHL

2.2 V

tPLH

Output

SN65HVD230

SN65HVD231

SN65HVD232

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Parameter Measurement Information (continued)

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤500 kHz, 50% duty cycle, tr≤6

ns, tf≤6 ns, Zo= 50 Ω.

B. CLincludes probe and jig capacitance.

Figure 23. Receiver Test Circuit and Voltage Waveforms

Figure 24. Overvoltage Protection

l TEXAS INSTRUMENTS Genevalov PRR = 150 kHz sac/a Duly Cycle 1,, I. < 6="" ns="" 20="" :="" 5n="" 0="" r="" oulpul="" 10kq="" signal="" genevalov="" vmsw="">

10 kΩ

0 V

CL = 15 pF

R Output 1.3 V

t(WAKE)

V(Rs) 1.5 V

50 Ω

Signal

Generator

PRR = 150 kHz

50% Duty Cycle

tr, tf < 6 ns

Zo = 50 Ω

V(Rs)

ROutput

VCC

0 V

VCC

60 Ω

–

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SN65HVD231

SN65HVD232

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Parameter Measurement Information (continued)

Table 1. Receiver Characteristics Over Common Mode With V(Rs) = 1.2 V

VIC VID VCANH VCANL R OUTPUT

-2 V 900 mV -1.55 V -2.45 V L

VOL

7 V 900 mV 8.45 V 6.55 V L

1 V 6 V 4 V -2 V L

4 V 6 V 7 V 1 V L

-2 V 500 mV -1.75 V -2.25 V H

VOH

7 V 500 mV 7.25 V 6.75 V H

1 V -6 V -2 V 4 V H

4 V -6 V 1 V 7 V H

X X Open Open H

Figure 25. t(WAKE) Test Circuit and Voltage Waveforms

l TEXAS INSTRUMENTS unwkﬂ

50%50%

50% 50%

DUT

CANH

CANL

60 Ω ±1%

15 pF ±20%

0 Ω, 10 kΩ or

100 kΩ ±5%

t(LOOP2)

VCC

0 V

VOH

VOL

t(LOOP1)

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A. All VIinput pulses are supplied by a generator having the following characteristics: tror tf≤6 ns, Pulse Repetition

Rate (PRR) = 125 kHz, 50% duty cycle.

Figure 26. t(LOOP) Test Circuit and Voltage Waveforms

l TEXAS INSTRUMENTS 7 Vcc 1km 3 CANH and CANL Outpuls Oulpul

VCC

D Input

1 kΩ

9 V

Input

100 kΩ

VCC

Output

16 V

CANH and CANL Outputs

20 V

VCC

5 Ω

9 V

Output

R Output

VCC

Input

16 V

CANH and CANL Inputs

20 V

110 kΩ

45 kΩ

9 kΩ

SN65HVD230

SN65HVD231

SN65HVD232

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Figure 27. Equivalent Input and Output Schematic Diagrams

l TEXAS INSTRUMENTS Logic Ink Control Medium Access Conlml Physical Signaling Physical Medium Attachment %

CANL

CANH

SN65HVD230, SN65HVD231

Logic Diagram (Positive Logic)

RS8

Vref

VCC

CANL

CANH

SN65HVD232

Logic Diagram (Positive Logic)

TMS320Lx2403/6/7

3.3-V

DSP

Implementation

ISO 11898 Specification

Application Specific Layer

Data-Link

Layer

Logic Link Control

Medium Access Control

Physical

Layer

Physical Signaling

Physical Medium Attachment

Medium Dependent Interface

Embedded

CAN

Controller

SN65HVD230

CAN Bus-Line

SN65HVD230

SN65HVD231

SN65HVD232

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10 Detailed Description

10.1 Overview

ISO 11898 family of standards are the international standard for high speed serial communication using the

controller area network (CAN) bus protocol and physical layers (transceivers). It supports multimaster operation,

real time control, programmable data rates up to 1 Mbps, and powerful redundant error checking procedures that

provide reliable data transmission. It is suited for networking intelligent devices as well as sensors and actuators

within the rugged electrical environment of a machine chassis or factory floor. The SN65HVD23x family of 3.3 V

CAN transceivers implement the lowest layers of the ISO/OSI reference model, the ISO11898-2 standard. This is

the interface with the physical signaling output of the CAN controller of the Texas Instruments µPs, MCUs and

DSPs, such as TMS320Lx240x 3.3 V DSPs, as illustrated in Figure 28.

Figure 28. Layered ISO 11898 Standard Architecture

10.2 Functional Block Diagram

Figure 29. Logic Diagram (Positive Logic)

l TEXAS INSTRUMENTS D E GND I: Vcc I: RE 0‘me ‘4ou waA

TMS320LF2406

TMS320LF2407

IOPF6

GND

VCC

CANH

CANL

Vref

SN65HVD230

SN65HVD231

SN65HVD232

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10.3 Feature Description

The SN65HVD230/231/232 are pin-compatible (but not functionally identical) with one another and, depending

upon the application, may be used with identical circuit boards.

These transceivers feature single 3.3 V supply operation and standard compatibility with signaling rates up to 1

Mbps, ±16 kV HBM ESD protection on the bus pins, thermal shutdown protection, bus fault protection, and open-

circuit receiver failsafe. The fail-safe design of the receiver assures a logic high at the receiver output if the bus

wires become open circuited.

The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free

power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also

means that an unpowered node does not disturb the bus. Transceivers without this feature usually have a very

low output impedance. This results in a high current demand when the transceiver is unpowered, a condition that

could affect the entire bus.

10.3.1 Vref Voltage Reference

The Vref pin (pin 5) on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference. This pin

can be connected to the common mode point of a split termination to help further stabilize the common mode

voltage of the bus. If the Vref pin is not used it may be left floating.

10.3.2 Thermal Shutdown

If a high ambient temperature or excessive output currents result in thermal shutdown, the driver will be disabled

and the bus pins become high impedance. During thermal shutdown the D pin to bus transmission path is

blocked and the CAN bus pins are high impedance and biased to a recessive level. Once the thermal shutdown

condition is cleared and the junction temperature drops below the thermal shutdown temperature the driver will

be reactivated and resume normal operation. During a thermal shutdown the receiver to R pin path remains

operational.

10.4 Device Functional Modes

The RSpin (Pin 8) of the SN65HVD230 and SN65HVD231 provides three different modes of operation: high-

speed mode, slope-control mode, and low-power mode.

10.4.1 High-Speed Mode

The high-speed mode can be selected by applying a logic low to the RSpin (pin 8). The high-speed mode of

operation is commonly employed in industrial applications. High-speed allows the output to switch as fast as

possible with no internal limitation on the output rise and fall slopes. If the high speed transitions are a concern

for emissions performance slope control mode can be used.

If both high speed mode and the low-power standby mode is to be used in the application, direct connection to a

µP, MCU or DSP general purpose output pin can be used to switch between a logic-low level (< 1.2 V) for high

speed operation, and the logic-high level (> 0.75 VCC) for standby. Figure 30 shows a typical DSP connection,

and Figure 31 shows the HVD230 driver output signal in high-speed mode on the CAN bus.

Figure 30. RS(Pin 8) Connection to a TMS320LF2406/07 for High Speed/Standby Operation

TEXAS INSTRUMENTS Tek Run: SUUVI'SIs Sam ple [ . Gil] 'soom' ' ' ' VI icon; ch4 '.r —s'00mv 10kQ D I: 1' a J—va—[ GND I: 2 7 ] Vcc I: 3 6 J R I: 4 5 ]

TMS320LF2406

TMS320LF2407

IOPF6

GND

VCC

CANH

CANL

Vref

10 kΩ

100 kΩ

1 Mbps

Driver Output

NRZ Data

SN65HVD230

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Device Functional Modes (continued)

Figure 31. Typical High Speed SN65HVD230 Output Waveform into a 60-ΩLoad

10.4.2 Slope Control Mode

Electromagnetic compatibility is essential in many applications while still making use of unshielded twisted pair

bus cable to reduce system cost. Slope control mode was added to the SN65HVD230 and SN65HVD231

devices to reduce the electromagnetic interference produced by the rise and fall times of the driver and resulting

harmonics. These rise and fall slopes of the driver outputs can be adjusted by connecting a resistor from RS(pin

8) to ground or to a logic low voltage, as shown in Figure 32. The slope of the driver output signal is proportional

to the pin's output current. This slope control is implemented with an external resistor value of 10 kΩto achieve a

~15 V/μs slew rate, and up to 100 kΩto achieve a ~2.0 V/μs slew rate as displayed in Figure 33.

Figure 32. Slope Control/Standby Connection to a DSP

Slope Control Resistance – kW

0 10 20 30 40 50 60 70 80 90

4.70 6.8 10 15 22 33 47 68 100

Driver Outout Signal Slope – V/ sm

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SN65HVD231

SN65HVD232

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Device Functional Modes (continued)

Figure 33. HVD230 Driver Output Signal Slope vs Slope Control Resistance Value

10.4.3 Standby Mode (Listen Only Mode) of the HVD230

If a logic high (> 0.75 VCC) is applied to RS(pin 8) in Figure 30 and Figure 32, the circuit of the SN65HVD230

enters a low-current, listen only standby mode, during which the driver is switched off and the receiver remains

active. In this listen only state, the transceiver is completely passive to the bus. It makes no difference if a slope

control resistor is in place as shown in Figure 32. The µP can reverse this low-power standby mode when the

rising edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The µP, sensing

bus activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on RS(pin 8).

10.4.4 The Babbling Idiot Protection of the HVD230

Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what is

referred to in CAN jargon as a babbling idiot). When this occurs, the µP, MCU or DSP can engage the listen-only

standby mode of the transceiver to disable the driver and release the bus, even when access to the CAN

controller has been lost. When the driver circuit is deactivated, its outputs default to a high-impedance state

(recessive).

10.4.5 Sleep Mode of the HVD231

The unique difference between the SN65HVD230 and the SN65HVD231 is that both driver and receiver are

switched off in the SN65HVD231 when a logic high is applied to RS(pin 8). The device remains in a very low

power-sleep mode until the circuit is reactivated with a logic low applied to RS(pin 8). While in this sleep mode,

the bus-pins are in a high-impedance state, while the D and R pins default to a logic high.

10.4.6 Summary of Device Operating Modes

Table 2 shows a summary of the operating modes for the SN65HVD230 and SN65HVD231. Please note that the

SN65HVD232 is a basic CAN transceiver has only the normal high speed mode of operation; pins 5 and 8 are no

connection (NC).

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Device Functional Modes (continued)

(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.

Table 2. SN65HVD230 and SN65HVD231 Operating Modes

RSPin MODE DRIVER RECEIVER RXD Pin

LOW, V(Rs) < 1.2 V, strong

pull down to GND High Speed Mode Enabled (ON) High

Speed Enabled (ON) Mirrors Bus State(1)

LOW, V(Rs) < 1.2 V, 10 kΩ

to 100 kΩpull down to

GND

Slope Control Mode Enabled (ON) with

Slope Control Enabled (ON) Mirrors Bus State

HIGH, V(Rs) > 0.75 VCC Low Current

Mode SN65HVD230: Standby

Mode Disabled (OFF) Enabled (ON) Mirrors Bus State

SN65HVD231: Sleep Mode Disabled (OFF) High

(1) H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance

Table 3. SN65HVD230 and SN65HVD231 Driver Functions

DRIVER (SN65HVD230, SN65HVD231)(1)

INPUT D RSOUTPUTS BUS STATE

CANH CANL

L V(Rs) < 1.2 V (including 10

kΩto 100 kΩpull down to

GND)

H L Dominant

H Z Z Recessive

Open X Z Z Recessive

X V(Rs) > 0.75 VCC Z Z Recessive

(1) H = high level; L = low level; X = irrelevant; ? = indeterminate

Table 4. SN65HVD230 Receiver Functions

RECEIVER (SN65HVD230)(1)

DIFFERENTIAL INPUTS RSOUTPUT R

VID ≥0.9 V X L

0.5 V < VID < 0.9 V X ?

VID ≤0.5 V X H

Open X H

(1) H = high level; L = low level; X = irrelevant; ? = indeterminate

Table 5. SN65HVD231 Receiver Functions

RECEIVER (SN65HVD231)(1)

DIFFERENTIAL INPUTS RSOUTPUT R

VID ≥0.9 V V(Rs) < 1.2 V (including 10 kΩto 100 kΩpull

down to GND)

0.5 V < VID < 0.9 V ?

VID ≤0.5 V H

X V(Rs) > 0.75 VCC H

X 1.2 V < V(Rs) < 0.75 VCC ?

Open X H

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(1) H = high level; L = low level; X = irrelevant; ? = indeterminate

Table 6. SN65HVD232 Receiver Functions

RECEIVER (SN65HVD232)(1)

DIFFERENTIAL INPUTS OUTPUT R

VID ≥0.9 V L

0.5 V < VID < 0.9 V ?

VID ≤0.5 V H

Open H

(1) H = high level; L = low level; Z = high impedance

Table 7. SN65HVD232 Driver Functions

DRIVER (SN65HVD232)(1)

INPUT D OUTPUTS BUS STATE

CANH CANL

L H L Dominant

H Z Z Recessive

Open Z Z Recessive

l TEXAS INSTRUMENTS ime, t

RXD

VCC/2

CANH

CANL

Recessive

Logic H

Dominant

Logic L

Recessive

Logic H

Time, t

Typical Bus Voltage (V)

CANL

CANH

Vdiff(D)

Vdiff(R)

1234

SN65HVD230

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SN65HVD232

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11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Application Information

This application section provides information concerning the implementation of the physical medium attachment

layer in a CAN network according to the ISO 11898 standard. It presents a typical application circuit and test

results, as well as discussions on slope control, total loop delay, and interoperability in 5-V CAN systems.

11.1.1 CAN Bus States

The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus

state is when the bus is driven differentially, corresponding to a logic low on the D and R pin. A recessive bus

state is when the bus is biased to VCC / 2 via the high-resistance internal resistors RIand RDiff of the receiver,

corresponding to a logic high on the D and R pins. See Figure 34 and Figure 35.

Figure 34. CAN Bus States (Physical Bit Representation)

Figure 35. Simplified Recessive Common Mode Bias and Receiver

{9 TEXAS INSTRUMENTS 1200 v v CAN Bus Line CANL

CANH

CANL

CAN Bus Line

ECU ECU ECU

1 2 n

120 Ω120 Ω

TMS320Lx2403/6/7

CAN Bus Line

CAN-Controller

CANTX/IOPC6

SN65HVD230

Electronic Control Unit (ECU)

CANH CANL

D R

CANRX/IOPC7

SN65HVD230

SN65HVD231

SN65HVD232

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11.2 Typical Application

Figure 36 illustrates a typical application of the SN65HVD23x family. The output of the host µP's CAN controller

(TXD) is connected to the transceivers driver input, pin D, and the transceivers receiver output, pin R, is

connected to the input of the CAN controller (RXD). The transceiver is attached to the differential bus lines at

pins CANH and CANL. Typically, the bus is a twisted pair of wires with a characteristic impedance of 120 Ω, in

the standard half-duplex multipoint topology of Figure 37. Each end of the bus is terminated with 120 Ωresistors

in compliance with the standard to minimize signal reflections on the bus.

Figure 36. Details of a Typical CAN Node

Figure 37. Typical CAN Network

11.2.1 Design Requirements

11.2.1.1 CAN Termination

The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with

120 Ωcharacteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used

to terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting

nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be on

the cable or in a node, but if nodes may be removed from the bus the termination must be carefully placed so

that it is not removed from the bus.

f i f I f I //

CAN

Transceiver

CANL

CANH

CSPLIT

CAN

Transceiver RTERM

Standard Termination Split Termination

CANL

CANH

R /2

TERM

R /2

TERM

MCU or DSP

CAN

Controller

CAN

Transceiver

Node 1

MCU or DSP

CAN

Controller

CAN

Transceiver

Node 2

MCU or DSP

CAN

Controller

CAN

Transceiver

Node 3

MCU or DSP

CAN

Controller

CAN

Transceiver

Node n

(with termination)

RTERM

SN65HVD230

SN65HVD231

SN65HVD232

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Typical Application (continued)

Figure 38. Typical CAN Bus

Termination is typically a 120 Ωresistor at each end of the bus. If filtering and stabilization of the common mode

voltage of the bus is desired, then split termination may be used (see Figure 39). Split termination utilizes two

60Ωresistors with a capacitor in the middle of these resistors to ground. Split termination improves the

electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common mode voltages

at the start and end of message transmissions.

Care should be taken in the power ratings of the termination resistors used. Typically the worst case condition

would be if the system power supply was shorted across the termination resistance to ground. In most cases the

current flow through the resistor in this condition would be much higher than the transceiver's current limit.

Figure 39. CAN Bus Termination Concepts

11.2.1.2 Loop Propagation Delay

Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the

driver input (D pin) to the differential outputs (CANH and CANL pins), plus the delay from the receiver inputs

(CANH and CANL) to its output (R pin).

l TEXAS INSTRUMENTS Tek Ium: 2 lJULiS/s U Sample [. .:r .. .. .. .. Driver \nput —> Receiver Output 24 ﬂoor Chz '1.oov‘ Misnns'Aux': —i1sv

( )

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Typical Application (continued)

A typical loop delay for the SN65HVD230 transceiver is displayed in Figure 40. This loop delay will increase as

the slope of the driver output is slowed during slope control mode. This increased loop delay means that there is

a tradeoff between the total bus length able to be used and the driver's output slope used via the slope control

pin of the device. For example, the loop delay for a 10-kΩresistor from the RSpin to ground is ~100 ns, and the

loop delay for a 100-kΩresistor is ~500 ns. Therefore, if we use the following rule-of-thumb that the propagation

delay of typical twisted pair bus cable is 5 ns/m, we can calculate an approximate cable length trade-off between

normal high-speed mode and slope control mode with a 100-kΩresistor. Using typical values, the loop delay for

a recessive to dominant bit with RStied directly to ground is 70ns, and with a 100-kΩresistor is 535 ns. At 5ns/m

of propagation delay, which you have to count in both directions the difference is 46.5 meters (535-70)/(2*5).

Another option to improving the elctromagnetic emissions of the device besides slowing down the edge rates of

the driver in slope control mode is using quality shielded bus cabling.

Figure 40. 70.7-ns Loop Delay Through the HVD230 With RS= 0

11.2.1.3 Bus Loading, Length and Number of Nodes

The ISO11898 Standard specifies up to 1 Mbps data rate, maximum bus length of 40 meters, maximum drop line

(stub) length of 0.3 meters and a maximum of 30 nodes. However, with careful network design, the system may

have longer cables, longer stub lengths, and many more nodes. Many CAN organizations and standards have

scaled the use of CAN for applications outside the original ISO11898 standard. They have made system level

trade-offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications

are ARINC825, CANopen, CAN Kingdom, DeviceNet and NMEA200.

A high number of nodes requires a transceiver with high input impedance and wide common mode range such

as the SN65HVD23x CAN family. ISO11898-2 specifies the driver differential output with a 60 Ωload (two 120 Ω

termination resistors in parallel) and the differential output must be greater than 1.5 V. The SN65HVD23x devices

are specified to meet the 1.5 V requirement with a 60 Ωload, and additionally specified with a differential output

voltage minimum of 1.2 V across a common mode range of –2 V to 7 V via a 167 Ωcoupling network. This

network represents the bus loading of 120 SN65HVD23x transceivers based on their minimum differential input

resistance of 40 kΩ. Therefore, the SN65HVD23x supports up to 120 transceivers on a single bus segment with

margin to the 1.2 V minimum differential input voltage requirement at each node. For CAN network design,

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Typical Application (continued)

margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances,

ground offsets and signal integrity thus a practical maximum number of nodes may be lower. Bus length may

also be extended beyond the original ISO11898 standard of 40 meters by careful system design and data rate

tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km with changes in

the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.

This flexibility in CAN network design is one of the key strengths of the various extensions and additional

standards that have been built on the original ISO11898 CAN standard. In using this flexibility comes the

responsibility of good network design.

11.2.2 Detailed Design Procedure

The following system level considerations should be looked at when designing your application. There are trade-

offs between the total number of nodes, the length of the bus, and the slope of the driver output that need to be

evaluated when building up a system

11.2.2.1 Transient Protection

Typical applications that use CAN will sometime require some form of ESD, burst, or surge protection

performance at the system level. If these requirements are higher than those of the device some form of external

protection may be needed to shield the transceiver against these high power transients that can cause damage.

Transient voltage suppressor (TVS) are very commonly used and can help clamp the amount of energy that

reaches the transceiver.

11.2.2.2 Transient Voltage Suppressors

Transient voltage suppressors are the preferred protection components for CAN bus applications due to their low

capacitance, fast response times and high peak power dissipation limits. The low bus capacitance allows these

devices to be used at many, if not all, nodes on the network without having to reduce the data rate. The quick

response times in the order of a few picoseconds enable these devices to clamp the energy of very fast

transients like ESD and EFT. Lastly, the high peak power ratings enable these devices to handle high energy

surge pulses without being damaged.

11.2.3 Application Curve

Typical driver output waveforms from a pulse input signal with different slope control resistances are displayed in

Figure 41. The top waveform show the typical differential signal when transitioning from a recessive level to a

dominant level on the CAN bus with RS tied to GND through a zero ohm resistor. The second waveform shows

the same signal for the condition with a 10k ohm resistor tied from RSto ground. The bottom waveform shows

the typical differential signal for the case where a 100k ohm resistor is tied from the RSpin to ground.

l TEXAS INSTRUMENTS Tek Run: 250MS/s Sample [ Y , 1 ChZ 1.00V M 200ns Aux! 3.20V

RS = 0 Ω

RS = 10 kΩ

RS = 100 kΩ

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

www.ti.com

Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

Typical Application (continued)

Figure 41. Typical SN65HVD230 250-kbps Output Pulse Waveforms With Slope Control

11.3 System Example

11.3.1 ISO 11898 Compliance of SN65HVD23x Family of 3.3 V CAN Transceivers

11.3.1.1 Introduction

Many users value the low power consumption of operating their CAN transceivers from a 3.3 V supply. However,

some are concerned about the interoperability with 5 V supplied transceivers on the same bus. This report

analyzes this situation to address those concerns.

11.3.1.2 Differential Signal

CAN is a differential bus where complementary signals are sent over two wires and the voltage difference

between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage

difference and outputs the bus state with a single-ended output signal.

l TEXAS INSTRUMENTS Em soomv

75% SAMPLEPOINT

500 mVThreshold

900 mVThreshold

NOISEMARGIN

RECEIVERDETECTIONWINDOW

SN65HVD230

SN65HVD231

SN65HVD232

www.ti.com

SLOS346O –MARCH 2001–REVISED APRIL 2018

Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

System Example (continued)

Figure 42. Typical SN65HVD230 Differential Output Voltage Waveform

The CAN driver creates the differential voltage between CANH and CANL in the dominant state. The dominant

differential output of the SN65HVD23x is greater than 1.5 V and less than 3 V across a 60 ohm load as defined

by the ISO 11898 standard. These are the same limiting values for 5 V supplied CAN transceivers. Typically, the

bus termination resistors drive the bus back to the recessive bus state and not the CAN driver.

A CAN receiver is required to output a recessive state when less than 500 mV of differential voltage exists on the

bus, and a dominant state when more than 900 mV of differential voltage exists on the bus. The CAN receiver

must do this with common-mode input voltages from -2 V to 7 volts per the ISO 11898-2 standard. The

SN65HVD23x family receivers meet these same input specifications as 5 V supplied receivers.

11.3.1.2.1 Common Mode Signal

A common-mode signal is an average voltage of the two signal wires that the differential receiver rejects. The

common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Since the bias voltage

of the recessive state of the device is dependent on VCC, any noise present or variation of VCC will have an effect

on this bias voltage seen by the bus. The SN65HVD23x family has the recessive bias voltage set higher than

0.5*VCC to comply with the ISO 11898-2 CAN standard which states that the recessive bias voltage must be

between 2 V and 3 V. The caveat to this is that the common mode voltage will drop by a couple hundred

millivolts when driving a dominant bit on the bus. This means that there is a common mode shift between the

dominant bit and recessive bit states of the device. While this is not ideal, this small variation in the driver

common-mode output is rejected by differential receivers and does not effect data, signal noise margins or error

rates.

11.3.1.3 Interoperability of 3.3-V CAN in 5-V CAN Systems

The 3.3 V supplied SN65HVD23x family of CAN transceivers are fully compatible with 5 V CAN transceivers. The

differential output voltage is the same, the recessive common mode output bias is the same, and the receivers

have the same input specifications. The only difference is in the dominant common mode output voltage is lower

in 3.3 V CAN transceivers than with 5 V supplied transceiver (by a few hundred millivolts).

To help ensure the widest interoperability possible, the SN65HVD23x family has successfully passed the

internationally recognized GIFT ICT conformance and interoperability testing for CAN transceivers which is

shown in . Electrical interoperability does not always assure interchangeability however. Most implementers of

CAN buses recognize that ISO 11898 does not sufficiently specify the electrical layer and that strict standard

compliance alone does not ensure full interchangeability. This comes only with thorough equipment testing.

l TEXAS INSTRUMENTS

SN65HVD230

One Meter Belden Cable # 3105A

Competitor X251SN65HVD230 SN65HVD251

120 W120 W

TEKTRONIX

HFS-9003

Pattern

Generator

Trigger

Input

TEKTRONIX

784D

Oscilloscope

TEKTRONIX

P6243

Single-Ended

Probes

HP E3516A

3.3-VPower

Supply

HP E3516A

5-VPower

Supply

+ +

– –

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

www.ti.com

Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

System Example (continued)

Figure 43. 3.3-V and 5-V CAN Transceiver System Testing

12 Power Supply Recommendations

The SN65HVD23x 3.3 V CAN transceivers provide the interface between the 3.3 V µPs, MCUs and DSPs and

the differential bus lines, and are designed to transmit data at signaling rates up to 1 Mbps as defined by the ISO

11898 standard.

To ensure reliable operation at all data rates and supply voltages, the VCC supply pin of each CAN transceiver

should be decoupled with a 100-nF ceramic capacitor located as close to the VCC and GND pins as possible. The

TPS76333 is a linear voltage regulator suitable for supplying the 3.3-V supply.

l TEXAS INSTRUMENTS

SN65HVD230

SN65HVD231

SN65HVD232

www.ti.com

SLOS346O –MARCH 2001–REVISED APRIL 2018

Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

13 Layout

13.1 Layout Guidelines

In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because

ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency

layout techniques must be applied during PCB design. On chip IEC ESD protection is good for laboratory and

portable equipment but is usually not sufficient for EFT and surge transients occurring in industrial environments.

Therefore robust and reliable bus node design requires the use of external transient protection devices at the bus

connectors. Placement at the connector also prevents these harsh transient events from propagating further into

the PCB and system.

Use VCC and ground planes to provide low inductance. Note: high frequency current follows the path of least

inductance and not the path of least resistance.

Design the bus protection components in the direction of the signal path. Do not force the transient current to

divert from the signal path to reach the protection device.

An example placement of the Transient Voltage Suppression (TVS) device indicated as D1 (either bi-directional

diode or varistor solution) and bus filter capacitors C8 and C9 are shown in .

The bus transient protection and filtering components should be placed as close to the bus connector, J1, as

possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing other devices.

Bus termination: Figure 44 shows split termination. This is where the termination is split into two resistors, R7

and R8, with the center or split tap of the termination connected to ground via capacitor C7. Split termination

provides common mode filtering for the bus. When termination is placed on the board instead of directly on the

bus, care must be taken to ensure the terminating node is not removed from the bus as this will cause signal

integrity issues of the bus is not properly terminated on both ends. See the application section for information on

power ratings needed for the termination resistor(s).

Bypass and bulk capacitors should be placed as close as possible to the supply pins of transceiver, examples

C2, C3 (VCC).

Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize

trace and via inductance.

To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3 and R4.

To filter noise on the digital IO lines, a capacitor may be used close to the input side of the IO as shown by C1

and C4.

Since the internal pull up and pull down biasing of the device is weak for floating pins, an external 1k to 10k ohm

pull-up or down resistor should be used to bias the state of the pin more strongly against noise during transient

events.

Pin 1: If an open drain host processor is used to drive the D pin of the device an external pull-up resistor

between 1k and 10k ohms should be used to drive the recessive input state of the device (R1).

Pin 8: is shown assuming the mode pin, RS, will be used. If the device will only be used in normal mode or slope

control mode, R3 is not needed and the pads of C4 could be used for the pull down resistor to GND.

Pin 5 in is shown for the SN65HVD230 and SN65HVD231 devices which have a Vref output voltage reference. If

used, this pin should be tied to the common mode point of the split termination. If this feature is not used, the pin

can be left floating.

For the SN65HVD232, pins 5 and 8 are no connect (NC) pin. This means that the pins are not internally

connected and can be left floating.

l TEXAS INSTRUMENTS

GND

RXD

VCC

TXD

GND

C8 C9

GND

Vref can be routed

under the device

VCC R1

SN65HVD230

SN65HVD231

SN65HVD232

SLOS346O –MARCH 2001–REVISED APRIL 2018

www.ti.com

Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

13.2 Layout Example

Figure 44. SN65HVD23x Board Layout

l TEXAS INSTRUMENTS

SN65HVD230

SN65HVD231

SN65HVD232

www.ti.com

SLOS346O –MARCH 2001–REVISED APRIL 2018

Product Folder Links: SN65HVD230 SN65HVD231 SN65HVD232

14 Device and Documentation Support

14.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 8. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

SN65HVD230 Click here Click here Click here Click here Click here

SN65HVD231 Click here Click here Click here Click here Click here

SN65HVD232 Click here Click here Click here Click here Click here

14.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

14.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

14.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

14.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN65HVD230D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP230

SN65HVD230DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP230

SN65HVD230DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP230

SN65HVD230DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP230

SN65HVD231D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP231

SN65HVD231DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP231

SN65HVD231DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP231

SN65HVD231DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP231

SN65HVD232D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP232

SN65HVD232DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP232

SN65HVD232DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP232

SN65HVD232DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP232

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pi» Reel Diame|er AD Dimension designed to accommodate the componeni width ED Dimension deSigned to eccemmodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w Overeii Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN65HVD230DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65HVD231DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65HVD232DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN65HVD230DR SOIC D 8 2500 340.5 336.1 25.0

SN65HVD231DR SOIC D 8 2500 340.5 336.1 25.0

SN65HVD232DR SOIC D 8 2500 340.5 336.1 25.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

SN65HVD230D D SOIC 8 75 507 8 3940 4.32

SN65HVD230DG4 D SOIC 8 75 507 8 3940 4.32

SN65HVD231D D SOIC 8 75 507 8 3940 4.32

SN65HVD231DG4 D SOIC 8 75 507 8 3940 4.32

SN65HVD232D D SOIC 8 75 507 8 3940 4.32

SN65HVD232DG4 D SOIC 8 75 507 8 3940 4.32

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN65HVD230-32 Datasheet by Texas Instruments

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