OPA333, 2333 Datasheet by Texas Instruments

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OPA333
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OPAx333 1.8-V, microPower, CMOS Operational Amplifiers, Zero-Drift Series
1 Features 3 Description
The OPAx333 series of CMOS operational amplifiers
1 Low Offset Voltage: 10 μV (Maximum) use a proprietary auto-calibration technique to
Zero Drift: 0.05 μV/°C (Maximum) simultaneously provide very low offset voltage
0.01-Hz to 10-Hz Noise: 1.1 μVPP (10 μV, maximum) and near-zero drift over time and
temperature. These miniature, high-precision, low
Quiescent Current: 17 μAquiescent current amplifiers offer high-impedance
Single-Supply Operation inputs that have a common-mode range 100 mV
Supply Voltage: 1.8 V to 5.5 V beyond the rails, and rail-to-rail output that swings
within 50 mV of the rails. Single or dual supplies as
Rail-to-Rail Input/Output low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V) can
microSize Packages: SC70 and SOT23 be used. These devices are optimized for low-
voltage, single-supply operation.
2 Applications The OPAx333 family offers excellent CMRR without
• Transducers the crossover associated with traditional
Temperature Measurements complementary input stages. This design results in
Electronic Scales superior performance for driving analog-to-digital
converters (ADCs) without degradation of differential
Medical Instrumentation linearity.
Battery-Powered Instruments The OPA333 (single version) is available in the 5-pin
Handheld Test Equipment SOT-23, SOT, and 8-pin SOIC packages, while the
OPA2333 (dual version) is available in the 8-pin
VSON, SOIC, and VSSOP packages. All versions are
specified for operation from –40°C to 125°C.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOT-23 (5) 2.90 mm × 1.60 mm
OPA333 SOT (5) 2.00 mm x 1.25 mm
SOIC (8) 4.90 mm × 3.90 mm
VSON (8) 3.00 mm × 3.00 mm
OPA2333 SOIC (8) 4.90 mm × 3.90 mm
VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
0.1-Hz to 10-Hz Noise OPAx333 Pinout Diagrams
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 15
8.1 Application Information............................................ 15
2 Applications ........................................................... 18.2 Typical Applications ............................................... 15
3 Description ............................................................. 18.3 System Examples ................................................... 20
4 Revision History..................................................... 29 Power Supply Recommendations...................... 22
5 Pin Configuration and Functions......................... 310 Layout................................................................... 23
6 Specifications......................................................... 510.1 Layout Guidelines ................................................. 23
6.1 Absolute Maximum Ratings ...................................... 510.2 Layout Example .................................................... 23
6.2 ESD Ratings.............................................................. 511 Device and Documentation Support ................. 24
6.3 Recommended Operating Conditions....................... 511.1 Device Support...................................................... 24
6.4 Thermal Information: OPA333 .................................. 611.2 Documentation Support ........................................ 24
6.5 Thermal Information: OPA2333 ................................ 611.3 Related Links ........................................................ 24
6.6 Electrical Characteristics........................................... 711.4 Community Resources.......................................... 24
6.7 Typical Characteristics.............................................. 811.5 Trademarks........................................................... 24
7 Detailed Description............................................ 12 11.6 Electrostatic Discharge Caution............................ 24
7.1 Overview ................................................................. 12 11.7 Glossary................................................................ 25
7.2 Functional Block Diagram....................................... 12 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 12 Information ........................................................... 25
7.4 Device Functional Modes........................................ 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (November 2013) to Revision E Page
Added Pin Configuration and Functions section, ESD Ratings and Thermal Information tables, Feature Description
section, Device Functional Modes,Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
Changes from Revision C (May 2007) to Revision D Page
Changed data sheet format to most current standard look and feel...................................................................................... 1
Added OPA2333 DFN-8 pinout to front page......................................................................................................................... 1
Changed 2nd signal input terminals parameter in the Absolute Maximum Ratings from "voltage" to "current" (typo).......... 5
Added Table 1 ........................................................................................................................................................................ 8
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5 Pin Configuration and Functions
OPA333 DBV Package OPA333 DCK Package
5-Pin SOT 5-Pin SC70
Top View Top View
OPA333 D Package
8-Pin SOIC
Top View
Pin Functions: OPA333
PIN I/O DESCRIPTION
NAME SOIC SOT SC70
+IN 3 3 1 I Noninverting input
–IN 2 4 3 I Inverting input
NC 1, 5, 8 No internal connection (can be left floating)
OUT 6 1 4 O Output
V+ 7 5 5 Positive (highest) power supply
V– 4 2 2 Negative (lowest) power supply
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OPA333
,
OPA2333
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OPA2333 DRB Package OPA2333 D or DGK Package
8-Pin VSON With Exposed Thermal Pad 8-Pin SOIC or VSSOP
Top View Top View
Pin Functions: OPA2333
PIN I/O DESCRIPTION
NAME VSON SOIC, VSSOP
+IN I Noninverting input
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
–IN I Inverting input
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
OUT O Output
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
V+ 8 8 Positive (highest) power supply
V– 4 4 Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
Supply 7
Voltage V
Signal input terminals(2) –0.3 (V+) + 0.3
Signal input terminals(2) –1 1
Current mA
Output short-circuit(3) Continuous
Operating junction temperature, TJ150
Operating temperature, TA–40 150 °C
Storage temperature, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000
Electrostatic
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, VS1.8 5.5 V
Specified temperature –40 125 °C
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6.4 Thermal Information: OPA333
OPA333
THERMAL METRIC(1) D (SOIC) DBV (SOT) DCK (SC70) UNIT
8 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 140.1 220.8 298.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 89.8 97.5 65.4 °C/W
RθJB Junction-to-board thermal resistance 80.6 61.7 97.1 °C/W
ψJT Junction-to-top characterization parameter 28.7 7.6 0.8 °C/W
ψJB Junction-to-board characterization parameter 80.1 61.1 95.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2333
OPA2333
THERMAL METRIC(1) D (SOIC) DGK (VSSOP) DRB (VSON) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 124.0 180.3 46.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.7 48.1 26.3 °C/W
RθJB Junction-to-board thermal resistance 64.4 100.9 22.2 °C/W
ψJT Junction-to-top characterization parameter 18.0 2.4 1.6 °C/W
ψJB Junction-to-board characterization parameter 63.9 99.3 22.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 10.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.6 Electrical Characteristics
At TA= 25°C, RL= 10 kconnected to VS/ 2, VCM = VS/ 2, and VOUT = VS/ 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS= 5 V 2 10 μV
dVOS/dT Input offset voltage drift TA= –40°C to 125°C 0.02 0.05 μV/°C
PSRR Power-supply rejection ratio VS= 1.8 V to 5.5 V, TA= –40°C to 125°C 1 5 μV/V
Long-term stability(1) See note (1) µV
Channel separation, dc 0.1 μV/V
INPUT BIAS CURRENT
TA= 25°C ±70 ±200
IBInput bias current TA= –40°C to 125°C ±150 pA
IOS Input offset current ±140 ±400
NOISE
f = 0.01 Hz to 1 Hz 0.3
Input voltage noise μVPP
f = 0.1 Hz to 10 Hz 1.1
inInput current noise f = 10 Hz 100 fA/Hz
INPUT VOLTAGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
(V–) – 0.1 V < VCM < (V+) + 0.1 V,
CMRR Common-mode rejection ratio 106 130 dB
TA= –40°C to 125°C
INPUT CAPACITANCE
Differential 2 pF
Common-mode 4 pF
OPEN-LOOP GAIN
(V–) + 100 mV < VO< (V+) – 100 mV,
AOL Open-loop voltage gain 106 130 dB
RL= 10 k, TA= –40°C to 125°C
FREQUENCY RESPONSE
GBW Gain-bandwidth product CL= 100 pF 350 kHz
SR Slew rate G = +1 0.16 V/μs
OUTPUT
RL= 10 k30 50
Voltage output swing from rail mV
RL= 10 k, TA= –40°C to 125°C 70
ISC Short-circuit current ±5 mA
CLCapacitive load drive See Typical Characteristics
Open-loop output impedance f = 350 kHz, IO= 0 A 2 k
POWER SUPPLY
VSSpecified voltage range 1.8 5.5 V
IO= 0 A 17 25
IQQuiescent current per amplifier μA
TA= –40°C to 125°C 28
Turn-on time VS= +5 V 100 μs
TEMPERATURE
Specified range –40 125 °C
TAOperating range –40 150 °C
Tstg Storage range –65 150 °C
(1) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.
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OPA333
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6.7 Typical Characteristics
Table 1. List of Typical Characteristics
TITLE FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Production Distribution Figure 2
Open-Loop Gain vs Frequency Figure 3
Common-Mode Rejection Ratio vs Frequency Figure 4
Power-Supply Rejection Ratio vs Frequency Figure 5
Output Voltage Swing vs Output Current Figure 6
Input Bias Current vs Common-Mode Voltage Figure 7
Input Bias Current vs Temperature Figure 8
Quiescent Current vs Temperature Figure 9
Large-Signal Step Response Figure 10
Small-Signal Step Response Figure 11
Positive Overvoltage Recovery Figure 12
Negative Overvoltage Recovery Figure 13
Settling Time vs Closed-Loop Gain Figure 14
Small-Signal Overshoot vs Load Capacitance Figure 15
0.1-Hz to 10-Hz Noise Figure 16
Current and Voltage Noise Spectral Density vs Frequency Figure 17
At TA= 25°C, VS= 5 V, and CL= 0 pF, unless otherwise noted.
Figure 2. Offset Voltage Drift Production Distribution
Figure 1. Offset Voltage Production Distribution
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l TEXAS INSTRUMENTS 120 250 we Frequency (Hz) ‘20 ‘H 3 rPSRR Output Current (mA) mm 200 Temperature (c)
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At TA= 25°C, VS= 5 V, and CL= 0 pF, unless otherwise noted.
Figure 4. Common-Mode Rejection Ratio vs Frequency
Figure 3. Open-Loop Gain and Phase vs Frequency
Figure 5. Power-Supply Rejection Ratio vs Frequency Figure 6. Output Voltage Swing vs Output Current
Figure 7. Input Bias Current vs Common-Mode Voltage Figure 8. Input Bias Current vs Temperature
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Settling Time ( s)m
1
600
500
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200
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100
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0.01%
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2 V/div
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Input
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10 kW
1 kW
OPA333
+2.5 V
-2.5 V
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10 kW
1 kW
OPA333
+2.5 V
-2.5 V
Time (50 s/div)m
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Time (5 s/div)m
G = +1
R = 10 kW
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Time (50 s/div)m
G = 1
R = 10 kW
L
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At TA= 25°C, VS= 5 V, and CL= 0 pF, unless otherwise noted.
Figure 9. Quiescent Current vs Temperature Figure 10. Large-Signal Step Response
Figure 11. Small-Signal Step Response Figure 12. Positive Overvoltage Recovery
Figure 13. Negative Overvoltage Recovery Figure 14. Settling Time vs Closed-Loop Gain
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At TA= 25°C, VS= 5 V, and CL= 0 pF, unless otherwise noted.
Figure 16. 0.1-Hz to 10-Hz Noise
Figure 15. Small-Signal Overshoot
vs Load Capacitance
Figure 17. Current and Voltage Noise Spectral Density vs Frequency
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+IN
-IN
CHOP1 CHOP2 Notch
Filter
GM_FF
GM2 GM3
C2
C1
OUT
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7 Detailed Description
7.1 Overview
The OPAx333 is a family of Zero-Drift, low-power, rail-to-rail input and output operational amplifiers. These
devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The Zero-Drift architecture provides ultra low offset voltage and near-zero offset voltage drift.
7.2 Functional Block Diagram
7.3 Feature Description
The OPA333 and OPA2333 are unity-gain stable and free from unexpected output phase reversal. These
devices use a proprietary auto-calibration technique to provide low offset voltage and very low drift over time and
temperature. For lowest offset voltage and precision performance, optimize circuit layout and mechanical
conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple
junctions formed from connecting dissimilar conductors. Cancel these thermally-generated potentials by assuring
they are equal on both input terminals. Other layout and design considerations include:
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
Thermally isolate components from power supplies or other heat sources.
Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
7.3.1 Operating Voltage
The OPA333 and OPA2333 operational amplifiers operate over a power-supply range of 1.8 V to 5.5 V (±0.9 V to
±2.75 V). Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics
section.
CAUTION
Supply voltages higher than +7 V (absolute maximum) can permanently damage the
device.
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VOUT
R = 20 kW
P
Op Amp V = GND-
OPA333
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+5 V
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VOUT
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Current-limiting resistor
required if input voltage
exceeds supply rails by
³0.5 V.
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Feature Description (continued)
7.3.2 Input Voltage
The OPA333 and OPA2333 input common-mode voltage range extends 0.1 V beyond the supply rails. The
OPA333 is designed to cover the full range without the troublesome transition region found in some other rail-to-
rail amplifiers.
Typically, input bias current is approximately 70 pA; however, input voltages that exceed the power supplies can
cause excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply
can be tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input
resistor, as shown in Figure 18.
Figure 18. Input Current Protection
7.3.3 Internal Offset Correction
The OPA333 and OPA2333 operational amplifiers use an auto-calibration technique with a time-continuous
350-kHz operational amplifier in the signal path. This amplifier is zero-corrected every 8 μs using a proprietary
technique. Upon power up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This
design has no aliasing or flicker noise.
7.3.4 Achieving Output Swing to the Op Amp Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply operational amplifiers, problems arise when the output signal
approaches 0 V, near the lower output swing limit of a single-supply operational amplifier. A good, single-supply
operational amplifier may swing close to single-supply ground, but does not reach ground. The output of the
OPA333 and OPA2333 can be made to swing to, or slightly below, ground on a single-supply power source. This
swing is achieved with the use of the use of another resistor and an additional, more negative power supply than
the operational amplifier negative supply. A pulldown resistor can be connected between the output and the
additional negative supply to pull the output down below the value that the output would otherwise achieve, as
shown in Figure 19.
Figure 19. VOUT Range to Ground
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Feature Description (continued)
The OPA333 and OPA2333 have an output stage that allows the output voltage to be pulled to the negative
supply rail, or slightly below, using the technique previously described. This technique only works with some
types of output stages. The OPA333 and OPA2333 are characterized to perform with this technique; the
recommended resistor value is approximately 20 k.
NOTE
This configuration increases the current consumption by several hundreds of microamps.
Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occur below –2 mV, but
excellent accuracy returns after the output is again driven above –2 mV. Lowering the resistance of the pulldown
resistor allows the operational amplifier to swing even further below the negative rail. Resistances as low as
10 kcan be used to achieve excellent accuracy down to –10 mV.
7.3.5 DFN Package
The OPA2333 is offered in an DFN-8 package (also known as SON). The DFN is a QFN package with lead
contacts on only two sides of the bottom of the package. This leadless package maximizes board space and
enhances thermal and electrical characteristics through an exposed pad.
DFN packages are physically small, have a smaller routing area, improved thermal performance, and improved
electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard PCB assembly techniques. See Application Reports
SLUA271,QFN/SON PCB Attachment and SCBA017,Quad Flatpack No-Lead Logic Packages, both are
available for download at www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the package should be connected to V–
or left unconnected.
7.4 Device Functional Modes
The OPAx333 device has a single functional mode. The device is powered on as long as the power supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
14 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
V+
ILOAD
A1
A2
Q1
Q2
+
+
+
±
VIN
RLOAD
RS1
RS2 RS3
IRS1
IRS2 IRS3
VRS2 VRS3
VRS1 VLOAD
V+
C6
C7
R3
R5
R4
R2
470 4.7
2200 pF
330
10 k
200
1000 pF
10 k
2 k
OPA333
,
OPA2333
www.ti.com
SBOS351E MARCH 2006REVISED DECEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx333 family is a unity-gain stable, precision operational amplifier with very low offset voltage drift; these
devices are also free from output phase reversal. Applications with noisy or high-impedance power supplies
require decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are
adequate.
8.2 Typical Applications
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 20 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V
to 2 V to and output current of 0 mA to 100 mA. Figure 21 shows the measured transfer function for this circuit.
The low offset voltage and offset drift of the OPA333 facilitate excellent dc accuracy for the circuit.
Figure 20. High-Side Voltage-to-Current (V-I) Converter
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: OPA333 OPA2333
l TEXAS INSTRUMENTS 01
Input Voltage (V)
Output Current (A)
0 0.5 1 1.5
0
0.025
0.05
0.1
Load
0.075
2
D001
OPA333
,
OPA2333
SBOS351E –MARCH 2006REVISED DECEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.1.1 Design Requirements
The design requirements are as follows:
Supply Voltage: 5 V DC
Input: 0 V to 2 V DC
Output: 0 mA to 100 mA DC
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2333 CMOS operational amplifier is a high-
precision, 5-uV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 50 mV of the positive rail. The OPA2333 family uses chopping techniques to provide low initial
offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset
error in the system, making these devices appropriate for precise dc control. The rail-to-rail output stage of the
OPA2333 ensures that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in TIPD102.
8.2.1.3 Application Curve
Figure 21. Measured Transfer Function for High-Side V-I Converter
16 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
+
R3 100 k
C1 10 nFR4 100 k
VIN
+
OPA333
5 V
Rset
100 k
RLOAD IOUT
+
AM1
A
±
R1
R1
R2
U2
INA326
R1
40.2 k
5 V
VOUT_OPA
VOUT_INA
R2
200 kC2 1 nF
+
OPA333
,
OPA2333
www.ti.com
SBOS351E MARCH 2006REVISED DECEMBER 2015
Typical Applications (continued)
8.2.2 Precision, Low-Level Voltage-to-Current (V-I) Converter
The circuit shown in Figure 22 is a precision, low-level voltage-to-current (V-I) converter. The converter translates
in input voltage of 0 V to 5 V and output current of 0 µA to 5 µA. Figure 23 shows the measured transfer function
for this circuit. The low offset voltage and offset drift of the OPA333 facilitate excellent dc accuracy for the circuit.
Figure 24 shows the calibrated error for the entire range of the circuit.
Figure 22. Low-Level, Precision V-I Converter
8.2.2.1 Design Requirements
The design requirements are as follows:
Supply Voltage: 5 V DC
Input: 0 V to 5 V DC
Output: 0 μA to 5 μA DC
8.2.2.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, RSET, and the
instrumentation amplifier (INA) gain. During operation, the input voltage divided by the INA gain appears across
the set resistor in Equation 1:
VSET = VIN/GINA (1)
The current through RSET must flow through the load, so IOUT is VSET / RSET. IOUT remains a well-regulated current
as long as the total voltage across RSET and RLOAD does not violate the output limits of the operational amplifier
or the input common-mode limits of the INA. The voltage across the set resistor (VSET) is the input voltage
divided by the INA gain (that is, VSET = 1 V / 10 = 0.1 V). The current is determined by VSET and RSET shown in
Equation 2:
IOUT = VSET / RSET = 0.1 V / 100 kΩ= 1 μA (2)
A detailed error analysis, design procedure, and additional measured results are given in TIPD107.
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: OPA333 OPA2333
l TEXAS INSTRUMENTS
AVDD
AVDD
AVDD AVDD
AVDD
VCM 10
10nF
0.2
10µF
Vin
Temp
Gnd
Vout
Trim
REF5045
1µF
1k
1µF
+
-
+
THS4281
1k
1µF +
-
+
OPA333
20k
1µF
VIN+
+
VIN-
++
THS4521
V+
AINP
AINM
REFP
GND
AVDD
CONVST
CONVST
ADS8881
10
INPUT DRIVER
REFERENCE DRIVE CIRCUIT
18-Bit 1MSPS
SAR ADC
-
-
1K 1K
1K 1K
+
Input Voltage (V)
Output Current (µA)
0 1 23
0
0.025
0.05
0.1
0.075
5
D002
4
Desired Output Current, (µA)Iout_desired
Measured Output Current Error (pA)
0 1 23
–100
40
100
60
5
D002
4
80
20
0
–20
–40
–60
–80
OPA333
,
OPA2333
SBOS351E –MARCH 2006REVISED DECEMBER 2015
www.ti.com
Typical Applications (continued)
8.2.2.3 Application Curves
Figure 23. Measured Transfer Function for Low-Level Figure 24. Calibrated Output Error for Low-Level V-I
Precision V-I
8.2.3 Composite Amplifier
The circuit shown in Figure 25 is a composite amplifier used to drive the reference on the ADS8881. The
OPA333 provides excellent dc accuracy, and the THS4281 allows the output of the circuit to respond quickly to
the transient current requirements of a typical SAR data converter reference input. The ADS8881 system was
optimized for THD and achieved a measured performance of –110 dB. The linearity of the ADC is shown
Figure 26.
Figure 25. Composite Amplifier Reference Driver Circuit
18 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
l TEXAS INSTRUMENTS 15
ADC Differential Input
Integral Non-Linearity Error (LSB)
–4.5 –3.5
–1.5
–1
0
1.5
D002
–2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5
–0.5
0.5
1
OPA333
,
OPA2333
www.ti.com
SBOS351E MARCH 2006REVISED DECEMBER 2015
Typical Applications (continued)
8.2.3.1 Design Requirements
The design requirements for this block design are:
System Supply Voltage: 5 V DC
ADC Supply Voltage: 3.3 V DC
ADC Sampling Rate: 1 MSPS
ADC Reference Voltage (VREF): 4.5 V DC
ADC Input Signal: A differential input signal with amplitude of Vpk = 4.315 V (–0.4 dBFS to avoid clipping) and
frequency, fIN = 10 kHz are applied to each differential input of the ADC
8.2.3.2 Detailed Design Procedure
The two primary design considerations to maximize the performance of a high-resolution SAR ADC are the input
driver and the reference driver design. The circuit comprises the critical analog circuit blocks, the input driver,
anti-aliasing filter, and the reference driver. Each analog circuit block should be carefully designed based on the
ADC performance specifications in order to maximize the distortion and noise performance of the data
acquisition system while consuming low power. The diagram includes the most important specifications for each
individual analog block. This design systematically approaches the design of each analog circuit block to achieve
a 16-bit, low-noise and low-distortion data acquisition system for a 10-kHz sinusoidal input signal. The first step
in the design requires an understanding of the requirement of extremely low distortion input driver amplifier. This
understanding helps in the decision of an appropriate input driver configuration and selection of an input amplifier
to meet the system requirements. The next important step is the design of the anti-aliasing RC-filter to attenuate
ADC kick-back noise while maintaining the amplifier stability. The final design challenge is to design a high-
precision reference driver circuit, which would provide the required value VREF with low offset, drift, and noise
contributions.
In designing a very low distortion data acquisition block, it is important to understand the sources of nonlinearity.
Both the ADC and the input driver introduce nonlinearity in a data acquisition block. To achieve the lowest
distortion, the input driver for a high-performance SAR ADC must have a distortion that is negligible against the
ADC distortion. This parameter requires the input driver distortion to be 10 dB lower than the ADC THD. This
stringent requirement ensures that overall THD of the system is not degraded by more than –0.5 dB.
THDAMP < THDADC – 10 dB (3)
It is therefore important to choose an amplifier that meets the above criteria to avoid the system THD from being
limited by the input driver. The amplifier nonlinearity in a feedback system depends on the available loop gain. A
detailed error analysis, design procedure, and additional measured results are given in TIPD115.
8.2.3.3 Application Curve
Figure 26. Linearity of the ADC8881 System
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: OPA333 OPA2333
m 3%
OPA333
ADS1100
Load
V
I C
2
R1
4.99 kW
R3
4.99 kW
R4
48.7 kW
R2
49.9 kW
+5 V
3 V
REF3130
R7
1.18 kW
RSHUNT
1W
R6
71.5 kWRN
56 W
RN
56 W
(PGA Gain = 4)
FS = 3.0 V
Stray Ground-Loop Resistance
ILOAD
R1
VEX
VOUT
VREF
R1
OPA333
R
R
R R
+5 V
+ +
+
- -
+
4.096 V
0.1 Fm
+5 V
Zero
Adjust
K-Type
Thermocouple
40.7 V/ Cm °
R2
549 W
R9
150 kW
R5
31.6 kW
R1
6.04 kW
R6
200 W
+5 V
0.1 Fm
R2
2.94 kW
VO
R3
60.4 W
R4
6.04 kW
OPA333
D1
REF3140
OPA333
,
OPA2333
SBOS351E –MARCH 2006REVISED DECEMBER 2015
www.ti.com
8.3 System Examples
8.3.1 Temperature Measurement Application
Figure 27 shows a temperature measurement application.
Figure 27. Temperature Measurementf
8.3.2 Single Operational Amplifier Bridge Amplifier Application
Figure 28 shows the basic configuration for a bridge amplifier.
Figure 28. Single Operational Amplifier Bridge Amplifier
8.3.3 Low-Side Current Monitor Application
A low-side current shunt monitor is shown in Figure 29. RNare operational resistors used to isolate the ADS1100
from the noise of the digital I2C bus. The ADS1100 is a 16-bit converter; therefore, a precise reference is
essential for maximum accuracy. If absolute accuracy is not required and the 5-V power supply is sufficiently
stable, the REF3130 can be omitted.
NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.
Figure 29. Low-Side Current Monitor
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Product Folder Links: OPA333 OPA2333
V1
-In
V2
+In
R1
R2
2
3
5
6
1
R2
OPA333
OPA333
INA152
VO
V = (1 + 2R / R
O 2 1 2 1
) (V V )-
OPA333
3 V
1 MW60 kW
100 kW
1 MW
NTC
Thermistor
OPA333
Output
RSHUNT
Load
V+
V+
RG
RL
R(2)
1
10 kW
RBIAS
+5V
zener(1)
Two zener
biasing methods
are shown.(3)
MOSFET rated to
stand-off supply voltage
such as BSS84 for
up to 50 V.
OPA333
,
OPA2333
www.ti.com
SBOS351E MARCH 2006REVISED DECEMBER 2015
8.3.4 Other Applications
Additional application ideas are shown in Figure 30 through Figure 33.
(1) Zener rated for op amp supply capability (that is, 5.1 V for OPA333).
(2) Current-limiting resistor.
(3) Choose zener biasing resistor or dual N-MOSFETs (FDG6301N, NTJD4001N, or Si1034).
Figure 30. High-Side Current Monitor
Figure 31. Thermistor Measurement
Figure 32. Precision Instrumentation Amplifier
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: OPA333 OPA2333
l TEXAS INSTRUMENTS 0mm + Go
R1
100 kW
1/2
OPA2333
RA
Inverted
VCM
+VS
INA321(1)
+VS
VOUT
+VS
+VS
+VS
OPA333
+VS
1/2 VS
dc
3
21
4
5
6
G = 1 kV/V
TOT
G = 5
INA
G = 200
OPA
f = 150 Hz
LPF
f = 0.5 Hz
HPF
(provides ac signal coupling)
V = +2.7 V to +5.5 V
S
BW = 0.5 Hz to 150 Hz
f = 0.5 Hz
O
Wilson
VCENTRAL
(RA + LA + LL) / 3
7
ac
1/2 VS
R2
100 kW
1/2
OPA2333
LL
+VS
R3
100 kW
1/2
OPA2333
LA
R4
100 kW
R9
20 kW
R6
100 kW
RL
+VS
+VS
1/2
OPA2333
1/2
OPA2333
1/2
OPA2333
C4
1.06 nF
C3
1 Fm
R14
1 MW
R12
5 kW
R13
318 kW
R7
100 kW
R8
100 kW
R10
1 MW
C2
0.64 Fm
R11
1 MW
C1
47 pF
R5
390 kW
OPA333
,
OPA2333
SBOS351E –MARCH 2006REVISED DECEMBER 2015
www.ti.com
(1) Other instrumentation amplifiers can be used, such as the INA326, which has lower noise, but higher quiescent
current.
Figure 33. Single-Supply, Very Low Power, ECG Circuit
9 Power Supply Recommendations
The OPAx333 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from
–40°C to 125°C. The Typical Characteristics presents parameters that can exhibit significant variance with regard
to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings).
TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in
from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement,
refer to the Layout section.
22 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
l TEXAS INSTRUMENTS HG
N/C
±IN
+IN
V±
V+
OUTPUT
N/C
N/C
VS+
GND
VS±
GND
Ground (GND) plane on another layer
VOUT
VIN
GND
Run the input traces
as far away from
the supply lines
as possible
Use low-ESR, ceramic
bypass capacitor
RF
RG
Place components
close to device and to
each other to reduce
parasitic errors
+
VIN VOUT
RG
RF
(Schematic Representation)
Use low-ESR,
ceramic bypass
capacitor
OPA333
,
OPA2333
www.ti.com
SBOS351E MARCH 2006REVISED DECEMBER 2015
10 Layout
10.1 Layout Guidelines
10.1.1 General Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA333 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
10.1.2 DFN Layout Guidelines
Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing
showing an example layout is attached at the end of this data sheet. Refinements to this layout may be
necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet
list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are
intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
10.2 Layout Example
Figure 34. Layout Example
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: OPA333 OPA2333
l TEXAS INSTRUMENTS
OPA333
,
OPA2333
SBOS351E –MARCH 2006REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support on this product, see the following:
High-Side V-I Converter, 0 V to 2 V to 0 mA to 100 mA, 1% Full-Scale Error, TIPD102
Low-Level V-to-I Converter Reference Design, 0-V to 5-V Input to 0-µA to 5-µA Output, TIPD107
18-Bit, 1-MSPS, Serial Interface, microPower, Truly-Differential Input, SAR ADC, ADS8881
Very Low-Power, High-Speed, Rail-To-Rail Input/Output, Voltage Feedback Operational Amplifier, THS4281
Data Acquisition Optimized for Lowest Distortion, Lowest Noise, 18-bit, 1-MSPS Reference Design, TIPD115
Self-Calibrating, 16-Bit Analog-to-Digital Converter, ADS1100
20-ppm/Degrees C Max, 100-µA, SOT23-3 Series Voltage Reference, REF3130
Precision, Low Drift, CMOS Instrumentation Amplifier, INA326, INA326
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
QFN/SON PCB Attachment,SLUA271
Quad Flatpack No-Lead Logic Packages,SCBA017
11.3 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
OPA333 Click here Click here Click here Click here Click here
OPA2333 Click here Click here Click here Click here Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
24 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
l TEXAS INSTRUMENTS
OPA333
,
OPA2333
www.ti.com
SBOS351E MARCH 2006REVISED DECEMBER 2015
11.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: OPA333 OPA2333
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 11-Aug-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
OPA2333AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A
OPA2333AIDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A
OPA2333AIDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ
OPA2333AIDGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ
OPA2333AIDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ
OPA2333AIDGKTG4 ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 OBAQ
OPA2333AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A
OPA2333AIDRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ
OPA2333AIDRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ
OPA2333AIDRBTG4 ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 BQZ
OPA2333AIDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O2333A
OPA333AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O333A
OPA333AIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ
OPA333AIDBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ
OPA333AIDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ
OPA333AIDBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 OAXQ
OPA333AIDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BQY
OPA333AIDCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BQY
OPA333AIDCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BQY
OPA333AIDCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BQY
I TEXAS INSTRUMENTS Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 11-Aug-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
OPA333AIDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O333A
OPA333AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O333A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2333, OPA333 :
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 11-Aug-2021
Addendum-Page 3
Automotive : OPA2333-Q1, OPA333-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
I TEXAS INSTRUMENTS 5:. V.’
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA2333AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2333AIDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2333AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2333AIDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA2333AIDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
OPA333AIDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA333AIDBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA333AIDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA333AIDCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
OPA333AIDCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
OPA333AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2333AIDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
OPA2333AIDGKT VSSOP DGK 8 250 364.0 364.0 27.0
OPA2333AIDR SOIC D 8 2500 356.0 356.0 35.0
OPA2333AIDRBR SON DRB 8 3000 356.0 356.0 35.0
OPA2333AIDRBT SON DRB 8 250 210.0 185.0 35.0
OPA333AIDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA333AIDBVR SOT-23 DBV 5 3000 200.0 183.0 25.0
OPA333AIDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
OPA333AIDCKR SC70 DCK 5 3000 200.0 183.0 25.0
OPA333AIDCKT SC70 DCK 5 250 200.0 183.0 25.0
OPA333AIDR SOIC D 8 2500 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA2333AID D SOIC 8 75 506.6 8 3940 4.32
OPA2333AIDG4 D SOIC 8 75 506.6 8 3940 4.32
OPA333AID D SOIC 8 75 506.6 8 3940 4.32
OPA333AIDG4 D SOIC 8 75 506.6 8 3940 4.32
Pack Materials-Page 3
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane fit Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com
LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencfl tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'fle' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercfl des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncfl rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/F 06/2021
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
GENERIC PACKAGE VIEW DRB 8 VSON - 1 mm max heigfl PLASTIC SMALL OUTLINE , N0 LEAD Images above are JUSI a representation of me package family, aclual package may vary. Refer lo the product data sheel for package details, 4203462/L ' TEXAS INSTRUMENTS
SM“ 1 w““‘+“‘ \\
www.ti.com
PACKAGE OUTLINE
C
8X 0.35
0.25
2.4 0.05
2X
1.95
1.65 0.05
6X 0.65
1 MAX
8X 0.5
0.3
0.05
0.00
A3.1
2.9 B
3.1
2.9
(0.2) TYP
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
(OPTIONAL)
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
T» h
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
8X (0.3)
(2.4)
(2.8)
6X (0.65)
(1.65)
( 0.2) VIA
TYP
(0.575)
(0.95)
8X (0.6)
(R0.05) TYP
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
SYMM
1
45
8
LAND PATTERN EXAMPLE
SCALE:20X
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(R0.05) TYP
8X (0.3)
8X (0.6)
(1.47)
(1.06)
(2.8)
(0.63)
6X (0.65)
VSON - 1 mm max heightDRB0008B
PLASTIC SMALL OUTLINE - NO LEAD
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
SYMM
1
45
8
METAL
TYP
SYMM
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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