ADS7846 Datasheet by Texas Instruments

Burr-Brown Products ‘ from Texas Instruments » *5“ TEXAS INSTRUM ENTS
FEATURES
●SAME PINOUT AS ADS7843
●2.2V TO 5.25V OPERATION
●INTERNAL 2.5V REFERENCE
●DIRECT BATTERY MEASUREMENT (0V to 6V)
●ON-CHIP TEMPERATURE MEASUREMENT
●TOUCH-PRESSURE MEASUREMENT
●QSPITM/SPITM 3-WIRE INTERFACE
●AUTO POWER-DOWN
●TSSOP-16, SSOP-16, QFN-16,
AND VFBGA-48 PACKAGES
APPLICATIONS
●PERSONAL DIGITAL ASSISTANTS
●PORTABLE INSTRUMENTS
●POINT-OF-SALE TERMINALS
●PAGERS
●TOUCH SCREEN MONITORS
●CELLULAR PHONES
TOUCH SCREEN CONTROLLER
DESCRIPTION
The ADS7846 is a next-generation version to the industry
standard ADS7843 4-wire touch screen controller. The
ADS7846 is 100% pin-compatible with the existing ADS7843,
and drops into the same socket. This allows for easy upgrade
of current applications to the new version. Only software
changes are required to take advantage of the added fea-
tures of direct battery measurement, temperature measure-
ment, and touch-pressure measurement. The ADS7846 also
has an on-chip 2.5V reference that can be used for the
auxiliary input, battery monitor, and temperature measure-
ment modes. The reference can also be powered down when
not used to conserve power. The internal reference operates
down to 2.7V supply voltage while monitoring the battery
voltage from 0V to 6V.
The low-power consumption of < 0.75mW (typ at 2.7V,
reference off), high speed (up to 125kHz clock rate), and on-
chip drivers make the ADS7846 an ideal choice for battery-
operated systems such as personal digital assistants (PDAs)
with resistive touch screens, pagers, cellular phones, and
other portable equipment. The ADS7846 is available in the
small TSSOP-16, SSOP-16, QFN-16, and VFBGA-48 pack-
ages and is specified over the –40°C to +85°C temperature
range.
CDAC
Internal 2.5V
Reference
SAR
ADS7846
Comparator
6-Channel
MUX Serial
Data
Out
Temperature
Sensor
Battery
Monitor
DOUT
BUSY
CS
DCLK
DIN
V
BAT
AUX
V
REF
+V
CC
X+
X–
Y+
Y–
PENIRQ
ADS7846
SBAS125H – SEPTEMBER 1999 – REVISED JANUARY 2005
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999-2005, Texas Instruments Incorporated
US Patent No. 6246394
QSPI and SPI are registered trademarks of Motorola.
®
ADS7846
ADS7846
ADS7846
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
*5“ TEXAS INSTRUM ENTS
ADS7846
2SBAS125H
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ............................................. –0.3V to +VCC + 0.3V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above these ratings can cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
MAXIMUM
INTEGRAL SPECIFIED
LINEARITY PACKAGE TEMPERATURE PACKAGE ORDERING
PRODUCT ERROR (LSB) PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER
ADS7846E ±2 SSOP-16 DBQ –40°C to +85°C ADS7846E ADS7846E
"" " " " " ADS7846E/2K5
ADS7846N ±2 TSSOP-16 PW –40°C to +85°C ADS7846N ADS7846N
"" " " " " ADS7846N/2K5
"" " " " " ADS7846N/2K5G4
ADS7846I ±2 VFBGA-48 GQC –40°C to +85°C ADS7846 ADS7846IGQCR
ADS7846I ±2 QFN-16 RGV –40°C to +85°C ADS7846 ADS7846IRGVT
"" " " " " ADS7846IRGVR
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site
at www.ti.com.
PACKAGE/ORDERING INFORMATION(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
*5“ TEXAS INSTRUM ENTS
ADS7846 3
SBAS125H www.ti.com
ANALOG INPUT
Full-Scale Input Span Positive Input-Negative Input 0 VREF V
Absolute Input Range Positive Input –0.2 +VCC + 0.2 V
Negative Input –0.2 +0.2 V
Capacitance 25 pF
Leakage Current 0.1 µA
SYSTEM PERFORMANCE
Resolution 12 Bits
No Missing Codes 11 Bits
Integral Linearity Error ±2 LSB(1)
Offset Error ±6LSB
Gain Error External VREF ±4LSB
Noise Including Internal VREF 70 µVrms
Power-Supply Rejection 70 dB
SAMPLING DYNAMICS
Conversion Time 12 CLK Cycles
Acquisition Time 3 CLK Cycles
Throughput Rate 125 kHz
Multiplexer Settling Time 500 ns
Aperture Delay 30 ns
Aperture Jitter 100 ps
Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz 100 dB
SWITCH DRIVERS
On-Resistance
Y+, X+ 5Ω
Y–, X–6Ω
Drive Current(2) Duration 100ms 50 mA
REFERENCE OUTPUT
Internal Reference Voltage 2.45 2.50 2.55 V
Internal Reference Drift 15 ppm/°C
Quiescent Current 500 µA
REFERENCE INPUT
Range 1.0 +VCC V
Input Impedance SER/DFR = 0, PD1 = 0, 1 GΩ
Internal Reference Off
Internal Reference On 250 Ω
BATTERY MONITOR
Input Voltage Range 0.5 6.0 V
Input Impedance
Sampling Battery 10 kΩ
Battery Monitor Off 1GΩ
Accuracy External VREF = 2.5V –2+2%
Internal Reference –3+3%
TEMPERATURE MEASUREMENT
Temperature Range –40 +85 °C
Resolution Differential Method(3) 1.6 °C
TEMP0(4) 0.3 °C
Accuracy Differential Method(3) ±2°C
TEMP0(4) ±3°C
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Levels, Except
PENIRQ
VIH | IIH | ≤ +5µA+V
CC • 0.7 +VCC + 0.3
VIL | IIL | ≤ +5µA–0.3 +0.8 V
VOH IOH = –250µA+V
CC • 0.8 V
VOL IOL = 250µA 0.4 V
PENIRQ
VOL TA = 0°C to +85°C, 50kΩ Pull-Up 0.8 V
Data Format Straight Binary
POWER-SUPPLY REQUIREMENTS
+VCC(5) Specified Performance 2.7 3.6 V
Operating Range 2.2 5.25 V
Quiescent Current Internal Reference Off 280 650 µA
Internal Reference On 780 µA
fSAMPLE = 12.5kHz 220 µA
Power-Down Mode with 3 µA
CS = DCLK = DIN = +VCC
Power Dissipation +VCC = +2.7V 1.8 mW
TEMPERATURE RANGE
Specified Performance –40 +85 °C
NOTES: (1) LSB means least significant bit. With VREF equal to +2.5V, one LSB is 610µV. (2) Ensured by design, but not tested. Exceeding 50mA source current
may result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement. No calibration necessary. (4) Temperature drift is –2.1mV/°C.
(5) ADS7846 operates down to 2.2V.
ADS7846E
PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = 2.5V internal voltage, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital inputs = GND or +VCC,
unless otherwise noted.
NINW‘ fk Q\ C O O O o o o o Q C , 33333333 EEEEEEEE 3333 flflflfl UUUU O CCCC , INSTRUM ENTS *5“ TEXAS
ADS7846
4SBAS125H
www.ti.com
PIN CONFIGURATION
Top View SSOP, TSSOP Top View VFBGA
1
2
3
4
5
6
7
8
+VCC
X+
Y+
X–
Y–
GND
VBAT
AUX
DCLK
CS
DIN
BUSY
DOUT
PENIRQ
+VCC
VREF
16
15
14
13
12
11
10
9
ADS7846
NC
NCA
21 3 4 5 6 7
DCLK
+V
CC
+V
CC
X+
Y+
PENIRQ
+V
CC
V
REF
AUX
CS DIN BUSY DOUT
X–Y–GND GND V
BAT
NC
NC
NC
NC
NC
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC
NC
NC
NC
NCNC
NCG
BUSY
DIN
CS
DCLK
AUX
VBAT
GND
Y–
1
2
3
4
12
11
10
9
ADS7846
DOUT
PENIRQ
+VCC
VREF
16
15
14
13
+VCC
X+
Y+
X–
5
6
7
8
Top View QFN
SSOP AND
TSSOP PIN # VFBGA PIN # QFN PIN # NAME DESCRIPTION
1 B1 and C1 5 +VCC Power Supply
2 D1 6 X+ X+ Position Input
3 E1 7 Y+ Y+ Position Input
4G28X–X– Position Input
5G39Y–Y– Position Input
6 G4 and G5 10 GND Ground
7G611V
BAT Battery Monitor Input
8 E7 12 AUX Auxiliary Input to ADC
9D713V
REF Voltage Reference Input/Output
10 C7 14 +VCC Digital I/O Power Supply
11 B7 15
PENIRQ
Pen Interrupt. Open anode output (requires 10kΩ to 100kΩ pull-up resistor externally).
12 A6 16 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when
CS
is high.
13 A5 1 BUSY Busy Output. This output is high impedance when
CS
is high.
14 A4 2 DIN Serial Data Input. If
CS
is low, data is latched on rising edge of DCLK.
15 A3 3
CS
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS
high = power-down mode (ADC only).
16 A2 4 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
I/O.
PIN DESCRIPTION
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TYPICAL CHARACTERISTICS
At TA = +25°C, +VCC = +2.7V, VREF = External +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
SUPPLY CURRENT vs TEMPERATURE
20–40 100–20 0 40
Temperature (°C)
Supply Current (µA)
400
350
300
250
200
150
100 60 80
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
20–40 100–20 0 40
Temperature (°C)
Supply Current (nA)
140
120
100
80
60
40
20 60 80
SUPPLY CURRENT vs +V
CC
3.52.0 5.02.5 4.0
+V
CC
(V)
Supply Current (µA)
390
370
350
330
310
290
270
250 4.53.0
f
SAMPLE
= 12.5kHz
MAXIMUM SAMPLE RATE vs +V
CC
3.52.0 5.02.5 4.0
+V
CC
(V)
Sample Rate (Hz)
1M
100k
10k
1k 4.53.0
CHANGE IN GAIN vs TEMPERATURE
20–40 100–20 0 40
Temperature (°C)
Delta from +25°C (LSB)
0.15
0.10
0.05
0
–0.05
–0.10
–0.15 60 80
CHANGE IN OFFSET vs TEMPERATURE
20–40 100–20 0 40
Temperature (°C)
Delta from +25°C (LSB)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6 60 80
{4‘ TEXAS INSTRUM ENTS
ADS7846
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = External +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
REFERENCE CURRENT vs SAMPLE RATE
750 12525 50 100
Sample Rate (kHz)
Reference Current (µA)
14
12
10
8
6
4
2
0
REFERENCE CURRENT vs TEMPERATURE
20–40 100–20 0 40
Temperature (°C)
Reference Current (µA)
18
16
14
12
10
8
660 80
SWITCH-ON RESISTANCE vs TEMPERATURE
(X+, Y+: +V
CC
to Pin; X–, Y–: Pin to GND)
20–40 100–20
X+ Y+
Y–X–
40
Temperature (°C)
R
ON
(Ω)
1
8
7
6
5
4
3
2
60 800
2.4920
2.4915
2.4910
2.4905
2.4900
2.4895
2.4890
2.4885
2.4880
2.4875
Internal V
REF
(V)
Temperature (°C)
INTERNAL V
REF
vs TEMPERATURE
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
SWITCH-ON RESISTANCE vs +V
CC
(X+, Y+: +V
CC
to Pin; X–, Y–: Pin to GND)
3.52.0 5.02.5
X+Y+
Y–
X–
4.0
+VCC (V)
R
ON
(Ω)
1
8
7
6
5
4
3
2
4.53.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Error (LSB)
20 40 60 80 100 120 140 160 180 200
Sampling Rate (kHz)
MAXIMUM SAMPLING RATE vs R
IN
INL: R = 2k
INL: R = 500
DNL: R = 2k
DNL: R = 500
Tuern Me (n {4‘ TEXAS INSTRUM ENTS
ADS7846 7
SBAS125H www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = External +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
2.4865
2.4860
2.4855
2.4850
2.4845
2.4840
V
REF
(V)
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
V
CC
(V)
INTERNAL V
REF
vs V
CC
850
800
750
700
650
600
550
500
450
TEMP Diode Voltage (mV)
Temperature (°C)
–40
–35
–30
–25
–20
–15
–10
–05
0
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
TEMP DIODE VOLTAGE
vs TEMPERATURE (2.7V SUPPLY)
102.7mV
132.25mV
TEMP0
TEMP1
100
80
60
40
20
0
Internal VREF (%)
0200 400 600 800 1000 1200
INTERNAL VREF vs TURN-ON TIME
Turn-On Time (µS)
1µF Cap
(1110µS)
12-Bit
Settling
No Cap
(52µS)
12-Bit
Settling
620
618
616
614
612
610 2.7 3.0 3.3
V
SUPPLY
(V)
TEMP0 DIODE VOLTAGE vs V
SUPPLY
(25°C)
TEMP0 Diode Voltage (mV)
732
730
728
726
724
722 2.7 3.0 3.3
V
SUPPLY
(V)
TEMP1 DIODE VOLTAGE vs V
SUPPLY
(25°C)
TEMP1 Diode Voltage (mV)
}}}}}}}j {CCrinCifi 3 xi, 7324/2 2/» INSTRUM ENTS *5“ TEXAS
ADS7846
8SBAS125H
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THEORY OF OPERATION
The ADS7846 is a classic successive approximation register
(SAR) analog-to-digital converter (ADC). The architecture is
based on capacitive redistribution which inherently includes
a sample-and-hold function. The converter is fabricated on a
0.6µm CMOS process.
The basic operation of the ADS7846 is shown in Figure 1.
The device features an internal 2.5V reference and an
external clock. Operation is maintained from a single supply
of 2.7V to 5.25V. The internal reference can be overdriven
with an external, low impedance source between 1V and
+VCC. The value of the reference voltage directly sets the
input range of the converter.
The analog input (X-, Y-, and Z-position coordinates, auxil-
iary input, battery voltage, and chip temperature) to the
converter is provided via a multiplexer. A unique configura-
tion of low on-resistance touch panel driver switches allows
an unselected ADC input channel to provide power and its
accompanying pin to provide ground for an external device,
such as a touch screen. By maintaining a differential input to
the converter and a differential reference architecture, it is
possible to negate the error from each touch panel driver
switch’s on-resistance (if this is a source of error for the
particular measurement).
ANALOG INPUT
See Figure 2 for a block diagram of the input multiplexer on
the ADS7846, the differential input of the ADC, and the
differential reference of the converter. Table I and Table II
show the relationship between the A2, A1, A0, and
SER/DFR
control bits and the configuration of the ADS7846. The
control bits are provided serially via the DIN pin—see the
Digital Interface section of this data sheet for more details.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (see Figure 2) is
captured on the internal capacitor array. The input current
into the analog inputs depends on the conversion rate of the
device. During the sample period, the source must charge
the internal sampling capacitor (typically 25pF). After the
capacitor has been fully charged, there is no further input
current. The rate of charge transfer from the analog source
to the converter is a function of conversion rate.
FIGURE 1. Basic Operation of the ADS7846.
A2 A1 A0 V
BAT
AUX
IN
TEMP Y–X+ Y+ Y-POSITION X-POSITION Z
1
-POSITION Z
2
-POSITION X-DRIVERS Y-DRIVERS
000
+IN (TEMP0) Off Off
0 0 1 +IN Measure Off On
010+IN Off Off
0 1 1 +IN Measure X–, On Y+, On
1 0 0 +IN Measure X–, On Y+, On
1 0 1 +IN Measure On Off
110 +IN Off Off
111
+IN (TEMP1)
Off Off
TABLE I. Input Configuration (DIN), Single-Ended Reference Mode (
SER/DFR
high).
TABLE II. Input Configuration (DIN), Differential Reference Mode (
SER/DFR
low).
A2 A1 A0 +REF –REF Y–X+ Y+ Y-POSITION X-POSITION Z
1
-POSITION Z
2
-POSITION DRIVERS ON
001Y+Y–+IN Measure Y+, Y–
011Y+X–+IN Measure Y+, X–
100Y+X–+IN Measure Y+, X–
101X+X–+IN Measure X+, X–
+VCC
X+
Y+
X–
Y–
GND
VBAT
AUX
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCLK
CS
DIN
BUSY
DOUT
PENIRQ
+VCC
VREF
Serial/Conversion Clock
Chip Select
Serial Data In
Converter Status
Serial Data Out
+
1µF
to
10µF
(Optional)
+2.7V to +5V
ADS7846
Auxiliary Input
To Battery
Voltage
Regulator
Touch
Screen
0.1µF
Pen Interrupt
50kΩ
ADS7846 9
SBAS125H www.ti.com
INTERNAL REFERENCE
The ADS7846 has an internal 2.5V voltage reference that can
be turned on or off with the control bit, PD1 = 1 (see Table V and
Figure 3). Typically, the internal reference voltage is only used
in the single-ended mode for battery monitoring, temperature
measurement, and for using the auxiliary input. Optimal touch
screen performance is achieved when using the differential
mode. The internal reference voltage of the ADS7846 must be
commanded to be off to maintain compatibility with the ADS7843.
Therefore, after power-up, a write of PD1 = 0 is required to
insure the reference is off (see the Typical Characteristics for
power-up time of the reference from power-down).
REFERENCE INPUT
The voltage difference between +REF and –REF (shown in
Figure 2) sets the analog input range. The ADS7846 oper-
ates with a reference in the range of 1V to +VCC. There are
several critical items concerning the reference input and its
wide voltage range. As the reference voltage is reduced, the
analog voltage weight of each digital output code is also
reduced. This is often referred to as the LSB (least significant
bit) size and is equal to the reference voltage divided by 4096
in 12-bit mode. Any offset or gain error inherent in the ADC
appears to increase, in terms of LSB size, as the reference
voltage is reduced. For example, if the offset of a given
converter is 2LSBs with a 2.5V reference, it is typically
5LSBs with a 1V reference. In each case, the actual offset of
the device is the same, 1.22mV. With a lower reference
FIGURE 2. Simplified Diagram of Analog Input.
Converter
–REF
+REF
+IN
–IN
V
BAT
AUX
Battery
On
GND
A2-A0
(Shown 001
B
)
2.5V
Reference
Ref On/Off
SER/DFR
(Shown High)
X+
X–
+V
CC
TEMP1
PENIRQ
Y+
Y–
V
REF
TEMP0
7.5kΩ
2.5kΩ
Buffer
Band
Gap
Reference
Power Down
To
CDAC
Optional
V
REF
FIGURE 3. Simplified Diagram of the Internal Reference.
0?
ADS7846
10 SBAS125H
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voltage, more care must be taken to provide a clean layout
including adequate bypassing, a clean (low-noise, low-ripple)
power supply, a low-noise reference (if an external reference
is used), and a low-noise input signal.
The voltage into the VREF input directly drives the capacitor
digital-to-analog converter (CDAC) portion of the ADS7846.
Therefore, the input current is very low (typically < 13µA).
There is also a critical item regarding the reference when
making measurements where the switch drivers are on. For
this discussion, it is useful to consider the basic operation of
the ADS7846 (see Figure 1). This particular application
shows the device being used to digitize a resistive touch
screen. A measurement of the current Y position of the
pointing device is made by connecting the X+ input to the
ADC, turning on the Y+ and Y– drivers, and digitizing the
voltage on X+ (Figure 4 shows a block diagram). For this
measurement, the resistance in the X+ lead does not affect
the conversion (it does affect the settling time, but the
resistance is usually small enough that this is not a concern).
However, since the resistance between Y+ and Y– is fairly
low, the on-resistance of the Y drivers does make a small
difference. Under the situation outlined so far, it is not
possible to achieve a 0V input or a full-scale input regardless
of where the pointing device is on the touch screen, because
some voltage is lost across the internal switches. In addition,
the internal switch resistance is unlikely to track the resis-
tance of the touch screen, providing an additional source of error.
FIGURE 4. Simplified Diagram of Single-Ended Reference
(
SER/DFR
High, Y Switches Enabled, X+ is
Analog Input).
This situation can be remedied as shown in Figure 5. By
setting the
SER/DFR
bit low, the +REF and –REF inputs are
connected directly to Y+ and Y–, respectively, which makes
the analog-to-digital conversion ratiometric. The result of the
conversion is always a percentage of the external resistance,
regardless of how it changes in relation to the on-resistance of
the internal switches. Note that there is an important consid-
eration regarding power dissipation when using the ratiometric
mode of operation (see the Power Dissipation section for
more details).
FIGURE 5. Simplified Diagram of Differential Reference
(
SER/DFR
Low, Y Switches Enabled, X+ is
Analog Input).
Converter
+IN +REF
Y+
+V
CC
X+
Y–
GND
–REF
–IN
As a final note about the differential reference mode, it must
be used with +VCC as the source of the +REF voltage and
cannot be used with VREF. It is possible to use a high
precision reference on VREF and single-ended reference
mode for measurements which do not need to be ratiometric.
In some cases, it is possible to power the converter directly
from a precision reference. Most references can provide
enough power for the ADS7846, but might not be able to
supply enough current for the external load (such as a
resistive touch screen).
TOUCH SCREEN SETTLING
In some applications, external capacitors may be required
across the touch screen for filtering noise picked up by the
touch screen (for example, noise generated by the LCD panel
or backlight circuitry). These capacitors provide a low-pass
filter to reduce the noise, but cause a settling time requirement
when the panel is touched that typically shows up as a gain
error. The problem is that the input and/or reference has not
settled to the final steady-state value prior to the ADC sam-
pling the input(s) and providing the digital output. Additionally,
the reference voltage may still be changing during the mea-
surement cycle. There are several methods for minimizing or
eliminating this issue. Option 1 is to stop or slow down the
ADS7846 DCLK for the required touch screen settling time.
This allows the input and reference to have stable values for
the Acquire period (3 clock cycles of the ADS7846; see Figure
9). This works for both the single-ended and the differential
modes. Option 2 is to operate the ADS7846 in the differential
mode only for the touch screen measurements and command
the ADS7846 to remain on (touch screen drivers on) and not
go into power-down (PD0 = 1). Several conversions are made
depending on the settling time required and the ADS7846 data
rate. Once the required number of conversions have been
made, the processor commands the ADS7846 to go into the
power-down state on the last measurement. This process is
Converter
+IN +REF
Y+
+VCC VREF
X+
Y–
GND
–REF
–IN
$3,,
ADS7846 11
SBAS125H www.ti.com
required for X-position, Y-position, and Z-position measure-
ments. Option 3 is to operate in the 15 Clock-per-Conversion
mode which overlaps the analog-to-digital conversions and
maintains the touch screen drivers on until commanded to
stop by the processor (see Figure 12).
TEMPERATURE MEASUREMENT
In some applications, such as battery recharging, a measure-
ment of ambient temperature is required. The temperature
measurement technique used in the ADS7846 relies on the
characteristics of a semiconductor junction operating at a
fixed current level. The forward diode voltage (VBE) has a
well-defined characteristic versus temperature. The ambient
temperature can be predicted in applications by knowing the
25°C value of the VBE voltage and then monitoring the delta
of that voltage as the temperature changes. The ADS7846
offers two modes of operation. The first mode requires
calibration at a known temperature, but only requires a single
reading to predict the ambient temperature. The
PENIRQ
diode is used (turned on) during this measurement cycle.
The voltage across the diode is connected through the MUX
for digitizing the forward bias voltage by the ADC with an
address of A2 = 0, A1 = 0, and A0 = 0 (see Table I and Figure
6 for details). This voltage is typically 600mV at +25°C with
a 20µA current through the diode. The absolute value of this
diode voltage can vary a few millivolts. However, the TC of
this voltage is very consistent at –2.1mV/°C. During the final
test of the end product, the diode voltage would be stored at
a known room temperature, in memory, for calibration pur-
poses by the user. The result is an equivalent temperature
measurement resolution of 0.3°C/LSB (in 12-bit mode).
FIGURE 7. Battery Measurement Functional Block Diagram.
represented by kT/q • ln (N), where N is the current ratio
= 91, k = Boltzmann’s constant (1.38054 • 10–23 electron
volts/degrees Kelvin), q = the electron charge (1.602189 •
10–19 C), and T = the temperature in degrees Kelvin. This
method can provide improved absolute temperature mea-
surement over the first mode at the cost of less resolution
(1.6°C/LSB). The equation for solving for °K is:
°K = q • ∆V/(k • ln (N)) (1)
where, ∆V = V (I91) – V (I1) (in mV)
∴ °K = 2.573°K/mV • ∆V
°C = 2.573 • ∆V(mV) – 273°K
NOTE: The bias current for each diode temperature mea-
surement is only on for 3 clock cycles (during the acquisition
mode). Therefore, it does not add any noticeable increase in
power, especially if the temperature measurement only oc-
curs occasionally.
BATTERY MEASUREMENT
An added feature of the ADS7846 is the ability to monitor the
battery voltage on the other side of the voltage regulator (DC/DC
converter), as shown in Figure 7. The battery voltage can vary
from 0.5V to 6V, while maintaining the voltage to the ADS7846
at 2.7V, 3.3V, etc. The input voltage (V
BAT
) is divided down by
4 so that a 6.0V battery voltage is represented as 1.5V to the
ADC. This simplifies the multiplexer and control logic. In order
to minimize the power consumption, the divider is only on
during the sampling period when A2 = 0, A1 = 1, and A0 = 0
(see Table I for the relationship between the control bits and
configuration of the ADS7846).
+VCC
VBAT
7.5kΩ
2.5kΩ
DC/DC
Converter
Battery
0.5V
to
6.0V
0.125V to 1.5V
2.7V
+
FIGURE 6. Functional Block Diagram of Temperature Mea-
surement Mode.
ADC
MUX
PENIRQ
+V
CC
External
Pull-Up X+
Temperature Select
TEMP0 TEMP1
The second mode does not require a test temperature
calibration, but uses a two-measurement method to eliminate
the need for absolute temperature calibration and for achiev-
ing 2°C accuracy. This mode requires a second conversion
with an address of A2 = 1, A1 = 1, and A0 = 1, with a 91 times
larger current. The voltage difference between the first
and second conversion using 91 times the bias current is
Unveriw {5‘ TEXAS INSTRUM ENTS
ADS7846
12 SBAS125H
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The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer and reference inputs appropriately, the converter
enters the acquisition (sample) mode and, if needed,
the touch panel drivers are turned on. After three more
clock cycles, the control byte is complete and the converter
enters the conversion mode. At this point, the input
FIGURE 9. Conversion Timing, 24 Clocks-per-Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
PRESSURE MEASUREMENT
Measuring touch pressure can also be done with the ADS7846.
To determine pen or finger touch, the pressure of the touch
needs to be determined. Generally, it is not necessary to have
very high performance for this test; therefore, the 8-bit resolu-
tion mode is recommended (however, calculations will be
shown here are in 12-bit resolution mode). There are several
different ways of performing this measurement. The ADS7846
supports two methods. The first method requires knowing the
X-plate resistance, measurement of the X-Position, and two
additional cross-panel measurements (Z1 and Z2) of the touch
screen, as shown in Figure 8. Using Equation 2 calculates the
touch resistance:
R R plate X Position Z
Z
TOUCH X
=
–•
––
4096 1
2
1
(2)
The second method requires knowing both the X-plate and
Y-plate resistance, measurement of X-Position and Y-Posi-
tion, and Z1. Using Equation 3 also calculates the touch
resistance:
RR plate •X Position
4096
4096
Z–1
–R plate Y Position
4096
TOUCH X
1
Y
=−−
−•
1–
(3)
DIGITAL INTERFACE
Figure 9 shows the typical operation of the ADS7846 digital
interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface. Each communication between
the processor and the converter, such as SPI/SSI or
Microwire™ synchronous serial interface, consists of eight
clock cycles. One complete conversion can be accom-
plished with three serial communications for a total of 24
clock cycles on the DCLK input.
FIGURE 8. Pressure Measurement Block Diagrams.
tACQ
AcquireIdle Conversion Idle
1
DCLK
CS
81
11
DOUT
BUSY
DRIVERS 1 AND 2(1)
(SER/DFR High)
DRIVERS 1 AND 2(1, 2)
(SER/DFR Low)
(MSB)
(START)
(LSB)
A2S
On
On
Off Off
Off Off
DIN
A1 A0
MODE
SER/
DFR
PD1 PD0
1098765 4 3210 Zero Filled...
81 8
NOTES: (1) For Y-Position, Driver 1 is on, X+ is selected, and Driver 2 is off. For X-Position, Driver 1 is off, Y+ is selected, and
Driver 2 is on. Y– will turn on when power-down mode is entered and PD0 = 0B. (2) Drivers will remain on if PD0 = 1 (no power
down) until selected input channel, reference mode, or power-down mode is changed, or CS is HIGH.
X-Position
Measure X-Position
Measure Z
1
-Position
Touch
X+ Y+
X–Y–
Z
1
-Position
Touch
X+ Y+
Y–X–
Measure Z
2
-Position
Z
2
-Position
Touch
X+ Y+
Y–X–
*5“ TEXAS INSTRUM ENTS
ADS7846 13
SBAS125H www.ti.com
sample-and-hold goes into the hold mode and the touch
panel drivers turn off (in single-ended mode). The next 12
clock cycles accomplish the actual analog-to-digital conver-
sion. If the conversion is ratiometric (
SER/DFR
= 0), the
drivers are on during the conversion and a 13th clock cycle
is needed for the last bit of the conversion result. Three more
clock cycles are needed to complete the last byte (DOUT will
be low), which are ignored by the converter.
Control Byte
The control byte (on DIN), as shown in Table III, provides the
start conversion, addressing, ADC resolution, configuration,
and power-down of the ADS7846. Figure 9 and Tables III
and IV give detailed information regarding the order and
description of these control bits within the control byte.
SER/DFR
—The
SER/DFR
bit controls the reference mode,
either single-ended (high) or differential (low). The differential
mode is also referred to as the ratiometric conversion mode
and is preferred for X-Position, Y-Position, and Pressure-
Touch measurements for optimum performance. The refer-
ence is derived from the voltage at the switch drivers, which
is almost the same as the voltage to the touch screen. In this
case a reference voltage is not needed, as the reference
voltage to the ADC is the voltage across the touch screen. In
the single-ended mode, the converter reference voltage is
always the difference between the VREF and GND pins (see
Tables I and II, and Figures 2 through 5 for further informa-
tion).
If X-Position, Y-Position, and Pressure-Touch are measured
in the single-ended mode, an external reference voltage is
needed. The ADS7846 should also be powered from the
external reference. Caution must be observed when using
the single-ended mode such that the input voltage to the
ADC does not exceed the internal reference voltage, espe-
cially if the supply voltage is greater than 2.7V.
NOTE: The differential mode can only be used for X-Position,
Y-Position, and Pressure-Touch measurements. All other
measurements require the single-ended mode.
PD0 and PD1—Table V describes the power-down and the
internal reference voltage configurations. The internal refer-
ence voltage can be turned on or off independently of the
ADC. This can allow extra time for the internal reference
voltage to settle to the final value prior to making a conver-
sion. Make sure to also allow this extra wake-up time if the
internal reference is powered down. The ADC requires no
wake-up time and can be instantaneously used. Also note
that the status of the internal reference power-down is
latched into the part (internally) with BUSY going high.
Therefore, in order to turn the reference off, an additional
write to the ADS7846 is required after the channel is con-
verted.
Bit 7 Bit 0
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB)
S A2 A1 A0 MODE
SER/DFR
PD1 PD0
TABLE III. Order of the Control Bits in the Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first high bit on DIN.
A new control byte can start every 15th clock cycle
in 12-bit conversion mode or every 11th clock cycle
in 8-bit conversion mode (see Figure 12).
6-4 A2-A0 Channel Select Bits. Along with the
SER/DFR
bit,
these bits control the setting of the multiplexer input,
touch driver switches, and reference inputs (see
Tables I and II).
3 MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls
the number of bits for the next conversion: 12-bits
(low) or 8-bits (high).
2
SER/DFR
Single-Ended/Differential Reference Select Bit. Along
with bits A2-A0, this bit controls the setting of the
multiplexer input, touch driver switches, and reference
inputs (see Tables I and I).
1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for
details.
TABLE IV. Descriptions of the Control Bits within the Control
Byte.
Initiate START—The first bit, the S bit, must always be high
and initiates the start of the control byte. The ADS7846
ignores inputs on the DIN pin until the start bit is detected.
Addressing—The next three bits (A2, A1, and A0) select the
active input channel(s) of the input multiplexer (see Tables I,
II, and Figure 2), touch screen drivers, and the reference
inputs.
MODE—The mode bit sets the resolution of the ADC. With
this bit low, the next conversion has 12 bits of resolution; with
this bit high, the next conversion has 8 bits of resolution.
PD1 PD0 PENIRQ DESCRIPTION
0 0 Enabled Power-Down Between Conversions. When each
conversion is finished, the converter enters a
low-power mode. At the start of the next conver-
sion, the device instantly powers up to full power.
There is no need for additional delays to assure
full operation and the very first conversion is
valid. The Y– switch is on when in power-down.
0 1 Disabled Reference is off and ADC is on.
1 0 Enabled Reference is on and ADC is off.
1 1 Disabled Device is always powered. Reference is on and
ADC is on.
TABLE V. Power-Down and Internal Reference Selection.
*5“ TEXAS INSTRUM ENTS
ADS7846
14 SBAS125H
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16 Clocks-per-Conversion
The control bits for conversion n + 1 can be overlapped with
conversion n to allow for a conversion every 16 clock cycles,
as shown in Figure 10. This figure also shows possible serial
communication occurring with other serial peripherals be-
tween each byte transfer from the processor to the converter.
This is possible provided that each conversion completes
within 1.6ms of starting. Otherwise, the signal that is cap-
tured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the ADS7846 is fully
powered while other serial communications are taking place
during a conversion.
Digital Timing
Figures 9, 11, and Table VI provide detailed timing for the
digital interface of the ADS7846.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tACQ Acquisition Time 1.5 µs
tDS DIN Valid Prior to DCLK Rising 100 ns
tDH DIN Hold After DCLK High 10 ns
tDO DCLK Falling to DOUT Valid 200 ns
tDV
CS
Falling to DOUT Enabled 200 ns
tTR
CS
Rising to DOUT Disabled 200 ns
tCSS
CS
Falling to First DCLK Rising 100 ns
tCSH
CS
Rising to DCLK Ignored 0 ns
tCH DCLK High 200 ns
tCL DCLK Low 200 ns
tBD DCLK Falling to BUSY Rising 200 ns
tBDV
CS
Falling to BUSY Enabled 200 ns
tBTR
CS
Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+VCC = +2.7V and Above,
TA = –40°C to +85°C, CLOAD = 50pF).
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11
DOUT
BUSY
DIN
10
FIGURE 11. Detailed Timing Diagram.
FIGURE 10. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
1
DCLK
CS
81
11
DOUT
BUSY
SDIN
Control Bits
S
Control Bits
1098765 43210 11 10 9
81 18
“ A , fl Fl 7‘ —. ||||\||\||||\ \Illli ”TEXAS INSTRUM ENTS
ADS7846 15
SBAS125H www.ti.com
15 Clocks-per-Conversion
Figure 12 provides the fastest way to clock the ADS7846.
This method does not work with the serial interface of most
microcontrollers and digital signal processors, as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method can be used with field pro-
grammable gate arrays (FPGAs) or application specific inte-
grated circuits (ASICs). Note that this effectively increases
the maximum conversion rate of the converter beyond the
values given in the specification tables, which assume 16
clock cycles per conversion.
Data Format
The ADS7846 output data is in Straight Binary format as
shown in Figure 13. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
8-Bit Conversion
The ADS7846 provides an 8-bit conversion mode that can be
used when faster throughput is needed and the digital result
is not as critical. By switching to the 8-bit mode, a conversion
is complete four clock cycles earlier. Not only does this shorten
each conversion by four bits (25% faster throughput), but each
conversion can actually occur at a faster clock rate. This is
because the internal settling time of the ADS7846 is not as
critical—settling to better than 8 bits is all that is needed. The
clock rate can be as much as 50% faster. The faster clock rate
and fewer clock cycles combine to provide a 2x increase in
conversion rate.
POWER DISSIPATION
There are two major power modes for the ADS7846: full power
(PD0 = 1B) and auto power-down (PD0 = 0B). When operating
at full speed and 16 clocks-per-conversion (see Figure 10), the
ADS7846 spends most of the time acquiring or converting.
There is little time for auto power-down, assuming that this
mode is active. Therefore, the difference between full-power
mode and auto power-down is negligible. If the conversion
rate is decreased by slowing the frequency of the DCLK input,
the two modes remain approximately equal. However, if the
DCLK frequency is kept at the maximum rate during a conver-
sion but conversions are done less often, the difference
between the two modes is dramatic.
FIGURE 12. Maximum Conversion Rate, 15 Clocks-per-Conversion.
1
DCLK
CS
11DOUT
BUSY
A2SDIN A1 A0
MODE SGL/
DIF
PD1 PD0
109876543210 11 10 9 8 7 Tri-State
A1 A0
15 1 15
Power Down
1
A2SA1A0
MODE
PD1 PD0
A2S
SGL/
DIF
FIGURE 13. Ideal Input Voltages and Output Codes.
Output Code
0V
FS = Full-Scale Voltage = VREF(1)
1LSB = VREF(1)/4096
FS – 1LSB
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
NOTES: (1) Reference voltage at converter: +REF – (–REF), see Figure 2.
(2) Input voltage at converter, after multiplexer: +IN – (–IN), see Figure 2.
Input Voltage(2) (V)
{4‘ TEXAS INSTRUM ENTS
ADS7846
16 SBAS125H
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Figure 14 shows the difference between reducing the DCLK
frequency (scaling DCLK to match the conversion rate) or
maintaining DCLK at the highest frequency and reducing the
number of conversions per second. In the latter case, the
converter spends an increasing percentage of time in power-
down mode (assuming the auto power-down mode is active).
LAYOUT
The following layout suggestions provide the most optimum
performance from the ADS7846. However, many portable
applications have conflicting requirements concerning power,
cost, size, and weight. In general, most portable devices
have fairly clean power and grounds because most of the
internal components are very low power. This situation means
less bypassing for the converter power and less concern
regarding grounding. Still, each situation is unique and the
following suggestions should be reviewed carefully.
For optimum performance, care must be taken with the
physical layout of the ADS7846 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the analog
comparator. Therefore, during any single conversion for an
n-bit SAR converter, there are n ‘windows’ in which large
external transient voltages can easily affect the conversion
result. Such glitches can originate from switching power
supplies, nearby digital logic, and high-power devices. The
degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event.
The error can change if the external event changes in time
with respect to the DCLK input.
With this in mind, power to the ADS7846 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. A 1µF to 10µF
capacitor may also be needed if the impedance of the
connection between +VCC and the power supply is high. Low-
leakage capacitors should be used to minimize power dissi-
pation through the bypass capacitors when the ADS7846 is
in power-down mode.
A bypass capacitor is generally not needed on the VREF pin
because the internal reference is buffered by an internal op
amp. If an external reference voltage originates from an op
amp, make sure that it can drive any bypass capacitor that
is used without oscillation.
The ADS7846 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply appears directly in the digital results.
Whereas high-frequency noise can be filtered out, voltage
variation due to line frequency (50Hz or 60Hz) can be difficult
to remove.
10k 100k1k 1M
fSAMPLE (Hz)
Supply Current (µA)
100
10
1
1000
fCLK = 2MHz
fCLK = 16 • fSAMPLE
TA = 25°C
+VCC = +2.7V
FIGURE 14. Supply Current versus Directly Scaling the Fre-
quency of DCLK with Sample Rate or Maintain-
ing DCLK at the Maximum Possible Frequency.
Another important consideration for power dissipation is the
reference mode of the converter. In the single-ended refer-
ence mode, the touch panel drivers are on only when the
analog input voltage is being acquired (see Figure 9 and
Table I). Therefore, the external device (e.g., a resistive
touch screen) is only powered during the acquisition period.
In the differential reference mode, the external device must
be powered throughout the acquisition and conversion peri-
ods (see Figure 9). If the conversion rate is high, this could
substantially increase power dissipation.
CS
also puts the ADS7846 into power-down mode. When
CS
goes high, the ADS7846 immediately goes into power-
down and does not complete the current conversion. How-
ever, the internal reference does not turn off with
CS
going
high. To turn the reference off, an additional write is required
before
CS
goes high (PD1 = 0).
*5“ TEXAS INSTRUM ENTS
ADS7846 17
SBAS125H www.ti.com
FIGURE 15. ADS7846
PENIRQ
Functional Block Diagram.
PENIRQ
+V
CC
100kΩ
On
Y or X drivers on,
or TEMP0, TEMP1
measurements
activated.
Y+
X+
Y–
The GND pin must be connected to a clean ground point. In
many cases, this is the analog ground. Avoid connections
which are too near the grounding point of a microcontroller or
digital signal processor. If needed, run a ground trace directly
from the converter to the power-supply entry or battery-
connection point. The ideal layout includes an analog ground
plane dedicated to the converter and associated analog
circuitry.
In the specific case of use with a resistive touch screen, care
should be taken with the connection between the converter
and the touch screen. Although resistive touch screens have
fairly low resistance, the interconnection should be as short
and robust as possible. Longer connections are a source of
error, much like the on-resistance of the internal switches.
Likewise, loose connections can be a source of error when
the contact resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error
in touch screen applications (for example, applications that
require a backlit LCD panel). This EMI noise can be coupled
through the LCD panel to the touch screen and cause
“flickering” of the converted data. Several things can be done
to reduce this error, such as using a touch screen with a
bottom-side metal layer connected to ground to shunt the
majority of noise to ground. Additionally, filtering capacitors,
from Y+, Y–, X+, and X– pins to ground can also help.
Caution should be observed under these circumstances for
settling time of the touch screen, especially operating in the
single-ended mode and at high data rates.
PENIRQ
OUTPUT
The pen-interrupt output function is shown in Figure 15. While
in power-down mode with PD0 = 0, the Y– driver is on and
connects the Y-plane of the touch screen to GND. The
PENIRQ
output is connected to the X+ input through two
transmission gates. When the screen is touched, the X+ input
is pulled to ground through the touch screen. The
PENIRQ
output goes low due to the current path through the touch
screen to ground, which initiates an interrupt to the processor.
During the measurement cycle for X-, Y-, and Z-Position, the
X+ input is disconnected from the external pull-up resistor.
This is done to eliminate any leakage current from the
external pull-up resistor through the touch screen, thus caus-
ing no errors.
Furthermore, the
PENIRQ
output is disabled and low during
the measurement cycle for X-, Y-, and Z-Position. The
PENIRQ
output is disabled and high during the measurement cycle for
battery monitor, auxiliary input, and chip temperature. If the last
control byte written to the ADS7846 contains PD0 = 1, the pen-
interrupt output function is disabled and is not able to detect
when the screen is touched. In order to re-enable the pen-
interrupt output function under these circumstances, a control
byte needs to be written to the ADS7846 with PD0 = 0. If the
last control byte written to the ADS7846 contains PD0 = 0, the
pen-interrupt output function is enabled at the end of the
conversion. The end of the conversion occurs on the falling
edge of DCLK after bit 1 of the converted data is clocked out
of the ADS7846.
It is recommended that the processor mask the interrupt
PENIRQ
is associated with whenever the processor sends a
control byte to the ADS7846. This prevents false triggering
of interrupts when the
PENIRQ
output is disabled, as in the
cases discussed in this section.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7846E/2K5 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS7846N/2K5 TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7846E/2K5 SSOP DBQ 16 2500 367.0 367.0 35.0
ADS7846N/2K5 TSSOP PW 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ADS7846E DBQ SSOP 16 75 506.6 8 3940 4.32
ADS7846EG4 DBQ SSOP 16 75 506.6 8 3940 4.32
ADS7846N PW TSSOP 16 90 530 10.2 3600 3.5
ADS7846NG4 PW TSSOP 16 90 530 10.2 3600 3.5
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2022
Pack Materials-Page 3
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GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VQFN - 1 mm max heightRGV 16
PLASTIC QUAD FLATPACK - NO LEAD
4 x 4, 0.65 mm pitch
4224748/A
MECHANICAL DATA YGV (Si'flmeim 13> 3‘ WSWC QUAD H A '/'\'3K K37 7/0 4 fl » \ V V 4 v V 4 v \ \ U U M ‘ A ‘ fl“ 3 P , 3 x ' H H H >4 NC‘LS A‘ hue/Jr mmenswons are m mflhmetem Dwmens amng C’vd (c‘erancv‘g per ASML W45N719§4 fimDOm) Tm: draw'flq ‘5 subject to change We“: rohce Quad F‘ut' , NW‘euds (ow) pucmge omngmum, The par, as warm pod r'ust be so‘deved to the board 101 (hevmu‘ and 'vvedvuvicn‘ peflorvnuuce See me uscwhoru‘ Ngme n we swam pm Sweet ‘01 salads 'eguvdvg he exucsed UVev'vvu‘ pod Vectmes and dwnens'w'vs Fm S w M 1 yEDEC M07220 {if TEXAS INSTRUMENTS www.1i.com
THERMAL PAD MECHANICAL DATA RGV ($7PVQFN7NTB) PLASTlC QUAD FLATPACK NoiLEAD THERMAL lNFORMATlON This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad rnust be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. in addition. through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device. or alternatively. can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (lC), For iniormation on the Quad Flatpack NoiLead (OFN) package and its advantages, refer to Application Report. OFN/SON PCB Attachment. Texas instruments Literature No. SLUA27l. This document is available at www,ticom, The exposed thermal pad dimensions (or this package are shown in the following illustration. Pin I indicator is electrically tied to the exposed thermal pad Pin I indicator metal require may not be present on some devices O,‘l6:t:0,05 (2 Places) — “5:035 (2 PM“) l 4 t U U U fiExpased Thermal Pad l 16 4 ‘/C5 2.16:0,10 D + C D C t ‘3 ‘5 C5 '1 {T {T r 12 9 2.1610,“) Bottom View Exposed Thermal Pad Dimensions 4206351—2/L 05/i3 NOTE: All linear dimensions are in millimeters {I} TEXAS INSTRUMENTS www.ti.cum
LAND PATTERN DATA &"V (S PVQ N \h) JLASHC QU/U LNPACK Ni) L,AD pm 1 txampie jourd Layout Exampie Stencii Design Va Keep on Area 0175mm s:enc’i rnickness 072er square (Nu-,5 E) - : 1i, » \ - is _ \ 69% Primed Soider Coverage Ce'iter 3nd ,uyoui Emmpte \ (Nuts D) * Snider Musk Opeiirig ' (Note F) 3nd Geo'riet'y (Nate 0) « NOTES. A, At "ieur d"rierisi'ur‘s are in rriit"rieters. in: drawing is subject ta :tidr‘ge wit'iuu: 'iut'ice PJbticut'dri tPCr7351 is recommended for atterriute cesig'is rnis Duckcge is d 'gned tn be sciderec to c ttierrridi pad on t'ie bocrc Re‘er to Appi'icdtiar Nate, arN Pacmqes‘ Texcs tr‘s. umerits Literature No SLUA271‘ c'id csa the Product Data St‘eets Jar specific thermut iriturr'iut'dri, via requirements, uric recommended bodrc tcyuut Tt‘ese cucumer‘ts are uvu'itubte at www ticom <'ittp. www="" ti.cum=""> E Laser cutti'ig coeriu'es witt‘ trupezuidut wcts arid atso rmrid'irq carriers w'iH o‘te' better pusie retease CJSTO'HEFS stimtd curitdct the'r :uurd cssemby site ‘or stencit desiqri recommendut'uris. Re‘er :0 WC 7525 for StE'iCit des'gri coris'derctioris, F Custcmers st‘oud :o'ituct their tmc'c fubr'catiori site for sutde' musk tuterurices 30:7 {i TEXAS INSTRUMENTS www.|i.ccm
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘ fimmamfl J
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
DBQOO16A
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PACKAGE OUTLINE
C
TYP-.244.228
-6.195.80[ ]
.069 MAX
[1.75]
14X .0250
[0.635]
16X -.012.008
-0.300.21[ ]
2X
.175
[4.45]
TYP-.010.005
-0.250.13[ ]
0- 8 -.010.004
-0.250.11[ ]
(.041 )
[1.04]
.010
[0.25]
GAGE PLANE
-.035.016
-0.880.41[ ]
A
NOTE 3
-.197.189
-5.004.81[ ]
B
NOTE 4
-.157.150
-3.983.81[ ]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
116
.007 [0.17] C A B
9
8
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
DBQOO16A 4%? ““‘+““‘ Egg P 4L
www.ti.com
EXAMPLE BOARD LAYOUT
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
(.213)
[5.4]
14X (.0250 )
[0.635]
16X (.063)
[1.6]
16X (.016 )
[0.41]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:8X
SYMM
1
89
16
SEE
DETAILS
DBQOO16A ¢§EE ““‘+““‘ Egg?
www.ti.com
EXAMPLE STENCIL DESIGN
16X (.063)
[1.6]
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
(.213)
[5.4]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
89
16
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