SSD1961 by Displaytech Datasheet

7 SOLOMON SVSTECII

SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

This document contains information on a new product. Specifications and information herein are subject to change

without notice.

http://www.solomon-systech.com

SSD1961

Advance Information

675KB Embedded Display SRAM

LCD Display Controller

V emion Change Items Effective Date

Solomon Systech Jul 2011 P 2/90 Rev 1.3 SSD1961

Appendix: IC Revision history of SSD1961 Specification

Version Change Items Effective Date

0.10

27-Mar-08 1st Release

02-Apr-08

0.20

17-Jul-08

1. Added Table 6-5.

2. Updated Table 12-1.

3. VSSIO and VSSD are tied together and renamed as VSS. Modified Figure 5-1,

Table 5-1 and Table 6-4.

4. Updated package information in Section 13.4.

5. Added Section 13.1.

28-Jul-08

0.30

09-Sep-08

1. Added Section 11 and 11.1.

2. Updated Figure 13-1, Figure 13-2 and Figure 13-3. 10-Sep-08

0.40

21-Nov-08

1. Added command descriptions in section 9

2. Added application circuit in section 13.4

3. Added SSD1961G40R part number

4. Added Tape & Reel drawing in section 15

5. Revised the VSS pin # (D5 and E5) in Table 6-4

6. Revised the Tape & Reel drawing in section 15

7. Updated maximum input clock frequency in Table 13-2

8. Updated 6-bit serial RGB in Table 6-5

9. Updated 9-bit interface in Table 7-1

24-Nov-08

0.50

08-Dec-08

1. Changed the set_pll_mnk to set_pll_mn in section 7.2

2. Change register name in section 8

3. Removed ABC

4. Revised description for REG 0x00, 0x01, 0x0C, 0x0D, 0x0E, 0x10, 0x11,

0x21, 0x26, 0x28, 0x2A, 0x2B, 0x2C, 0x2E, 0x33, 0x34, 0x35, 0x36, 0x37,

0x3A, 0x3C, 0x3E, 0x44, 0x45, 0xA1, 0xB0, 0xB1, 0xB4, 0xB5, 0xB6, 0xB7,

0xB8, 0xB9, 0xBE, 0xBF, 0xD0, 0xD1, 0xD4, 0xE5.

5. Added max VIH in Table 12-1

6. Added Table 9-1

7. Added Table 11-1

8. Revised Figure 9-19

9. Revised Figure 14-2

10. Revised Figure 13-5

11. Corrected typo for Table 7-2

12. Revised test condition for 12 and 13

10-Dec-08

1.0

07-May-09

1. Changed status to Advance Information

2. Update min/max rating of VDDD and VDDPLL in Table 11-1

3. Added serial RGB interface timing in Section 13.4

4. Revised Section 13.2

5. Added 12 bit in Table 7-1

6. Removed TTL interface

7. Changed the serial TFT interface from 6 bit to 8 bit

8. Revised section 7.1.5

9. Change the title of section 7.2

10. Revised command description in section 8.

11. Removed the command 0x0C and 0x3A

12. Added figures in section 13.4

13. Revised MCU Interface Timing in section 13.2

14. Revised figures in section 13.3

15. Revise Table 6-1

18-May-09

1.1

31-May-10

1. Updated Table 7-1

2. Revised section 9.72

3. Add table 13-7

15-Jul-10

1.2

11-Nov-10

1. Update Section 7.2 reset timing

2. Correct Section 13.4 the serial RGB timing

3. Correct Table 6.1-6.5 Pin Mapping -> Pin description

07-Dec-10

SSD1961 Rev 1.3 P 3/90 Jul 2011 Solomon Systech

1.3

21-Jul-11

1. Update Section 9.45 SET_PWM_CONF

Update Section 9.30 SET_TEAR_SCANLINE 25-Jul-11

 
 
Solomon Systech    Jul 2011 P 4/90  Rev 1.3  SSD1961 
 
 CONTENTS 
GENERAL DESCRIPTION ....................................................................................................... 9 
FEATURES................................................................................................................................... 9 
ORDERING INFORMATION................................................................................................... 9 
BLOCK DIAGRAM .................................................................................................................. 10 
PIN ARRANGEMENT.............................................................................................................. 11 
1 64 BALLS TFBGA...............................................................................................................................................11 
PIN DESCRIPTIONS................................................................................................................ 12 
FUNCTIONAL BLOCK DESCRIPTIONS............................................................................. 14 
1 MCU INTERFACE.................................................................................................................................................14 
1.1 6800 Mode ..................................................................................................................................................14 
1.2 8080 Mode ..................................................................................................................................................14 
1.3 Register Pin Mapping .................................................................................................................................14 
1.4 Pixel Data Format ......................................................................................................................................14 
1.5 Tearing Effect Signal (TE)..........................................................................................................................15 
2 SYSTEM CLOCK GENERATION .............................................................................................................................15 
3 FRAME BUFFER....................................................................................................................................................16 
4 SYSTEM CLOCK AND RESET MANAGER...............................................................................................................16 
5 LCD CONTROLLER ..............................................................................................................................................17 
5.1 Display Format...........................................................................................................................................17 
5.2 General Purpose Input/Output (GPIO) ......................................................................................................17 
COMMAND TABLE................................................................................................................. 18 
COMMAND DESCRIPTIONS................................................................................................. 21 
1 NOP......................................................................................................................................................................21 
2 SOFT_RESET.........................................................................................................................................................21 
3 GET_POWER_MODE..............................................................................................................................................21 
4 GET_ADDRESS_MODE ..........................................................................................................................................22 
5 GET_DISPLAY_MODE ...........................................................................................................................................22 
6 GET_TEAR_EFFECT_STATUS ................................................................................................................................23 
7 ENTER_SLEEP_MODE ...........................................................................................................................................24 
8 EXIT_SLEEP_MODE ..............................................................................................................................................24 
9 ENTER_PARTIAL_MODE .......................................................................................................................................24 
10 ENTER_NORMAL_MODE.......................................................................................................................................24 
11 EXIT_INVERT_MODE ............................................................................................................................................25 
12 ENTER_INVERT_MODE .........................................................................................................................................25 
13 SET_GAMMA_CURVE ...........................................................................................................................................26 
14 SET_DISPLAY_OFF ...............................................................................................................................................26 
15 SET_DISPLAY_ON.................................................................................................................................................26 
16 SET_COLUMN_ADDRESS ......................................................................................................................................27 
17 SET_PAGE_ADDRESS............................................................................................................................................27 
18 WRITE_MEMORY_START......................................................................................................................................28 
19 READ_MEMORY_START .......................................................................................................................................29 
20 SET_PARTIAL_AREA.............................................................................................................................................29 
21 SET_SCROLL_AREA..............................................................................................................................................31 
22 SET_TEAR_OFF ....................................................................................................................................................33 
23 SET_TEAR_ON......................................................................................................................................................33 
24 SET_ADDRESS_MODE...........................................................................................................................................33 
25 SET_SCROLL_START ............................................................................................................................................36 

 
SSD1961  Rev 1.3  P 5/90  Jul 2011    Solomon Systech
 
26 EXIT_IDLE_MODE ................................................................................................................................................37 
27 ENTER_IDLE_MODE .............................................................................................................................................37 
28 WRITE_MEMORY_CONTINUE................................................................................................................................38 
29 READ_MEMORY_CONTINUE .................................................................................................................................39 
30 SET_TEAR_SCANLINE...........................................................................................................................................40 
31 GET_SCANLINE ....................................................................................................................................................40 
32 READ_DDB...........................................................................................................................................................41 
33 SET_LCD_MODE...................................................................................................................................................41 
34 GET_LCD_MODE ..................................................................................................................................................43 
35 SET_HORI_PERIOD ...............................................................................................................................................44 
36 GET_HORI_PERIOD...............................................................................................................................................44 
37 SET_VERT_PERIOD...............................................................................................................................................45 
38 GET_VERT_PERIOD ..............................................................................................................................................46 
39 SET_GPIO_CONF...................................................................................................................................................47 
40 GET_GPIO_CONF ..................................................................................................................................................48 
41 SET_GPIO_VALUE ................................................................................................................................................49 
42 GET_GPIO_STATUS...............................................................................................................................................49 
43 SET_POST_PROC...................................................................................................................................................50 
44 GET_POST_PROC ..................................................................................................................................................50 
45 SET_PWM_CONF...................................................................................................................................................51 
46 GET_PWM_CONF ..................................................................................................................................................52 
47 SET_LCD_GEN0....................................................................................................................................................54 
48 GET_LCD_GEN0 ...................................................................................................................................................55 
49 SET_LCD_GEN1....................................................................................................................................................56 
50 GET_LCD_GEN1 ...................................................................................................................................................57 
51 SET_LCD_GEN2....................................................................................................................................................58 
52 GET_LCD_GEN2 ...................................................................................................................................................59 
53 SET_LCD_GEN3....................................................................................................................................................60 
54 GET_LCD_GEN3 ...................................................................................................................................................61 
55 SET_GPIO0_ROP ...................................................................................................................................................62 
56 GET_GPIO0_ROP...................................................................................................................................................62 
57 SET_GPIO1_ROP ...................................................................................................................................................63 
58 GET_GPIO1_ROP...................................................................................................................................................64 
59 SET_GPIO2_ROP ...................................................................................................................................................64 
60 GET_GPIO2_ROP...................................................................................................................................................65 
61 SET_GPIO3_ROP ...................................................................................................................................................66 
62 GET_GPIO3_ROP...................................................................................................................................................66 
63 SET_DBC_CONF....................................................................................................................................................67 
64 GET_DBC_CONF ...................................................................................................................................................68 
65 SET_DBC_TH........................................................................................................................................................69 
66 GET_DBC_TH .......................................................................................................................................................70 
67 SET_PLL...............................................................................................................................................................70 
68 SET_PLL_MN........................................................................................................................................................71 
69 GET_PLL_MN .......................................................................................................................................................72 
70 GET_PLL_STATUS ................................................................................................................................................72 
71 SET_DEEP_SLEEP .................................................................................................................................................72 
72 SET_LSHIFT_FREQ................................................................................................................................................73 
73 GET_LSHIFT_FREQ ...............................................................................................................................................73 
74 SET_PIXEL_DATA_INTERFACE .............................................................................................................................75 
75 GET_PIXEL_DATA_INTERFACE.............................................................................................................................75 
MAXIMUM RATINGS.......................................................................................................... 76 
RECOMMENDED OPERATING CONDITIONS ............................................................. 76 
1 POWER-UP SEQUENCE..........................................................................................................................................76 
DC CHARACTERISTICS..................................................................................................... 77 
AC CHARACTERISTICS..................................................................................................... 77 

Solomon Systech Jul 2011 P 6/90 Rev 1.3 SSD1961

13.1 CLOCK TIMING ....................................................................................................................................................77

13.2 MCU INTERFACE TIMING....................................................................................................................................78

13.2.1 Parallel 6800-series Interface Timing ........................................................................................................78

13.2.2 Parallel 8080-series Interface Timing ........................................................................................................80

13.3 PARALLEL LCD INTERFACE TIMING....................................................................................................................82

13.4 SERIAL RGB INTERFACE TIMING ........................................................................................................................83

14 APPLICATION EXAMPLE.................................................................................................. 86

15 PACKAGE INFORMATION................................................................................................ 88

15.1 PACKAGE MECHANICAL DRAWING FOR TFBGA.................................................................................................88

15.2 TAPE & REEL DRAWING FOR TFBGA .................................................................................................................89

 
SSD1961  Rev 1.3  P 7/90  Jul 2011    Solomon Systech
 
TABLES 
TABLE 3-1: ORDERING INFORMATION ...................................................................................................................................9 
TABLE 5-1: TFBGA PIN ASSIGNMENT TABLE.....................................................................................................................11 
TABLE 6-1: MCU INTERFACE PIN DESCRIPTION .................................................................................................................12 
TABLE 6-2: LCD INTERFACE PIN DESCRIPTION...................................................................................................................12 
TABLE 6-3: CONTROL SIGNAL PIN DESCRIPTION.................................................................................................................13 
TABLE 6-4: POWER PIN  DESCRIPTION.................................................................................................................................13 
TABLE 6-5: LCD INTERFACE PIN MAPPING.........................................................................................................................13 
TABLE 7-1: PIXEL DATA FORMAT .......................................................................................................................................14 
TABLE 7-2: FRAME BUFFER SETTINGS REGARDING TO SET_ADDRESS_MODE COMMAND 0X36...........................................16 
TABLE 9-1: ENTER IDLE MODE MEMORY CONTENT VS DISPLAY COLOR ..............................................................................38 
TABLE 10-1: MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS)...................................................................................76 
TABLE 11-1: RECOMMENDED OPERATING CONDITION........................................................................................................76 
TABLE 12-1: DC CHARACTERISTICS....................................................................................................................................77 
TABLE 13-1: CLOCK INPUT REQUIREMENTS FOR CLK (PLL-BYPASS) ................................................................................77 
TABLE 13-2: CLOCK INPUT REQUIREMENTS FOR CLK (PLL-ENABLED)..............................................................................77 
TABLE 13-3: CLOCK INPUT REQUIREMENTS FOR CRYSTAL OSCILLATOR XTAL (PLL-ENABLED) .......................................77 
TABLE 13-4: PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (USE CS# AS CLOCK)...................................78 
TABLE 13-5: PARALLEL 6800-SERIES INTERFACE TIMING CHARACTERISTICS (USE E AS CLOCK).......................................79 
TABLE 13-6: PARALLEL 8080-SERIES INTERFACE TIMING CHARACTERISTICS.....................................................................80 
TABLE 13-7: QUICK REFERENCE TABLE FOR LCD PARAMETER SETTING .............................................................................85 

 
 
Solomon Systech    Jul 2011 P 8/90  Rev 1.3  SSD1961 
 
FIGURES 
FIGURE 4-1: SSD1961 BLOCK DIAGRAM ............................................................................................................................10 
FIGURE 5-1: PINOUT DIAGRAM – 64 BALLS TFBGA (TOP VIEW) ........................................................................................11 
FIGURE 7-1: RELATIONSHIP BETWEEN TEARING EFFECT SIGNAL AND MCU MEMORY WRITING........................................15 
FIGURE 7-2: CLOCK CONTROL DIAGRAM ............................................................................................................................16 
FIGURE 7-3: STATE DIAGRAM OF SSD1961 ........................................................................................................................17 
FIGURE 9-1: EXIT INVERT MODE EXAMPLE..........................................................................................................................25 
FIGURE 9-2: ENTER INVERT MODE EXAMPLE.......................................................................................................................26 
FIGURE 9-3: SET COLUMN ADDRESS EXAMPLE ...................................................................................................................27 
FIGURE 9-4: SET PAGE ADDRESS EXAMPLE .........................................................................................................................28 
FIGURE 9-5: SET PARTIAL AREA WITH  SET_ADDRESS_MODE (0X36) A[4] = 0 WHEN END ROW > START ROW..................30 
FIGURE 9-6: SET PARTIAL AREA WITH  SET_ADDRESS_MODE (0X36) A[4] = 1 WHEN END ROW > START ROW..................30 
FIGURE 9-7: SET PARTIAL AREA WITH  SET_ADDRESS_MODE (0X36) A[4] = 0 WHEN START ROW > END ROW..................30 
FIGURE 9-8: SET PARTIAL AREA WITH  SET_ADDRESS_MODE (0X36) A[4] = 1 WHEN START ROW > END ROW..................31 
FIGURE 9-9: SET SCROLL AREA  WITH SET_ADDRESS_MODE (0X36) A[4] = 0.....................................................................32 
FIGURE 9-10: SET SCROLL AREA  WITH SET_ADDRESS_MODE (0X36) A[4] = 1...................................................................32 
FIGURE 9-11: A[7] PAGE ADDRESS ORDER .........................................................................................................................34 
FIGURE 9-12: A[6] COLUMN ADDRESS ORDER....................................................................................................................34 
FIGURE 9-13: A[5] PAGE / COLUMN ADDRESS ORDER ........................................................................................................34 
FIGURE 9-14: A[3] RGB ORDER..........................................................................................................................................35 
FIGURE 9-15: A[1] FLIP HORIZONTAL .................................................................................................................................35 
FIGURE 9-16: A[0] FLIP VERTICAL......................................................................................................................................36 
FIGURE 9-17: SET SCROLL START  WITH SET_ADDRESS_MODE (0X36) A[4] = 0..................................................................36 
FIGURE 9-18: SET SCROLL START  WITH SET_ADDRESS_MODE (0X36) A[4] = 1..................................................................37 
FIGURE 9-19: PWM SIGNAL ................................................................................................................................................51 
FIGURE 11-1: POWER-UP SEQUENCE ...................................................................................................................................76 
FIGURE 13-1: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE CS# AS CLOCK)...............................................78 
FIGURE 13-2: PARALLEL 6800-SERIES INTERFACE TIMING DIAGRAM (USE E AS CLOCK)...................................................79 
FIGURE 13-3: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (WRITE CYCLE) .......................................................80 
FIGURE 13-4: PARALLEL 8080-SERIES INTERFACE TIMING DIAGRAM (READ CYCLE).........................................................81 
FIGURE 13-5: GENERIC TFT PANEL TIMING........................................................................................................................82 
FIGURE 13-6: SERIAL RGB INTERFACE TIMING (WITHOUT DUMMY MODE).........................................................................83 
FIGURE 13-7: SERIAL RGB INTERFACE TIMING (WITH DUMMY MODE) ...............................................................................84 
FIGURE 14-1: APPLICATION CIRCUIT FOR SSD1961 (WITH DIRECT CLOCK INPUT) .............................................................86 
FIGURE 14-2: APPLICATION CIRCUIT FOR SSD1961 (WITH CRYSTAL OSCILLATOR INPUT)..................................................87 
  

SSD1961 Rev 1.3 P 9/90 Jul 2011 Solomon Systech

1 GENERAL DESCRIPTION

SSD1961 is a display controller of 5,529,600 bit frame buffer to support up to 640 x 480 x 18bit graphics

content. It also equips parallel MCU interfaces in different bus width to receive graphics data and command

from MCU. Its display interface supports common RAM-less LCD driver of color depth up to 18 bit-per-

pixel.

2 FEATURES

• Display feature

− 675kbyte (5,529,600bit) built-in frame buffer. Support up to 640 x 480 at 18bpp display

− Support TFT 18 bit generic RGB interface panel

− Support 8-bit serial RGB interface

− Hardware rotation of 0, 90, 180, 270 degree

− Hardware display mirroring

− Hardware windowing

− Programmable brightness, contrast and saturation control

− Dynamic Backlight Control (DBC) via PWM signal

• MCU connectivity

− 8/9/16/18-bit MCU interface

− Tearing effect signal

• I/O Connectivity

− 4 GPIO pins

• Built-in clock generator

• Deep sleep mode for power saving

• 64 pin BGA package

• Core supply power (VDDPLL and VDDD): 1.2V±0.1V

• I/O supply power (VDDIO): 1.65V to 3.6V

• LCD interface supply power (VDDLCD): 1.65V to 3.6V

3 ORDERING INFORMATION

Table 3-1: Ordering Information

Ordering Part Number Package Form

SSD1961G40 TFBGA-64 (Tray)

SSD1961G40R TFBGA-64 (Tape & Reel)

csu u/ca Registers MAME EWDW} R/WMWRW MCU LLINE [mm] Interface mm .— 00: LCD 8 Controller 5 LWNM' 2'33)??? g System crock , , I mm 8 (worm! and Reset Mgr Rc|alron/ error GAMASU or Crock Generator FWM DBC

Solomon Systech Jul 2011 P 10/90 Rev 1.3 SSD1961

4 BLOCK DIAGRAM

Figure 4-1: SSD1961 Block Diagram

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SSD1961 Rev 1.3 P 11/90 Jul 2011 Solomon Systech

5 PIN ARRANGEMENT

5.1 64 Balls TFBGA

Figure 5-1: Pinout Diagram – 64 balls TFBGA (Top view)

Table 5-1: TFBGA Pin Assignment Table

Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name

A1 VDDLCD C1 LDATA13 E1 LDATA5 G1 D[16]

A2 LDATA16 C2 LDATA12 E2 LDATA4 G2 D[14]

A3 GAMAS1 C3 LDATA11 E3 LDATA3 G3 D[12]

A4 TE C4 LDATA10 E4 LDATA2 G4 D[9]

A5 LSHIFT C5 LDEN E5 VSS G5 D[6]

A6 GPIO3 C6 LFRAME E6 R/W#(WR#) G6 D/C#

A7 VSSPLL C7 GPIO1 E7 D[3] G7 RESET#

A8 VDDPLL C8 XTAL_IN E8 CLK G8 D[0]

B1 LDATA15 D1 LDATA9 F1 LDATA1 H1 D[17]

B2 LDATA14 D2 LDATA8 F2 LDATA0 H2 D[15]

B3 GAMAS0 D3 LDATA7 F3 D[13] H3 D[11]

B4 PWM D4 LDATA6 F4 D[10] H4 D[8]

B5 LLINE D5 VSS F5 D[7] H5 D[5]

B6 GPIO2 D6 VDDD F6 E(RD#) H6 CS#

B7 GPIO0 D7 D[4] F7 D[2] H7 CONF

B8 XTAL_OUT D8 LDATA17 F8 D[1] H8 VDDIO

Level

Solomon Systech Jul 2011 P 12/90 Rev 1.3 SSD1961

6 PIN DESCRIPTIONS

Key: I = Input

O =Output

IO = Bi-directional (input/output)

P = Power pin

Hi-Z = High impedance

Table 6-1: MCU Interface Pin Description

Pin Name Type Reference

Voltage

Level Pin # Description

CLK I VDDIO E8

TTL clock input. This pin should be tied to VSS if TTL

clock input is not used

XTAL_IN I - C8

Crystal oscillator input. This pin should be tied to VSS if

not used

XTAL_OUT O - B8

Crystal oscillator output. This pin should be floating if not

used

CS# I VDDIO H6 Chip select

D/C# I VDDIO G6 Data/Command select

E(RD#) I VDDIO F6

6800 mode: E (enable signal)

8080 mode: RD# (read strobe signal)

R/W#(WR#) I VDDIO E6

6800 mode: R/W#

0: Write cycle

1: Read cycle

8080 mode: WR# (write strobe signal)

D[17:0] IO VDDIO

D7, E7,

F3-F5,

F7-F8,

G1-G5,

G8, H1-

H5

Data bus. Pins not used should be floating

TE O VDDLCD A4 Tear effect

Table 6-2: LCD Interface Pin Description

Pin Name Type Reference

Voltage

Level Pin # Description

LFRAME O VDDLCD C6 Vertical sync (Frame pulse)

LLINE O VDDLCD B5 Horizontal sync (Line pulse)

LSHIFT O VDDLCD A5 Pixel clock (Pixel shift signal)

LDEN O VDDLCD C5 Data valid

LDATA[17:0] O VDDLCD

A2, B1-

B2, C1-

C4, D1-

D4, D8,

E1-E4,

F1-F2

RGB data

GPIO[3:0] IO VDDLCD

A6, B6-

B7, C7 These pins be configured for display miscellaneous signals

or as general purpose I/O. Default as input

GAMAS [1:0] O VDDLCD A3, B3 Gamma selection for panel

PWM O VDDLCD B4 PWM output for backlight driver

SSD1961 Rev 1.3 P 13/90 Jul 2011 Solomon Systech

Table 6-3: Control Signal Pin Description

Pin Name Type Reference

Voltage

Level Pin # Description

RESET# I VDDIO G7 Master synchronize reset

CONF I VDDIO H7

MCU interface configuration

0: 6800 Interface

1: 8080 Interface

Table 6-4: Power Pin Description

Pin Name Type Pin # Description

VDDD P D6 Power supply for internal digital circuit

VDDLCD P A1 Power supply for LCD interface related pads

VDDPLL P A8

Power supply for internal analog circuit and analog I/O

pads

VDDIO P H8 Power supply for digital I/O pads

VSS P D5, E5 Ground for internal digital circuit

VSSPLL P A7 Ground for internal analog circuit and analog I/O pads

Table 6-5: LCD Interface Pin Mapping

Pin Names 18-bit TFT 8-bit Serial

LFRAME FRAME

LLINE LINE

LSHIFT SHIFT

LDEN DEN

LDATA17 R5 Drive 0

LDATA16 R4 Drive 0

LDATA15 R3 Drive 0

LDATA14 R2 Drive 0

LDATA13 R1 Drive 0

LDATA12 R0 Drive 0

LDATA11 G5 Drive 0

LDATA10 G4 Drive 0

LDATA9 G3 Drive 0

LDATA8 G2 Drive 0

LDATA7 G1 D7

LDATA6 G0 D6

LDATA5 B5 D5

LDATA4 B4 D4

LDATA3 B3 D3

LDATA2 B2 D2

LDATA1 B1 D1

LDATA0 B0 D0

Note

(1) These pin mappings use signal names commonly used for each panel type, however signal names

may differ between panel manufacturers.

Solomon Systech Jul 2011 P 14/90 Rev 1.3 SSD1961

7 FUNCTIONAL BLOCK DESCRIPTIONS

7.1 MCU Interface

The MCU interface connects the MCU and SSD1961 graphics controller. The MCU interface can be

configured as 6800 mode and 8080 mode by the CONF pin. By pulling the CONF pin to VSS, the MCU

interface will be configured as 6800 mode interface. If the CONF pin is connected to VDDIO, the MCU

interface will be configured as 8080 mode.

7.1.1 6800 Mode

The 6800 mode MCU interface consist of CS#, D/C#, E, R/W#, D[17:0], and TE signals (Please refer to

Table 6-1 for pin multiplexed with 8080 mode). This interface supports both fixed E and clock E scheme to

define a read/write cycle. If the E signal is kept high and used as enable signal, the CS# signal acts as a bus

clock, the data or command will be latched into the system at the rising edge of CS#. If the user wants to use

the E pin as the clock pin, the CS# pin then need to be fixed to logic 0 to select the chip. Then the falling

edge of the E signal will latch the data or command. For details, please refer to the timing diagram in chapter

13.2.1.

7.1.2 8080 Mode

The 8080 mode MCU interface consist of CS#, D/C#, RD#, WR#, D[17:0] and TE signals (Please refer to

Table 6-1 for pin multiplexed with 6800 mode). This interface use WR# to define a write cycle and RD# for

read cycle. If the WR# goes low when the CS# signal is low, the data or command will be latched into the

system at the rising edge of WR#. Similarly, the read cycle will start when RD# goes low and end at the

rising edge of RD#. The detailed timing will show in the chapter Error! Reference source not found..

7.1.3 Register Pin Mapping

When user access the registers via the parallel MCU interface, only D[7:0] will be used regardless the width

of the pixel data is. Therefore, D[17:8] will only be used to address the display data only. This provided the

possibility that the pixel data format as shown in Table 7-1 can be configured by command 0xF0.

7.1.4 Pixel Data Format

Both 6800 and 8080 support 8 bit, 16 bit, 18 bit data bus. Depending on the width of the data bus, the display

data are packed into the data bus in different ways.

Table 7-1: Pixel Data Format

Interface Cycle D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

18 bits 1

st

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

16 bits (565 format) 1

st

R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1

1

st

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0

2

nd

B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 R3 R2 R1 R0

3

rd

G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

1

st

R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4

2

nd

G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

1

st

R5 R4 R3 R2 R1 R0 G5 G4 G3

2

nd

G2 G1 G0 B5 B4 B3 B2 B1 B0

1

st

R7 R6 R5 R4 R3 R2 R1 R0

2

nd

G7 G6 G5 G4 G3 G2 G1 G0

3

rd

B7 B6 B5 B4 B3 B2 B1 B0

X: Don't Care

16 bits

8 bits

9 bits

12 bits

Display Period Display Period TE 100% Memon/ Access 0% Fasl Write MCU Slow Write MCU — LCD Controller

SSD1961 Rev 1.3 P 15/90 Jul 2011 Solomon Systech

7.1.5 Tearing Effect Signal (TE)

The Tearing Effect Signal (TE) is a feedback signal from the LCD Controller to MCU. This signal reveals

the display status of LCD controller. In the non-display period, the TE signal will go high. Therefore, this

signal enables the MCU to send data by observing the non-display period to avoid tearing.

Figure 7-1 shows how the TE signal helps to avoid tearing. If the MCU writing speed is slower than the

display speed, the display data should be updated after the LCD controller start to scan the frame buffer.

Then the LCD controller will always display the old memory content until the next frame. However, if the

MCU is faster than the LCD controller, it should start updating the display content in the vertical non-display

period (VNDP) to enable the LCD controller will always get the newly updated data.

Figure 7-1: Relationship between Tearing Effect Signal and MCU Memory Writing

In SSD1961, users can configure the TE signal to reflect the vertical non-display period only or reflect both

vertical and horizontal non-display period. With the additional horizontal non-display period information, the

MCU can control the refresh action in more accurately by counting the horizontal line scanned by the LCD

controller. Usually, a fast MCU will not need horizontal non-display period. But a slow MCU will need it to

ensure the frame buffer update process always lags behind the LCD controller.

7.2 System Clock Generation

The system clock of SSD1961 is generated by the built-in PLL. The reference clock of the PLL can come

from either the CLK pin or the external crystal oscillator. Since the CLK pin and the output of the oscillator

was connected to PLL with an “OR” gate, the unused clock must be tied to VSS.

Before the PLL output is configured as the system clock by the bit 1 of “set_pll” command 0xE0, the system

will be clocked by the reference clock. This enables the user to send the “set_pll_mn” command 0xE2 to the

PLL for frequency configuration. When the PLL frequency is configured and the PLL was enabled with the

Opllon 1 Horizontal: lncremenl Vertical' Increment 36 : 0, B7 : 0 Option 2 Horizontal lncrement Vertical Decrement BS : 0, B7 : 1 Oplion 3 Horizontal: Decremenl Venical' Incremenl BS : 1. B7 : 0 0pm" 4 Horlzonlal: Decrement Vemcal' Decremenl BS : 1‘ B7 : 1 Horlzonlal Frame Buffer Mode B5 = 0 OODDDh 00000h DDDDOh OOUOOh / \ \ /' 4BOOOh 4BOODh 4BUUUh 4EOOOh Vemcal Frame Buﬂer Mode BS : 1 00000h OOOOOh ODDDDh UUUUDh / \ \ / 4BOOOh 45000h 4BOOOh ABOOOh

Solomon Systech Jul 2011 P 16/90 Rev 1.3 SSD1961

bit 0 of “set_pll” command 0xE0, the user should still wait for 100us for the PLL to lock. Then the PLL is

ready and can be configured as system clock with the bit 1 of “set_pll” command 0xE0.

Figure 7-2: Clock Control Diagram

7.3 Frame Buffer

There are 5,529,600 bit built-in SRAM inside SSD1961 to use as frame buffer. When the frame buffer is

written or read, the “address counter” will automatically increase by one or decrease by one depends on the

frame buffer settings.

Table 7-2: Frame Buffer Settings regarding to set_address_mode command 0x36

7.4 System Clock and Reset Manager

The “System Clock and Reset Manager” distributes the reset signal and clock signal to the entire system. It

controls the Clock Generator and contains clock gating circuitry to turn on and off the clock of each

functional module. Also, it divides the root clock from Clock Generator to operation clocks for different

module. The System Clock and Reset Manager also manage the reset signals to ensure all the module are

reset to appropriate status when the system are in reset state, deep sleep state, sleep state and display state.

Figure 7-3 shows a state diagram of four operation states of SSD1961.

1/N

1/M

CLK

PLL

REF

FB

1

0

set_pll bit 1

System Clock

OSC

XTAL_IN XTAL_OUT

EXTERNAL

CRYSTAL

EN

set_pll bit 0

Rc‘casc REsz Reset S‘am Dummy Read RESET» Gm Law RESET» Gnes Law RESET" Goes Low Deep Sleep Slate msplay on Command been S‘eeD msplay on Command Command Dccv sleep Command Dwsp‘ay Slate Resel Sla‘e Deep S‘eep Stake' Sleep Skale' D‘sp‘ay Stale Cmck Generator Smp mack Generamr Slap C‘ock Generalar On C‘ock Generamr 0n Ab‘e to Reserve Command Unab‘e to Recewe Command Unab‘e to Recewe Command Ab‘e to Recewe Cammand Uname to Update Frame Buﬂer Unab‘e (o Updale Frame Buwer Ab‘e to Updale Frame Buffer Ame to Update Frame Buffer Dwsp‘ay on Dwsp‘ay on Dwsp‘ay 0n Drsmay Off AH Semngs Relam AH Senings Ream Au Semngs Resel Au Senings Retam

SSD1961 Rev 1.3 P 17/90 Jul 2011 Solomon Systech

Figure 7-3: State Diagram of SSD1961

7.5 LCD Controller

7.5.1 Display Format

The LCD controller reads the frame buffer and generates display signals according to the selected display

panel format. SSD1961 supports common RAM-less TFT driver using generic RGB data.

7.5.2 General Purpose Input/Output (GPIO)

The GPIO pins can operate in 2 modes, GPIO mode and miscellaneous display signal mode. When the pins

are configured as GPIOs, these pins can be controlled directly by MCU. Therefore, user can use these pins to

emulate other interface such as SPI or I2C. If these pins are configured as display signals, they will toggle

with display periodically according to the signal settings. They can be set to toggle once a frame, once a line

or in arbitrary period. Therefore they can be configured as some common signal needed for different panels

such as STH or LP.

Solomon Systech Jul 2011 P 18/90 Rev 1.3 SSD1961

8 COMMAND TABLE

Hex Code Command Description

0x00 nop No operation

0x01 soft_reset Software Reset

0x0A get_power_mode Get the current power mode

0x0B get_address_mode Get the frame buffer to the display panel read order

0x0C Reserved Reserved

0x0D get_display_mode The SSD1961 returns the Display Image Mode.

0x0E get_tear_effect_status Get the Tear Effect status

0x0F Reserved Reserved

0x10 enter_sleep_mode

Turn off the panel. This command will pull low the GPIO0.

If GPIO0 is configured as normal GPIO or LCD

miscellaneous signal with command set_gpio_conf, this

command will be ignored.

0x11 exit_sleep_mode

Turn on the panel. This command will pull high the GPIO0.

If GPIO0 is configured as normal GPIO or LCD

miscellaneous signal with command set_gpio_conf, this

command will be ignored.

0x12 enter_partial_mode Part of the display area is used for image display.

0x13 enter_normal_mode The whole display area is used for image display.

0x20 exit_invert_mode Displayed image colors are not inverted.

0x21 enter_invert_mode Displayed image colors are inverted.

0x26 set_gamma_curve Selects the gamma curve used by the display panel.

0x28 set_display_off Blanks the display panel

0x29 set_display_on Show the image on the display panel

0x2A set_column_address Set the column address

0x2B set_page_address Set the page address

0x2C write_memory_start Transfer image information from the host processor interface

to the SSD1961 starting at the location provided by

set_column_address and set_page_address

0x2E read_memory_start Transfer image data from the SSD1961 to the host processor

interface starting at the location provided by

set_column_address and set_page_address

0x30 set_partial_area Defines the partial display area on the display panel

0x33 set_scroll_area Defines the vertical scrolling and fixed area on display area

0x34 set_tear_off Synchronization information is not sent from the SSD1961 to

the host processor

0x35 set_tear_on Synchronization information is sent from the SSD1961 to the

host processor at the start of VFP

0x36 set_address_mode Set the read order from frame buffer to the display panel

0x37 set_scroll_start Defines the vertical scrolling starting point

0x38 exit_idle_mode Full color depth is used for the display panel

0x39 enter_idle_mode Reduce color depth is used on the display panel.

0x3A Reserved Reserved

0x3C write_memory_continue

Transfer image information from the host processor interface

to the SSD1961 from the last written location

0x3E read_memory_continue

Read image data from the SSD1961 continuing after the last

read_memory_continue or read_memory_start

SSD1961 Rev 1.3 P 19/90 Jul 2011 Solomon Systech

Hex Code Command Description

0x44 set_tear_scanline Synchronization information is sent from the SSD1961to the

host processor when the display panel refresh reaches the

provided scanline

0x45 get_scanline Get the current scan line

0xA1 read_ddb Read the DDB from the provided location

0xA8 Reserved Reserved

0xB0 set_lcd_mode_ Set the LCD panel mode and resolution

0xB1 get_lcd_mode Get the current LCD panel mode, pad strength and resolution

0xB4 set_hori_period Set front porch

0xB5 get_hori_period Get current front porch settings

0xB6 set_vert_period Set the vertical blanking interval between last scan line and

next LFRAME pulse

0xB7 get_vert_period Set the vertical blanking interval between last scan line and

next LFRAME pulse

0xB8 set_gpio_conf Set the GPIO configuration. If the GPIO is not used for LCD,

set the direction. Otherwise, they are toggled with LCD

signals.

0xB9 get_gpio_conf Get the current GPIO configuration

0xBA set_gpio_value Set GPIO value for GPIO configured as output

0xBB get_gpio_status Read current GPIO status. If the individual GPIO was

configured as input, the value is the status of the

corresponding pin. Otherwise, it is the programmed value.

0xBC set_post_proc Set the image post processor

0xBD get_post_proc Set the image post processor

0xBE set_pwm_conf Set the image post processor

0xBF get_pwm_conf Set the image post processor

0xC0 set_lcd_gen0 Set the rise, fall, period and toggling properties of LCD signal

generator 0

0xC1 get_lcd_gen0 Get the current settings of LCD signal generator 0

0xC2 set_lcd_gen1 Set the rise, fall, period and toggling properties of LCD signal

generator 1

0xC3 get_lcd_gen1 Get the current settings of LCD signal generator 1

0xC4 set_lcd_gen2 Set the rise, fall, period and toggling properties of LCD signal

generator 2

0xC5 get_lcd_gen2 Get the current settings of LCD signal generator 2

0xC6 set_lcd_gen3 Set the rise, fall, period and toggling properties of LCD signal

generator 3

0xC7 get_lcd_gen3 Get the current settings of LCD signal generator 3

0xC8 set_gpio0_rop Set the GPIO0 with respect to the LCD signal generators

using ROP operation. No effect if the GPIO0 is configured as

general GPIO.

0xC9 get_gpio0_rop Get the GPIO0 properties with respect to the LCD signal

generators.

0xCA set_gpio1_rop Set the GPIO1 with respect to the LCD signal generators

using ROP operation. No effect if the GPIO1 is configured as

general GPIO.

0xCB get_gpio1_rop Get the GPIO1 properties with respect to the LCD signal

generators.

0xCC set_gpio2_rop Set the GPIO2 with respect to the LCD signal generators

using ROP operation. No effect if the GPIO2 is configured as

general GPIO.

Solomon Systech Jul 2011 P 20/90 Rev 1.3 SSD1961

Hex Code Command Description

0xCD get_gpio2_rop Get the GPIO2 properties with respect to the LCD signal

generators.

0xCE set_gpio3_rop Set the GPIO3 with respect to the LCD signal generators

using ROP operation. No effect if the GPIO3 is configured as

general GPIO.

0xCF get_gpio3_rop Get the GPIO3 properties with respect to the LCD signal

generators.

0xD0 set_dbc_conf Set the dynamic back light configuration

0xD1 get_dbc_conf Get the current dynamic back light configuration

0xD4 set_dbc_th Set the threshold for each level of power saving

0xD5 get_dbc_th Get the threshold for each level of power saving

0xE0 set_pll Start the PLL. Before the start, the system was operated with

the crystal oscillator or clock input

0xE2 set_pll_mn Set the PLL

0xE3 get_pll_mn Get the PLL settings

0xE4 get_pll_status Get the current PLL status

0xE5 set_deep_sleep Set deep sleep mode

0xE6 set_lshift_freq Set the LSHIFT (pixel clock) frequency

0xE7 get_lshift_freq Get current LSHIFT (pixel clock) frequency setting

0xE8 Reserved Reserved

0xE9 Reserved Reserved

0xF0 set_pixel_data_interface Set the pixel data format of the parallel host processor

interface

0xF1 get_pixel_data_interface Get the current pixel data format settings

0xFF Reserved Reserved

SSD1961 Rev 1.3 P 21/90 Jul 2011 Solomon Systech

9 COMMAND DESCRIPTIONS

9.1 nop

Command 0x00

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 0 0 0 0 0 00

Description

No operation. .

9.2 soft_reset

Command 0x01

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 0 0 0 0 1 01

Description

The SSD1961 performs a software reset. All the configuration register will be reset except command 0xE0 to 0xE5.

Note :

The host processor must wait 5ms before sending any new commands to a SSD1961 following this command.

9.3 get_power_mode

Command 0x0A

Parameters 1

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 0 1 0 1 0 0A

Parameter 1 1 0 A6 A

5 A

4 A

3 A

2 0 0 xx

Description

Get the current power mode

A[6] : Idle mode on/off (POR = 0)

0 Idle mode off

1 Idle mode on

A[5] : Partial mode on/off (POR = 0)

0 Partial mode off

1 Partial mode on

A[4] : Sleep mode on/off (POR = 0)

0 Sleep mode on

1 Sleep mode off

A[3] : Display normal mode on/off (POR = 1)

0 Display normal mode off

Solomon Systech Jul 2011 P 22/90 Rev 1.3 SSD1961

1 Display normal mode on (partial mode and vertical scroll off)

A[2] : Display on/off (POR = 0)

0 Display is off

1 Display is on

9.4 get_address_mode

Command 0x0B

Parameters 1

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 0 1 0 1 1 0B

Parameter 1 1 A7 A

6 A

5 A

4 A

3 A

2 0 0 xx

Description

Get the frame buffer to the display panel read order

A[7] : Page address order (POR = 0)

0 Top to bottom

1 Bottom to top

A[6] : Column address order (POR = 0)

0 Left to right

1 Right to left

A[5] : Page / Column order (POR = 0)

0 Normal mode

1 Reverse mode

A[4] : Line address order (POR = 0)

0 LCD refresh top to bottom

1 LCD refresh bottom to top

A[3] : RGB / BGR order (POR = 0)

0 RGB

1 BGR

A[2] : Display data latch data (POR = 0)

0 LCD refresh left to right

1 LCD refresh right to left

9.5 get_display_mode

Command 0x0D

Parameters 1

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 0 1 1 0 1 0D

Parameter 1 1 A7 0 A5 0 0 A2 A

1 A

0 xx

Description

The SSD1961 returns the Display Image Mode status.

A[7] : Vertical scrolling status on/off (POR = 0)

0 Vertical scrolling is off

1 Vertical scrolling is on

SSD1961 Rev 1.3 P 23/90 Jul 2011 Solomon Systech

A[5] : Invert mode on/off (POR = 0)

0 Inversion is off

1 Inversion is on

A[2:0] : Gamma curve selection (POR = 011)

000 Gamma curve 0

001 Gamma curve 1

010 Gamma curve 2

011 Gamma curve 3

100 Reserved

101 Reserved

110 Reserved

111 Reserved

9.6 get_tear_effect_status

Command 0x0E

Parameters 1

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 0 1 1 1 0 0E

Parameter 1 1 A7 0 0 0 0 0 0 0 xx

Description

Get the current Tear Effect mode from the SSD1961

A[7] : Tearing effect line mode (POR = 0)

0 Tearing effect off

1 Tearing effect on

Solomon Systech Jul 2011 P 24/90 Rev 1.3 SSD1961

9.7 enter_sleep_mode

Command 0x10

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 1 0 0 0 0 10

Description

Turn off the panel. This command causes the SSD1961 to enter sleep mode and pull low the GPIO[0] if set_gpio_conf

(0xB8) B0 = 0.

If GPIO[0] is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf (0xB8), this

command will not affect the GPIO[0].

Note :

The host processor must wait 5ms before sending any new commands to a SSD1961 following this command.

9.8 exit_sleep_mode

Command 0x11

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 1 0 0 0 1 11

Description

Turn on the panel. This command causes the SSD1961 to exit sleep mode and will pull high the GPIO[0] if

set_gpio_conf (0xB8) B0 = 0.

If GPIO[0] is configured as normal GPIO or LCD miscellaneous signal with command set_gpio_conf (0xB8), this

command will not affect the GPIO[0].

Note : The host processor must wait 5ms after sending this command before sending another command.

**This command will automatic trigger set_display_on (0x29)

9.9 enter_partial_mode

Command 0x12

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 1 0 0 1 0 12

Description

Once enter_partial_mode is triggered, the Partial Display Mode window is described by the set_partial_area (0x30).

Once enter_normal_mode (0x13) is triggered, partial display mode will end.

9.10 enter_normal_mode

Command 0x13

Parameters None

SSD1961 Rev 1.3 P 25/90 Jul 2011 Solomon Systech

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 0 1 0 0 1 1 13

Description

This command causes the SSD1961 to enter the normal mode. Normal mode is defined as partial display and vertical

scroll mode are off. That means the whole display area is used for image display.

9.11 exit_invert_mode

Command 0x20

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 0 0 0 0 20

Description

This command causes the SSD1961 to stop inverting the image data on the display panel. The frame buffer contents

remain unchanged.

Figure 9-1: Exit Invert mode example

Frame Buffer Display Panel

Ö

9.12 enter_invert_mode

Command 0x21

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 0 0 0 1 21

Description

This command causes the SSD1961 to invert the image data only on the display panel. The frame buffer contents remain

unchanged.

Solomon Systech Jul 2011 P 26/90 Rev 1.3 SSD1961

Figure 9-2: Enter Invert mode example

Frame Buffer Display Panel

Ö

9.13 set_gamma_curve

Command 0x26

Parameters 1

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 0 1 1 0 26

Parameter 1 1 0 0 0 0 A3 A

2 A

1 A

0 xx

Description

Selects the gamma curve used by the display panel.

A[3:0] Gamma curve selection (POR = 1000) GAMAS[1] GAMAS[0]

0000 No gamma curve selected (Same as 0001b) 0 0

0001 Gamma curve 0 0 0

0010 Gamma curve 1 0 1

0100 Gamma curve 2 1 0

1000 Gamma curve 3 1 1

Others Reserved

9.14 set_display_off

Command 0x28

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 1 0 0 0 28

Description

Blanks the display panel. The frame buffer contents remain unchanged.

9.15 set_display_on

Command 0x29

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 1 0 0 1 29

Description

Show the image on the display panel

SSD1961 Rev 1.3 P 27/90 Jul 2011 Solomon Systech

9.16 set_column_address

Command 0x2A

Parameters 4

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 1 0 1 0 2A

Parameter 1 1 SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 xx

Parameter 2 1 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 xx

Parameter 3 1 EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 xx

Parameter 4 1 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 xx

Description

Set the column address of frame buffer accessed by the host processor with the read_memory_continue (0x3E) and

write_memorty_continue (0x3C)..

SC[15:8] : Start column number high byte (POR = 00000000)

SC[7:0] : Start column number low byte (POR = 00000000)

EC[15:8] : End column number high byte (POR = 00000000)

EC[7:0] : End column number low byte (POR = 00000000)

Note : SC[15:0] must always be equal to or less than EC[15:0]

Figure 9-3: Set Column Address example

SC[15:0

]

EC[15:0]

9.17 set_page_address

Command 0x2B

Parameters 4

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 1 0 0 1 2B

Parameter 1 1 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 xx

Parameter 2 1 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 xx

Parameter 3 1 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 xx

Parameter 4 1 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 xx

Description

Set the page address of the frame buffer accessed by the host processor with the read_memory_start (0x2C),

write_memory_start (0x2E), read_memory_continue (0x3E) and write_memory_continue (0x3C))..

Solomon Systech Jul 2011 P 28/90 Rev 1.3 SSD1961

SP[15:8] : Start page (row) number high byte (POR = 00000000)

SP[7:0] : Start page (row) number low byte (POR = 00000000)

EP[15:8] : End page (row) number high byte (POR = 00000000)

EP[7:0] : End page (row) number low byte (POR = 00000000)

Note : SP[15:0] must always be equal to or less than EP[15:0]

Figure 9-4: Set Page Address example

SP[15:0]

EP[15:0]

9.18 write_memory_start

Command 0x2C

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 1 1 0 0 2C

Description

Transfer image information from the host processor interface to the SSD1961 starting at the location provided by

set_column _address (0x2A) and set _page_address (0x2B).

If set_address_mode (0x36) A[5] = 0:

The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively.

Pixel Data 1 is stored in frame buffer at (SC, SP). The column address is then incremented and pixels are written to the

frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the

page address is incremented. Pixels are written to the frame buffer until the page address equals the End Page (EP) value

and the column address equals the EC value, or the host processor sends another command. If the number of pixels

exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored.

If set_address_mode (0x36) A[5] = 1:

The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively.

Pixel Data 1 is stored in frame buffer at (SC, SP). The page address is then incremented and pixels are written to the

frame buffer until the page address equals the End Page (EP) value. The page address is then reset to SP and the column

address is incremented. Pixels are written to the frame buffer until the column address equals the End column (EC) value

and the page address equals the EP value, or the host processor sends another command. If the number of pixels exceeds

(EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored.

SSD1961 Rev 1.3 P 29/90 Jul 2011 Solomon Systech

9.19 read_memory_start

Command 0x2E

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 0 1 1 1 0 2E

Description

Transfer image data from the SSD1961 to the host processor interface starting at the location provided by

set_column_address (0x2A) and set_page_address (0x2B).

If set_address_mode A[5] = 0:

The column and page address are reset to the Start Column (SC) and Start Page (SP), respectively.

Pixels Data1are read from frame buffer at (SC, SP). The column address is then incremented and pixels read from the

frame buffer until the column address equals the End Column (EC) value. The column address is then reset to SC and the

page address is incremented. Pixels are read from the frame buffer until the page address equals the End Page (EP) value

and the column address equals the EC value, or the host processor sends another command.

If set_address_mode (0x36) A[5] = 1:

The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively.

Pixels Data1are read from frame buffer at (SC, SP). The page address is then incremented and pixels read from the frame

buffer until the page address equals the End Page (EP) value. The page address is then reset to SP and the column

address is incremented. Pixels are read from the frame buffer until the column address equals the End Column (EC)

value and the page address equals the EP value, or the host processor sends another command.

9.20 set_partial_area

Command 0x30

Parameters 4

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 0 0 0 0 30

Parameter 1 1 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 xx

Parameter 2 1 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 xx

Parameter 3 1 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 xx

Parameter 4 1 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 xx

Description

This command defines the Partial Display mode’s display area. There are two parameters associated with this command,

the first defines the Start Row (SR) and the second the End Row (ER). SR and ER refer to the Frame Buffer Line Pointer.

SR[15:8] : Start display row number high byte (POR = 00000000)

SR[7:0] : Start display row number low byte (POR = 00000000)

ER[15:8] : End display row number high byte (POR = 00000000)

ER[7:0] : End display row number low byte (POR = 00000000)

Note : SR[15:0] and ER[15:0] cannot be 0000h nor exceed the last vertical line number.

Solomon Systech Jul 2011 P 30/90 Rev 1.3 SSD1961

If End Row > Start Row

Figure 9-5: Set Partial Area with set_address_mode (0x36) A[4] = 0 when End Row > Start Row

SR[15:0]

Partial Area

ER[15:0]

Figure 9-6: Set Partial Area with set_address_mode (0x36) A[4] = 1 when End Row > Start Row

ER[15:0]

Partial Area

SR[15:0]

If Start Row > End Row

Figure 9-7: Set Partial Area with set_address_mode (0x36) A[4] = 0 when Start Row > End Row

Partial Area

ER[15:0]

SR[15:0] Partial Area

SSD1961 Rev 1.3 P 31/90 Jul 2011 Solomon Systech

Figure 9-8: Set Partial Area with set_address_mode (0x36) A[4] = 1 when Start Row > End Row

Partial Area

SR[15:0]

ER[15:0]

Partial Area

9.21 set_scroll_area

Command 0x33

Parameters 6

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 0 0 1 1 33

Parameter 1 1 TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8 xx

Parameter 2 1 TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 xx

Parameter 3 1 VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8 xx

Parameter 4 1 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 xx

Parameter 5 1 BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8 xx

Parameter 6 1 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 xx

Description

Defines the vertical scrolling and fixed area on display area

TFA[15:8] : High byte of Top Fixed Area number in lines from the top of the frame buffer (POR = 00000000)

TFA[7:0] : Low byte of Top Fixed Area number in lines from the top of the frame buffer (POR = 00000000)

VSA[15:8] : High byte of Vertical scrolling area in number of lines of the frame buffer (POR = 00000000)

VSA[7:0] : Low byte of Vertical scrolling area in number of lines of the frame buffer (POR = 00000000)

BFA[15:8] : High byte of Bottom Fixed Area in number of lines from the bottom of the frame buffer (POR = 00000000)

BFA[7:0] : Low byte of Bottom Fixed Area in number of lines from the bottom of the frame buffer (POR = 00000000)

If set_address_mode (0x36) A[4] = 0 :

The TFA[15:0] describes the Top Fixed Area in number of lines from the top of the frame buffer. The top of the frame

buffer and top of the display panel are aligned.

The VSA[15:0] describes the height of the Vertical Scrolling Area in number of lines of frame buffer from the Vertical

Scrolling Start Address. The first line of the Vertical Scrolling Area starts immediately after the bottom most line of the

Top Fixed Area. The last line of the Vertical Scrolling Area ends immediately before the top most line of the Bottom

Fixed Area.

The BFA[15:0] describes the Bottom Fixed Area in number of lines from the bottom of the frame buffer. The bottom of

the frame buffer and bottom of the display panel are aligned.

TFA, VSA and BFA refer to the Frame Buffer Line Pointer.

Solomon Systech Jul 2011 P 32/90 Rev 1.3 SSD1961

Figure 9-9: Set Scroll Area with set_address_mode (0x36) A[4] = 0

(0,0)

Top Fixed Area

TFA[15:0]

First line read from memory

VSA[15:0]

BFA[15:0]

Bottom Fixed Area

If set_address_mode (0x36) A[4] = 1 :

The TFA[15:0], describes the Top Fixed Area in number of lines from the bottom of the frame buffer. The bottom of the

frame buffer and bottom of the display panel are aligned.

The VSA[15:0] describes the height of the Vertical Scrolling Area in number of lines of frame buffer from the Vertical

Scrolling Start Address. The first line of the Vertical Scrolling Area starts immediately after the top most line of the Top

Fixed Area. The last line of the Vertical Scrolling Area ends immediately before the bottom most line of the Bottom

Fixed Area.

The BFA[15:0] describes the Bottom Fixed Area in number of lines from the top of the frame buffer. The top of the

frame buffer and top of the display panel are aligned.

TFA, VSA and BFA refer to the Frame Buffer Line Pointer.

Figure 9-10: Set Scroll Area with set_address_mode (0x36) A[4] = 1

(0,0)

Bottom Fixed Area

BFA[15:0]

VSA[15:0]

First line read from memory

TFA[15:0]

Top Fixed Area

Note :

The sum of TFA, VSA and BFA must equal the number of the display panel’s horizontal lines (pages), otherwise

Scrolling mode is undefined.

In Vertical Scroll Mode, set_address_mode (0x36) A[5] should be set to ‘0’ – this only affects the Frame Buffer Write.

SSD1961 Rev 1.3 P 33/90 Jul 2011 Solomon Systech

9.22 set_tear_off

Command 0x34

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 0 1 0 0 34

Description

TE signal is not sent from the SSD1961 to the host processor.

9.23 set_tear_on

Command 0x35

Parameters 1

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 0 1 0 1 35

Parameter 1 1 0 0 0 0 0 0 0 A0 xx

Description

TE signal is sent from the SSD1961 to the host processor at the start of VFP.

A[0] : Tearing effect line mode (POR = 0)

0 The tearing effect output line consists of V-blanking information only.

1 The tearing effect output line consists of both V-blanking and H-blanking information by

set_tear_scanline (0x44)..

The TE signal shall be active low when the display panel is in Sleep mode.

9.24 set_address_mode

Command 0x36

Parameters 1

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 0 1 1 0 36

Parameter 1 1 A7 A

6 A

5 A

4 A

3 A

2 A

1 A

0 xx

Description

Set the read order from host processor to frame buffer by A[7:5] and A[3] and from frame buffer to the display panel by

A[2:0] and A[4].

A[7] : Page address order (POR = 0)

This bit controls the order that pages of data are transferred from the host processor to the SSD1961’s frame buffer.

0 Top to bottom, pages transferred from SP (Start Page) to EP (End Page).

1 Bottom to top, pages transferred from EP (End Page) to SP (Start Page).

Solomon Systech Jul 2011 P 34/90 Rev 1.3 SSD1961

Figure 9-11: A[7] Page Address Order

A[7]=0,

A[6]=A[5]=0,A[3]=x A[7]=1,

A[6]=A[5]=0,A[3]=x

Host Frame Buffer Host Frame Buffer

SP SP

SP EP

EP EP

EP SP

SC 　 EC SC 　 EC SC 　 EC SC 　 EC

A[6] : Column address order (POR = 0)

This bit controls the order that columns of data are transferred from the host processor to the SSD1961’s frame buffer.

0 Left to right, columns transferred from SC (Start Column) to EC (End Column).

1 Right to left, columns transferred from EC (End Column) to SC (Start Column).

Figure 9-12: A[6] Column Address Order

A[6]=0,

A[7]=A[5]=0,A[3]=x A[6]=1,

A[7]=A[5]=0,A[3]=x

Host Frame Buffer Host Frame Buffer

SP SP

EP EP

SC 　 EC SC 　 EC SC 　 EC EC 　 SC

A[5] : Page / Column order (POR = 0)

This bit controls the order that columns of data are transferred from the host processor to the SSD1961’s frame buffer.

0 Normal mode

1 Reverse mode

Figure 9-13: A[5] Page / Column Address Order

A[5]=0,

A[7]=A[6]=0,A[3]=x A[5]=1,

A[7]=A[6]=0,A[3]=x

Host Frame Buffer Host Frame Buffer

SP SP

SP SC

EP EP

EP EC

SC 　 EC SC 　 EC SC 　 EC SP 　 EP

SSD1961 Rev 1.3 P 35/90 Jul 2011 Solomon Systech

A[4] : Line address order (POR = 0)

This bit controls the display panel’s horizontal line refresh order. The image shown on the display panel is unaffected,

regardless of the bit setting.

0 LCD refresh from top line to bottom line.

1 LCD refresh from bottom line to top line.

A[3] : RGB / BGR order (POR = 0)

This bit controls the RGB data order transferred from the SSD1961’s frame buffer to the display panel.

0 RGB

1 BGR

Figure 9-14: A[3] RGB Order

A[3] = 0 A[3] = 1

Frame Buffer Display Panel Frame Buffer Display Panel

R G B 　 R G B R G B 　 B G R

A[2] : Display data latch data (POR = 0)

This bit controls the display panel’s vertical line data latch order. The image shown on the display panel is unaffected,

regardless of the bit setting.

0 LCD refresh from left side to right side

1 LCD refresh from right side to left side

A[1] : Flip Horizontal (POR = 0)

This bit flips the image shown on the display panel left to right. No change is made to the frame buffer.

0 Normal

1 Flipped

Figure 9-15: A[1] Flip Horizontal

A[1]=0,

A[4]=A[2]=A[0]=0 A[1]=1,

A[4]=A[2]=A[0]=0

Frame Buffer Display Panel Frame Buffer Display Panel

1 1 1 1

n n n n

1 　 m 1 　 m 1 　 m m 　 1

Solomon Systech Jul 2011 P 36/90 Rev 1.3 SSD1961

A[0] : Flip Vertical (POR = 0)

This bit flips the image shown on the display panel top to bottom. No change is made to the frame buffer.

0 Normal

1 Flipped

Figure 9-16: A[0] Flip Vertical

A[0]=0,

A[4]=A[2]=A[1]=0 A[0]=1,

A[4]=A[2]=A[1]=0

Frame Buffer Display Panel Frame Buffer Display Panel

1 1 1 n

n n n 1

1 　 m 1 　 m 1 　 m 1 　 m

9.25 set_scroll_start

Command 0x37

Parameters 2

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 0 1 1 1 37

Parameter 1 1 VSP15 VSP14 VSP13 VSP12 VSP11 VSP10 VSP9 VSP8 xx

Parameter 2 1 VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP1 VSP0 xx

Description

This command sets the start of the vertical scrolling area in the frame buffer. The vertical scrolling area is fully defined

when this command is used with the the set_scroll_area (0x33).

VSP[15:8] : High byte of the line number in frame buffer that is written to the display as the first line of the vertical

scrolling area (POR = 00000000)

VSP[7:0] : Low byte of the line number in frame buffer that is written to the display as the first line of the vertical

scrolling area (POR = 00000000)

If set_address_mode (0x36) A[4] = 0:

Example:

When Top Fixed Area = Bottom Fixed Area = 0, Vertical Scrolling Area = YY and VSP = 3.

Figure 9-17: Set Scroll Start with set_address_mode (0x36) A[4] = 0

Frame Buffer Display Panel

(0,0) VSP[15:0]

VSP[15:0]

(0,YY-1)

(0,0)

(0,YY-1)

SSD1961 Rev 1.3 P 37/90 Jul 2011 Solomon Systech

If set_address_mode (0x36) A[4] = 1:

Example:

When Top Fixed Area = Bottom Fixed Area = 0, Vertical Scrolling Area = YY and VSP = 3.

Figure 9-18: Set Scroll Start with set_address_mode (0x36) A[4] = 1

Frame Buffer Display Panel

(0,YY-1)

(0,0)

(0,YY-1)

VSP[15:0]

(0,0) VSP[15:0]

Note :

If set_address_mode, (0x36) A[4] = 0, TFA[15:0] - 1< VSP[15:0] < # of lines in frame buffer - BFA[15:0]

If set_address_mode, (0x36) A[4] = 1, BFA[15:0] - 1 < VSP[15:0] < # of lines in frame buffer - TFA[15:0]

9.26 exit_idle_mode

Command 0x38

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 1 0 0 0 38

Description

This command causes the SSD1961 to exit Idle Mode.

Full color depth is used for the display panel.

9.27 enter_idle_mode

Command 0x39

Parameters None

D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex

Command 0 0 0 1 1 1 0 0 1 39

Description

This command causes the SSD1961 to enter Idle Mode.

In Idle Mode, color depth is reduced. Colors are shown on the display panel using the MSB of each of the R, G and B

color components in the frame buffer.

R7 RaR; R4 R1 R: Rl R41 B7 13. E; 345131 El 130

Solomon Systech Jul 2011 P 38/90 Rev 1.3 SSD1961

Table 9-1: Enter Idle Mode memory content vs display color

Color R7 R6 R5 R4 R3 R2 R1 R0 G

7 G6 G5 G4 G3 G2 G1 G0 B

7 B6 B5 B4 B3 B2 B1 B0

Black 0XXXXXXX 0XXXXXXX 0XXXXXXX

Blue 0XXXXXXX 0XXXXXXX 1XXXXXXX

Red 1XXXXXXX 0XXXXXXX 0XXXXXXX

Magenta 1XXXXXXX 0XXXXXXX 1XXXXXXX

Green 0XXXXXXX 1XXXXXXX 0XXXXXXX

Cyan 0XXXXXXX 1XXXXXXX 1XXXXXXX

Yellow 1XXXXXXX 1XXXXXXX 0XXXXXXX

White 1XXXXXXX 1XXXXXXX 1XXXXXXX

SSD1961 Datasheet by Displaytech